Biasing circuit for constant triode collector current

Abstract

The invention discloses a bias circuit for constant triode collector current, which comprises a triode Q1, a bias current generating circuit, a current sensing circuit and a current copying circuit, bias current IBIAS output by the bias current generating circuit and triode base current IB are added and then input into the current sensing circuit; the current copy circuit copies the current of the current induction circuit and inputs the copied current to the emitter of the triode. The current sensing and copying loop is formed at the emitting electrode and the base electrode of the triode, constant circuit bias of collector current can be achieved, and the magnitude of the collector current is irrelevant to the current amplification coefficient of the triode.

Description

Technical Field

[0001] The invention relates to a bias circuit, in particular to a bias circuit for a constant transistor collector current, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] In integrated circuit design, transistors are often used to implement circuits such as reference voltage and temperature detection. The parasitic transistors in the CMOS process have the problem of too low current amplification factor, and the current amplification factor will change with the bias current, manufacturing process deviation and temperature, which will cause the bias circuit to bias the transistor emitter current and the required collector current to be too large. For example, if the collector current needs to be biased to 1mA, the bias circuit is implemented to give a bias current of 1mA from the emitter. When the transistor current amplification factor is 200, the bias current obtained by the collector is 200 / 201*1mA=0.995mA, which is less than 1% compared with the collector current that needs to be biased. When the transistor current amplification factor is reduced to 1, the bias current obtained by the collector is 1 / 2*1mA=0.5mA. At this time, the error is as high as 50% compared with the collector current that needs to be biased.

[0003] The existing constant transistor collector current bias structure diagram is as follows Figure 5 As shown. By additionally compensating the emitter of the transistor with a compensation current that is consistent with the base current, the collector current deviation caused by the transistor amplification factor is eliminated. For example, when the collector bias current is 1mA, when the transistor current amplification factor is 200, the compensation current of the existing solution is 0.005mA; when the transistor current amplification factor is 1, the compensation current of the existing solution is 2mA. The compensation current changes by up to 400 times. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a bias circuit for a constant transistor collector current, so as to achieve that the magnitude of the transistor collector current is independent of the transistor current amplification factor.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A bias circuit for a constant transistor collector current comprises a transistor Q1, a bias current generating circuit, a current sensing circuit and a current copying circuit. The bias current generating circuit outputs a bias current I BIAS The transistor base current I B After addition, the current is input into the current sensing circuit. The current copying circuit copies the current of the current sensing circuit and inputs it into the emitter of the transistor.

[0006] Furthermore, the transistor Q1 is a PNP transistor or an NPN transistor.

[0007] Furthermore, when the transistor Q1 is a PNP transistor, the collector of the transistor Q1 is grounded, the current sensing circuit includes an NMOS transistor NM1, the gate of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM1, the base of the transistor Q1 and the output end of the bias current generating circuit, and the source of the NMOS transistor NM1 is grounded.

[0008] Furthermore, the current copy circuit includes an NMOS tube NM2, a PMOS tube PM1 and a PMOS tube PM2, the gate of the NMOS tube NM2 is connected to the gate of the NMOS tube NM1, the source of the NMOS tube NM2 is grounded, the drain of the NMOS tube NM2 is connected to the drain of the PMOS tube PM2, the gate of the PMOS tube PM2 and the gate of the PMOS tube PM1, the source of the PMOS tube PM2 and the source of the PMOS tube PM1 are connected to the power supply VCC, and the drain of the PMOS tube PM1 is connected to the emitter of the transistor Q1.

[0009] Further, the current copy circuit includes an NMOS tube NM3, an NMOS tube NM4, an amplifier A1, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5 and a PMOS tube PM6, the gate of the NMOS tube NM3 is connected to the gate of the NMOS tube NM1 and the same-direction input terminal of the amplifier A1, the source of the NMOS tube NM3 is grounded, the drain of the NMOS tube NM3 is connected to the reverse input terminal of the amplifier A1 and the source of the NMOS tube NM4, the gate of the NMOS tube NM4 is connected to the output terminal of the amplifier A1, the drain of the NMOS tube NM4 is connected to the drain of the PMOS tube PM6, the gate of the PMOS tube PM4 and the gate of the PMOS tube PM3, and the gate of the PMOS tube PM6 and the gate of the PMOS tube PM5 are connected to the bias voltage V BIAS The source of the PMOS tube PM6 is connected to the drain of the PMOS tube PM4, the source of the PMOS tube PM4 and the source of the PMOS tube PM3 are connected to the power supply VCC, the drain of the PMOS tube PM3 is connected to the source of the PMOS tube PM5, and the drain of the PMOS tube PM5 is connected to the emitter of the transistor Q1.

[0010] Further, when the transistor Q1 adopts an NPN transistor, the collector of the transistor Q1 is connected to the power supply VCC, the current sensing circuit includes a PMOS transistor PM7, the gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM7, the base of the transistor Q1 and the input end of the bias current generating circuit, and the source of the PMOS transistor PM7 is connected to the power supply VCC.

[0011] Furthermore, the current copy circuit includes a PMOS tube PM8, an NMOS tube NM5 and an NMOS tube NM6, the gate of the PMOS tube PM8 is connected to the gate of the PMOS tube PM7, the source of the PMOS tube PM8 is connected to the power supply VCC, the drain of the PMOS tube PM8 is connected to the drain of the NMOS tube NM6, the gate of the NMOS tube NM6 is connected to the gate of the NMOS tube NM5, the source of the NMOS tube NM6 and the source of the NMOS tube NM5 are grounded, and the drain of the NMOS tube NM5 is connected to the emitter of the transistor Q1.

[0012] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a bias circuit for a constant transistor collector current, which senses the sum of the transistor base current and the current generated by the current bias, and then accurately copies the induced current by current copying, and uses it as the bias current of the transistor emitter, and part of the emitter current will flow to the base; by forming the above-mentioned current sensing and copying loop at the transistor emitter and base, a circuit bias with a constant collector current can be achieved, and the collector current size is independent of the transistor current amplification factor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The present invention is a schematic diagram of a bias circuit for a constant transistor collector current.

[0014] Figure 2 It is a circuit diagram of Embodiment 1 of a bias circuit for a constant transistor collector current of the present invention.

[0015] Figure 3 It is a circuit diagram of Embodiment 2 of a bias circuit for a constant transistor collector current of the present invention.

[0016] Figure 4 It is a circuit diagram of Embodiment 3 of a bias circuit for a constant transistor collector current of the present invention.

[0017] Figure 5 It is a circuit diagram of a bias structure of a constant transistor collector current in the prior art. DETAILED DESCRIPTION In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0019] like Figure 1As shown, a bias circuit of a constant transistor collector current of the present invention comprises a transistor Q1, a bias current generating circuit, a current sensing circuit and a current copying circuit. The bias current generating circuit outputs a bias current I BIAS The transistor base current I B After addition, the current is input into the current sensing circuit. The current copying circuit copies the current of the current sensing circuit and inputs it into the emitter of the transistor.

[0020] Embodiment 1;

[0021] like Figure 2 As shown, when the transistor Q1 adopts a PNP transistor, the collector of the transistor Q1 is grounded, the current sensing circuit includes an NMOS transistor NM1, the gate of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM1, the base of the transistor Q1 and the output end of the bias current generating circuit, and the source of the NMOS transistor NM1 is grounded.

[0022] The current copy circuit includes an NMOS tube NM2, a PMOS tube PM1 and a PMOS tube PM2, a gate of the NMOS tube NM2 is connected to a gate of the NMOS tube NM1, a source of the NMOS tube NM2 is grounded, a drain of the NMOS tube NM2 is connected to a drain of the PMOS tube PM2, a gate of the PMOS tube PM2 and a gate of the PMOS tube PM1, a source of the PMOS tube PM2 and a source of the PMOS tube PM1 are connected to a power supply VCC, and a drain of the PMOS tube PM1 is connected to an emitter of the transistor Q1.

[0023] Among them, NMOS tube NM1 and NMOS tube NM2 form a 1:1 current mirror circuit, so that the induced current I1 on NMOS tube NM1 is copied to NMOS tube NM2, the current of PMOS tube PM2 is equal to that of NMOS tube NM2, and PMOS tube PM1 and PMOS tube PM2 form a 1:1 current mirror circuit, and the current on PMOS tube PM2 is copied to PMOS tube PM1, that is, the emitter current I of transistor Q1 is finally E =I1.

[0024] Embodiment 2;

[0025] like Figure 3 As shown, when the transistor Q1 adopts a PNP transistor, the collector of the transistor Q1 is grounded, the current sensing circuit includes an NMOS transistor NM1, the gate of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM1, the base of the transistor Q1 and the output end of the bias current generating circuit, and the source of the NMOS transistor NM1 is grounded.

[0026] The current copy circuit includes an NMOS tube NM3, an NMOS tube NM4, an amplifier A1, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5 and a PMOS tube PM6. The gate of the NMOS tube NM3 is connected to the gate of the NMOS tube NM1 and the same-direction input terminal of the amplifier A1, the source of the NMOS tube NM3 is grounded, the drain of the NMOS tube NM3 is connected to the reverse input terminal of the amplifier A1 and the source of the NMOS tube NM4, the gate of the NMOS tube NM4 is connected to the output terminal of the amplifier A1, the drain of the NMOS tube NM4 is connected to the drain of the PMOS tube PM6, the gate of the PMOS tube PM4 and the gate of the PMOS tube PM3, and the gate of the PMOS tube PM6 and the gate of the PMOS tube PM5 are connected to the bias voltage V BIAS The source of the PMOS tube PM6 is connected to the drain of the PMOS tube PM4, the source of the PMOS tube PM4 and the source of the PMOS tube PM3 are connected to the power supply VCC, the drain of the PMOS tube PM3 is connected to the source of the PMOS tube PM5, and the drain of the PMOS tube PM5 is connected to the emitter of the transistor Q1.

[0027] Among them, NMOS tube NM1 and NMOS tube NM3 form a 1:1 current mirror circuit, so that the induced current I1 on NMOS tube NM1 is copied to NMOS tube NM3, the current of PMOS tube PM4 is equal to that of NMOS tube NM3, and PMOS tube PM3 and PMOS tube PM4 form a 1:1 current mirror circuit, and the current on PMOS tube PM4 is copied to PMOS tube PM3, that is, the emitter current I of transistor Q1 is finally E =I1.

[0028] In addition, amplifier A1 and NMOS tube NM4 form a feedback loop, so that the drain voltages of NMOS tubes NM1 and NMOS tubes NM3 in the current mirror are the same, improving the accuracy of the current mirror. PMOS tubes PM3, PM4, PM5 and PM6 form a current mirror with cascode tubes, and PMOS tubes PM5 and PM6 are cascode tubes, which improve the accuracy of the current mirror.

[0029] Embodiment 3;

[0030] like Figure 4 As shown, when the transistor Q1 adopts an NPN transistor, the collector of the transistor Q1 is connected to the power supply VCC, the current sensing circuit includes a PMOS transistor PM7, the gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM7, the base of the transistor Q1 and the input end of the bias current generating circuit, and the source of the PMOS transistor PM7 is connected to the power supply VCC.

[0031] The current copy circuit includes a PMOS tube PM8, an NMOS tube NM5 and an NMOS tube NM6. The gate of the PMOS tube PM8 is connected to the gate of the PMOS tube PM7, the source of the PMOS tube PM8 is connected to the power supply VCC, the drain of the PMOS tube PM8 is connected to the drain of the NMOS tube NM6, the gate of the NMOS tube NM6 is connected to the gate of the NMOS tube NM5, the source of the NMOS tube NM6 and the source of the NMOS tube NM5 are grounded, and the drain of the NMOS tube NM5 is connected to the emitter of the transistor Q1.

[0032] Among them, the PMOS tube PM7 and the PMOS tube PM8 form a 1:1 current mirror circuit, so that the induced current I1 on the PMOS tube PM7 is copied to the PMOS tube PM8, the current of the PMOS tube PM8 is equal to that of the NMOS tube NM6, and the NMOS tube NM5 and the NMOS tube NM6 form a 1:1 current mirror circuit, and the current on the NMOS tube NM6 is copied to the NMOS tube NM5, that is, the emitter current I of the final transistor Q1 E =I1.

[0033] The working principle of a bias circuit for a constant transistor collector current of the present invention is: Taking Example 1 as an example, the induced current I1 of the current sensing circuit is the bias current I generated by the bias current generating circuit. BIAS The transistor base current I B The sum of, that is: I1=I BIAS +I B (1); The emitter current I of transistor Q1 E The base current I of transistor Q1 B The relationship between them is: I B =1 / (1+β)*I E (2); Among them, β is the current amplification factor of transistor Q1.

[0034] At the same time, the emitter current I E The current copy circuit copies the induced current I1 at a ratio of 1:1, that is, I E =I1(3); Substituting formula (1) and (2) into formula (3), we can obtain I E =I1=I BIAS +I B =I BIAS +1 / (1+β)*I E (4); From the above formula, we can get I E =(1+β)*I BIAS / β (5); Since the emitter current I E is the base current I of transistor Q1 B and the collector current I of transistor Q1 C The sum of I E =I B +I C (6); Substituting formula (2) into formula (6) yields I E =I B +I C =1 / (1+β)*I E + I C (7); From formula (7), we can get I E =(1+β)*I C / β (8); From formula (5) and formula (8), we can know that I C =I BIAS .

[0035] That is, the collector current I of the transistor Q1 of the present invention is C It has nothing to do with the current amplification factor β of the transistor.

[0036] The present invention provides a bias circuit for a constant transistor collector current, which senses the sum of the transistor base current and the current generated by the current bias, and then uses the current copy to accurately copy the sensed current and use it as the bias current of the transistor emitter, and part of the emitter current will flow to the base. By forming the above-mentioned current sensing and copying loop at the transistor emitter and base, a circuit bias with a constant collector current can be achieved, and the collector current size is independent of the transistor current amplification factor.

[0037] Compared with the existing solutions, the solution proposed by the present invention can reduce the compensation current change caused by different transistor current magnification factors. For example, the collector bias current of the prior art is 1mA. When the transistor current magnification factor is 200, the compensation current of the existing solution is 0.005mA; when the transistor current magnification factor is 1, the compensation current of the existing solution is 2mA, and the compensation current change is as high as 400 times. In the solution of the present invention, when the same transistor current magnification factor changes from 200 to 1, the current of the current sensing and current copying circuit changes by about 2 times.

[0038] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A bias circuit for a constant transistor collector current, characterized in that: It includes transistor Q1, bias current generating circuit, current sensing circuit and current copying circuit. The bias current generating circuit outputs bias current I BIAS The transistor base current I B After addition, the current is input into the current sensing circuit. The current copying circuit copies the current of the current sensing circuit and inputs it into the emitter of the transistor.

2. The bias circuit for a constant transistor collector current according to claim 1, characterized in that: The transistor Q1 is a PNP transistor or an NPN transistor.

3. The bias circuit for a constant transistor collector current according to claim 2, characterized in that: When the transistor Q1 is a PNP transistor, the collector of the transistor Q1 is grounded, the current sensing circuit includes an NMOS transistor NM1, the gate of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM1, the base of the transistor Q1 and the output end of the bias current generating circuit, and the source of the NMOS transistor NM1 is grounded.

4. The bias circuit for a constant transistor collector current according to claim 3, characterized in that: The current copy circuit comprises an NMOS tube NM2, a PMOS tube PM1 and a PMOS tube PM2, the gate of the NMOS tube NM2 is connected to the gate of the NMOS tube NM1, the source of the NMOS tube NM2 is grounded, the drain of the NMOS tube NM2 is connected to the drain of the PMOS tube PM2, the gate of the PMOS tube PM2 and the gate of the PMOS tube PM1, the source of the PMOS tube PM2 and the source of the PMOS tube PM1 are connected to the power supply VCC, and the drain of the PMOS tube PM1 is connected to the emitter of the transistor Q1.

5. The bias circuit for a constant transistor collector current according to claim 3, characterized in that: The current copy circuit comprises an NMOS tube NM3, an NMOS tube NM4, an amplifier A1, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5 and a PMOS tube PM6. The gate of the NMOS tube NM3 is connected to the gate of the NMOS tube NM1 and the same-direction input terminal of the amplifier A1, the source of the NMOS tube NM3 is grounded, the drain of the NMOS tube NM3 is connected to the reverse input terminal of the amplifier A1 and the source of the NMOS tube NM4, the gate of the NMOS tube NM4 is connected to the output terminal of the amplifier A1, the drain of the NMOS tube NM4 is connected to the drain of the PMOS tube PM6, the gate of the PMOS tube PM4 and the gate of the PMOS tube PM3, and the gate of the PMOS tube PM6 and the gate of the PMOS tube PM5 are connected to the bias voltage V BIAS The source of the PMOS tube PM6 is connected to the drain of the PMOS tube PM4, the source of the PMOS tube PM4 and the source of the PMOS tube PM3 are connected to the power supply VCC, the drain of the PMOS tube PM3 is connected to the source of the PMOS tube PM5, and the drain of the PMOS tube PM5 is connected to the emitter of the transistor Q1.

6. The bias circuit for a constant transistor collector current according to claim 2, characterized in that: When the transistor Q1 is an NPN transistor, the collector of the transistor Q1 is connected to the power supply VCC, the current sensing circuit includes a PMOS transistor PM7, the gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM7, the base of the transistor Q1 and the input end of the bias current generating circuit, and the source of the PMOS transistor PM7 is connected to the power supply VCC.

7. A bias circuit for a constant transistor collector current according to claim 6, characterized in that: The current copy circuit includes a PMOS tube PM8, an NMOS tube NM5 and an NMOS tube NM6, the gate of the PMOS tube PM8 is connected to the gate of the PMOS tube PM7, the source of the PMOS tube PM8 is connected to the power supply VCC, the drain of the PMOS tube PM8 is connected to the drain of the NMOS tube NM6, the gate of the NMOS tube NM6 is connected to the gate of the NMOS tube NM5, the source of the NMOS tube NM6 and the source of the NMOS tube NM5 are grounded, and the drain of the NMOS tube NM5 is connected to the emitter of the transistor Q1.

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