Clock switching circuit and clock chip
By using cascading registers and clock exception handling modules in the clock switching circuit, the problem of glitches and clock loss switching failure during clock switching is solved, and automatic switching and stable output when clock loss is achieved.
Patent Information
- Application Number
- CN202411262722.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2024-12-13
AI Technical Summary
The existing clock switching circuit is prone to glitches during the switching of the clock, and cannot switch the clock when the clock is lost, resulting in the circuit malfunctioning or being unable to switch.
A clock switching circuit is designed, including n-channel clock synchronization branch, clock exception handling module, source selection module and logic or module. The clock synchronization is realized through cascading registers, and the register is reset when the clock is lost to ensure the switching signal. Enable the output of the signal, avoid glitches, and automatically switch the clock source when the clock is lost.
The occurrence of glitches is avoided during the clock switching process, and normal clock switching is ensured when the clock is lost, improving the reliability and stability of the circuit.
Smart Images
Figure CN119126917A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of clock circuits, and in particular to a clock switching circuit and a clock chip. Background Art
[0002] In modern electronic technology, clock circuits play an important role. In order to avoid the situation where a single clock source is damaged and the clock cannot be obtained, multiple clock sources need to be used in related technologies, and multiple clock sources need to be switched using a clock switching circuit.
[0003] However, in the related art, a clock switching circuit using a multiplexer will generate glitches during clock switching, which may cause circuit malfunctions. Although other clock switching circuits do not generate glitches, they cannot switch clocks when the clock is lost. Summary of the invention
[0004] The invention provides a clock switching circuit and a clock chip, so that no burrs are generated during clock switching and the clock can still be switched when the clock is lost.
[0005] According to one aspect of the present invention, a clock switching circuit is provided, the clock switching circuit comprising: n clock synchronization branches, a clock abnormality processing module, a source selection module and a logic OR module, wherein n≥2, n is a positive integer;
[0006] The clock synchronization branch is electrically connected to the source selection module, the clock exception processing module, the logic or module and the rest of the clock synchronization branches; the clock synchronization branch includes at least two stages of cascaded registers, and the clock synchronization branch is used to synchronize the input clock of its clock input end and then output it when enabled;
[0007] Optionally, the clock synchronization branch also includes a first logic AND unit and a second logic AND unit; the first input end of the first logic AND unit is electrically connected to the output end of the source selection module, and the n-1 second input ends of the first logic AND unit are electrically connected to the enable output ends of the remaining n-1 clock synchronization branches in a one-to-one correspondence; the output end of the first logic AND unit is electrically connected to the shift input end of the first-stage register; the clock end of the register is used to be electrically connected to the corresponding clock source, the reset end of the register is electrically connected to the output end of the clock exception processing module, the output end of the register of the last stage is electrically connected to the first input end of the second logic AND unit, and the output signal of the register of the last stage is inverted and output by the enable output end; the second input end of the second logic AND unit is used to be electrically connected to the corresponding clock source; the output end of the second logic AND unit is electrically connected to the input end of the logic OR module;
[0008] The input end of the clock exception processing module is used to input the clock loss indication signal of the clock source currently output by the clock switching circuit, and the output end of the clock exception processing module is electrically connected to the control end of the source selection module; the clock exception processing module is used to respond to the clock loss indication signal, reset the registers of each of the clock synchronization circuits, and control the source selection module to output an enable signal to a clock synchronization branch corresponding to a clock source that has not lost the clock.
[0009] Optionally, the clock exception handling module includes a pulse generating unit, which is electrically connected to each of the clock sources and the reset end of the register; the pulse generating unit is used to generate a reset pulse in response to the clock loss indication signal to reset the register of each of the clock synchronization circuits; wherein the pulse width of the reset pulse is less than or equal to 0.1 milliseconds.
[0010] Optionally, the clock exception processing module further includes an enable signal generating unit, and the source selection module includes an abnormal source selection unit;
[0011] The enable signal generating unit is electrically connected to the control end of each of the clock sources and the abnormal source selection unit. The enable signal generating unit is used to generate an abnormal status signal in response to the clock loss indication signal. The abnormal source selection unit is used to output an enable signal to a clock synchronization branch corresponding to a clock source that has not lost a clock in response to the abnormal status signal.
[0012] Optionally, the source selection module also includes a normal source selection unit, an input end of the normal source selection unit is connected to an external source selection signal, an output end of the normal source selection unit is electrically connected to an output end of the source selection module, an enable end of the normal source selection unit is electrically connected to an output end of the enable signal generating unit, and the normal source selection unit is used to shield its output in response to the abnormal state signal.
[0013] Optionally, the clock exception processing module includes a storage unit, which is electrically connected to each of the clock sources and is used to record clock loss events.
[0014] Optionally, the clock switching circuit also includes a clock loss detection module, which is electrically connected to each of the clock sources and the clock exception handling module, and the clock loss detection module is used to detect the state of the clock source currently output by the clock switching circuit, and generate the clock loss indication signal when the clock of the clock source is lost.
[0015] Optionally, the clock switching circuit further includes n clock sources, the n clock sources are electrically connected to the n clock synchronization branches in a one-to-one correspondence, and the n clock sources are electrically connected to the clock loss detection module.
[0016] Optionally, the clock switching circuit includes n clock sources, and the clock sources are used to generate a clock signal and the clock loss indication signal;
[0017] The n clock sources are electrically connected to the n clock synchronization branches in a one-to-one correspondence, and the n clock sources are electrically connected to the input end of the clock exception processing module.
[0018] Optionally, the first logic AND unit includes a first AND gate, and the register includes a D flip-flop; each of the clock synchronization branches includes an inverter, and the output end of the register at the last stage is electrically connected to the corresponding enable output end through the inverter.
[0019] According to another aspect of the present invention, a clock chip is provided, wherein the clock chip comprises the clock switching circuit as described above.
[0020] The technical solution of this embodiment adopts a clock switching circuit, which resets the registers in each clock synchronization branch when the clock is lost, so that the clock synchronization branch that needs to select a source can receive an enable signal when the clock source that needs to be switched loses the clock, thereby ensuring that the clock can be switched normally when the clock is lost. In addition, each clock synchronization branch adopts a sequential logic circuit composed of registers, and no glitches will be generated during the clock switching process.
[0021] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0023] Figure 1 A schematic diagram of the circuit structure of a clock switching circuit provided by an embodiment of the present invention;
[0024] Figure 2 A schematic diagram of the circuit structure of a clock synchronization branch and a logic or module;
[0025] Figure 3 A timing diagram of a clock switching circuit normally switching according to an embodiment of the present invention;
[0026] Figure 4 A timing diagram of a clock switching circuit provided by an embodiment of the present invention when the clock is abnormally lost;
[0027] Figure 5 A schematic diagram of the circuit structure of another clock switching circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0030] Figure 1 A schematic diagram of a circuit structure of a clock switching circuit provided by an embodiment of the present invention, Figure 2 This is a schematic diagram of the circuit structure of the clock synchronization branch and the logic or module, refer to Figure 1 and Figure 2 The clock switching circuit includes: n clock synchronization branches 11, a clock exception processing module 12, a source selection module 13 and a logic OR module 14, wherein n≥2, and n is a positive integer. The clock synchronization branch 11 is electrically connected to the source selection module 13, the clock exception processing module 12, the logic OR module 14 and the remaining clock synchronization branches; the clock synchronization branch 11 includes at least two stages of cascaded registers, and the clock synchronization branch 11 is used to synchronize the clock input to its clock input end and output it when enabled.
[0031] The input end of the clock exception processing module 12 is used to input the clock loss indication signal of the clock source currently output by the clock switching circuit, and the output end of the clock exception processing module 12 is electrically connected to the control end of the source selection module 13; the clock exception processing module 12 is used to respond to the clock loss indication signal, reset the registers of each clock synchronization circuit 11, and control the source selection module 13 to output an enable signal to a clock synchronization branch 11 corresponding to a clock source that has not lost the clock.
[0032] Specifically, the clock switching circuit corresponds to n clock sources, the clock frequencies output by each clock source can be the same or different, and the clock sources can be synchronous or asynchronous. The clock switching circuit can switch between the clock sources, so that the clock output terminal CLK_OUT_o of the clock switching circuit can output the clock output by a clock source.
[0033] Each clock synchronization branch 11 is connected to a clock source, and different clock synchronization branches 11 are connected to different clock sources. In this embodiment, the clock switching circuit includes two clock synchronization branches 11, which are respectively a first clock synchronization branch 11A and a second clock synchronization branch 11B.
[0034] When the clock synchronization branch is enabled, the source selection signal output by the source selection module 13 can be enabled to the input end of the cascaded register. After the clock at the clock input end is beat, the source selection signal can be output to the first input end of the second logic AND unit, so that the clock signal input at the clock input end is output. It should be noted that the enabling of this embodiment can be understood as inputting a high-level signal.
[0035] It can be seen that in the clock switching circuit of this embodiment, the source selection signal of the clock synchronization branch will be beaten by the register, and only after a certain delay will the clock synchronization branch be able to output the corresponding clock signal. When enabled, it will also output a signal at its enable output terminal to control the remaining clock synchronization branches to be unable to be enabled. During the clock switching process, for example, the first clock synchronization branch 11A is currently outputting the clock, at this time the first source selection enable terminal CLK_SEL_[0] is 1, and the second source selection enable terminal CLK_SEL_[1] is 0; if clock switching is required, the first source selection enable terminal CLK_SEL_[0] is set to 0, and the second source selection enable terminal CLK_SEL_[1] is set to 1. Since the clock synchronization branch 11 is provided with cascaded registers, after the registers are beat, the 0 signal of the first source selection enable terminal CLK_SEL_[0] will make the first clock synchronization branch 11A have no output; and after the output signal of the first register of the last stage is inverted, that is, the output signal of the first enable output terminal ENO[0] must be beaten by the second register cascaded in the second clock synchronization branch 11B, the second clock synchronization branch can be enabled to output the clock of the second clock input terminal CLK_i[1]. During the beating of the second cascaded register, the clock output terminal CLK_OUT_o of the clock synchronization circuit has no output. From the above analysis, it can be seen that the clock synchronization branch of this embodiment has no output during the clock switching process and will not generate glitches.
[0036] However, the above clock switching process needs to ensure that the clocks input by each clock input terminal are in place before the switching can be successful. If the clock is lost, the switching cannot be performed. Similarly, the first clock synchronization branch 11A currently outputs the clock, and it needs to be switched to the second clock synchronization branch 11B as an example for explanation, and the clock source corresponding to the first clock synchronization branch is lost. When the clock switching is required, the first source selection enable terminal CLK_SEL_[0] is set to 0, and the second source selection enable terminal CLK_SEL_[1] is set to 1. Due to the loss of the clock source, the clock end of the first register 112A has no input, and the cascaded first register 112A cannot beat. Then the 0 signal of the first source selection enable terminal CLK_SEL_[0] cannot be output by the last level first register 112A. Therefore, the last level first register 112A still maintains the output as 1, and the output of the first enable output terminal ENO[0] is 0 after negation, that is, the second clock synchronization branch 11B is still unable to be enabled, so that the clock switching circuit clock switching is unsuccessful.
[0037] In this embodiment, by setting a clock exception processing module 12, when the clock source clock currently output is lost, the clock exception processing module 12 receives a clock loss indication signal, thereby generating a reset signal to reset the registers in each clock synchronization branch 11, so that the last level output of each register is 0. After negation, the enable input terminal of each clock synchronization branch 11 is input to 1. After the reset signal is canceled, the clock synchronization branch whose source selection enable terminal is also enabled can beat the source selection signal to the first input terminal of the second logic and unit, that is, it can be output normally. Therefore, the clock switching circuit of this embodiment can also complete the clock switching when the clock source is lost.
[0038] In addition, when the clock of the clock source is lost, the clock exception handling module 12 will automatically receive a clock loss indication signal, and can control the source selection module 13 to select a clock source that has not lost the clock according to the clock loss indication signal, that is, the clock switching circuit of this embodiment can automatically switch the clock when the clock source is lost.
[0039] The technical solution of this embodiment adopts a clock switching circuit, which resets the registers in each clock synchronization branch when the clock is lost, so that the clock synchronization branch that needs to select a source can receive an enable signal when the clock source that needs to be switched loses the clock, thereby ensuring that the clock can be switched normally when the clock is lost. In addition, each clock synchronization branch adopts a sequential logic circuit composed of registers, and no glitches will be generated during the clock switching process.
[0040] Optionally, the clock synchronization branch 11 includes a first logic AND unit, at least two cascaded registers and a second logic AND unit; the first input end of the first logic AND unit is electrically connected to the output end of the source selection module 13, and the n-1 second input ends of the first logic AND unit are electrically connected one-to-one with the enable output ends of the remaining n-1 clock synchronization branches 11; the output end of the first logic AND unit is electrically connected to the shift input end of the first-stage register; the clock end of the register is used to be electrically connected to the corresponding clock source, the reset end of the register is electrically connected to the output end of the clock exception handling module 12, the output end of the last-stage register is electrically connected to the first input end of the second logic AND unit, and the output signal of the last-stage register is inverted and output from the enable output end; the second input end of the second logic AND unit is used to be electrically connected to the corresponding clock source; the output end of the second logic AND unit is electrically connected to the input end of the logic OR module 14.
[0041] Specifically, the first clock synchronization branch 11A includes a first first logic AND unit 111A, a plurality of cascaded first registers 112A, and a first second logic AND unit 113A; the second clock synchronization branch 11B includes a second first logic AND unit 111B, a plurality of cascaded second registers 112B, and a second second logic AND unit 113B. Each clock synchronization branch includes a clock input terminal, n-1 enable input terminals, a reset input terminal rst_n, an intermediate clock output terminal, a source selection enable terminal, and an enable output terminal. In the first clock synchronization branch 11A, the clock input terminal is the first clock input terminal CLK_i[0], the enable input terminal is the first enable input terminal ENI[0], the source selection enable terminal is the first source selection enable terminal CLK_SEL[0], the enable output terminal is the first enable output terminal ENO[0], and the intermediate clock output terminal is the first intermediate clock output terminal CLK_OUT[0]. In the second clock synchronization branch 11B, the clock input terminal is the second clock input terminal CLK_i[1], the enable input terminal is the second enable input terminal ENI[1], the source selection enable terminal is the second source selection enable terminal CLK_SEL[1], the enable output terminal is the second enable output terminal ENO[1], and the intermediate clock output terminal is the second intermediate clock output terminal CLK_OUT[1]. Taking the first clock synchronization branch 11A as an example to illustrate the relationship between each port and the internal unit, the first source selection enable terminal CLK_SEL_[0] is electrically connected to the first input terminal of the first first logic AND unit 111A, the n-1 first enable input terminals ENI[0] are electrically connected to the enable output terminals in the remaining n-1 clock synchronization branches in a one-to-one correspondence, and are electrically connected to the n-1 second input terminals of the first logic AND unit 111A in a one-to-one correspondence. The reset input terminal rst_n is electrically connected to the reset terminal CLR of the register, the first clock input terminal CLK_i[0] is electrically connected to the clock terminal of the first register 112A and the second input terminal of the first second logic and unit 113A, and the first clock input terminal CLK_i[0] is used to connect to the corresponding clock source. The output signal of the last-stage first register is inverted and output through the first enable output terminal ENO[0]. The first intermediate clock output terminal CLK_OUT[0] is electrically connected to the output terminal of the first second logic and unit 113A, and is electrically connected to an input terminal of the logic or module 14.
[0042] When all inputs of the first logic AND unit are enabled, the source selection signal output by the source selection module 13 can be enabled to the input of the cascaded register. After the clock of the clock input is tapped, the source selection signal can be output to the first input of the second logic AND unit, so that the second logic AND unit can output the clock signal input by the clock input. It should be noted that the enabling of this embodiment can be understood as inputting a high-level signal.
[0043] For ease of understanding, the following first combines Figure 1 and Figure 2 The specific working process of the clock switching circuit is described.
[0044] like Figure 2 As shown, it is taken as an example that each clock synchronization branch includes three registers, and in each clock synchronization branch, the clock end of the last level register is valid on the falling edge, the clock ends of the first two levels of registers are valid on the rising edge, and the reset end of the register is valid at a low level.
[0045] Figure 3 A timing diagram of a clock switching circuit normally switching according to an embodiment of the present invention, combined with Figures 1 to 3 In the initial state, the clock output terminal CLK_OUT_o outputs the clock signal of the first clock input terminal CLK_i[0]. Specifically:
[0046] In the initial state, the first source selection enable terminal CLK_SEL[0] is 1, the second source selection enable terminal CLK_SEL[1] is 0, and the clock output terminal CLK_OUT_o outputs the clock signal of the first clock input terminal CLK_i[0].
[0047] When the clock is switched normally, the first source enable terminal CLK_SEL[0] is set to 0, and the second source enable terminal CLK_SEL[1] is set to 1. Under the beat of the clock signal of the first clock input terminal CLK_i[0], after one and a half cycles (i.e., two rising edges and one falling edge), the output terminal B1 of the last-stage first register 112A is set to 0. At this time, the first second logic AND unit 113A has no output, and the first input terminal A2 of the second first logic AND unit 111B of the second clock synchronization branch 11B is set to 0. Under the beat of the clock signal of the second clock input terminal CLK_i[1], after one and a half cycles, the output terminal B2 of the last-stage second register 112B is set to 1, so that the second second logic AND unit 113B outputs the clock of the second clock input terminal CLK_i[1], thereby finally completing the clock switching.
[0048] Figure 4 A timing diagram of a clock switching circuit provided by an embodiment of the present invention when the clock is abnormally lost, combined with Figure 1 , Figure 2 and Figure 4 In the initial state, the clock output terminal CLK_OUT_o outputs the clock signal of the first clock input terminal CLK_i[0]. Specifically:
[0049] In the initial state, the first source selection enable terminal CLK_SEL[0] is 1, the second source selection enable terminal CLK_SEL[1] is 0, and the clock output terminal CLK_OUT_o outputs the clock signal of the first clock input terminal CLK_i[0].
[0050] When the clock of the first source enable terminal CLK_SEL[0] is lost, the clock needs to be switched automatically. At this time, the clock abnormality processing module 12 receives the clock loss indication signal and generates a reset signal ( Figure 4 The low level pulse of rst_n in the reset signal is used to set the output terminal B1 of the last level first register 112A to 0, and the output terminal B2 of the last level second register 112B to 0, so that the first input terminal A2 of the second first logic AND unit 111B is set to 1. When the reset signal is cancelled, the output terminal B2 of the last level second register 112B is set to 1 after one and a half cycles under the beat of the clock signal of the second clock input terminal CLK_i[1], thereby completing the clock switching. At the same time, the first input terminal A1 of the first first logic AND unit 111A is set to 0, and the first clock synchronization branch 11 will not output.
[0051] Optionally, Figure 5 A schematic diagram of a circuit structure of another clock switching circuit provided by an embodiment of the present invention, referring to Figure 5 The clock exception processing module 12 includes a pulse generating unit 122, which is electrically connected to each clock source and the reset end of the register; the pulse generating unit 122 is used to generate a reset pulse in response to the clock loss indication signal to reset the register of each clock synchronization circuit; wherein the pulse width of the reset pulse is less than or equal to 0.1 milliseconds.
[0052] Specifically, the pulse generating unit 122 may be a circuit that generates a reset pulse according to a clock loss indication signal. For example, when the clock is normal, the clock loss indication signal is 1, and when the clock is lost, the clock loss indication signal is 0. The pulse generating unit 122 may generate a reset pulse according to the falling edge of the clock loss indication signal, and the reset pulse is also the reset signal described above. Of course, the pulse generating unit 122 only outputs a reset pulse in response to the clock loss indication signal of the clock source output by the current clock switching circuit. During the duration of the reset pulse, since the first input end of the second logic and unit 113A of each clock synchronization branch is set to 0, each clock synchronization branch 11 has no output, and the clock output end CLK_OUT_o of the clock switching circuit also has no output. After the reset pulse is canceled, the clock switching circuit can complete the clock switching after the cascaded register beats. That is to say, there is a time when the clock switching circuit has no output, and the time when the clock switching circuit has no output is the duration of the reset pulse and the beat time of the cascaded register. If the time is too long, it will seriously affect the normal operation of the chip using the clock switching circuit. In this embodiment, the reset pulse time is set to be less than 0.1 milliseconds, and the chip has a short time without clock, which has little impact on the normal operation of the chip, or does not affect the normal operation of the chip. The pulse generating unit 122 can be any circuit that can generate pulses, and this embodiment does not limit its specific structure.
[0053] Optionally, continue to refer to Figure 5 The clock exception processing module also includes an enable signal generating unit 121, and the source selection module 13 includes an abnormal source selection unit 131; the enable signal generating unit 121 is electrically connected to the control end of each clock source and the abnormal source selection unit 131, the enable signal generating unit 121 is used to generate an abnormal status signal in response to the clock loss indication signal, and the abnormal source selection unit 131 is used to output an enable signal to a clock synchronization branch corresponding to a clock source that has not lost a clock in response to the abnormal status signal.
[0054] Specifically, the enable signal generating unit 121 can modulate the clock loss indication signal into a signal that can drive the abnormal source selection unit 131, that is, modulate it into an abnormal state signal, such as performing amplitude modulation. The abnormal source selection unit 131 is electrically connected to each clock source, and the abnormal source selection unit 131 can detect the state of each clock source and the clock source corresponding to the clock currently output by the detection clock switching circuit. When receiving the abnormal state signal, a clock source that has not lost the clock can be selected according to the state of each other clock source, and an enable signal can be sent to the corresponding clock synchronization branch, while controlling the currently enabled clock synchronization branch to be disabled. For example, when the clock input by the first clock input terminal CLK_i[0] is lost, the abnormal source selection unit 131 outputs an enable signal, sets the second source selection enable terminal CLK_SEL[1] to 1, and the abnormal source selection unit 131 sets the first source selection enable terminal CLK_SEL[0] to 0.
[0055] Further, continue to refer to Figure 5 The source selection module 13 also includes a normal source selection unit 132, the input end of the normal source selection unit 132 is connected to the external source selection signal, the output end of the normal source selection unit 132 is electrically connected to the output end of the source selection module 13, the enable end of the normal source selection unit 132 is electrically connected to the output end of the enable signal generating unit 121, and the normal source selection unit 132 is used to shield its output in response to the abnormal state signal.
[0056] Specifically, the external source selection signal is, for example, the default source selection input of the user or chip, which configures the signal of the source selection enable terminal of each clock synchronization branch 11. For example, the first source selection enable terminal CLK_SEL[0] is 1 by default, and the second source selection enable terminal CLK_SEL[1] is 0. The user can complete the normal clock switching process by modifying the external source selection signal. When the clock source is lost, the user may not be aware of it. At this time, the external source selection signal remains as follows: the first source selection enable terminal CLK_SEL[0] is 1, and the second source selection enable terminal CLK_SEL[1] is 0. The normal source selection unit 132 is, for example, a switch. When the clock signal of the clock source is not lost, the switch is in the on state, and the external source selection signal can be input to the source selection enable terminal of each clock synchronization branch 11. When the normal source selection unit 132 receives an abnormal state signal, the switch is turned off, thereby preventing the external source selection signal from being input to each clock synchronization branch. Each clock synchronization branch can only receive the source selection signal output by the abnormal source selection unit 131, so as to avoid the source selection failure caused by the competition between the source selection signal output by the abnormal source selection unit 131 and the external source selection signal.
[0057] Optionally, continue to refer to Figure 5 The clock exception processing module 12 further includes a storage unit 123, which is electrically connected to each clock source and is used to record clock loss events.
[0058] Specifically, the storage unit 123 can record the start time of the clock source clock loss, etc., and the user can read the log in the storage unit 123 to analyze the status of the clock source. The storage unit 123 includes, for example, a high-speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices.
[0059] Optionally, in some embodiments, the clock source is an analog clock source, and the clock source is used to generate a clock signal and a clock loss indication signal. The clock switching circuit includes n clock sources, each of the n clock sources is electrically connected to the n clock synchronization branches in a one-to-one correspondence, and the n clock sources are electrically connected to the input end of the clock abnormality processing module.
[0060] Specifically, in this embodiment, the clock source itself can output a clock loss indication signal, so the clock abnormality processing module 12 can be directly electrically connected to the clock source, thereby directly acquiring the clock loss indication signal.
[0061] In some other embodiments, optionally, the clock switching circuit also includes a clock loss detection module, which is electrically connected to each clock source and the clock exception processing module. The clock loss detection module is used to detect the state of the clock source currently output by the clock switching circuit and generate a clock loss indication signal when the clock of the clock source is lost.
[0062] Furthermore, the clock switching circuit also includes n clock sources, the n clock sources are electrically connected to the n clock synchronization branches in a one-to-one correspondence, and the n clock sources are electrically connected to the clock loss detection module.
[0063] Specifically, in this embodiment, the clock source may be a clock source that does not have a clock loss detection function. The clock loss detection module may be used for detection, thereby providing a clock loss detection signal for each clock synchronization branch. In some optional implementations, the clock loss detection module is, for example, a sampling and counting circuit that samples and counts the clock signal output by the clock source. When the counting result changes, it indicates that the clock is lost.
[0064] For example, Figure 2 As shown, the first logic AND unit includes a first AND gate, the register includes a D flip-flop, the clock synchronization branch includes an inverter, and the output end of the last-stage register is electrically connected to the corresponding enable output end through the inverter.
[0065] Specifically, the D end of the D flip-flop is the input end of the register, and the Q end of the D flip-flop is the output end of the register. The inverter in the first clock synchronization branch 11A is the first inverter 114A, and the inverter in the second clock synchronization branch 11B is the second inverter 114B. The input end of the inverter is electrically connected to the output end of the last stage of the register, and the output end is electrically connected to the enable output end of the clock synchronization branch, so that the output signal of the cascaded register is inverted and output from the enable output end. In some other implementations, the enable output end may also be directly connected to the output end of the last stage of the D flip-flop. In addition, the output end of the logic or module 14 can be electrically connected to the clock output end of the clock switching circuit through a buffer.
[0066] The present invention further provides a clock chip, which includes the clock switching circuit provided by any embodiment of the present invention. Since the clock chip provided by the embodiment of the present invention includes the clock switching circuit provided by any embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.
[0067] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0068] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A clock switching circuit, characterized in that: The clock switching circuit comprises: n clock synchronization branches, a clock abnormality processing module, a source selection module and a logic OR module, wherein n≥2, and n is a positive integer; The clock synchronization branch is electrically connected to the source selection module, the clock exception processing module, the logic or module and the rest of the clock synchronization branches; the clock synchronization branch includes at least two stages of cascaded registers, and the clock synchronization branch is used to synchronize the input clock of its clock input end and then output it when enabled; The input end of the clock exception processing module is used to input the clock loss indication signal of the clock source currently output by the clock switching circuit, and the output end of the clock exception processing module is electrically connected to the control end of the source selection module; the clock exception processing module is used to respond to the clock loss indication signal, reset the registers of each of the clock synchronization circuits, and control the source selection module to output an enable signal to a clock synchronization branch corresponding to a clock source that has not lost the clock.
2. The clock switching circuit according to claim 1, characterized in that: The clock synchronization branch also includes a first logic AND unit and a second logic AND unit; the first input end of the first logic AND unit is electrically connected to the output end of the source selection module, and the n-1 second input ends of the first logic AND unit are electrically connected to the enable output ends of the remaining n-1 clock synchronization branches in a one-to-one correspondence; the output end of the first logic AND unit is electrically connected to the shift input end of the first-stage register; the clock end of the register is used to be electrically connected to the corresponding clock source, the reset end of the register is electrically connected to the output end of the clock exception processing module, the output end of the register of the last stage is electrically connected to the first input end of the second logic AND unit, and the output signal of the register of the last stage is inverted and output by the enable output end; the second input end of the second logic AND unit is used to be electrically connected to the corresponding clock source; The output terminal of the second logic AND unit is electrically connected to the input terminal of the logic OR module.
3. The clock switching circuit according to claim 1, characterized in that: The clock exception processing module includes a pulse generating unit, which is electrically connected to each of the clock sources and the reset end of the register; the pulse generating unit is used to generate a reset pulse in response to the clock loss indication signal to reset the register of each of the clock synchronization circuits; wherein the pulse width of the reset pulse is less than or equal to 0.1 milliseconds; and / or, The clock exception processing module includes a storage unit, which is electrically connected to each of the clock sources and is used to record clock loss events.
4. The clock switching circuit according to claim 1, characterized in that: The clock exception processing module further includes an enable signal generating unit, and the source selection module includes an abnormal source selection unit; The enable signal generating unit is electrically connected to the control end of each of the clock sources and the abnormal source selection unit. The enable signal generating unit is used to generate an abnormal status signal in response to the clock loss indication signal. The abnormal source selection unit is used to output an enable signal to a clock synchronization branch corresponding to a clock source that has not lost a clock in response to the abnormal status signal.
5. The clock switching circuit according to claim 4, characterized in that: The source selection module also includes a normal source selection unit, an input end of the normal source selection unit is connected to an external source selection signal, an output end of the normal source selection unit is electrically connected to an output end of the source selection module, an enable end of the normal source selection unit is electrically connected to an output end of the enable signal generating unit, and the normal source selection unit is used to shield its output in response to the abnormal state signal.
6. The clock switching circuit according to claim 1, characterized in that: The clock switching circuit also includes a clock loss detection module, which is electrically connected to each of the clock sources and the clock exception processing module. The clock loss detection module is used to detect the state of the clock source currently output by the clock switching circuit and generate the clock loss indication signal when the clock of the clock source is lost.
7. The clock switching circuit according to claim 6, characterized in that: The clock switching circuit also includes n clock sources, the n clock sources are electrically connected to the n clock synchronization branches in a one-to-one correspondence, and the n clock sources are electrically connected to the clock loss detection module.
8. The clock switching circuit according to claim 1, characterized in that: The clock switching circuit includes n clock sources, and the clock sources are used to generate clock signals and the clock loss indication signal; The n clock sources are electrically connected to the n clock synchronization branches in a one-to-one correspondence, and the n clock sources are electrically connected to the input end of the clock exception processing module.
9. The clock switching circuit according to claim 2, characterized in that: The first logic AND unit includes a first AND gate, and the register includes a D flip-flop; each of the clock synchronization branches includes an inverter, and the output end of the last-stage register is electrically connected to the corresponding enable output end through the inverter.
10. A clock chip, characterized in that: The clock chip comprises the clock switching circuit according to any one of claims 1-9.