Data processing system and integrated circuit device

Abstract

The invention provides a data processing system and an integrated circuit device. The data processing system has a data bus, a source node device located on the data bus, and a group of bus node devices located on the data bus. The source node device is configured to transmit a group read status command on the data bus. The bus node devices in the group are configured to sequentially respond to group read status commands by transmitting status data on the data bus in respective non-overlapping timing windows. The system may be a memory system.

Description

Technical Field

[0001] The technology provided herein relates to data processing systems, such as memory systems, and integrated circuit devices, and to sharing state data between elements of such systems. Background Art

[0002] Data processing systems may include multiple processing nodes linked to a communications network. These systems may execute programs arranged in a server / client configuration, where a server program transmits commands from one node in the network to other nodes on the network where client programs directed by the commands are to be executed. In some cases, the server program collects status data from nodes in the network for use in managing commands issued to various client programs.

[0003] For example, a memory system may include a memory controller device and a plurality of memory devices arranged in a bus topology. The memory controller device may include a bus master interface connected to a communication bus. A group of memory devices may have respective bus slave interfaces connected to the communication bus. The memory devices maintain status data about one or more status units on the devices. In order for the memory controller to access such status data, the memory controller issues a status read command to each of the devices on the communication bus. In response to the read status command, the memory device transmits the status data back to the memory controller on the communication bus.

[0004] For example, a memory system known as a solid-state disk (SSD) may include a memory controller and a plurality (e.g., 64) high-density NAND flash memory devices. Each of the NAND flash memory devices may include one or more state cells, each of which has a different state and is capable of performing a memory operation requested by the memory controller. The process of sequentially transmitting commands regarding the state to each of the plurality of NAND flash memory devices consumes a large amount of bus overhead, thereby reducing the data throughput of the memory system.

[0005] Therefore, the process for collecting status data in memory systems and other data processing systems may involve a large amount of read status timing overhead, and the overhead increases as the number of nodes on the communication network increases.

[0006] It is desirable to provide techniques for improving the efficiency of data processing systems including memory systems. Summary of the invention

[0007] A technique is described that can significantly reduce the communication overhead involved in retrieving status data from client nodes in a network including a bus topology network.

[0008] One aspect of the technology is a data processing system, the system comprising a data bus, a source node device located on the data bus, and a group of bus node devices located on the data bus. The source node device is configured to transmit a group read status command on the data bus. The bus node devices in the group are configured to respond to the group read status command in sequence by transmitting status data on the data bus in respective non-overlapping timing windows.

[0009] The technology can be applied in various network configurations. According to one configuration described herein, the data bus includes a set of bus signal lines. The group read status command is transmitted on a specific line in the set of bus signal lines, and the status data is transmitted on one or more specific lines of the same specific lines in the set of bus signal lines. According to another configuration described herein, the set of bus signal lines on the data bus includes a set of data lines and a set of separate command / address lines. The group read status command can be transmitted on the command / address line. In some embodiments, the source node device and the bus node device can transmit the group read status command and status data on the same command / address line.

[0010] According to another aspect of the technology described herein, for each bus node device, the status data includes a plurality of bits. For example, the bus node device may include a plurality of status units, each of which has a status such as a ready status and a busy status. The status data transmitted by the bus node device in this case may include the status of the plurality of status units of the bus node device.

[0011] Embodiments of the present technology may be implemented in which bus node devices each include a plurality of bonding pads connected to reference voltages (e.g., power supply lines and ground supply lines of a data bus) in different bonding patterns to provide local device addresses. The logic on the bus node device may use the local device address to determine a timing window for transmitting a local state onto the bus.

[0012] In aspects of the technology described herein, a bus node device includes an integrated circuit device. The integrated circuit device may include a bus interface for connecting to a data bus and circuits such as a status buffer for providing the status of resources on the integrated circuit device. For example, the integrated circuit device may include a high-density NAND flash memory device having a plurality of state cells. The status buffer or other status indicator may provide status data for each of the state cells in the plurality of state cells.

[0013] The integrated circuit device may include circuitry for providing a local device identifier (e.g., a local device address within a group on a bus). A command decoder on the integrated circuit device is communicatively coupled to the bus interface. The command decoder includes circuitry for detecting a group read status command associated with the initial device identifier. In response to detecting the group read status command, the integrated circuit device performs operations including:

[0014] a) comparing the initial device identifier with the local device identifier and, when they match, outputting status data to the data bus during the initial bus timing window, and when they do not match, disabling output to the data bus;

[0015] b) incrementing the initial device identifier to an incremented device identifier, comparing the local device identifier to the incremented device identifier, and outputting the state of the bus node to the data bus in a subsequent bus timing window when there is a match, and disabling the output to the data bus when there is a mismatch; and

[0016] c) Repeat step b) until the termination event occurs.

[0017] Furthermore, the operations may include outputting a conversion state to the bus during a conversion timing window of at least one of before the output state and after the output state.

[0018] Other aspects and advantages of the technology provided herein can be seen by reading the following drawings, detailed description and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a simplified block diagram of a data processing system configured for the group read state operations described herein.

[0020] Figure 2 is configured to be in Figure 1 A simplified block diagram of an integrated circuit device acting as a bus node in a system similar to the system shown.

[0021] Figure 3 is in conjunction with the bus read status operation described in this document Figure 2 The bus node shown is similar to a flow chart of operations performed in a bus node.

[0022] Figure 4 It is right Figure 2 The data bus shown is similar to the timing diagram of the group read state operation performed on the data bus.

[0023] Figure 5 is configured to be in Figure 1 A simplified block diagram of an integrated circuit memory device acting as a bus node in a system similar to the one shown, the integrated circuit memory device having multiple state cells and examples of different data bus configurations.

[0024] Figure 6 It is right Figure 5 The data bus shown is similar to the timing diagram of the group read state operation performed on the data bus.

[0025] Figure 7 is a simplified diagram of a circuit for providing a local device address on a bus node device suitable for use as described herein.

[0026] Description of Reference Numerals

[0027] 100: Source node device / source node

[0028] 110, 120: signal line / bus signal line

[0029] 111, 112, 113, 121, 122, 123: Bus node devices

[0030] 200, 500: Integrated circuit devices / devices

[0031] 201: Circuit

[0032] 210, 510: bus interface

[0033] 211: Bus signal line

[0034] 220: Local DA circuit / circuit

[0035] 230: Controller Logic

[0036] 231: Device address counter

[0037] 232: Multi-bit status register

[0038] 234: Command decoder

[0039] 300, 301, 302, 303, 305, 306, 311, 312, 315, 316, 317, 318, 319: Blocks / Steps 304, 310: Points

[0040] 350: Dashed box / initial window / window

[0041] 351: Dashed box / window

[0042] 400, WE#: write enable signal

[0043] 401, RE#: read enable signal

[0044] 402: Bus frequency DQS

[0045] 403: DA counter

[0046] 410, 411, 412, 700, DQS: Line

[0047] 501: Circuit

[0048] 511: Bus line

[0049] 520, 521, 522, 523, P[0], P[1], P[2], P[3]: plane

[0050] 710, 711, 712: pads

[0051] 721: Bus power VDD line / VDD line

[0052] 722: bus ground VSS line

[0053] CA[1:0]: Command / address line / command address status line

[0054] CA_CE#: Command / address line enable / command / address chip enable signal

[0055] CA_CLK: Command / address frequency

[0056] CE#: Chip enable signal

[0057] CMD: Fields

[0058] DA=1:Initial Device Address Field

[0059] I / O[7∶0]: data line / line

[0060] LDA, LDA1, LDA2, LDAm, LDAn: Local device address

[0061] t1, t2, t3, t4, t5, t6, t7, tn: time DETAILED DESCRIPTION

[0062] refer to Figures 1 to 7 A detailed description of embodiments of one or more aspects of the present technology is provided.

[0063] Figure 1 1 is a simplified diagram of a data processing system (e.g., a memory system) having a communication network utilizing a bus topology. The system includes a source node device 100 having a bus master interface for multiple buses (I / O bus 1 and I / O bus 2), each of which includes a set of bus signal lines 110, 120.

[0064] A first group of bus node devices 111, 112, ..., 113 are disposed on I / O bus 1. A second group of bus node devices 121, 122, ..., 123 are disposed on I / O bus 2. Bus node devices 111, 112, ..., 113 include a bus slave interface that reaches the bus signal line on I / O bus 1. Bus node devices 111, 112, ..., 113 each have a local device identifier, such as a device address that is unique relative to other bus node devices on the same bus. In this example, bus node devices 111, 112, ..., 113 have respective local device addresses LDA1, LDA2, LDAn, each of which is unique on I / O bus 1. Bus node devices 121, 122, ..., 123 include a bus slave interface that reaches the bus signal line on I / O bus 2. Each bus node device 121, 122, ..., 123 has a local device identifier, such as a device address that is unique relative to other bus node devices on the same bus. In this example, the bus node devices 121, 122, ..., 123 have respective local device addresses LDA1, LDA2, LDAm, each of which is unique on the I / O bus 2.

[0065] The source node device 100 includes group read status logic that performs operations to collect status data from bus node devices in Group 1 and Group 2. In this scenario, the source node device can be distinguished by having the logic act as the source of the group read status command. In this scenario, the bus node device can be distinguished by having logic that responds to the group read status command. There may be more than one source node device. In addition, the source node device may also include logic that acts as a bus node device in a system with multiple source nodes.

[0066] To collect status data from bus node devices in group 1, the group read status logic at the source node device 100 transmits a group read status command on signal line 110 of I / O bus 1. Bus node devices 111, 112, 113 respond with status data in respective non-overlapping timing windows. The group read status logic at the source node 100 links the status data with corresponding operations at a particular bus node device based on the timing window in which the status data was received.

[0067] Likewise, to collect status data from bus node devices in group 2, the group read status logic at the source node device 100 transmits a group read status command on signal line 120 of I / O bus 2. Bus node devices 121, 122, 123 respond with status data in respective non-overlapping timing windows. The group read status logic at the source node device 100 links the status data with corresponding operations at a particular bus node device based on the timing window in which the status data was received.

[0068] Figure 2 2 is a simplified block diagram of an integrated circuit device 200 configured to operate as a bus node device supporting group read state operations. The integrated circuit device 200 may be implemented on a single integrated circuit chip, or on multiple integrated circuit chips configured in a multi-chip package. The integrated circuit device 200 includes a circuit 201 for operation with more than one state, and thus may be characterized as a circuit with a state. Examples of the circuit 201 include a memory array, a computing circuit, an analog circuit system, etc. The circuit 201 may include one or more state cells each having a separate state. The state cells with states in this context may include separate physical circuits, such as separate planes of a memory array and separate elements on a so-called system-on-chip (SOC) device. In addition, the state cells with states in this context may include separate functions performed by circuit systems such as a microprocessor, a programmable logic gate array (FPGA), or other types of configurable circuits or programmable circuits.

[0069] The circuit 201 is connected for data communication with a bus interface 210 or other type of input / output I / O circuit. The bus interface 210 may be, for example, a reference Figure 1 The bus slave interface discussed. Bus interface 210 includes pins or other connection paths for linking to bus signal lines 211. In this example, the bus signal lines include bus control signals, such as chip enable CE#, write enable WE#, and read enable RE#. The bus signal lines also include data lines I / O[7:0]. In this example, there are eight data lines. In other embodiments, there may be different numbers of data lines and different types and numbers of control signal lines to suit a particular bus system configuration. The bus may include other signal lines not shown, such as bus frequency lines and bus power lines and bus ground lines.

[0070] The bus interface 210 is connected to the controller logic 230 on the integrated circuit device 200. In this example, the controller logic includes a device address counter 231, a multi-bit status register 232, and a command decoder 234. A local device address (LDA) circuit 220 connected to the control logic is provided to provide a local device address LDA. The local device address LDA is a device identifier that is unique relative to other bus node devices on the bus. The local DA circuit 220 may include a configuration register for the integrated circuit device 200. The configuration register may be implemented using a non-volatile memory cell or a one-time programmable memory cell. In some implementations, the local DA circuit 220 may be implemented using a register file, a static random access memory (SRAM), or other types of memory. In addition, the local DA circuit 220 may be implemented using multiple pads on the integrated circuit device 200, and the multiple pads are connected to reference voltages such as a bus power line and a bus ground line in a pattern that sets the local device address of the device 200. For example, see Figure 7 .

[0071] In response to the command decoder 234 detecting the group read status command, the controller logic 230 performs operations by which status data from the multi-bit status register 232 is transmitted to the bus via the bus interface 210 in a time window identified by the local device address indicated in the local DA circuit 220. In this way, the status data of the integrated circuit device 200 is provided in a time window that is unique relative to other bus node devices in the group. In some embodiments, the status data may be transmitted in a data packet without the bus node identifier, rather than in a timing window. In other embodiments, the status data may be transmitted in a data packet with the bus node identifier as part of the data packet.

[0072] Figure 3Flowchart of operations performed by controller logic 230 or other corresponding logic on other bus nodes in a group of bus nodes. The operations begin when a group read status command is detected (300). Then, an initial device identifier associated with the group read status command is loaded into the device address counter 231 (301). The initial device identifier may be associated with the group read status command by being immediate data in a data packet of the group read status command and received as an input at the bus interface. The circuit may store the initial device identifier to provide a local device identifier, for example, by loading the received input into a counter register in the device address counter 231. Alternatively, the initial device identifier may be a static value associated with the group read command by logic at the bus node device and may be provided by the circuit to provide a local device identifier. For example, the initial device identifier may be provided by setting the counter register in the device address counter 231 to a preset value (e.g., 000 or 111) used as the initial device identifier using a counter reset when a group read command is detected.

[0073] After loading the initial device identifier, the logic compares the local device address LDA provided by the circuit 220 with the output of the device address counter 231 (302). Next, it is determined whether the comparison of the local device address LDA provided by the circuit 220 with the output of the device address counter 231 matches (303). If so, the flow proceeds to point 304, and the logic controller then outputs a status packet (305) followed by a transition packet (306). If there is no match at block 303, the flow proceeds to point 310, and the logic controller disables the output on the bus (311), while the matching node outputs the status packet as indicated by block 305, and disables the output on the bus (312), while the matching node outputs the transition packet as indicated by block 306.

[0074] The conversion interval occurs between the timing windows when one of the bus nodes transmits status data on the bus. When the conversion interval occurs, the controller logic outputs the conversion state on the bus (306, 318). In the conversion state, the node outputs a fixed voltage or fixed data to avoid bus contention problems between the matching tube core in the previous cycle and the matching tube core in the next cycle. The frequency signals received by the two tube cores may have overlapping cycles, and if the two tube cores output different data, there may be bus contention problems. Therefore, during the conversion cycle, fixed data is output for the two tube cores (the same data pattern or voltage is output for the two tube cores) to avoid bus contention. The conversion state is output at the end of the state output of the matching tube core of the current cycle and at the beginning of the state output of the matching tube core of the next cycle. The unmatched tube core can disable the corresponding bus driver by setting a high impedance state.

[0075] After step 306 or step 312, in this example, the DA counter is raised by incrementing the counter (315). The logic then compares the local device address LDA provided by circuit 220 with the output of the device address counter 231 (316). Next, it is determined whether the comparison of the local device address LDA provided by circuit 220 with the output of the device address counter 231 matches (317). If so, the logic controller outputs an output conversion packet that matches the output conversion packet of the previous matching node. After block 318, the operation then loops back to point 304 to output the status packet. If not matched at block 317, the logic controller disables the output on the bus (319) and then loops back to point 310 to continue disabling the output.

[0076] As shown, the operation includes a bus timing window for outputting a status packet (dashed line frame 350 ) and a bus timing window for outputting a transition packet (dashed line frame 351 ).

[0077] If a command termination event (not shown) occurs, the operation is terminated. The command termination event may include a transition of a control signal such as the chip enable CE# control signal. Some alternative examples of command termination events may be overflow of the device address counter 231, cessation of toggling of the read enable signal, and expiration of a timeout interval.

[0078] Figure 3 The operations shown are:

[0079] a) comparing the initial device identifier to the local device identifier and, when they match, outputting status data to the data bus (305) during an initial bus timing window (initial window 350), and when they do not match, disabling output to the data bus;

[0080] b) upgrading the initial device identifier to an advanced device identifier, comparing the local device identifier with the advanced device identifier, and when a match is found, outputting the state data of the bus node to the data bus in a subsequent timing window (subsequent window 350) (305), and when a match is found, disabling the output to the data bus;

[0081] c) Repeat step b).

[0082] also, Figure 3 The operations shown include outputting a transition state (306, 318) to a bus during a transition timing window (window 351) at least one of before the output state and after the output state.

[0083] Figure 3 The flowchart of shows the logic executed by the memory controller or other bus node device. The logic can be implemented as follows: using a processor programmed by a computer program, the computer program is stored in a memory accessible by a computer system and can be executed by the processor; by dedicated logic hardware including field programmable integrated circuits; and by a combination of dedicated logic hardware and computer programs. It should be understood that many steps can be combined, performed in parallel, or performed in a different order without affecting the functions achieved. In some cases, as the reader should understand, the rearrangement of steps will achieve the same result only if certain other changes are made. In other cases, as the reader should understand, the rearrangement of steps will achieve the same result only if certain conditions are met. In addition, it should be understood that the flowcharts herein only show steps related to understanding the technology provided, and it should also be understood that many additional steps for achieving other functions can be performed before, after, and between the steps shown.

[0084] Figure 4 During a group read status operation Figure 2 4:0] and the outputs of the Die 1 node and the Die 2 node on the I / O[7:0] line are set to a high impedance state (High Z) during the interval indicated by the dashed lines.

[0085] As shown, the source node transmits a group read status command packet including a CMD field and an initial device address field DA=1. At time t1, after the switching of WE#, the bus node loads the initial device address into the counter. At time t2, the bus node prepares its output for transmitting status data, and RE# begins to switch and continues to switch until the operation is completed. In addition, the DQS signal switches in coordination with the data transmitted by the bus node. At time t3, the bus node shown on line 411 outputs the status packet received at the source node on line 410 on the bus. The status packet timing window ends at time t4. The bus node performs a conversion interval between time t4 and time t6, and the address counter on the bus node increments. At time t6, the bus node shown on line 412 outputs the status packet received at the source node on the bus. The timing window of the status packet ends at time t7. Thereafter, a transition interval is executed by the bus node and a counter in the bus node is incremented, and this process continues until a termination event occurs, at which time all bus nodes in the group of bus nodes on a given bus have transmitted status data to the source node. An example of a termination event may be a control signal on the bus changing from a toggled state to a stable state. For example, during a group read state operation, the source node may toggle the read enable signal RE#, and the termination event may be ceasing to toggle the read enable signal.

[0086] As shown, the source node transmits a group read status command on data lines I / O[7:0], and the status packet includes a plurality of bits, and the bus node transmits the status packet on one or more of the same data lines I / O[7:0].

[0087] Figure 5 Shown with Figure 2 Another integrated circuit device 500 is similar to the integrated circuit device shown but has a different bus interface. In addition, the circuit 501 is used in an operation with more than one state and can therefore be characterized as having Figure 5 The circuit for determining the state in the integrated circuit device 500 is a memory (e.g., NAND flash memory). The memory has multiple planes (520, 521, 522, 523) labeled P[3:0]. In some embodiments, each plane is a separate state unit of the device 500. Figure 2 Components similar to those of the illustrated device are assigned the same reference numerals. Integrated circuit device 500 has a different bus interface 510. As shown, bus interface 510 has a connection path to bus lines 511, which includes CA_CE# (command / address line enable), CA[1:0] (command / address line), CA_CLK (command / address clock), RE# (read enable), and I / O[7:0] (data line).

[0088] Figure 6 During a group read status operation Figure 5 1. A timing diagram of signals on the bus shown. The illustrated bus signals include command / address chip enable CA_CE#, command / address frequency CA_CLK, and command / address lines CA[0] and CA[1]. The separate data line I / O[7:0] is not shown and is not used in this example. In other examples, the data line I / O[7:0] may be used to carry a status packet or other data associated with a group read status operation. The group read status operation begins when the CA_CE# signal switches at time t1 and terminates at time tn. Between time t2 and time t3, CA_CLK switches at a first frequency speed, and the source node outputs a group read status command and device address on the command address status lines CA[0] and CA[1]. In this example, the group read status command includes a two-bit header and four bits on each row, followed by a two-bit header and device address.

[0089] At time t4, the CA output write header is output on the CA[1:0] line to start the output sequence. CA_CLK begins switching at the second clock rate. There are three frequency cycles in this example to output the state of each node. The first two frequency cycles are state output cycles that carry 4 state bits, with one frequency cycle applied to each plane of the CA[1] line. The third frequency cycle corresponds to a transition interval in which the current node outputs the same voltage as the next node to prevent bus contention. As shown, there is a delay from the CA_CLK rising edge and the CA_CLK falling edge to the data output at each node. Therefore, as shown, during the timing window between t5 and t6, the status packet from device D0 is transmitted on the CA[1:0] line. During the timing window between t6 and t7, the status packet from device D1 is transmitted on the CA[1:0] line, and so on, until the termination event at time tn (indicated by the CA_CE# signal transitioning to a high value).

[0090] As seen in this example, the Group Read Status Command is sent by the source node on a specific line (which in this example is the CA[1:0] line), and the Status Packet is sent by the bus node on a specific one of the same CA[1:0] lines (CA[1]). In other embodiments, both of the CA[1:0] lines may be used for the Status Packet. In other embodiments, the I / O[7:0] lines may be used for one or both of the Command and Status Packets.

[0091] exist Figure 2 and Figure 5In an embodiment of the present invention, each bus node has circuitry for providing a local device address LDA that is unique with respect to other bus nodes on the bus. Figure 7 is a schematic diagram showing a circuit suitable for such use. Each bus node may include an integrated circuit having a plurality of pads (e.g., pads 710, 711, 712). Reference voltage sources such as a bus power VDD line 721 and a bus ground VSS line 722 are connected to the plurality of pads in a pattern that is unique relative to other bus nodes on the same bus. In this example, pad 710 and pad 712 are connected to VDD line 721, and pad 711 is connected to the VSS line. This sets the local device address LDA to 101b, and the local device address LDA is provided on line 700 to logic on the device for assigning a timing window for transmitting status data on the bus in a group read status operation. In one example, such as Figure 5 The multiple memory devices shown can be mounted in a multi-chip package, and the pads on each device can be wire bonded in a unique pattern. For an eight device package, pads [2:0] of device 0 are wire bonded to ground which sets the local device address to 000b. Pads [2:0] of device 1 are wire bonded to 001b, ..., and pads [2:0] of device 7 are wire bonded to 111b.

[0092] Although the present invention is disclosed by reference to preferred embodiments and the examples described in detail above, it should be understood that these examples are intended to be illustrative only and not to have a limiting meaning. Those skilled in the art will easily think of various modifications and combinations, as long as these modifications and combinations fall within the spirit of the present invention and the scope of the appended claims.

Claims

1. A data processing system, comprising: Data bus; a source node device located on the data bus, the source node device being configured to transmit a group read status command on the data bus; as well as A group of bus node devices are located on the data bus, the bus node devices in the group being configured to respond sequentially to the group read status command by transmitting status data on the data bus in respective non-overlapping timing windows.

2. The data processing system according to claim 1, wherein the data bus includes a set of input / output signal lines, the group read status command is issued on a specific line in the set of input / output signal lines, and the status data is transmitted sequentially on one or more specific lines in the specific lines in the set of input / output signal lines.

3. The data processing system of claim 1, wherein the data bus includes a set of data lines and a separate set of command / address lines, and the group read status command is issued on the set of command / address lines.

4. A data processing system according to claim 1, wherein the data bus includes a group of data lines connected to the bus node devices in the group and a separate group of command / address lines, and the group read status command is issued on the group of command / address lines, and the status data is transmitted sequentially on the group of command / address lines.

5. A data processing system according to claim 1, wherein at least one bus node device in the group of bus node devices has multiple status units, and wherein the status data transmitted sequentially includes the ready / busy status of the multiple status units of the at least one bus node device in the group. 6 . The data processing system of claim 1 , wherein the bus node devices in the group respectively include a plurality of bonding pads connected to a reference voltage in different bonding patterns to provide a local device address.

7. The data processing system of claim 1 , wherein the bus node devices in the group each comprise an integrated circuit device, the integrated circuit device comprising: A bus interface, used for connecting to the data bus; circuitry for providing a status of a resource on the integrated circuit device; Circuitry for providing a local device identifier; as well as A command decoder in communication with the bus interface is configured to detect a group read status command associated with an initial device identifier and, in response to detecting the group read status command, perform operations including: a) comparing the initial device identifier with the local device identifier and, when they match, outputting the status data to the data bus during an initial bus timing window, and when they do not match, disabling output to the data bus; b) upgrading the initial device identifier to an advanced device identifier, comparing the local device identifier with the advanced device identifier, and when they match, outputting the status data of the bus node device to the data bus in a subsequent timing window, and when they do not match, disabling the output to the data bus; c) Repeat step b).

8. The data processing system of claim 7, wherein the operation comprises outputting a conversion status to the data bus during a conversion timing window at least one of before outputting the status data and after outputting the status data.

9. The data processing system of claim 7 , wherein the integrated circuit device of one or more of the bus node devices comprises a circuit having a plurality of status units, and wherein the status data of the bus node device comprises a ready / busy status of the plurality of status units.

10. The data processing system of claim 7, wherein the integrated circuit device comprises a memory having a plurality of status cells, and wherein the status data of the bus node device comprises ready / busy states of the plurality of status cells.

11. An integrated circuit device comprising: A bus interface for connecting to a data bus; circuitry for providing status data of resources on the integrated circuit device; Circuitry for providing a local device identifier; as well as A command decoder in communication with the bus interface is configured to detect a group read status command associated with an initial device identifier and, in response to detecting the group read status command, perform operations including: a) comparing the initial device identifier with the local device identifier and, when they match, outputting the status data to the data bus during an initial bus timing window, and when they do not match, disabling output to the data bus; b) upgrading the initial device identifier to an advanced device identifier, comparing the local device identifier with the advanced device identifier, and when they match, outputting the status data to the data bus in a subsequent bus timing window, and when they do not match, disabling the output to the data bus; c) Repeat step b).

12. The integrated circuit device according to claim 11, wherein the operation comprises outputting a conversion status to the bus during a conversion timing window at least one of before outputting the status data and after outputting the status data.

13. An integrated circuit device according to claim 11, wherein the bus interface includes a set of input / output signal lines, the group read status command is received on a specific line in the set of input / output signal lines, and the status output data is transmitted on one or more specific lines in the specific lines in the set of input / output signal lines.

14. The integrated circuit device of claim 11, wherein the bus interface comprises a set of data lines and a separate set of command / address lines, and the group read status command is received on the set of command / address lines.

15. The integrated circuit device of claim 11, wherein the bus interface comprises a set of data lines and a separate set of command / address lines, and the group read status command is received on the set of command / address lines and the status output data is transmitted on the set of command / address lines.

16. The integrated circuit device according to claim 11, wherein the circuit for providing the local device identifier comprises a plurality of bonding pads connected to an external voltage in a bonding pattern.

17. The integrated circuit device according to claim 11, wherein the circuit for providing a local device identifier comprises a register.

18. The integrated circuit device according to claim 11, comprising a circuit having one or more status cells, and wherein the status data of the integrated circuit device comprises a ready / busy status of the one or more status cells.

19. The integrated circuit device according to claim 11, comprising a memory having one or more status cells, and wherein the status data of the integrated circuit device comprises a ready / busy status of the one or more status cells.

20. The integrated circuit device according to claim 19, wherein the memory is a NAND flash memory.

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