Dma controller, chip, root complex and endpoint device

Abstract

The application discloses a DMA controller, a chip, a root complex and an endpoint device, and belongs to the field of communication. The DMA controller provided by the application is applied to RC or EP, and comprises an acquisition module and a control module. The acquisition module is used for acquiring DMA control information from a target processor, wherein the DMA control information comprises information of a target memory, and the information of the target memory is used for indicating a storage position of a description character chain table. The acquisition module is further used for determining the target memory according to the DMA control information, and acquiring description character information in the description character chain table from the target memory, wherein the target memory comprises an RC memory or an EP memory. The control module is used for performing data transmission between the RC memory and the EP memory according to the description character information in the description character chain table. The DMA controller provided by the application can be applied to RC and EP, has multiplexing, and solves the problem of single application scene of the DMA controller in the related art.

Description

Technical Field

[0001] This application belongs to the field of communications, specifically relating to a DMA controller, chip, root complex, and endpoint device. Background Technology

[0002] In the field of communications, communication devices such as 5G and 4G support both RC (Root Complex) mode (master mode) and EP (End Point) mode (slave mode) of the PCIe (Peripheral Component Interconnect Express) high-speed interface. In RC mode, the communication device can act as a master device to connect external expansion devices, while in EP mode, the communication device can act as a slave device to connect to a host computer.

[0003] In related technologies, in RC mode, the communication device can act as a master device and use a DMA (Direct Memory Access) controller to transmit data, thereby improving the data transmission rate between the communication device and external expansion devices. Alternatively, in EP mode, the communication device can act as a slave device and use a different DMA controller to transmit data, thereby improving the data transmission rate between the communication device and the host computer.

[0004] However, existing DMA controllers cannot be used in communication devices that support multiple modes (such as simultaneously supporting RC and EP modes), resulting in a limited range of application scenarios for DMA controllers in related technologies. Summary of the Invention

[0005] This application provides a DMA controller, chip, root complex, and endpoint device, which can solve the problem of the limited application scenarios of DMA controllers in related technologies.

[0006] In a first aspect, embodiments of this application provide a DMA controller, which is applied to a root complex RC or an endpoint device EP, and the DMA controller includes: an acquisition module and a control module;

[0007] The acquisition module is used to acquire DMA control information from the target processor. The DMA control information includes information about the target memory, which is used to indicate the storage location of the character linked list.

[0008] The acquisition module is further configured to determine the target memory based on the DMA control information, and acquire the description character information in the description character linked list from the target memory, wherein the target memory includes an RC memory or an EP memory;

[0009] The control module is used to perform data transmission between the RC memory and the EP memory according to the description character information in the description character linked list.

[0010] Secondly, embodiments of this application provide a chip, including: a processor, a memory, and a DMA controller as described in the first aspect, wherein the processor is connected to the memory and the DMA controller respectively, and the memory is connected to the DMA controller.

[0011] Thirdly, embodiments of this application provide a root complex, including: an RC processor, an RC memory, a DMA controller as described in the first aspect, and a first PCIe controller;

[0012] The RC processor is connected to the RC memory and the DMA controller respectively. The RC memory is connected to the DMA controller, and the DMA controller is connected to the first PCIe controller.

[0013] Fourthly, embodiments of this application provide an endpoint device, including: an EP processor, an EP memory, a DMA controller as described in the first aspect, and a second PCIe controller;

[0014] The EP processor is connected to the EP memory and the DMA controller respectively. The EP memory is connected to the DMA controller, and the DMA controller is connected to the second PCIe controller.

[0015] In this embodiment, the DMA controller includes an acquisition module and a control module. The acquisition module acquires DMA control information from the target processor, including information about the target memory, which indicates the storage location of the descriptive character list. The acquisition module also determines the target memory based on the DMA control information and acquires descriptive character information from the descriptive character list in the target memory, which may include an RC memory or an EP memory. The control module performs data transfer between the RC memory and the EP memory based on the descriptive character information in the descriptive character list. Thus, the DMA controller can determine the storage location of the descriptive character list based on the DMA control information from the target processor. Furthermore, the DMA controller can acquire the descriptive character information by accessing local memory or the peer memory, depending on the storage location of the descriptive character list. This allows the DMA controller to switch the direction of reading descriptive character information, enabling it to be used for both RC and EP, thus solving the problem of limited application scenarios for DMA controllers in related technologies. Attached Figure Description

[0016] Figure 1This is a schematic structural diagram of a DMA controller provided in an embodiment of this application;

[0017] Figure 2 This is a schematic structural diagram of another DMA controller provided in an embodiment of this application;

[0018] Figure 3 This is a schematic structural diagram of another DMA controller provided in an embodiment of this application;

[0019] Figure 4 This is a schematic structural diagram of another DMA controller provided in an embodiment of this application;

[0020] Figure 5 This is a schematic diagram illustrating the storage of a character linked list in a non-contiguous storage space of the target memory, as provided in the embodiments of this application.

[0021] Figure 6 This is a schematic structural diagram of a chip provided in an embodiment of this application;

[0022] Figure 7 This is a schematic diagram illustrating data transmission between a root complex and an endpoint device, as provided in an embodiment of this application.

[0023] Figure 8 This is a schematic diagram illustrating data transmission between a root complex and an endpoint device, as provided in an embodiment of this application.

[0024] Explanation of reference numerals in the attached figures:

[0025] 100 - DMA controller; 110 - Acquisition module; 120 - Control module; 1201 - Parsing module; 1202 - Data channel control module; 130 - Status write-back module; 140 - Interrupt reporting module. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0027] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0028] The applicant noted that, in the relevant technologies, existing DMA controllers cannot be used in communication devices that support multiple modes (such as simultaneously supporting RC mode and EP mode), resulting in the problem of limited application scenarios for DMA controllers.

[0029] Based on this, embodiments of this application provide a DMA controller. The DMA controller can determine the storage location of the description character linked list based on DMA control information from the target processor. Then, the DMA controller can acquire the description character information by accessing local memory or accessing peer memory based on the storage location of the description character linked list. It can switch the direction of reading description character information by the DMA controller, so that the DMA controller can be used for both RC and EP. Compared with related technologies, the DMA controller has reusability and solves the problem of the single application scenario of the DMA controller in related technologies.

[0030] The DMA controller, chip, root complex, and endpoint device provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0031] Figure 1 This is a schematic structural diagram of a DMA controller provided in an embodiment of this application.

[0032] like Figure 1 As shown, the DMA controller 100 provided in this application embodiment is applied to RC or EP and may include: an acquisition module 110 and a control module 120;

[0033] The acquisition module 110 is used to acquire DMA control information from the target processor. The DMA control information includes information about the target memory, which is used to indicate the storage location of the character linked list.

[0034] The acquisition module 110 is further configured to determine the target memory based on the DMA control information, and acquire the description character information in the description character linked list from the target memory, wherein the target memory includes an RC memory or an EP memory;

[0035] The control module 120 is used to perform data transmission between the RC memory and the EP memory according to the description character information in the description character linked list.

[0036] In the embodiments of this application, the target processor can be an RC processor or an EP processor, and this application does not impose any specific limitations.

[0037] For example, when a DMA controller is applied to an RC (Regulator-Controller), the target processor can be the RC processor, which is the local processor. The RC processor communicates with the DMA controller via the AXI bus, and the DMA controller's acquisition module can obtain DMA control information from the RC processor through the AXI bus. Alternatively, when a DMA controller is applied to an RC, the target processor can also be an EP (External Processor), which is the peer processor. The EP processor communicates with the DMA controller via the PCIe bus, and the DMA controller's acquisition module can obtain DMA control information from the EP processor through the PCIe bus.

[0038] For example, when the DMA controller is applied to the EP (Extended Processor), the target processor can be the RC (Remote Processor). In this case, the RC processor is the peer processor, and the RC processor and the DMA controller communicate via the PCIe bus. The DMA controller's acquisition module can obtain DMA control information from the RC processor through the PCIe bus. Alternatively, when the DMA controller is applied to the EP, the target processor can also be the EP processor. In this case, the EP processor is the local processor, and the EP processor and the DMA controller communicate via the AXI (Automatic Input / Output) bus. The DMA controller's acquisition module can obtain DMA control information from the EP processor through the AXI bus.

[0039] In this embodiment, the DMA control information can be configuration information pre-set by the target processor to control how the DMA controller operates. For example, the DMA control information may include information about the target memory, which indicates the storage location of the descriptive character list. The target memory can be RC memory or EP memory. The descriptive character list includes at least one descriptive character, which can be used to indicate the relevant control parameters for the DMA controller to move data.

[0040] In practical applications, DMA control information may also include other information such as DMA enable information and doorbell information to instruct the DMA controller to start working. This application does not impose specific limitations on these information.

[0041] In this embodiment, when the DMA controller is applied to the RC, the target memory can be the RC memory. In this case, the RC memory is a local memory, and the RC memory communicates with the DMA controller via an AXI bus. The DMA controller's acquisition module can retrieve description character information from the description character list in the RC memory via the AXI bus. Alternatively, when the DMA controller is applied to the RC, the target memory can also be an EP memory. In this case, the EP memory is the peer memory, and the EP memory communicates with the DMA controller via a PCIe bus. The DMA controller's acquisition module can retrieve description character information from the description character list in the EP memory via the PCIe bus.

[0042] In this embodiment, when the DMA controller is applied to the EP, the target memory can be an RC memory. In this case, the RC memory is the peer memory, and the RC memory and the DMA controller communicate via a PCIe bus. The DMA controller's acquisition module can retrieve description character information from the description character list in the RC memory via the PCIe bus. Alternatively, when the DMA controller is applied to the EP, the target memory can also be the EP memory. In this case, the EP memory is local memory, and the EP memory and the DMA controller communicate via an AXI bus. The DMA controller's acquisition module can retrieve description character information from the description character list in the EP memory via the AXI bus.

[0043] It is understood that, in this embodiment of the application, the target processor pre-configures DMA control information for the DMA controller, informing the DMA controller of the storage location of the description character linked list. Subsequently, the DMA controller can acquire the description character information by accessing the local memory via an AXI link or the peer memory via a PCIe link, based on the storage location of the description character linked list. This improves the flexibility of the target processor in controlling the DMA controller, enables switching the direction in which the DMA controller reads the description character information, and broadens the application scenarios of the DMA controller, allowing it to be used for both RC and EP.

[0044] Especially for communication devices compatible with both RC and EP modes, related technologies require the design of two different DMA controllers for RC and EP modes. However, the DMA controller provided in this application can be used in both RC and EP modes of the communication device, exhibiting reusability. Compared with related technologies, this broadens the application scenarios of the DMA controller and reduces the cost of the DMA controller in the communication device, thus solving the problem of the limited application scenarios of the DMA controller in related technologies.

[0045] According to the DMA controller provided in the embodiments of this application, the DMA controller includes an acquisition module and a control module. The acquisition module is used to acquire DMA control information from the target processor. The DMA control information includes information about the target memory, which indicates the storage location of the description character list. The acquisition module is also used to determine the target memory based on the DMA control information and to acquire description character information from the description character list in the target memory. The target memory includes an RC memory or an EP memory. The control module is used to perform data transfer between the RC memory and the EP memory based on the description character information in the description character list. In this way, the DMA controller can determine the storage location of the description character list based on the DMA control information from the target processor. Then, the DMA controller can acquire the description character information by accessing local memory or accessing the peer memory, depending on the storage location of the description character list. This allows the DMA controller to switch the direction of reading description character information, enabling it to be used for both RC and EP, thus solving the problem of the limited application scenarios of DMA controllers in related technologies.

[0046] Figure 2 This is a schematic structural diagram of another DMA controller provided in the embodiments of this application.

[0047] In a specific embodiment, such as Figure 2 As shown, in the DMA controller 100 provided in this application embodiment,

[0048] The control module 120 may include a parsing module 1201 and a data channel control module 1202;

[0049] The parsing module 1201 is used to extract the description character information, convert the description character information into data transport information in the target instruction format, and transmit the data transport information to the data channel control module;

[0050] The data channel control module 1202 is used to perform data transmission between the RC memory and the EP memory according to the data transfer information.

[0051] The data channel control module 1202 can be a data channel controller, and the target instruction format can be the instruction required by the data channel controller. For example, when the amount of descriptive character information is large, the parsing module 1201 can decompose the descriptive character information, extract the information required by the data channel controller from the descriptive character information, and convert it into data transfer information required by the data channel controller, so that the data channel controller can perform data transfer between the RC memory and the EP memory according to the data transfer information.

[0052] For example, in embodiments of this application, the descriptive character information may include at least one of data descriptive characters, status descriptive characters, and chain connection descriptive characters.

[0053] The data description character can be used to store the source address, destination address, and data block length of the DMA-transferred data.

[0054] The status description character can be used to store the DMA execution result. Physically, it is stored in the same location as the corresponding data description character (i.e., it overwrites the original data description character). This storage space can be reclaimed after the specified processor has finished reading the status description character.

[0055] Among them, the chain connection description character can be used to connect the description characters stored in discrete storage space, so as to realize the non-contiguous storage of description characters in storage space.

[0056] The description character information extracted by the parsing module 1201 is the data description character, which may contain the source address information of the data to be transferred, the destination address information of the data to be transferred, and the data volume information of the data to be transferred.

[0057] The parsing module can be used to extract the data description characters in the description character information, convert the source address information, destination address information, and data volume information of the data to be transferred in the data description characters into data transfer information in the target instruction format, and transmit the data transfer information to the data channel control module.

[0058] For example, Table 1 below is a schematic data structure diagram of the data description character:

[0059]

[0060] Table 1

[0061] The data description characters can include 6 double words (DW), each double word being 32 bits in size.

[0062] The “DAR Low” field in the first double word and the “DAR High” field in the second double word can represent the destination address information of the data to be transferred.

[0063] The “SAR Low” field in the third double word and the “SAR High” field in the fourth double word can represent the source address information of the data to be transferred.

[0064] The "Transfer Size" field in the fifth double character indicates the amount of data to be transferred.

[0065] The sixth double word is divided into 7 fields, including the "Stop" field, which indicates the order of this data description character in the character list. For example, a "Stop" field of "0" indicates that this data description character is not the last data description character in the character list. A "Stop" field of "1" indicates that this data description character is the last data description character in the character list, and after executing this data description character, a DMA completion interrupt information needs to be reported to the designated processor.

[0066] The “Reserve” field indicates that this field is a reserved field.

[0067] The "LLP" field indicates the type of this data description character. For example, an "LLP" field of "1" indicates that the type of this description character is a chain concatenation description character, while an "LLP" field of "0" indicates that the type of this description character is a data description character or a status description character.

[0068] The "LIE" field indicates the direction of interrupt reporting. For example, a "LIE" field of "1" indicates that the interrupt information needs to be reported to the local processor, while a "LIE" field of "0" indicates that the interrupt information does not need to be reported to the local processor.

[0069] The "RIE" field can also indicate the direction of interrupt reporting. For example, a "RIE" field of "1" indicates that the interrupt information needs to be reported to the peer processor, while a "RIE" field of "0" indicates that the interrupt information does not need to be reported to the peer processor.

[0070] The "OWN" field indicates whether the description character has been executed. For example, an "OWN" value of "1" indicates that it has not been executed, and "0" indicates that it has been executed. Generally, the "OWN" field in the data description character is "1", while the "OWN" field in the status description character is "0".

[0071] Thus, taking the structure of the data description characters shown in Table 1 as an example, the parsing module can be used to extract the data description characters from the description character information, extract the information from the "SAR Low", "SAR High", "DAR Low", "DAR High" and "Transfer Size" fields in the data description characters, convert it into data transfer information in the target instruction format, and transmit the data transfer information to the data channel control module so that the data channel control module can perform data transfer between the RC memory and the EP memory according to the data transfer information.

[0072] Figure 3 This is a schematic structural diagram of another DMA controller provided in the embodiments of this application.

[0073] In a specific embodiment, such as Figure 3 As shown, in the DMA controller 100 provided in this application embodiment, the data channel control module 1201 is further configured to generate DMA execution results after data transfer between the RC memory and the EP memory; the DMA execution results include status information reflecting the DMA controller's transmission of the data to be transferred;

[0074] For example, the DMA execution result may indicate that the DMA controller has successfully transferred the data to be transferred, or it may indicate that the DMA controller has failed to transfer the data to be transferred, or it may indicate the type of failure of the DMA controller in transferring the data to be transferred, etc. This application does not limit the specific content of the DMA execution result.

[0075] like Figure 3 As shown, the DMA controller 100 provided in this application embodiment also includes a status write-back module 130;

[0076] The status write-back module 130 is used to obtain the DMA execution result from the data channel control module, and generate a status description character corresponding to the data description character based on the DMA execution result;

[0077] The status write-back module 130 is also used to transmit the status description character to the target memory so that the target memory stores the status description character in a manner that overwrites the data description character.

[0078] For example, Table 2 below is a schematic data structure diagram of the status description characters:

[0079]

[0080] Table 2

[0081] The difference between the status description characters shown in Table 2 and those shown in Table 1 is as follows:

[0082] In the "Reserve" field of the sixth double word (bits 6-31), two fields are redefined: the "SEC" field and the "Error Type" field.

[0083] The “SEC” and “Error Type” fields are used to indicate the DMA execution result.

[0084] The "SEC" field indicates whether the DMA controller successfully transferred the data. For example, "SEC" of "1" indicates success, and "SEC" of "0" indicates failure.

[0085] The "Error Type" field indicates the type of failure in which the DMA controller failed to transfer the data to be moved. This application does not impose any restrictions on the specific failure type.

[0086] Thus, taking the structure of the status description characters shown in Table 2 as an example, during the process of the status write-back module 130 generating the status description characters corresponding to the data description characters, the status write-back module 130 can write the "OWN" field as "0" to indicate that this data description character has been executed, and write the corresponding content in the "SEC" field and the "Error Type" field according to the DMA execution result.

[0087] In another specific embodiment, after all data description characters in the description character list have been executed, the DMA controller can also report DMA completion interrupt information to the designated processor, so that the designated processor can retrieve the status description characters from the target memory and determine the DMA execution result based on the status description characters. An example is given below:

[0088] In this embodiment of the application, the description character chain includes a target data description character, which is the last data description character in the description character chain. The target data description character includes configuration information for indicating the direction of interrupt reporting.

[0089] For example, taking the structure of the data description characters shown in Table 1 as an example, the "Stop" field of the target data description character is "1", indicating that the target data description character is the last data description character in the description character linked list. The configuration information contained in the target data description character for indicating the direction of interruption reporting can be stored in the "LIE" field and / or the "RIE" field.

[0090] like Figure 4 As shown, the DMA controller 100 provided in this application embodiment may further include: an interrupt control module 140;

[0091] The interrupt control module 140 can be used to determine the designated processor according to the configuration information in the target data description character that indicates the interrupt reporting direction, and report the DMA completion interrupt information to the designated processor, so that the designated processor can obtain the status description character from the target memory and determine the DMA execution result according to the status description character.

[0092] The configuration information used to indicate the direction of interrupt reporting includes: first configuration information and / or second configuration information; the first configuration information is used to indicate that the specified processor includes the local processor; the second configuration information is used to indicate that the specified processor includes the peer processor.

[0093] Taking the data description character structure shown in Table 1 as an example, the first configuration information can be stored in the "LIE" field, and the second configuration information can be stored in the "RIE" field. For example, a "LIE" field of "1" indicates that the DMA completion interrupt information is reported to the local memory. Alternatively, a "RIE" field of "1" indicates that the DMA completion interrupt information is reported to the peer memory. Or, both the "LIE" and "RIE" fields can be "1", indicating that the DMA completion interrupt information is reported to both the local memory and the peer memory.

[0094] In the case where the DMA controller is applied to the RC, the first configuration information is used to indicate that the specified processor includes the RC processor, and the second configuration information is used to indicate that the specified processor includes the EP processor.

[0095] In the case where the DMA controller is applied to the EP, the first configuration information is used to indicate that the specified processor includes the EP processor, and the second configuration information is used to indicate that the specified processor includes the RC processor.

[0096] In the embodiments of this application, the designated processor can be an RC processor, an EP processor, or both an RC processor and an EP processor; this application does not impose any specific limitations.

[0097] The specified processor and the target processor can be the same processor or different processors; this application does not impose specific restrictions.

[0098] For example, when the DMA controller is applied to the RC, the "LIE" field of the data description character is "1", which indicates that the specified processor can be the RC processor. In this case, the RC processor is the local processor. The RC processor and the DMA controller communicate through the AXI bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the RC processor through the AXI bus, so that the RC processor can obtain the status description character from the target memory and determine the DMA execution result based on the status description character.

[0099] Alternatively, when the DMA controller is applied to RC, the "RIE" field of the data description character is "1", and the specified processor can be the EP processor. In this case, the EP processor is the peer processor. The EP processor and the DMA controller communicate through the PCIe bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the EP processor through the PCIe bus, so that the EP processor can obtain the status description character from the target memory and determine the DMA execution result based on the status description character.

[0100] Alternatively, when the DMA controller is applied to the RC, both the "LIE" field and the "RIE" field of the data description character are "1". The specified processor can be the RC processor or the EP processor. In this case, the RC processor is the local processor and the EP processor is the peer processor. The RC processor communicates with the DMA controller via the AXI bus, and the EP processor communicates with the DMA controller via the PCIe bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the RC processor via the AXI bus and to the EP processor via the PCIe bus, so that the RC processor and the EP processor can obtain the status description character from the target memory and determine the DMA execution result based on the status description character.

[0101] For example, when the DMA controller is applied to the EP, the "RIE" field of the data description character is "1", which indicates that the specified processor can be the RC processor. In this case, the RC processor is the peer processor. The RC processor and the DMA controller communicate through the PCIe bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the RC processor through the PCIe bus, so that the RC processor can obtain the status description character from the target memory and determine the DMA execution result based on the status description character.

[0102] Alternatively, when the DMA controller is applied to the EP, the "LIE" field of the data description character is "1", indicating that the specified processor can be the EP processor. In this case, the EP processor is a local processor, and the EP processor communicates with the DMA controller through the AXI bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the EP processor through the AXI bus, so that the EP processor can obtain the status description character from the target memory and determine the DMA execution result based on the status description character.

[0103] Alternatively, when the DMA controller is applied to the EP, both the "RIE" and "LIE" fields of the data description character are "1". The specified processor can be the RC processor or the EP processor. In this case, the RC processor is the peer processor and the EP processor is the local processor. The RC processor communicates with the DMA controller via the PCIe bus, and the EP processor communicates with the DMA controller via the AXI bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the RC processor via the PCIe bus and to the EP processor via the AXI bus, so that the RC processor and the EP processor can obtain the status description character from the target memory and determine the DMA execution result based on the status description character.

[0104] In this way, the direction of DMA completion interrupt information reporting is configured in advance for the DMA controller by using the first and / or second configuration information in the data description characters, informing the DMA controller to report DMA completion interrupt information to the local processor and / or the peer processor. Furthermore, the DMA controller can report DMA completion interrupt information to the local controller via the AXI link or to the peer controller via the PCIe link, based on the first and / or second configuration information in the data description characters. This improves the flexibility of the DMA controller and allows it to switch the direction of DMA completion interrupt information reporting.

[0105] For example, taking the data description character structure shown in Table 1 as an example, the "RIE" and "LIE" fields in the data description character obtained by the DMA controller indicate whether the DMA completion interrupt information needs to be sent to the peer processor or the local processor. After parsing the data description character, the DMA controller can directly report the DMA completion interrupt information to the peer processor and / or the local processor. In particular, when it is necessary to report the DMA completion interrupt information to the peer processor, the DMA controller directly reports the DMA interrupt message to the peer processor through the PCIe link, without the local processor's involvement in forwarding.

[0106] Furthermore, for communication devices compatible with both RC and EP modes, the DMA controller can dynamically control the direction of interrupt reporting in both RC and EP modes, enabling the DMA controller to be used in both RC and EP modes, thus broadening the application scenarios of the DMA controller.

[0107] Thus, the DMA controller provided in this application embodiment can be applied to communication devices compatible with EP mode and RC mode, and the reporting direction of DMA completion interrupt information can also be directly controlled through the "RIE" and "LIE" fields in the data description characters, which has higher robustness.

[0108] In practical applications, when the descriptor character linked list is long and the contiguous space in the target memory is insufficient, embodiments of this application can store the descriptor character linked list non-contiguously in the target memory. When physically non-contiguous storage of the descriptor character linked list is required, descriptor characters can be linked to point to the physical address of the next data descriptor character. This ensures the normal operation of the DMA controller even when the target memory storage space is discrete and the descriptor character linked list is long. An example is given below.

[0109] In one specific embodiment, the description character linked list includes multiple description character information entries, which are stored non-contiguously in multiple storage spaces of the target memory;

[0110] The multiple descriptive character information includes: a chain connection descriptive character stored in the first storage space of the target memory, and a data descriptive character stored in the second storage space of the target memory; the second storage space is a storage space discrete from the first storage space.

[0111] In this embodiment of the application, the chain connection description character includes a target pointer, which is used to indicate the physical address of the data description character stored in the second storage space of the target memory.

[0112] by Figure 5 Taking the target memory as an example, multiple descriptive character information entries in the descriptive character linked list are stored non-contiguously in the first, second, and third storage spaces. The first, second, and third storage spaces are all discrete storage spaces. The linking descriptive character 1 is stored in the first storage space of the target memory, and the data descriptive character 4 is stored in the second storage space of the target memory. The linking descriptive character 1 contains a target pointer, used to indicate the physical address of the data descriptive character 4.

[0113] certainly, Figure 5 The target memory shown is merely an example. This application does not limit the number of discrete storage spaces in the target memory, the number of data description characters stored in each storage space, or the number of chain connection description characters.

[0114] Thus, this embodiment of the application connects the description characters by linking them together, thereby connecting the data description characters stored in discrete storage space. This achieves non-contiguous storage of the description character information in the storage space, and enables non-contiguous storage of the description character linked list when the target memory has insufficient contiguous space when the description character linked list is long.

[0115] The following section details the content of the chain connection descriptor characters in the character linked list, using the data structure of the chain connection descriptor characters as an example. For instance, Table 3 provides a schematic data structure diagram of the chain connection descriptor characters:

[0116]

[0117] Table 3

[0118] The chain connection description character can include 6 double words (DW), each double word being 32 bits in size.

[0119] The first, second, and third double-word fields are "Reserve", indicating that this field is a reserved field.

[0120] The “Next Transfer List Pointer Address Low” field in the fourth double word and the “Next Transfer List Pointer Address High” field in the fifth double word can represent the target pointer, which is used to indicate the physical address of the next data description character stored in the discrete storage space.

[0121] The sixth double character is divided into three fields. The "LLP" field indicates the type of this data description character. For example, an "LLP" field of "1" indicates that the type of this description character is a chained description character. The two "Reserve" fields indicate that this field is a reserved field.

[0122] In this way, Figure 5 Taking the target memory shown as an example, the "Next Transfer List Pointer Address Low" and "Next Transfer List Pointer Address High" fields in the linked description character 1 are used to indicate the physical address of the data description character 4; the data description characters stored in the first storage space (e.g., data description character 3) are connected with the data description characters stored in the second storage space (e.g., data description character 4) to realize the non-contiguous storage of the description character information in the storage space. This realizes the non-contiguous storage of the description character linked list when the target memory has insufficient contiguous space due to the long description character linked list.

[0123] Furthermore, in the DMA controller 100 provided in this application embodiment, the acquisition module 100 can be specifically used to acquire the chain connection description character from the target memory according to the target memory information in the DMA control information, and acquire the data description character stored in the second storage space of the target memory according to the target pointer contained in the chain connection description character.

[0124] For example, with Figure 5 Taking the target memory shown as an example, the acquisition module 100 can obtain the chain connection description character 1 from the target memory according to the target memory information in the DMA control information, and then obtain the data description character 4 stored in the second storage space according to the target pointer contained in the chain connection description character 1.

[0125] Thus, in this embodiment of the application, the target pointer contained in the linked description character indicates the physical address of the next data description character stored in the discrete memory space. Consequently, the DMA controller can obtain the description character information in the discrete memory space based on the target pointer, ensuring the normal operation of the DMA controller even when the description character linked list is not stored contiguously in the target memory.

[0126] Based on the same concept as the DMA controller provided in the embodiments of this application, the embodiments of this application also provide a chip.

[0127] Figure 6 This is a schematic structural diagram of a chip provided in an embodiment of this application.

[0128] like Figure 6 As shown in the figure, this application embodiment also provides a chip, including a processor, a memory, and a DMA controller provided in any of the above embodiments, wherein the processor is connected to the memory and the DMA controller respectively, and the memory is connected to the DMA controller.

[0129] The chips provided in this application may include 4G chips, 5G chips, etc., and this application does not impose specific restrictions on the type of chip.

[0130] The chip provided in this application embodiment can implement all the processes implemented by the above-mentioned DMA controller and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0131] Based on the same concept as the DMA controller provided in the embodiments of this application, the embodiments of this application also provide a root complex.

[0132] like Figure 7 As shown, this application embodiment also provides a root complex, which may include an RC processor, an RC memory, a DMA controller provided in any of the above embodiments, and a first PCIe controller;

[0133] The RC processor is connected to the RC memory and the DMA controller respectively. The RC memory is connected to the DMA controller, and the DMA controller is connected to the first PCIe controller.

[0134] In the embodiments of this application, such as Figure 7 As shown, the process of DMA data transfer in the root complex can include:

[0135] ①The RC processor stores the description character linked list into the RC memory;

[0136] ②The RC processor sends DMA control information to the DMA controller;

[0137] ③The DMA controller's acquisition module retrieves the description character information from the description character linked list in the RC memory based on the DMA control information;

[0138] ④ The DMA controller's parsing module extracts the data description characters and converts them into data transfer information in the target instruction format;

[0139] ⑤ The parsing module of the DMA controller transmits the data transfer information to the data channel control module of the DMA controller;

[0140] ⑥ The data channel control module of the DMA controller performs data transfer between the RC memory and the EP memory according to the data transfer information, and generates the DMA execution result;

[0141] ⑦ The DMA controller's status write-back module obtains the DMA execution result and generates a status description character corresponding to the data description character based on the DMA execution result; and transmits the status description character to the RC memory so that the RC memory stores the status description character in a way that overwrites the data description character;

[0142] ⑧The interrupt control module of the DMA controller can determine the RC processor based on the configuration information in the data description character used to indicate the interrupt reporting direction, and report the DMA completion interrupt information to the RC processor.

[0143] ⑨ The RC processor retrieves the status description characters from the RC memory and determines the DMA execution result based on the status description characters.

[0144] In the embodiments of this application, in steps ① and ② above, in addition to the RC processor, the DMA controller can also be controlled by the EP processor, and this application does not limit this.

[0145] In the embodiments of this application, in addition to the RC memory, the description character linked list can also be stored in the EP memory, and this application does not limit this.

[0146] In step ⑥ above, the data channel control module of the DMA controller can access the RC memory through the AXI bus and the EP memory through the PCIe bus to complete the data transfer between the RC memory and the EP memory, and save the DMA execution results during the data transfer process.

[0147] In step ⑦ above, after the data channel control module completes the data transfer of a data description character, it sends the DMA execution result to the status write-back module. The status write-back module is responsible for writing the DMA execution result back to the storage space corresponding to the original data description character.

[0148] In step ⑧ above, if the data description character being executed is the last data description character in the description character chain (i.e., Stop field = 1), the interrupt control module of the DMA controller will determine the interrupt based on the values ​​of the "RIE" and "LIE" fields in the data description character. Figure 7 When the DMA controller operates in RC mode, the designated processor is the RC processor (RIE=0, LIE=1), and the DMA completion interrupt information is sent to the local processor (i.e., the RC processor).

[0149] Of course, in this embodiment, besides sending the DMA completion interrupt information to the local processor, the DMA completion interrupt information can also be sent to the peer processor (i.e., the EP processor). For example, the DMA completion interrupt information can be generated and reported to the EP processor by the RC processor writing a value to the EP's terminal register. Of course, this application can also use other methods to send the DMA completion interrupt information to the peer processor, and this application does not impose specific limitations here.

[0150] The root complex provided in this application embodiment can implement all the processes implemented by the above-mentioned DMA controller and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0151] Based on the same concept as the DMA controller provided in the embodiments of this application, the embodiments of this application also provide an endpoint device.

[0152] like Figure 8 As shown, this application embodiment also provides an endpoint device, which may include an EP processor, an EP memory, a DMA controller provided in any of the above embodiments, and a second PCIe controller;

[0153] The EP processor is connected to the EP memory and the DMA controller respectively. The EP memory is connected to the DMA controller, and the DMA controller is connected to the second PCIe controller.

[0154] In the embodiments of this application, such as Figure 8 As shown, the process of an endpoint device performing DMA data transfer may include:

[0155] ①The RC processor stores the character list description into the EP memory via the PCIe bus;

[0156] ②The RC processor sends DMA control information to the DMA controller via the PCIe bus;

[0157] ③The DMA controller's acquisition module retrieves the description character information from the description character linked list in the EP memory based on the DMA control information;

[0158] ④ The DMA controller's parsing module extracts the data description characters and converts them into data transfer information in the target instruction format;

[0159] ⑤ The parsing module of the DMA controller transmits the data transfer information to the data channel control module of the DMA controller;

[0160] ⑥ The data channel control module of the DMA controller performs data transfer between the RC memory and the EP memory according to the data transfer information, and generates the DMA execution result;

[0161] ⑦ The DMA controller's status write-back module obtains the DMA execution result and generates a status description character corresponding to the data description character based on the DMA execution result; and transmits the status description character to the EP memory so that the EP memory stores the status description character in a way that overwrites the data description character;

[0162] ⑧The interrupt control module of the DMA controller can determine the RC processor based on the configuration information in the data description character used to indicate the interrupt reporting direction, and report the DMA completion interrupt information to the RC processor through the PCIe bus.

[0163] ⑨ The RC processor retrieves the status description characters from the EP memory via the PCIe bus and determines the DMA execution result based on the status description characters.

[0164] In the embodiments of this application, in steps ① and ② above, in addition to the RC processor, the DMA controller can also be controlled by the EP processor, and this application does not limit this.

[0165] In the embodiments of this application, in addition to the EP memory, the description character linked list can also be stored in the RC memory, and this application does not limit this.

[0166] In step ⑥ above, the data channel control module of the DMA controller can access the EP memory through the AXI bus and the RC memory through the PCIe bus to complete the data transfer between the RC memory and the EP memory, and save the DMA execution results during the data transfer process.

[0167] In step ⑦ above, after the data channel control module completes the data transfer of a data description character, it sends the DMA execution result to the status write-back module. The status write-back module is responsible for writing the DMA execution result back to the storage space corresponding to the original data description character.

[0168] In step ⑧ above, if the data description character being executed is the last data description character in the description character chain (i.e., Stop field = 1), the interrupt control module of the DMA controller will determine the interrupt based on the values ​​of the "RIE" and "LIE" fields in the data description character. Figure 7 The DMA controller operates in EP mode, with the designated processor being the RC processor (RIE=1, LIE=0). It determines whether to send the DMA completion interrupt information to the peer processor (i.e., the RC processor). Specifically, it can choose any one of the three interrupt sending methods defined in the PCIe protocol: legacy, MSI, and MSI-X, to send the DMA completion interrupt information. This application does not impose any specific restrictions here.

[0169] Of course, in the embodiments of this application, in addition to sending the DMA completion interrupt information to the peer processor, the DMA completion interrupt information can also be sent to the local processor. This application does not impose any specific limitations here.

[0170] The endpoint device provided in this application embodiment can implement all the processes implemented by the DMA controller described above and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0171] Thus, the DMA controller provided in this application embodiment can determine the storage location of the description character list based on the DMA control information from the RC processor in both RC and EP modes. The DMA controller can then acquire the description character information by accessing either local memory or peer memory, depending on the storage location of the description character list. This allows the DMA controller to switch the direction of reading the description character information, enabling it to be used in both RC and EP modes. Compared to related technologies, the DMA controller is reusable, solving the problem of limited application scenarios for DMA controllers in related technologies. Furthermore, it reduces the cost of the DMA controller for communication devices compatible with both RC and EP modes.

[0172] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0173] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0174] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A DMA controller, characterized by The DMA controller is applied to a root complex (RC) or an endpoint device (EP), and comprises an obtaining module and a control module; The obtaining module is configured to obtain DMA control information from a target processor, wherein the DMA control information comprises information of a target memory, and the information of the target memory is used to indicate a storage location of a character list; the target processor is an RC processor or an EP processor; and the storage location of the character list is used for the DMA controller to access a local memory or a peer memory; The obtaining module is further configured to determine a target memory according to the DMA control information, and obtain character information in a character list from the target memory, wherein the target memory comprises an RC memory or an EP memory; The control module is configured to perform data transmission between the RC memory and the EP memory according to the character information in the character list.

2. The DMA controller of claim 1, wherein, The control module comprises an analyzing module and a data channel control module; The analyzing module is configured to extract the character information, convert the character information into data transfer information in a target instruction format, and transmit the data transfer information to the data channel control module; The data channel control module is configured to perform data transmission between the RC memory and the EP memory according to the data transfer information.

3. The DMA controller of claim 2, wherein, The character information comprises data character, and the data character comprises source address information of to-be-transferred data, destination address information of the to-be-transferred data, and data volume information of the to-be-transferred data; The analyzing module is configured to extract the data character in the character information, convert the source address information of the to-be-transferred data, the destination address information of the to-be-transferred data, and the data volume information of the to-be-transferred data in the data character into data transfer information in a target instruction format, and transmit the data transfer information to the data channel control module.

4. The DMA controller of claim 3, wherein The data channel control module is further configured to generate a DMA execution result after performing data transmission between the RC memory and the EP memory, wherein the DMA execution result comprises state information used to reflect a state of the DMA controller in transferring the to-be-transferred data; The DMA controller further comprises a state backwriting module; The state backwriting module is configured to obtain the DMA execution result from the data channel control module, and generate state character corresponding to the data character according to the DMA execution result; The state backwriting module is further configured to transmit the state character to the target memory, so that the target memory stores the state character in a manner of covering the data character.

5. The DMA controller of claim 4, wherein, The character list comprises target data character, the target data character is the last data character in the character list, and the target data character comprises configuration information used to indicate an interrupt reporting direction; The DMA controller further comprises an interrupt control module; The interrupt control module is configured to determine a specified processor according to configuration information in the target data description character for indicating an interrupt reporting direction, and report DMA completion interrupt information to the specified processor, so that the specified processor obtains the status description character from the target memory and determines a DMA execution result according to the status description character.

6. The DMA controller of claim 5, wherein, The configuration information for indicating the interrupt reporting direction includes first configuration information and / or second configuration information; the first configuration information is used to indicate that the specified processor includes a local processor; and the second configuration information is used to indicate that the specified processor includes a peer processor. In the case where the DMA controller is applied to RC, the first configuration information is used to indicate that the specified processor includes an RC processor, and the second configuration information is used to indicate that the specified processor includes an EP processor. In the case where the DMA controller is applied to EP, the first configuration information is used to indicate that the specified processor includes an EP processor, and the second configuration information is used to indicate that the specified processor includes an RC processor.

7. The DMA controller according to any one of claims 1-6, wherein: The description character chain table includes a plurality of description character information, and the plurality of description character information is discontinuously stored in a plurality of storage spaces of the target memory. The plurality of description character information includes a chain connection description character stored in a first storage space of the target memory and data description characters stored in a second storage space of the target memory; and the second storage space is a storage space discrete from the first storage space. The chain connection description character includes a target pointer, and the target pointer is used to indicate a physical address of the data description characters stored in the second storage space of the target memory.

8. The DMA controller of claim 7, wherein, The obtaining module is specifically configured to obtain the chain connection description character from the target memory according to information of the target memory in the DMA control information, and obtain the data description characters stored in the second storage space of the target memory according to the target pointer included in the chain connection description character.

9. A chip, characterized by A processor, a memory and the DMA controller according to any one of claims 1-8 are included, the processor is connected with the memory and the DMA controller respectively, and the memory is connected with the DMA controller.

10. A root complex, comprising: An RC processor, an RC memory, the DMA controller according to any one of claims 1-8 and a first PCIe controller are included. The RC processor is connected with the RC memory and the DMA controller respectively, the RC memory is connected with the DMA controller, and the DMA controller is connected with the first PCIe controller.

11. An endpoint device, comprising: An EP processor, an EP memory, the DMA controller according to any one of claims 1-8 and a second PCIe controller are included. The EP processor is connected with the EP memory and the DMA controller respectively, the EP memory is connected with the DMA controller, and the DMA controller is connected with the second PCIe controller.

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