Semiconductor layout IP information extraction method and storage medium
By extracting and comparing the semiconductor layout IP information, an initial screening form and information form are formed, which solves the problem of difficult to judge the accuracy of filling out IP information by customers or third-party, simplifies the IP synthesis process, and improves the accuracy and credibility of information comparison. , reduces the risk of filling out errors and improves customer service satisfaction.
Patent Information
- Application Number
- CN202411103679.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-12
- Publication Date
- 2024-12-13
AI Technical Summary
In semiconductor chip design, it is difficult to judge the accuracy of filling in IP information by customers or third-party, which may cause omissions, misalignment and other problems during IP synthesis, affecting the Tapeout schedule and may cause mask loss.
By extracting the specified IP information, forming an initial screening table, identifying information differences, forming an IP information form, and comparing it with exogenous IP information to judge accuracy, reducing IPmerge working time, and improving the accuracy and credibility of information comparison.
It reduces the risk caused by mistakes in filling out customer information, improves customer service satisfaction, simplifies the IP information comparison process, and improves the accuracy and reliability of IP synthesis.
Smart Images
Figure CN119127937A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a method and storage medium for extracting IP information from a semiconductor layout. Background Art
[0002] An IP module is a pre-designed or even verified integrated circuit, device or component with a certain function. Most of the client chip data, i.e., layout data, will call the IP module independently developed by the manufacturer (Foundary). The layout data used by the client only contains the physical library exchange format (LEF) file in the unit module that needs to synthesize the IP module. The LEF mainly defines the physical information of the unit module, such as the unit area size, geometry, wiring layer and other physical information. The unit module has no internal circuit. The unit module that needs to synthesize the IP module is equivalent to an IP black box with only connection information but no internal circuit. Before tape-out, the IP module needs to be synthesized (or incorporated) into the layout data provided by the client. The complete data synthesis needs to be operated by the Foundry engineers. The customer here refers to the chip designer. The manufacturer will carry out the specific production of the chip after receiving the customer's commission; the format of the layout data and IP module data are both in GDS format.
[0003] When the foundry IP or third-party IP is used in the customer data, the Tapeout team is required to perform IP merge processing. Currently, the information on the use of customer IP can be obtained from the OTO system. However, due to technical limitations, how to determine the accuracy of the customer's IP information has always been one of the problems that plagued the Tapeout team. Once the customer's information is filled in incorrectly, it is very likely to cause serious problems such as omissions and misalignments in the IP merge process, which may affect the Tapeout schedule at the least, or even cause mask loss at the worst. Summary of the invention
[0004] A series of simplified concepts are introduced in the Summary of the Invention, which are all simplifications of the prior art in the field, and will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.
[0005] The technical problem to be solved by the present invention is to provide a method and storage medium for extracting IP information from a semiconductor layout, which can reduce the complexity of IP information comparison for customers or third parties, reduce the working time of IPmerge, and improve the accuracy and credibility of information comparison, thereby reducing the risks that may be caused by problems in filling in customer information and improving customer service satisfaction.
[0006] In order to solve the above technical problems, the present invention provides a method for extracting IP information from a semiconductor layout, comprising:
[0007] S1, extract the specified IP information to form an IP information preliminary screening table in a specified format. The IP information preliminary screening table regards IPs with any information differences as independent individuals, and the representation of each independent individual IP is described separately in the IP information preliminary screening table;
[0008] S2, extracting IPs with the same name in the initial screening of IP information, obtaining IP information differences with the same name, and forming an IP information form in a specified format;
[0009] S3, compare the IP information form with the external IP information to determine whether the IP information is accurate.
[0010] Preferably, the semiconductor layout IP information extraction method is further improved, and the specified IP information includes: IP name, IP coordinate information, IP rotation angle, IP mirror status, IP size and IP size scaling status.
[0011] Preferably, the semiconductor layout IP information extraction method is further improved, and the specified format is .txt or .csv format.
[0012] Preferably, the semiconductor layout IP information extraction method is further improved, and when forming the IP information form, an error check is performed on each independent individual IP.
[0013] Preferably, the semiconductor layout IP information extraction method is further improved, and the error checking includes:
[0014] Among the IPs with the same name, if a certain information of a certain IP is different from that of other IPs, and the information of other IPs is the same, it is determined that the IP with this information is wrong and an error is reported.
[0015] Preferably, the semiconductor layout IP information extraction method is further improved, and the external IP information is IP information provided by the foundry production customer or IP information provided by a third party.
[0016] In order to solve the above technical problems, the present invention provides a computer-readable storage medium, which stores a computer program therein, and when the computer program is executed, it is used to implement the steps in any one of the above-mentioned semiconductor layout IP information extraction methods.
[0017] The present invention extracts designated IP information through layout software to form an IP information preliminary screening table of a designated format. The IP information preliminary screening table regards IPs with any information difference as independent individuals (even if two IPs are completely consistent except for coordinate information, they are still regarded as different IP statistics, which is beneficial to subsequent measurement). Each independent individual IP representation is described separately in the IP information preliminary screening table; then, computer programming technology (such as scripts) is used to extract IPs with the same name in the IP information preliminary screening, and obtain IP information differences with the same name (such as differences in rotation, mirroring, and scaling) to form an IP information form of a designated format; the IP information form is compared with the external IP information to determine whether the IP information is accurate.
[0018] The present invention can reduce the complexity of client or third-party IP information comparison, reduce the time of IPmerge work, and improve the accuracy and credibility of information comparison, thereby reducing the risks that may be caused by client information filling problems and improving customer service satisfaction. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific exemplary embodiments of the present invention, and to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the range of values or properties covered by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:
[0020] Figure 1 It is a schematic diagram of the process of the present invention.
[0021] Figure 2 It is the purpose of the initial screening of IP information.
[0022] Figure 3 This is a schematic diagram of information items in the IP information preliminary screening table.
[0023] Figure 4 This is a diagram of the IP information form. DETAILED DESCRIPTION
[0024] The following describes the implementation methods of the present invention through specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific implementation methods, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without deviating from the overall design concept of the invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other in the absence of conflict. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art.
[0025] First embodiment;
[0026] refer to Figure 1 The present invention provides a method for extracting IP information from a semiconductor layout, comprising:
[0027] S1, extract the specified IP information to form an IP information preliminary screening table of a specified format, for example, through Klayout, L-edit: extract information. This step can be implemented with existing layout software. The IP information preliminary screening table regards IPs with any information differences as independent individuals, and each independent individual IP representation is described separately in the IP information preliminary screening table;
[0028] S2, extracting IPs with the same name in the initial screening of IP information, obtaining IP information differences with the same name, and forming an IP information form in a specified format;
[0029] S3, compare the IP information form with the external IP information to determine whether the IP information is accurate.
[0030] Second embodiment;
[0031] The present invention provides a method for extracting IP information of a semiconductor layout, comprising:
[0032] S1, extract the specified IP information to form an IP information preliminary screening table in a specified format. The IP information preliminary screening table regards IPs with any information differences as independent individuals. Each independent individual IP representation is described separately in the IP information preliminary screening table. For example, refer to Figure 2 Shown and Figure 3 As shown;
[0033] The specified IP information includes: IP name, IP coordinate information, IP rotation angle, IP mirroring status, IP size and IP size scaling status; the specified format is .txt or .csv format;
[0034] S2, extract IPs with the same name in the initial screening of IP information, obtain the IP information differences with the same name, and form an IP information form in a specified format, refer to Figure 4 As shown;
[0035] S3, compare the IP information form with the external IP information to determine whether the IP information is accurate.
[0036] When forming the IP information form, each individual IP is checked for errors, including:
[0037] Among the IPs with the same name, if a certain information of a certain IP is different from that of other IPs, and the information of other IPs is the same, it is determined that the IP with this information is wrong and an error is reported.
[0038] Among them, the external IP information is the IP information provided by the OEM customer or the IP information provided by a third party.
[0039] Third embodiment;
[0040] The present invention provides a computer-readable storage medium, which stores a computer program therein. When the computer program is executed, it is used to implement the steps in the semiconductor layout IP information extraction method described in any one of the above embodiments.
[0041] The computer-readable medium includes permanent and non-permanent, removable and non-removable media and can be implemented by any method or technology to store information. Information can be computer-readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include non-transitory media such as modulated data signals and carrier waves.
[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not interpreted in an ideal or overly formal sense.
[0043] The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.
Claims
1. A method for extracting IP information from semiconductor layout. It is characterized in that include: S1, extract the specified IP information to form an IP information preliminary screening table in a specified format. The IP information preliminary screening table regards IPs with any information differences as independent individuals, and each independent individual IP representation is described separately in the IP information preliminary screening table; S2, extracting IPs with the same name in the initial screening of IP information, obtaining IP information differences with the same name, and forming an IP information form in a specified format; S3, compare the IP information form with the external IP information to determine whether the IP information is accurate.
2. The semiconductor layout IP information extraction method as claimed in claim 1, Features: The specified IP information includes: IP name, IP coordinate information, IP rotation angle, IP mirroring status, IP size, and IP size scaling status.
3. The semiconductor layout IP information extraction method as claimed in claim 1, Features: Specify the format to be .txt or .csv.
4. The semiconductor layout IP information extraction method as claimed in claim 1, Features: When forming the IP information form, error checking is performed on each individual IP.
5. The semiconductor layout IP information extraction method as claimed in claim 4, It is characterized in that Error checking includes: Among the IPs with the same name, if a certain information of a certain IP is different from that of other IPs, and the information of other IPs is the same, it is determined that the IP with this information is wrong and an error is reported.
6. The semiconductor layout IP information extraction method as claimed in claim 1, Features: External IP information refers to IP information provided by OEM customers or third parties.
7. A computer-readable storage medium, Features: A computer program is stored therein, and when the computer program is executed, it is used to implement the steps in the semiconductor layout IP information extraction method described in any one of claims 1-6.