A table-based frequency-domain behavior model parameter extraction method and system

Abstract

The present application belongs to but is not limited to the technical field of power amplifier chip, and particularly relates to a table-based frequency domain behavior model parameter extraction method and system, comprising: step 1, testing the output characteristics of the chip under different input powers; step 2, extracting the P2D model parameters of the power amplifier chip; step 3, extracting the bias current and third-order intermodulation product model files; step 4, dynamically calculating and realizing the third-order intermodulation and power added efficiency; and step 5, comparing and verifying the P2D model simulation and actual measurement of the power amplifier chip. The present application proposes a behavior model parameter extraction method capable of representing the power added efficiency and third-order intermodulation based on the table-based frequency domain P2D behavior model, and by combining the measured data of the dynamic drain current in the chip, the third-order intermodulation product output power of the chip and the simulation results of the fundamental wave output power of the chip, the dynamic calculation method of the power added efficiency and third-order intermodulation is broken through, and the simulation prediction of the power added efficiency and third-order intermodulation of the table-based frequency domain P2D model of the chip is realized.

Description

A method and system for extracting parameters of a table fundamental frequency domain behavior model Technical Field

[0001] This invention belongs to, but is not limited to, the field of power amplifier chip technology, and particularly relates to a method and system for extracting parameters of a table-based fundamental frequency domain behavioral model. Background Technology

[0002] Microwave power amplifier (PA) chips are crucial components of weapon and wireless communication systems. As core devices in RF transceiver front-end systems, their power characteristics and linearity play a decisive role in overall system performance. Therefore, establishing high-precision PA chip models to accurately characterize the chip's RF power and third-order intermodulation characteristics, and thus provide guidance for high-precision simulation design of the overall system link, is essential for developing high-performance RF front-end systems. RF power amplifier chip models can be broadly categorized into two types based on their modeling methods: behavioral models and equivalent circuit models. Equivalent circuit models require obtaining the equivalent circuit models of the chip's internal transistors and the electromagnetic data of the passive matching circuit, making parameter extraction complex. Behavioral models, as black-box models, only focus on the chip's input-output signal mapping relationship, without requiring knowledge of the device or circuit's working mechanism and its interactions. They can be quickly obtained by combining specific test systems. Furthermore, behavioral models offer advantages in model accuracy and convergence, and are therefore widely used in modeling various RF power amplifier chips.

[0003] Behavioral models can be further divided into time-domain behavioral models, which focus on the characterization of the input / output time-domain waveforms of communication systems, and frequency-domain behavioral models, which focus on describing port mismatch and higher harmonic characteristics. Research on RF power amplifier chips mainly focuses on frequency-domain behavioral models. Frequency-domain behavioral models mainly include X-parameter models (Keysight, USA), Cardiff models (Focus, Canada and Cardiff University, UK), tabular fundamental frequency domain P2D models, and simplified polynomial S2D ​​models (Keysight, USA). Among them, X-parameter models and Cardiff models, as extensions of the classic S-parameter models, can characterize frequency-domain nonlinear characteristics such as fundamental and higher harmonic outputs. However, parameter extraction for these two types of models requires dedicated testing equipment, resulting in high modeling costs and complex parameter extraction processes, making them difficult to promote in the modeling of RF power amplifier chips for practical engineering applications. In addition, S2D models only require S-parameters under different input powers to complete model parameter extraction, but do not support accurate characterization of nonlinear characteristics under deep compression of the power amplifier, and do not have the simulation capability for power-added efficiency. Unlike S2D behavioral models, tabular fundamental frequency domain P2D behavioral models consider the incident and reflection characteristics of all ports under different input powers. Therefore, P2D models can further simulate the fundamental amplitude and phase of power amplifier chips under deep compression, while also possessing the ability to characterize output characteristics such as S-parameters and noise. In terms of parameter extraction, P2D models can be used in conjunction with vector network analyzers commonly found in microwave and millimeter-wave laboratories to obtain measured S-parameter data under different input powers, thus completing the power amplifier chip modeling. Therefore, it is an ideal solution for achieving rapid behavioral modeling of low-cost power amplifier chips. However, traditional P2D models only consider the nonlinear relationship between the fundamental frequency domain signals of the power amplifier chip's input and output, lacking the ability to solve for the intermodulation components and the DC component at the static bias power supply. This results in the inability to simulate the power-added efficiency and third-order intermodulation performance of the power amplifier chip. This problem is also one of the difficulties in behavioral modeling of other RF chips. There is an urgent need to break through the limitations of P2D model parameter extraction methods that can accurately characterize third-order intermodulation and power-added efficiency, improving their characterization capabilities and accuracy in nonlinear RF power amplifier chip modeling.

[0004] To address this issue, several behavioral modeling teams both domestically and internationally have conducted related research. In 2009, H. Qi et al. and Qi Hao from the Tasker team at Cardiff University, UK, proposed an improved Cardiff model that uses polynomial equations to describe the output characteristics of the device under test, and used polynomial equations to simulate the harmonics of the device. In 2019, Bernhard Pichler et al. from the Vienna University of Technology compared the accuracy of the X parameters and the QPHD model under strong nonlinearity and load mismatch conditions under large-signal excitation, and used the QPHD model to simulate the power-added efficiency and third-order intermodulation under load pulling. In 2022, Ehsan M. Azad et al. from the Tasker team at Cardiff University, UK, proposed a new mathematical formula for the Cardiff nonlinear behavioral model, which extended the formula of the Cardiff nonlinear behavioral model using polynomial fitting, and introduced DC bias voltage (drain and gate) into the model to realize the simulation of power-added efficiency. However, the aforementioned methods are difficult to test, require specialized instruments, and involve complex data processing, making it challenging to directly transfer and apply these methods to tabular fundamental frequency domain P2D models. Therefore, how to further expand the simulation capabilities of power-added efficiency and third-order intermodulation based on traditional modeling methods is an urgent problem to be solved in chip behavior modeling based on tabular fundamental frequency domain P2D models.

[0005] Based on the above analysis, the urgent technical problems that need to be solved by existing technologies are: existing methods are difficult to test, require specialized instruments, and have complex data processing, making it difficult to directly transfer and apply these methods to tabular fundamental frequency domain P2D models. Therefore, how to further expand the simulation capabilities of power-added efficiency and third-order intermodulation based on traditional modeling methods is an urgent problem to be solved in chip behavior modeling based on tabular fundamental frequency domain P2D models. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention provides a method and system for extracting parameters of a table-based fundamental frequency domain behavior model, which improves the P2D model so that the improved P2D model can simulate power-added efficiency and third-order intermodulation.

[0007] This invention is implemented as follows: a method for extracting parameters of a table fundamental frequency domain behavior model, comprising:

[0008] Step 1: Test the chip output characteristics under different input powers;

[0009] Step 2: Extracting P2D model parameters of the power amplifier chip;

[0010] Step 3: Extraction of bias current and third-order intermodulation product model files;

[0011] Step 4: Dynamic calculation of third-order intermodulation power-added efficiency;

[0012] Step 5: Comparison and verification of P2D model simulation and actual measurement of power amplifier chip.

[0013] Furthermore, step 1 specifically includes: performing vector calibration and power calibration on the vector network analyzer to ensure the accuracy of the excitation power pin on the test reference surface of the vector network analyzer; the excitation power pin power range should cover the input power of the saturation region of the device under test, and saving calibration files for different excitation powers;

[0014] Scan the excitation power pin of the vector network analyzer (e.g., -15dBm to 30dBm), call the calibration file at the corresponding power to calibrate the vector network analyzer, read the DC voltage and current data on the DC source at different excitation powers and different frequencies (e.g., 37GHz to 43GHz) (obtained by viewing the DC source readings), and the S-parameters and third-order intermodulation product power of the vector network analyzer at different input powers, and record them.

[0015] Furthermore, step 2 specifically includes:

[0016] The parameter extraction of the fundamental frequency domain P2D model in the table requires taking the S-parameter files obtained under different excitation powers from the test, selecting the S-parameters under the minimum excitation power and placing them in the front data block of the P2D model file as the small signal parameter module, and selecting the S-parameters under other excitation powers and placing them in the AC data block of the P2D model file as the large signal parameter module, and indicating the magnitude of the excitation power of the input and output ports.

[0017] The bias current data and the third-order intermodulation product data are saved as MDF files, with the input variable being the input power pin, and the output results being the bias current and the third-order intermodulation product power, respectively. Finally, the P2D model file and the MDF file containing efficiency and third-order intermodulation product (IM3) information are imported into the commercial simulation software through the DAC control in the commercial simulation software.

[0018] Furthermore, step 3 specifically includes: writing the bias current information and third-order intermodulation product information measured in step 1 into the model file. The header of the bias current lookup file is temperature and frequency, the first column of data is input power, and the second column of data is bias current information; the header of the third-order intermodulation product lookup file is temperature and frequency, the first column of data is input power, and the second column of data is third-order intermodulation product power.

[0019] Furthermore, step 4 specifically includes:

[0020] In commercial SPICE simulation software, a P2D model simulation schematic is built, with a 50-ohm load connected to the output terminal. The input and output voltage and current wave characteristics of the model are calculated based on the harmonic balance simulator in the software. The results can be used to further obtain the simulation results of the chip's fundamental output power Pout, fundamental gain Gain, third-order intermodulation IMD3, and power-added efficiency PAE. Among them, the calculation of Pout can be based on the fundamental voltage and current components at the chip's load terminal, as shown in Equation (1). Gain is calculated based on Pout obtained from Equation (1) combined with the input power Pin, using Equation (2). The calculation of third-order intermodulation IMD3 requires combining Pout and the power of the third-order intermodulation product IM3 obtained from the table, as shown in Equation (3). The calculation of PAE requires combining Pout, Pin, and the bias voltage U corresponding to Pin obtained from the table. d and bias current I d The result is shown in equation (4);

[0021] Pout = 0.5 * real(V) load [1]*conj(I load [1]))(1)

[0022] Gain = Pout - Pin(2)

[0023] IMD3 = IM3 - Pout(3)

[0024]

[0025] Furthermore, step 5 specifically includes: Since the P2D model file and lookup table file store discrete points, points not covered by the simulation can be interpolated using cubic splines. The model data package can be called to simulate the third-order intermodulation and power-added efficiency, and interpolation can be performed between the data in the model file to perform a certain amount of extrapolation. The Pout interpolation method uses linear interpolation, while the third-order intermodulation and power-added efficiency use cubic spline interpolation.

[0026] Another object of the present invention is to provide a table fundamental frequency domain behavior model parameter extraction system for implementing the table fundamental frequency domain behavior model parameter extraction method, comprising:

[0027] Output characteristic testing module: Testing chip output characteristics under different input powers;

[0028] Model parameter extraction module: P2D model parameter extraction for power amplifier chips;

[0029] Model file extraction module: Extraction of bias current and third-order intermodulation product model files;

[0030] Dynamic calculation module: Implements dynamic calculation of third-order intermodulation power-added efficiency;

[0031] Comparison and verification module: Comparison and verification of P2D model simulation and actual measurement of power amplifier chip.

[0032] Another object of the present invention is to provide a computer device, the computer device including a memory and a processor, the memory storing a computer program, which, when executed by the processor, causes the processor to perform the steps of the table base frequency domain behavior model parameter extraction method.

[0033] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the table base frequency domain behavior model parameter extraction method.

[0034] Another objective of this invention is to provide an information data processing terminal, which includes the aforementioned table fundamental frequency domain behavior model parameter extraction system.

[0035] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0036] First, traditional frequency domain behavioral model parameter extraction does not consider the DC component of bias current and the third-order intermodulation product component, resulting in the model lacking power-added efficiency and third-order intermodulation prediction capabilities, making it difficult to use for RF power amplifier chip modeling. To address this, this invention proposes a behavioral model parameter extraction method based on a tabular fundamental frequency domain P2D behavioral model that can characterize power-added efficiency and third-order intermodulation. By combining measured data of dynamic drain current within the chip, simulation results of the chip's third-order intermodulation product output power, and chip fundamental output power, it overcomes the limitations of dynamic calculation methods for power-added efficiency and third-order intermodulation, achieving simulation prediction of chip power-added efficiency and third-order intermodulation using a tabular fundamental frequency domain P2D model.

[0037] Second, the technical solution of this invention fills a technological gap in the industry both domestically and internationally:

[0038] Current table-based fundamental frequency domain P2D models cannot simulate and predict chip power-added efficiency and third-order intermodulation. This invention, based on the traditional table-based fundamental frequency domain P2D model, adds current and third-order intermodulation information to achieve simulation and prediction of power-added efficiency and third-order intermodulation characteristics, filling a gap in the field of behavioral models.

[0039] The technical solution of this invention solves a long-standing technical problem that people have long desired to solve but have never been able to: power-added efficiency and third-order intermodulation characteristics are key indicators of radio frequency chips. In practical engineering applications, it is necessary to simulate and predict their power-added efficiency and third-order intermodulation characteristics. However, the current tabular fundamental frequency domain P2D model cannot simulate and predict the chip's power-added efficiency and third-order intermodulation. This invention achieves the simulation and prediction of power-added efficiency and third-order intermodulation characteristics by adding current and third-order intermodulation information to the traditional tabular fundamental frequency domain P2D model. Attached Figure Description

[0040] Figure 1 is a flowchart of the table fundamental frequency domain behavior model parameter extraction method provided in an embodiment of the present invention;

[0041] Figure 2 is a test principle diagram provided in an embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of the model file provided in an embodiment of the present invention;

[0043] Figure 4 is a structural diagram of the table fundamental frequency domain behavior model parameter extraction system provided in an embodiment of the present invention;

[0044] Figure 5 is a schematic diagram of the output power simulation and actual measurement results provided by the embodiment of the present invention;

[0045] Figure 6 is a schematic diagram of the gain simulation and measured results provided in the embodiment of the present invention;

[0046] Figure 7 is a schematic diagram of PAE simulation and actual measurement results provided in the embodiment of the present invention;

[0047] Figure 8 is a schematic diagram of the IMD3 simulation and measurement results provided in the embodiment of the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0049] Example 1: Parameter Extraction of a Table-Based Fundamental Frequency Domain Behavioral Model for Power Amplifier Chips

[0050] When designing high-frequency communication equipment, it is necessary to accurately model the nonlinear behavior of power amplifier chips to optimize the overall system performance. By extracting the tabular fundamental frequency domain behavioral model parameters of the power amplifier, the output characteristics of the chip can be accurately simulated, thereby improving design efficiency.

[0051] 1. Chip output characteristic test:

[0052] The power amplifier chip was tested using a vector network analyzer (VNA). First, the VNA was calibrated for both vector and power to ensure the accuracy of the excitation power. The test range covered the chip's saturation region, acquiring S-parameters, DC voltage and current data, and the power of third-order intermodulation products under different input powers.

[0053] 2. P2D model parameter extraction:

[0054] The S-parameters at the minimum excitation power are used as a small-signal parameter module, and the S-parameters at other powers are used as a large-signal parameter module, and stored in the P2D model file. The bias current and third-order intermodulation product data are saved as MDF files and then imported using the DAC control in commercial simulation software.

[0055] 3. Simulation and Verification:

[0056] A simulation schematic was built in commercial SPICE simulation software, and P2D model simulation was performed. The fundamental output power Pout, gain Gain, third-order intermodulation IMD3, and power-added efficiency PAE of the chip were calculated and compared with measured data to ensure the accuracy of the model.

[0057] 4. Results:

[0058] Through simulation analysis and verification with measured data, the behavior of the power amplifier chip under different operating conditions was determined, providing accurate model support for the optimized design of communication equipment.

[0059] Example 2: Parameter Extraction and Optimization of Behavioral Model for Radio Frequency Power Amplifiers

[0060] In radio frequency (RF) circuit design, the nonlinear effects of power amplifiers have a significant impact on system performance. By accurately extracting the behavioral model parameters of RF power amplifiers, device performance can be effectively predicted, and circuit design can be optimized.

[0061] step:

[0062] 1. Testing of RF amplifiers:

[0063] The RF power amplifier was tested using a vector network analyzer, covering the input power range from small to large signals. After ensuring calibration accuracy, S-parameters, DC voltage and current, and power data of third-order intermodulation products were acquired.

[0064] 2. Parameter extraction and model building:

[0065] Based on the test data, extract the parameters of the fundamental frequency domain P2D model from the table. Place the small-signal S-parameters into the model's pre-processor data block, and the S-parameters for other power levels into the AC data block. Save the bias current and third-order intermodulation product power data as an MDF file and import it into the simulation software.

[0066] 3. Simulation and Optimization:

[0067] A power amplifier was simulated using SPICE simulation software based on a harmonic balance simulator, and key parameters such as Pout, Gain, IMD3, and PAE were calculated. Based on the simulation results, the amplifier performance was optimized by adjusting the circuit design and bias conditions.

[0068] By comparing the simulation results with the measured data, the accuracy of the model was verified, and the design of the RF power amplifier was optimized accordingly, thereby improving the overall performance and efficiency of the RF circuit.

[0069] In the table-based fundamental frequency domain behavioral model parameter extraction method, the output characteristics of the power amplifier chip under different input powers are first tested using a vector network analyzer (VNA). To ensure the accuracy of the test, the VNA needs to perform vector calibration and power calibration to ensure the accuracy of the excitation power pin. During the test, the VNA gradually scans different excitation powers and collects the chip's S-parameters, DC voltage and current data, as well as the power of the third-order intermodulation products at each power level. These data will serve as the basis for subsequent P2D model parameter extraction, providing an accurate characterization of the chip at different power levels.

[0070] After completing the output characteristic test, the next step is to extract the parameters of the P2D model. The collected S-parameter data were categorized according to different excitation powers; the S-parameters at the minimum excitation power were used for small-signal analysis, while the S-parameters at other powers were used for large-signal analysis. This data was organized and written into the P2D model file, stored separately in the pre-processing data block and the AC data block. In addition, information on the bias current and third-order intermodulation products was also stored as MDF files for subsequent simulation. These model files were imported into the commercial simulation software using the DAC control, laying the foundation for subsequent simulation analysis.

[0071] Next, the P2D model was simulated and analyzed using commercial simulation software. By building the simulation schematic and connecting a suitable load, the simulator calculated the input and output voltage and current characteristics of the chip based on the harmonic balance method. Using these characteristics, the fundamental output power Pout, gain Gain, third-order intermodulation modulation (IMD3), and power-added efficiency (PAE) were further calculated. Specifically, Pout was determined by the fundamental voltage and current components at the chip's load terminals; Gain was calculated using the ratio of Pout to Pin; IMD3 was calculated by combining Pout with the power of the third-order intermodulation product IM3 obtained from a lookup table; and PAE was calculated using the relationship between Pout, Pin, and the bias voltage and current.

[0072] Since the data points in the model file and lookup table file are discrete, points not covered during simulation need to be processed using interpolation methods. For the output power Pout, linear interpolation is used; for third-order intermodulation and power-added efficiency, cubic spline interpolation is used. This interpolation process ensures the continuity and accuracy of the simulation results. Finally, by combining these interpolation methods, the simulation results are compared with measured data to verify the model's accuracy and reliability. Through this precise model and simulation, chip behavior can be effectively predicted, providing a scientific basis for design and optimization.

[0073] As shown in Figure 1, the table fundamental frequency domain behavior model parameter extraction method provided in this embodiment of the invention includes:

[0074] Step 1: Testing the chip's output characteristics under different input powers

[0075] Perform vector and power calibration on the vector network analyzer to ensure the accuracy of the excitation power pin on the test reference surface. The excitation power pin range should cover the input power in the saturation region of the device under test. Save calibration files for different excitation powers.

[0076] Scan the excitation power pin of the vector network analyzer (e.g., -15dBm to 30dBm), call the calibration file at the corresponding power to calibrate the vector network analyzer, read the DC voltage and current data on the DC source at different excitation powers and different frequencies (e.g., 37GHz to 43GHz) (obtained by viewing the DC source readings), and the S-parameters and third-order intermodulation product power of the vector network analyzer at different input powers, and record them.

[0077] Step 2: Extraction of P2D model parameters for power amplifier chip

[0078] The parameter extraction of the fundamental frequency domain P2D model requires obtaining S-parameter files under different excitation powers from the test. Select the S-parameters under the minimum excitation power and place them in the front data block of the P2D model file as the small signal parameter module. Select the S-parameters under other excitation powers and place them in the AC data block of the P2D model file as the large signal parameter module. Note the magnitude of the excitation power at the input and output ports.

[0079] In addition, the bias current data and the third-order intermodulation product data are saved as MDF files, with the input variable being the input power pin, and the outputs being the bias current and the third-order intermodulation product power, respectively. Finally, the P2D model file and the MDF file containing efficiency and third-order intermodulation product (IM3) information are imported into the DAC control in commercial simulation software.

[0080] Step 3: Extraction of bias current and third-order intermodulation product model files

[0081] Write the bias current information and third-order intermodulation product information obtained in step 1 into the model file. The header of the bias current lookup file is temperature and frequency, the first column of data is input power, and the second column of data is bias current information. The header of the third-order intermodulation product lookup file is temperature and frequency, the first column of data is input power, and the second column of data is third-order intermodulation product power.

[0082] Step 4: Dynamic Calculation of Third-Order Intermodulation Power-Added Efficiency

[0083] The P2D model simulation schematic was built in the commercial SPICE simulation software. A 50-ohm load was connected to the output terminal, and the input and output voltage and current wave characteristics of the model were calculated based on the harmonic balance simulator in the software. The results can be used to further obtain the simulation results of the chip's fundamental output power Pout, fundamental gain Gain, third-order intermodulation IMD3, and power-added efficiency PAE. Among them, the calculation of Pout can be based on the fundamental voltage and current components at the chip's load terminal, as shown in Equation (1). Gain is calculated based on Pout obtained from Equation (1) combined with the input power Pin, using Equation (2). The calculation of third-order intermodulation IMD3 requires combining Pout and the power of the third-order intermodulation product IM3 obtained from the table, as shown in Equation (3). The calculation of PAE requires combining Pout, Pin, and the bias voltage U corresponding to Pin obtained from the table. d and bias current I d The result is shown in equation (4).

[0084] Pout = 0.5 * real(V) load [1]*conj(I load [1]))(1)

[0085] Gain = Pout - Pin(2)

[0086] IMD3 = IM3 - Pout(3)

[0087]

[0088] Step 5: Comparison and verification of P2D model simulation and actual measurement of power amplifier chip

[0089] Since the P2D model file and lookup table file store discrete points, points not covered by the simulation can be interpolated using cubic splines. The model data package can be used to simulate third-order intermodulation and power-added efficiency, and interpolation can be performed between data in the model file to perform certain extrapolation. The Pout interpolation method uses linear interpolation, while the third-order intermodulation and power-added efficiency use cubic spline interpolation.

[0090] As shown in Figure 4, the table fundamental frequency domain behavior model parameter extraction system provided in this embodiment of the invention includes:

[0091] Output characteristic testing module: Testing chip output characteristics under different input powers;

[0092] Model parameter extraction module: P2D model parameter extraction for power amplifier chips;

[0093] Model file extraction module: Extraction of bias current and third-order intermodulation product model files;

[0094] Dynamic calculation module: Implements dynamic calculation of third-order intermodulation power-added efficiency;

[0095] Comparison and verification module: Comparison and verification of P2D model simulation and actual measurement of power amplifier chip.

[0096] 1) Output characteristic test module

[0097] The core task of this module is to test the output characteristics of the power amplifier chip under different input power conditions. A series of signals with varying power are input into the system, and the chip's output characteristic data, including output power, gain, and other relevant parameters, are recorded. This data will be used in the subsequent model parameter extraction process to ensure that the model accurately reflects the actual output behavior of the chip.

[0098] 2) Model parameter extraction module

[0099] After acquiring output characteristic data under different input power levels, the system inputs this data into the model parameter extraction module. This module is mainly responsible for extracting the P2D (power-to-current) model parameters of the power amplifier chip. Through advanced algorithms and data processing technology, it extracts the various parameters required for the P2D model, ensuring that the model can accurately describe the chip's output characteristics under various input conditions.

[0100] 3) Model file extraction module

[0101] Next, the system will use the P2D model parameters generated by the model parameter extraction module to further extract model files for the bias current and third-order intermodulation products. These files contain the behavioral characteristics of the power amplifier chip under different bias current conditions, as well as the output characteristics under third-order intermodulation distortion. These model files provide the necessary data support for subsequent dynamic calculations and simulation verification.

[0102] 4) Dynamic calculation and comparison verification module

[0103] Finally, the system enters the dynamic calculation module and the comparison and verification module stages. The dynamic calculation module uses the extracted model file to perform dynamic calculations of third-order intermodulation distortion and power-added efficiency, evaluating the chip's performance in actual operation. The comparison and verification module compares the simulation results of the P2D model with the actual test results to ensure the accuracy and reliability of the model. Through this closed-loop verification, the system can continuously optimize the model parameters to make them closer to the real chip behavior, providing reliable data support and performance prediction.

[0104] To verify the accuracy of the model, this invention simulated the power, gain, and power-added efficiency of the chip model in commercial simulation software under the conditions of an ambient temperature of 25℃, a frequency range of 38GHz-43GHz, and an input power of 18dBm. The results are shown in Figures 5, 6, 7, and 8, where circles represent measured results and solid lines represent model simulation results. The average errors of PAE, IMD3, output power, and gain at 25℃ between simulation and measurement are shown in Table 1. The errors were calculated using the mean absolute error within the frequency band, as follows.

[0105]

[0106] Table 1 Maximum errors in simulation and actual measurement

[0107]

[0108]

[0109] The results show that the maximum error of IMD3 simulation and actual measurement at 25℃ is within 0.2dBc, the maximum error of PAE simulation and actual measurement is within 0.1%, the maximum error of output power is within 0.02dBm, and the maximum error of gain is within 0.02dB, indicating that the method proposed in this patent has high accuracy.

[0110] An application embodiment of the present invention provides a computer device, which includes a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of a method.

[0111] An application embodiment of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of a method.

[0112] An application embodiment of the present invention provides an information data processing terminal, which includes a system.

[0113] It should be noted that embodiments of the present invention can be implemented in hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of the above-described hardware circuitry and software, such as firmware.

[0114] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for extracting parameters of a table fundamental frequency domain behavior model, characterized in that, include: Step 1: Testing chip output characteristics under different input power; Step 2: Extracting P2D model parameters of the power amplifier chip; Step 3: Extracting model files for bias current and third-order intermodulation products; Step 4: Dynamic calculation of third-order intermodulation and power-added efficiency; Step 5: Comparison and verification of P2D model simulation and actual measurement of the power amplifier chip; Step 4 specifically includes: building the P2D model simulation schematic in commercial SPICE simulation software, connecting a 50-ohm load to the output terminal, and calculating the input and output voltage, current, and wave characteristics of the model based on the harmonic balance simulator in the software; the results are used to further obtain the chip's corresponding... The simulation results of fundamental output power Pout, fundamental gain Gain, third-order intermodulation IMD3, and power-added efficiency PAE are presented. Among them, Pout is calculated based on the fundamental voltage and current components at the chip load end, as shown in Equation (1); Gain is calculated based on Pout obtained by Equation (1) combined with the excitation power Pin, using Equation (2); the calculation of third-order intermodulation IMD3 requires combining Pout and the power of the third-order intermodulation product IM3 obtained by looking up the table, as shown in Equation (3); the calculation of PAE requires combining Pout, Pin, and the bias voltage U corresponding to Pin obtained by looking up the table. d and bias current I d The calculation is shown in equation (4); Pout = 0.5 * real(V load [1]*conj(I load [1])) (1)Gain=Pout-Pin (2)IMD3=IM3-Pout (3) Step 5 specifically includes: Since the P2D model file and lookup table file store discrete points, points not covered by the simulation are interpolated using cubic splines. The model data package is called to simulate the third-order intermodulation and power-added efficiency, and interpolation is performed between the data in the model file to perform a certain amount of extrapolation. The Pout interpolation method uses linear interpolation, and the third-order intermodulation and power-added efficiency use cubic spline interpolation.

2. The method for extracting parameters of a table fundamental frequency domain behavior model as described in claim 1, characterized in that, Step 1 specifically includes: performing vector calibration and power calibration on the vector network analyzer to ensure the accuracy of the excitation power pin on the test reference surface of the vector network analyzer; the power range of the excitation power pin should cover the input power of the saturation region of the device under test, and saving the calibration files for different excitation powers; scanning the excitation power pin of the vector network analyzer, calling the calibration file for the corresponding power to calibrate the vector network analyzer, reading the DC voltage and current data on the DC source at different excitation powers and frequencies, and the S-parameters and third-order intermodulation product power of the vector network analyzer at different input powers, and recording them.

3. The method for extracting parameters of a table fundamental frequency domain behavior model as described in claim 1, characterized in that, Step 2 specifically includes: Parameter extraction of the fundamental frequency domain P2D model requires obtaining S-parameter files under different excitation powers from the tests. The S-parameters under the minimum excitation power are selected and placed in the pre-data block of the P2D model file as the small-signal parameter module. The S-parameters under other excitation powers are selected and placed in the AC data block of the P2D model file as the large-signal parameter module, with the magnitude of the excitation power at the input and output ports noted. The bias current data and the third-order intermodulation product data are saved as MDF files, with the excitation power Pin as the input variable and the bias current and third-order intermodulation product power as the outputs. Finally, the P2D model file and the MDF file containing efficiency and third-order intermodulation product information are imported into the DAC control within the commercial simulation software.

4. The method for extracting parameters of a table fundamental frequency domain behavior model as described in claim 1, characterized in that, Step 3 specifically includes: writing the bias current information and third-order intermodulation product information obtained in Step 1 into the model file. The header of the bias current lookup file is temperature and frequency, the first column of data is input power, and the second column of data is bias current information; the header of the third-order intermodulation product lookup file is temperature and frequency, the first column of data is input power, and the second column of data is third-order intermodulation product power.

5. A system for extracting table fundamental frequency domain behavior model parameters, implementing the table fundamental frequency domain behavior model parameter extraction method as described in any one of claims 1 to 4, characterized in that, include: Output characteristic testing module: Testing chip output characteristics under different input powers; Model parameter extraction module: P2D model parameter extraction for power amplifier chips; Model file extraction module: extraction of bias current and third-order intermodulation product model files; Dynamic calculation module: dynamic calculation of third-order intermodulation and power-added efficiency; Comparison and verification module: comparison and verification of power amplifier chip P2D model simulation and actual measurement.

6. A computer device, comprising a memory and a processor, the memory storing a computer program, which, when executed by the processor, causes the processor to perform the steps of the table fundamental frequency domain behavior model parameter extraction method as described in any one of claims 1 to 4.

7. A computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the table fundamental frequency domain behavior model parameter extraction method as described in any one of claims 1 to 4.

8. An information data processing terminal, comprising the table fundamental frequency domain behavior model parameter extraction system as described in claim 5.

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