Super-large-scale integrated circuit congestion prediction method and device, computer equipment and storage medium

Abstract

The invention discloses a super-large-scale integrated circuit congestion prediction method, which comprises the following steps of: constructing a neural network model based on a U-Net structure, taking the output of an EDA (Electronic Design Automation) tool, a unit distribution characteristic graph obtained through rapid calculation, wiring resource demand index rectangular region linear density (RUDY) and a rectangular region pin linear density graph (pinRUDY) as model input, obtaining a congestion hotspot map of global wiring, and predicting the congestion hotspot map of the global wiring. Therefore, the problem of long time consumption of accurate congestion prediction of the integrated circuit can be solved, and the result quality and the execution efficiency of the layout and wiring tool are improved. On the basis of the method, the congestion distribution calculation time of a single chip is about 0.0065 s, and is improved by 6 orders of magnitude compared with EDA (Electronic Design Automation); compared with a congestion map output by an EDA tool, the SSIM index is about 0.7935 (nrmse = 0.0045), and the prediction accuracy exceeds 80%.

Description

Technical Field

[0001] The present invention relates to the technical field of VLSI physical design, and in particular to a VLSI congestion prediction method, device, computer equipment and storage medium based on a U-Net structure. Background Art

[0002] As the process nodes of ultra-large-scale integrated circuits advance, the scale of integrated circuits is getting larger and larger, and the systems are becoming more and more complex. This also brings new challenges to electronic design automation (EDA) tools. In particular, new requirements are put forward for the performance and running speed of integrated circuit physical design (Physical Design) tools.

[0003] In the process of integrated circuit (IC) design, EDA (Electronic Design Automation) tools help designers automatically convert high-level descriptions (such as RTL code) to physical implementations (such as transistor layout GDSII files on silicon wafers). In this process, we can extract corresponding feature information from the output of each stage of the EDA tool, including cell distribution feature maps, rectangular line density distribution maps (RUDY), rectangular pin line density distribution maps (pinRUDY), and congestion distribution maps.

[0004] Among them, the cell distribution feature map shows how different types of logic modules (such as PLL, SRAM, FIFO, etc.) are distributed on the chip. We can quickly count and visualize this information from the output results of the EDA tool after the floorplan process, which is very useful for understanding the composition structure and possible hot spots of the design. The rectangular uniform line density reflects the usage of interconnect wiring, that is, the wiring resource occupancy of each unit block. Highly utilized areas may require additional resources to avoid signal integrity issues, timing violations, or congestion problems. Through the corresponding feature processing algorithm, these matrix data can be converted into image format data in a reasonable time. pinRUDY is similar to pin density. It calculates the distribution of wiring resources for each pin on a rectangular unit block and takes into account the network to which it is connected. This feature helps to evaluate wiring requirements, especially in high-density areas.

[0005] In contrast, the generation and analysis of congestion distribution maps is more complex. Congestion refers to the mismatch between the availability and demand of routing resources during the placement and routing phase of chip design. In highly dense areas, routing channels may not be sufficient to meet the needs of all connections, resulting in congestion. Calculating chip congestion distribution requires detailed routing attempts for the entire design, which involves the following factors:

[0006] Multi-layer wiring: Chip designs usually have multiple layers of metal for wiring, and the wiring direction and resources of each layer are different.

[0007] Dynamic programming: To find the optimal routing path, EDA tools must consider all possible routing options, which is an NP-hard problem.

[0008] Resource contention: Multiple networks may compete for the same routing resources at the same time, requiring complex algorithms to resolve conflicts.

[0009] Timing constraints: Routing length and quality directly impact signal propagation time and integrity, so congestion must be minimized while meeting timing requirements.

[0010] Due to the above reasons, calculating the congestion distribution map often takes longer (about 200s) and higher computing resources. Traditional EDA tools use advanced algorithms such as heuristic search, simulated annealing, genetic algorithms, etc. to approximate this problem, but it is still a time-consuming task, especially in large and complex chip designs. In addition, congestion analysis often requires repeated iterations to optimize routing strategies and reduce congestion, which further increases the overall calculation time. Summary of the invention

[0011] Aiming at the problem that the existing EDA takes a long time to calculate the congestion distribution diagram of a very large scale integrated circuit, the present invention provides a very large scale integrated circuit congestion prediction method based on a U-Net structure.

[0012] The present invention adopts the following technical scheme: a congestion prediction method for a very large scale integrated circuit, comprising: inputting a unit distribution feature map (macro_map), a rectangular uniform wire density (Rectangular Uniform wireDensitY, RUDY) distribution map and a rectangular area pin uniform wire density (pinRUDY) of the integrated circuit to be tested into a congestion prediction model to obtain a congestion distribution map.

[0013] The congestion prediction model adopts a neural network model with a U-Net structure, such as Figure 3 As shown, it includes an encoder and a decoder;

[0014] An encoder module, comprising: a first custom convolutional layer, a first maximum pooling layer, a first hybrid convolutional layer, a second custom convolutional layer, a second maximum pooling layer, a second hybrid convolutional layer, and a first output layer;

[0015] The first custom convolution layer and the second custom convolution layer are inherited from nn.Module, and use the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolution layer, an instance normalization layer, and a Leaky ReLU activation function;

[0016] The first mixed convolution layer and the second mixed convolution layer perform multi-branch convolution operations, both with 4 convolution kernels, and perform feature learning according to channel averaging;

[0017] The first output layer, inherited from nn.Module, uses the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolutional layer, a batch normalization layer (BatchNorm2d) and a Tanh activation function;

[0018] The decoder includes: a third custom convolution layer, a third mixed convolution layer, a first custom upsampling layer, a fourth custom convolution layer, a fourth mixed convolution layer, a second custom upsampling layer, and a second output layer.

[0019] The encoder and the decoder are connected by cross-connection, the output of the first custom convolutional layer in the encoder is connected to the second output layer of the decoder, and the output of the second custom convolutional layer of the encoder is connected to the fourth custom convolutional layer of the decoder;

[0020] The third custom convolution layer has the same structure as the custom convolution layer in the fourth custom convolution layer encoder;

[0021] The first custom upsampling layer and the second custom upsampling layer adopt the nn.Sequential splicing network structure, which is composed of a two-dimensional deconvolution layer nn.ConvTranspose2d, a normalization layer, and a nn.LeakyReLU activation layer in sequence;

[0022] The third and fourth hybrid convolutional layers have the same structure as the hybrid convolutional layers in the encoder;

[0023] The second output layer consists of a 2D convolutional layer and a sigmoid activation function.

[0024] Furthermore, the custom convolution layer adopts the network structure of nn.Sequential splicing, which includes the following 6 layers in sequence: two-dimensional convolution layer 1, instance normalization layer 1, leaky ReLU activation layer 1, two-dimensional convolution layer 2, instance normalization layer 2, leaky ReLU activation layer 2; the input channel of the two-dimensional convolution layer 1 is the same as the input channel of the custom convolution layer, and the output channel is determined by the output channel of the custom convolution layer. The convolution kernel size of the convolution layer is 3, the stride is 1, and the padding1 is 1; the difference between the two-dimensional convolution layer 2 and the two-dimensional convolution layer 1 is that the input and output channels of the convolution layer are both the number of output channels of the custom convolution layer; the affine parameters of the two instantiation layers are True, and a learnable linear transformation will be applied to each channel after normalization. The negative_slope and inplace parameters of the two leaky ReLU activation layers are set to 0.2 and true.

[0025] Furthermore, the encoder and / or decoder also includes a drop layer, which is arranged between any layers, and the drop layer adopts a random deactivation function nn.Dropout().

[0026] Furthermore, the encoder and / or decoder also includes a gradient clipping layer, which is arranged between any layers, and the gradient clipping layer uses the torch.nn.utils.clip_grad_value_() function in the python library to perform gradient clipping on the model.

[0027] Furthermore, the number of input channels of the first custom convolutional layer is the input feature number 3, and the number of output channels is 32; the number of input channels of the second custom convolutional layer is 32, and the number of output channels is 64; the number of input channels of the first output layer is 64, and the number of output channels is 32; the number of input channels of the third custom convolutional layer is 32, and the number of output channels is 32; the number of input channels of the fourth custom convolutional layer is 80, and the number of output channels is 16; the number of input channels of the second output layer is 36, and the number of output channels is 1.

[0028] Furthermore, both the first maximum pooling layer and the second maximum pooling layer adopt a 2*2 pooling window.

[0029] Furthermore, in the four mixed convolutional layers, the channels are equally divided into four parts, and each channel uses four convolution kernels of 3, 5, 7, and 9 respectively; the stride is 1, and the padding is determined according to the convolution kernel size, padding = (kernel_size-1) / 2, such as Fig.10 shown.

[0030] Furthermore, the kernel size of the 2D deconvolution layer is 4, the stride is 2, and the padding is 1.

[0031] Furthermore, the neural network model based on the U-Net structure is trained based on open source data, and the unit distribution feature map, RUDY map, and pinRUDY map of the open source integrated circuit obtained using the EDA tool are used as inputs to the neural network, and the congestion distribution map of the open source integrated circuit obtained using the EDA tool is used as an input label of the neural network.

[0032] The present invention also provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the above-mentioned prediction method by executing the computer instructions.

[0033] The present invention also provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to enable a computer to execute the above-mentioned prediction method.

[0034] The beneficial effects of the present invention are as follows: Based on the present invention, the time for calculating the congestion distribution of a single chip is about 0.0065s, which is 6 orders of magnitude higher than that of EDA; the SSIM index is about 0.7935 (nrmse = 0.0045); the prediction accuracy exceeds 80% BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of input feature extraction of the model of the present invention;

[0036] Figure 2 A schematic diagram of a 2-D image after input feature conversion of the model of the present invention;

[0037] Figure 3 Schematic diagram of the FCN prediction model based on the Unet structure established by the present invention;

[0038] Figure 4 It is a flow chart of the VLSI congestion prediction method based on U-Net structure of the present invention;

[0039] Figure 5 This is a schematic diagram of the ROC indicator of the model proposed in the present invention in the circuitnet-N28 data set;

[0040] Figure 6 This is a schematic diagram of the macro_map features of a set of data in the test set of the present invention;

[0041] Figure 7A schematic diagram of the RUDY characteristics of a set of data in the test set of the present invention;

[0042] Figure 8 This is a schematic diagram of the pinRUDY features of a set of data in the test set of the present invention;

[0043] Fig. 9 A schematic diagram of a VLSI congestion prediction device based on a U-Net structure;

[0044] Fig.10 Schematic diagram of the hybrid convolutional layer of the present invention;

[0045] Fig.11 It is a schematic diagram of the acceleration ratio of the present invention compared with traditional EDA tools and existing models. DETAILED DESCRIPTION

[0046] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.

[0047] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0048] It should be noted that the concepts of “first”, “second”, etc. may be mentioned in the present invention only to distinguish different devices, components or parts, and are not used to limit the order or interdependence of the functions performed by these devices, components or parts.

[0049] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Plurality" should be understood as two or more.

[0050] With the continuous advancement of technology, the complexity of physical design rules, which consist of a series of parameters provided by manufacturers, has increased significantly. Physical design, as the design stage that requires the most running time in integrated circuit design, has become more challenging with the emergence of advanced technology nodes. Through the output results of EDA design tools, the corresponding features are extracted, including cell distribution feature maps, rectangular area line density, rectangular area pin line density and congestion distribution maps. Among them, in large and complex chip designs, when calculating the congestion distribution map, EDA tools will use advanced algorithms such as heuristic search, simulated annealing, genetic algorithms, etc. to approximate the solution to this problem, which often takes longer time (about 200s) and higher computing resources.

[0051] Based on this, an embodiment of the present invention provides a VLSI congestion prediction method based on a neural network model with a U-Net structure. Through the output of the EDA tool, the unit distribution feature map, the wiring resource demand indicator rectangular area line density, and the rectangular area pin line density map are quickly calculated. Combined with the neural network based on the U-Net structure, a congestion hotspot map is obtained, thereby solving the time-consuming problem of accurately predicting the congestion results of the integrated circuit and improving the result quality and execution efficiency of the layout and wiring tools.

[0052] According to an embodiment of the present invention, an embodiment of a VLSI congestion prediction method based on a U-Net structure is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0053] In this embodiment, a VLSI congestion prediction method based on a U-Net structure is provided, which can be used for computer equipment, such as computers, servers, etc. Figure 4 is a flow chart of a method for predicting congestion of a very large scale integrated circuit based on a U-Net structure according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0054] Step S101, model training of a fully convolutional neural network model.

[0055] During the training process, the original data is normalized and converted into a feature map based on two-dimensional blocks for model training. The steps of this embodiment are as follows:

[0056] Step S1011: Generation of data set

[0057] The open source C906 project based on RISC-V architecture is selected as the basic design of RTL. The basic design consists of a series of RISC-V processing units, virtual memory management units (MMUs) and corresponding communication interface units. For the digital front end, the data set is expanded by adding additional 1-3 SRAM storage units and adding additional macros, and 100MHz, 200MHz, and 500MHz are selected for clock constraints. In addition, the DC library based on 55nm process is selected for synthesis. In order to further expand the data set, three core utilization rates (70%, 80%, and 90%) are set in the back-end design process, 5 macro placement methods are set through EDA tools, and 16 parameter combinations are selected to generate the corresponding power mesh. Finally, the pre-wiring filling and post-wiring filling are performed to expand the data set. As shown in the overview, 4*2*3*3*5*16*2 is expanded to obtain a total of 11520 sets of back-end layout and routing data. After removing some failed routing combinations, 9978 sets are left for routing feature extraction, as shown in Table 1.

[0058] Table 1

[0059]

[0060] Step S1012: Feature extraction

[0061] In this project, we mainly extract RUDY, pinRUDY and macro_map data from each set of data and the corresponding congestion situation. The entire layout is divided into 256*256 areas, and the extracted feature data is normalized and mapped to the corresponding areas to form a corresponding two-dimensional feature map, which reflects the congestion level of the corresponding area. As common knowledge in the field, macro_map reflects the distribution of corresponding logic modules, RUDY reflects the occupancy of wiring resources of each rectangular block, which is referred to as line density in the following text, and pinRUDY reflects the wiring resources required by the pins, which is referred to as pin line density in the following text.

[0062] The three features of the model are extracted from the output of the corresponding stages of the EDA tool, such as Figure 1 As shown in the figure. The unit distribution feature map (macro_map) is obtained after the layout (floorplan) is completed, and RUDY and pinRUDY come from the wiring (placement) stage. The macro area map (macro_map) reflects the distribution of relative routing resources, such as Figure 2 .a, where the macro coverage area and uncovered area are represented by different grayscale values. RUDY reflects the routing resources of the area, which is partially related to the routing congestion. It has a fast acquisition speed and can be directly encoded into a two-dimensional feature map, such as Figure 2pinRUDY can also be converted into a corresponding two-dimensional feature map, as shown in .b. Figure 2 .c.

[0063] In addition, if Figure 2 As shown in Figure .d, the congestion labels generated by Cadence Innovus clearly identify potential congestion areas. The solid red boxes highlight locations with high probability of congestion. These locations are consistent with Figure 2 The macro-dense layout area marked by the dotted box in .a is highly consistent, showing the congestion aggregation trend at the small gaps between adjacent macros. The remaining few hot spots, as shown by the purple circles in the figure, are sparsely distributed in the edge areas of some macros.

[0064] Step S1013: Model building and training

[0065] The dataset obtained by s1012 is divided into two parts, the first 8000 groups are used as training sets, and the last 1978 groups are used as test sets. The training set data is input into the U-Net model with variable convolution kernels and trained for 100000 iters. In addition, the corresponding model weights are saved once every 100 iters of training.

[0066] The basic structure of U-Net is as follows:

[0067] The encode module as a whole includes: the first custom convolution layer, the first maximum pooling layer, the first mixed convolution layer, the second custom convolution layer, the second maximum pooling layer, the second mixed convolution layer, and the first output layer; the decoder includes: the third custom convolution layer, the third mixed convolution layer, the first custom upsampling layer, the fourth custom convolution layer, the fourth mixed convolution layer, the second custom upsampling layer, and the second output layer. This model is a fully convolutional neural network model.

[0068] The first custom convolution layer and the second custom convolution layer are inherited from nn.Module, and use the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolution layer, an instance normalization layer, and a Leaky ReLU activation function;

[0069] The first output layer, inherited from nn.Module, uses the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolutional layer, a batch normalization layer (BatchNorm2d) and a Tanh activation function;

[0070] The third custom convolution layer has the same structure as the custom convolution layer in the fourth custom convolution layer encoder;

[0071] The first custom upsampling layer and the second custom upsampling layer adopt the nn.Sequential splicing network structure, which is composed of a two-dimensional deconvolution layer nn.ConvTranspose2d, a normalization layer, and a nn.LeakyReLU activation layer in sequence;

[0072] The third and fourth hybrid convolutional layers have the same structure as the hybrid convolutional layers in the encoder;

[0073] The second output layer consists of a 2D convolutional layer and a sigmoid activation function.

[0074] The encoder and decoder are cross-connected, the output of the first custom convolutional layer in the encoder is cross-connected to the second output layer of the decoder, and the output of the second custom convolutional layer of the encoder is cross-connected to the fourth custom convolutional layer of the decoder; the cross-connected structure splices the feature map of the corresponding encoding layer into the decoding layer to extract and retain detail information and promote feature reuse.

[0075] Four mixed convolution layers perform multi-branch convolution operations, each with 4 convolution kernels, and perform feature learning according to channel average distribution, flexibly learning features under different channels and enhancing feature extraction capabilities, such as Fig.10 shown.

[0076] Step S1014: Model prediction

[0077] The weights obtained by model training are called, and the remaining 1978 groups of two-dimensional feature data are used as the output of the model to obtain the congestion hotspot map of each group of congestion data. It is compared with the corresponding congestion label map, and the corresponding evaluation indicators SSIM, NRMSE, and peakNRMSE are calculated.

[0078] The structural similarity index SSIM is defined as follows:

[0079]

[0080] Among them, μ X and μ Y are the average values ​​of images X and Y respectively, and are the variances of X and Y respectively, It is the covariance between two images. It is based on a sliding window of size k×k and comprehensively measures the similarity of images from the dimensions of brightness, contrast, and structure. The higher the SSIM value, the higher the structural similarity of the two images, that is, the more similar the images are.

[0081] The normalized mean square error NRMSE is defined as follows:

[0082]

[0083] Among them, y max and min is the maximum and minimum value of the true image value, which is used to normalize the mean square error.

[0084] The peak mean square error (peak NRMSE) is calculated based on the ranking of congestion values ​​in the real congestion map, selecting the top 0.5%, 1%, and 5% of the elements.

[0085] The model parameters obtained after repeated debugging are as follows:

[0086] The number of input channels of the first custom convolution layer is the input feature number 3, and the number of output channels is 32; the number of input channels of the second custom convolution layer is 32, and the number of output channels is 64; the number of input channels of the first output layer is 64, and the number of output channels is 32; the number of input channels of the third custom convolution layer is 32, and the number of output channels is 32; the number of input channels of the fourth custom convolution layer is 80, and the number of output channels is 16; the number of input channels of the second output layer is 36, and the number of output channels is 1.

[0087] In the four mixed convolution layers, the channels are divided into four parts, and each channel uses four convolution kernels: 3, 5, 7, and 9; the stride is 1, and the padding is determined by the size of the convolution kernel, padding = (kernel_size-1) / 2, such as Fig.10 shown.

[0088] The first and second maximum pooling layers both use a pooling window of 2*2. The kernel size of the 2D deconvolution layer is 4, the stride is 2, and the padding is 1.

[0089] To ensure the fairness of the comparison and reflect the advanced nature of the model, we tested it on the open source dataset CircuitNet-N28 and obtained the following results: Figure 5 The ROC indicator diagram shown in the figure shows that the ROC indicator is significantly improved compared with the existing model. Considering the points with congestion values ​​exceeding 20% ​​as hot spots, the prediction accuracy can exceed 80%. In addition, as shown in Table 2, the SSIM, NRMSE and peakNRMSE indicators show, compared with the existing model, the SSIM is improved by more than 2%. Further testing on the open source dataset ISPD2015, the prediction indicators of the model are shown in Table 3, which are more than 19% better than the existing model. Fig.11 As shown in the figure, compared with the traditional EDA simulation time, the average acceleration ratio reaches 1231557x, and compared with the traditional model, the acceleration ratio of Congest-Net is 1.8x.

[0090] Table 2

[0091]

[0092] Table 3

[0093]

[0094] Step S102: VLSI congestion prediction based on U-Net structure

[0095] Step S1021: using existing EDA tools to extract a unit distribution feature map, a rectangular uniform line density map, and a rectangular area pin uniform line density map from the floorplan and placement data respectively;

[0096] The rectangular area line density (RUDY) of the indicator reflecting the wiring resources is as follows: Figure 7 The specific definitions are as follows:

[0097] s k =(min(x k,max ,x i,max )-max(x k,min ,x i,min ))×(min(y k,max ,y i,max )-max(y k,min ,y j,min ));

[0098] s ij =(x i,max -x i,min )×(y j,max -y j,min );

[0099] w k =x k,max -x k,min ;

[0100] h k =y k,max -y k,min ;

[0101]

[0102] Among them, {x k,min ,x k,max ,y k,min ,y k,max} is the bounding box of the given k-th network. Meanwhile, the bounding box of the (i,j)-th tile is given by {x i,min ,x i,max ,y i,min ,y i,max Here, s i,jrepresents the area of ​​cell (i, j), and sk represents the area occupied by network k when covering tile (i, j). Furthermore, RUDY(x, y) is the sum of the RUDY of all nets in the tile.

[0103] The cell distribution feature map macro_map is represented by different grayscale values ​​depending on whether the corresponding tile is covered by the macro. The area covered by the macro in the layout shows the relative wiring resource distribution, such as Figure 6 shown.

[0104] The pin density of the rectangular area, pinRUDY, is calculated based on the individual characteristics of the pins and the network they are connected to, as an analogy for the pin density. Specifically, for cell (i, j), the pinRUDY of the pins belonging to network k is calculated as follows:

[0105]

[0106] Among them, w k and h k As shown in the above RUDY definition, it is the width and height of the kth network.

[0107] Step S102, input the unit distribution feature map, the rectangular uniform line density map, and the rectangular uniform pin line density map into the congestion prediction model to obtain the congestion distribution map. The predicted value and the true value are as follows: Figure 8 As shown, the congestion hotspots are highly overlapped.

[0108] As a common technical means in this field, in this project, flipping, rotation, scaling and clipping can be further used to expand the data set to prevent overfitting and improve the generalization ability of the model. Specifically, a gradient clipping layer is set in the encoder and / or decoder, and is set between any layers. The gradient clipping layer uses the torch.nn.utils.clip_grad_value_() function in the python library to perform gradient clipping on the model. And / or a drop layer is set in the encoder and / or decoder, and is set between any layers. The drop layer uses a random deactivation function. In an embodiment of the present invention, three methods of network pruning, gradient pruning and random deactivation are used to delete unimportant crossovers. Only three crossovers are retained, from the first pooling layer in the encoder to the first upsampling layer in the decoding layer, from the second convolutional layer in the encoding layer to the second convolutional layer in the decoder, and from the pooling layer in the second encoder to the second upsampling layer in the decoder. Set the gradient upper limit 1, and use the torch.nn.utils.clip_grad_value_() function in python to perform gradient clipping on the model, control the gradient within a certain range, and make the training more stable. Finally, the random dropout function nn.Dropout() is used in the decoder and decoder, and a random dropout layer is added to set the output of some neurons to 0 to increase the generalization ability of the model.

[0109] This embodiment provides a VLSI congestion prediction device based on a U-Net structure. Fig. 9 As shown, including:

[0110] The acquisition module A is used to obtain the unit distribution characteristic diagram, rectangular uniform line density, and rectangular uniform pin line density of the integrated circuit to be tested. This module relies on EDA design tools and can quickly generate the unit distribution characteristic diagram, rectangular uniform line density distribution diagram, and rectangular uniform pin line density diagram of the integrated circuit to be tested.

[0111] Prediction module B is used to calculate macro_map, RUDY, and pinRUDY graphs using a pre-trained U-Net-based network model, and efficiently output congestion result graphs.

[0112] The embodiment of the present invention also provides a computer device having the above Fig. 9The U-Net structure-based VLSI congestion prediction device shown. The computer device generally includes: one or more processors, a memory, and an interface for connecting various components, including a high-speed interface and a low-speed interface. The various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0113] The processor may be a central processing unit, a network processor or a combination thereof. The processor may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0114] The memory stores instructions executable by at least one processor, so that the at least one processor executes the method shown in the above embodiment.

[0115] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0116] The memory may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid state drive; the memory may also include a combination of the above types of memory.

[0117] The computer device also includes an input device and an output device. The processor, memory, input device and output device can be connected via a bus or other methods.

[0118] The input device can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device may be a touch screen.

[0119] The computer device also includes a communication interface, which is used for the computer device to communicate with other devices or a communication network.

[0120] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0121] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for predicting congestion of a very large scale integrated circuit, characterized in that: include: Inputting the unit distribution characteristic map, the rectangular uniform line density distribution map and the rectangular area pin uniform line density of the integrated circuit to be tested into the congestion prediction model to obtain the congestion distribution map; The congestion prediction model adopts a neural network model based on a U-Net structure, including an encoder and a decoder; An encoder module, comprising: a first custom convolutional layer, a first maximum pooling layer, a first hybrid convolutional layer, a second custom convolutional layer, a second maximum pooling layer, a second hybrid convolutional layer, and a first output layer; The first custom convolution layer and the second custom convolution layer are inherited from nn.Module, and use the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolution layer, an instance normalization layer, and a Leaky ReLU activation function; The first mixed convolution layer and the second mixed convolution layer perform multi-branch convolution operations, both with 4 convolution kernels, and perform feature learning according to channel averaging; The first output layer, inherited from nn.Module, uses the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolutional layer, a batch normalization layer (BatchNorm2d) and a Tanh activation function; A decoder, comprising: a third custom convolution layer, a third hybrid convolution layer, a first custom upsampling layer, a fourth custom convolution layer, a fourth hybrid convolution layer, a second custom upsampling layer, and a second output layer; The encoder and the decoder are connected by cross-connection, the output of the first custom convolutional layer in the encoder is connected to the second output layer of the decoder, and the output of the second custom convolutional layer of the encoder is connected to the fourth custom convolutional layer of the decoder; The third and fourth custom convolutional layers have the same structure as the custom convolutional layers in the encoder; The first custom upsampling layer and the second custom upsampling layer adopt the nn.Sequential splicing network structure, which is composed of a two-dimensional deconvolution layer nn.ConvTranspose2d, a normalization layer, and a nn.LeakyReLU activation layer in sequence; The third and fourth hybrid convolutional layers have the same structure as the hybrid convolutional layers in the encoder; The second output layer consists of a 2D convolutional layer and a sigmoid activation function.

2. A VLSI congestion prediction method according to claim 1, characterized in that: The custom convolution layer adopts the network structure of nn.Sequential splicing, which includes the following 6 layers in sequence: two-dimensional convolution layer 1, instance normalization layer 1, leaky ReLU activation layer 1, two-dimensional convolution layer 2, instance normalization layer 2, leaky ReLU activation layer 2; the input channel of the two-dimensional convolution layer 1 is the same as the input channel of the custom convolution layer, and the output channel is determined by the output channel of the custom convolution layer. The convolution kernel size of the convolution layer is 3, the stride is 1, and the padding1 is 1; the difference between the two-dimensional convolution layer 2 and the two-dimensional convolution layer 1 is that the input and output channels of the convolution layer are both the number of output channels of the custom convolution layer; the affine parameters of the two instantiated layers are True, and a learnable linear transformation will be applied to each channel after normalization; the negative_slope and inplace parameters of the two leaky ReLU activation layers are set to 0.2 and true.

3. A VLSI congestion prediction method according to claim 1, characterized in that: The encoder and / or decoder further includes a drop layer, which is arranged between any layers, and the drop layer adopts a random deactivation function nn.Dropout().

4. A VLSI congestion prediction method according to claim 1, characterized in that: The encoder and / or decoder also includes a gradient clipping layer, which is arranged between any layers. The gradient clipping layer uses the torch.nn.utils.clip_grad_value_() function in the python library to perform gradient clipping on the model.

5. A VLSI congestion prediction method according to claim 1, characterized in that: The number of input channels of the first custom convolution layer is the input feature number 3, and the number of output channels is 32; the number of input channels of the second custom convolution layer is 32, and the number of output channels is 64; the number of input channels of the first output layer is 64, and the number of output channels is 32; the number of input channels of the third custom convolution layer is 32, and the number of output channels is 32; the number of input channels of the fourth custom convolution layer is 80, and the number of output channels is 16; the number of input channels of the second output layer is 36, and the number of output channels is 1.

6. A VLSI congestion prediction method according to claim 1, characterized in that: The first maximum pooling layer and the second maximum pooling layer both use a 2*2 pooling window.

7. A VLSI congestion prediction method according to claim 1, characterized in that: Four mixed convolutional layers divide the channel into four parts equally, and each channel uses four convolution kernels: 3, 5, 7, and 9 respectively; the stride is 1, and the padding is determined by the size of the convolution kernel, padding = (kernel_size-1) / 2.

8. A VLSI congestion prediction method according to claim 1, characterized in that: The 2D deconvolution layer has a kernel size of 4, a stride of 2, a padding of 1, and is normalized using the nn.InstanceNorm2d layer.

9. A VLSI congestion prediction method according to claim 1, characterized in that: The neural network model based on the U-Net structure is trained based on open source data, including a unit distribution feature map of the open source integrated circuit obtained by using an EDA tool, a rectangular uniform line density distribution map, and a rectangular area pin uniform line density as input features of the neural network, and a congestion distribution map of the open source integrated circuit obtained by using an EDA tool as an input label of the neural network.

10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 9 by executing the computer instructions.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 9.

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