A method and device for predicting congestion of a very large scale integrated circuit, a computer device and a storage medium

Abstract

The application discloses a congestion prediction method for a super large scale integrated circuit, constructs a neural network model based on a U-Net structure, takes output of an EDA tool, a cell distribution feature map calculated quickly, a rectangular region line density (RUDY) of a wiring resource demand index and a pinRUDY as model input, and obtains a congestion hotspot map of global wiring, so that a long time-consuming problem of accurate prediction of integrated circuit congestion can be solved, and the result quality and execution efficiency of a layout and wiring tool are improved. Based on the application, the time for calculating congestion distribution of a single chip is about 0.0065s, which is improved by 6 orders of magnitude compared with EDA; compared with a congestion map output by the EDA tool, the SSIM index is about 0.7935 (nrmse=0.0045), and the prediction accuracy is more than 80%.

Description

Technical Field

[0001] The present invention relates to the technical field of ultra-large-scale integrated circuit physical design, and in particular to an ultra-large-scale integrated circuit congestion prediction method, device, computer equipment and storage medium based on a U-Net structure. Background Art

[0002] As ultra-large-scale integrated circuit (VLSI) process nodes advance, integrated circuits (ICs) become larger and larger, and systems become increasingly complex. This poses new challenges to electronic design automation (EDA) tools, particularly those for physical design (PHY) of integrated circuits.

[0003] During the integrated circuit (IC) design process, EDA (Electronic Design Automation) tools help designers automatically convert high-level descriptions (such as RTL code) into physical implementations (such as GDSII files for transistor layouts on silicon wafers). During this process, we can extract relevant feature information from the output of each EDA tool stage, including cell distribution feature maps, rectangular line density distribution maps (RUDY), rectangular pin line density distribution maps (pinRUDY), and congestion distribution maps.

[0004] Among them, the cell distribution feature map shows how different types of logic modules (such as PLL, SRAM, FIFO, etc.) are distributed on the chip. We can quickly count and visualize this information from the output results of the EDA tool after the floorplan process, which is very useful for understanding the composition structure and possible hot spots of the design. The rectangular uniform line density reflects the usage of interconnect wiring, that is, the wiring resource occupancy of each unit block. Highly utilized areas may require additional resources to avoid signal integrity issues, timing violations or congestion problems. Through the corresponding feature processing algorithm, these matrix data can be converted into image format data in a reasonable time. pinRUDY is similar to pin density. It calculates the distribution of wiring resources for each pin on the rectangular unit block and takes into account the network it is connected to. This feature helps to evaluate wiring requirements, especially in high-density areas.

[0005] In contrast, generating and analyzing congestion distribution maps is more complex. Congestion refers to the mismatch between the availability and demand of routing resources during the place-and-route phase of chip design. In highly dense areas, routing channels may not be sufficient to meet the needs of all connections, leading to congestion. Calculating chip congestion distribution requires detailed routing attempts for the entire design, which involves the following factors:

[0006] Multi-layer wiring: Chip designs typically have multiple layers of metal for wiring, with each layer having different wiring directions and resources.

[0007] Dynamic programming: To find the optimal routing path, EDA tools must consider all possible routing options, which is an NP-hard problem.

[0008] Resource contention: Multiple networks may compete for the same routing resources simultaneously, requiring complex algorithms to resolve conflicts.

[0009] Timing constraints: Routing length and quality directly impact signal transmission time and integrity, so congestion must be minimized while meeting timing requirements.

[0010] For these reasons, calculating congestion distribution maps often requires longer processing times (approximately 200 seconds) and higher computational resources. Traditional EDA tools use advanced algorithms, such as heuristic search, simulated annealing, and genetic algorithms, to approximate this problem, but this remains a time-consuming task, especially for large and complex chip designs. Furthermore, congestion analysis often requires repeated iterations to optimize routing strategies and reduce congestion, further increasing overall computational time. Summary of the Invention

[0011] Aiming at the problem that existing EDA takes a long time to calculate the congestion distribution diagram of a very large scale integrated circuit, the present invention provides a very large scale integrated circuit congestion prediction method based on a U-Net structure.

[0012] The present invention adopts the following technical solution: a congestion prediction method for a very large-scale integrated circuit, comprising: inputting a cell distribution feature map (macro_map), a rectangular uniform wire density (Rectangular Uniform wireDensitY, RUDY) distribution map, and a rectangular area pin uniform wire density (pinRUDY) of the integrated circuit to be tested into a congestion prediction model to obtain a congestion distribution map.

[0013] The congestion prediction model adopts a neural network model with a U-Net structure, such as Figure 3 As shown, it includes an encoder and a decoder;

[0014] An encoder module, comprising: a first custom convolutional layer, a first maximum pooling layer, a first hybrid convolutional layer, a second custom convolutional layer, a second maximum pooling layer, a second hybrid convolutional layer, and a first output layer;

[0015] The first custom convolutional layer and the second custom convolutional layer inherit from nn.Module and use the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolutional layer, an instance normalization layer, and a Leaky ReLU activation function;

[0016] The first mixed convolution layer and the second mixed convolution layer perform multi-branch convolution operations, each with 4 convolution kernels, and perform feature learning according to channel averaging;

[0017] The first output layer, inherited from nn.Module, uses the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolutional layer, a batch normalization layer (BatchNorm2d), and a Tanh activation function;

[0018] The decoder includes: a third custom convolution layer, a third mixed convolution layer, a first custom upsampling layer, a fourth custom convolution layer, a fourth mixed convolution layer, a second custom upsampling layer, and a second output layer.

[0019] The encoder and decoder are connected by connecting the output of the first custom convolutional layer in the encoder to the second output layer of the decoder, and the output of the second custom convolutional layer in the encoder to the fourth custom convolutional layer in the decoder.

[0020] The third custom convolutional layer has the same structure as the custom convolutional layer in the fourth custom convolutional layer encoder;

[0021] The first and second custom upsampling layers use the nn.Sequential splicing network structure, which consists of a two-dimensional deconvolution layer nn.ConvTranspose2d, a normalization layer, and a nn.LeakyReLU activation layer.

[0022] The third and fourth hybrid convolutional layers have the same structure as the hybrid convolutional layers in the encoder;

[0023] The second output layer consists of a 2D convolutional layer and a sigmoid activation function.

[0024] Furthermore, the custom convolutional layer adopts an nn.Sequential splicing network structure, including the following six layers in sequence: 2D convolutional layer 1, instance normalization layer 1, leaky ReLU activation layer 1, 2D convolutional layer 2, instance normalization layer 2, and leaky ReLU activation layer 2. The input channels of 2D convolutional layer 1 are the same as those of the custom convolutional layer, and the output channels are determined by the output channels of the custom convolutional layer. The convolution kernel size of this convolutional layer is 3, the stride is 1, and the padding1 is 1. The only difference between 2D convolutional layer 2 and 2D convolutional layer 1 is that the input and output channels of this convolutional layer are the same as the output channels of the custom convolutional layer. The affine parameter of both instantiated layers is True, and a learnable linear transformation is applied to each channel after normalization. The negative_slope and inplace parameters of the two leaky ReLU activation layers are both set to 0.2 and true.

[0025] Furthermore, the encoder and / or decoder further includes a drop layer, which is arranged between any layers, and the drop layer adopts a random deactivation function nn.Dropout().

[0026] Furthermore, the encoder and / or decoder further includes a gradient clipping layer, which is provided between any layers. The gradient clipping layer uses the torch.nn.utils.clip_grad_value_() function in the python library to perform gradient clipping on the model.

[0027] Furthermore, the number of input channels of the first custom convolutional layer is the input feature number 3, and the number of output channels is 32; the number of input channels of the second custom convolutional layer is 32, and the number of output channels is 64; the number of input channels of the first output layer is 64, and the number of output channels is 32; the number of input channels of the third custom convolutional layer is 32, and the number of output channels is 32; the number of input channels of the fourth custom convolutional layer is 80, and the number of output channels is 16; the number of input channels of the second output layer is 36, and the number of output channels is 1.

[0028] Furthermore, both the first maximum pooling layer and the second maximum pooling layer adopt a 2*2 pooling window.

[0029] Furthermore, in the four mixed convolution layers, the channels are divided into four equal parts, and each channel uses four convolution kernels of 3, 5, 7, and 9 respectively; the stride is 1, and the padding is determined by the convolution kernel size, padding = (kernel_size-1) / 2, such as Figure 10 shown.

[0030] Furthermore, the convolution kernel size of the 2D deconvolution layer is 4, the stride is 2, and the padding is 1.

[0031] Furthermore, the neural network model based on the U-Net structure is trained based on open source data, and the unit distribution feature map, RUDY map, and pinRUDY map of the open source integrated circuit obtained using the EDA tool are used as the input of the neural network, and the congestion distribution map of the open source integrated circuit obtained using the EDA tool is used as the input label of the neural network.

[0032] The present invention also provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the above-mentioned prediction method by executing the computer instructions.

[0033] The present invention also provides a computer-readable storage medium, on which computer instructions are stored. The computer instructions are used to enable a computer to execute the above-mentioned prediction method.

[0034] The beneficial effects of the present invention are as follows: Based on the present invention, the time for calculating the congestion distribution of a single chip is about 0.0065s, which is 6 orders of magnitude faster than EDA; the SSIM index is about 0.7935 (nrmse = 0.0045); the prediction accuracy exceeds 80% BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of input feature extraction of the model of the present invention;

[0036] Figure 2 Schematic diagram of a 2-D image after feature conversion as input to the model of the present invention;

[0037] Figure 3 Schematic diagram of the FCN prediction model based on the Unet structure established by the present invention;

[0038] Figure 4 This is a flow chart of the VLSI congestion prediction method based on the U-Net structure of the present invention;

[0039] Figure 5 This is a schematic diagram of the ROC indicator of the model proposed in this invention on the circuitnet-N28 dataset;

[0040] Figure 6 This is a schematic diagram of the macro_map features of a set of data in the test set of the present invention;

[0041] Figure 7This is a schematic diagram of the RUDY characteristics of a set of data in the test set of the present invention;

[0042] Figure 8 This is a schematic diagram of the pinRUDY features of a set of data in the test set of the present invention;

[0043] Figure 9 Schematic diagram of a VLSI congestion prediction device based on the U-Net structure;

[0044] Figure 10 Schematic diagram of the hybrid convolutional layer of the present invention;

[0045] Figure 11 Schematic diagram of the acceleration ratio of the present invention compared with traditional EDA tools and existing models. DETAILED DESCRIPTION

[0046] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0047] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0048] It should be noted that the concepts of "first" and "second" may be mentioned in the present invention only to distinguish different devices, components or parts, and are not used to limit the order or interdependence of the functions performed by these devices, components or parts.

[0049] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative and non-restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, they should be understood as "one or more". "Plurality" should be understood as two or more.

[0050] With the continuous advancement of technology, the complexity of physical design rules, which consist of a series of parameters provided by manufacturers, has increased significantly. Physical design, as the most time-consuming design stage in integrated circuit design, has become more challenging with the emergence of advanced technology nodes. The output results of EDA design tools are used to extract corresponding features, including cell distribution feature maps, rectangular area line density, rectangular area pin line density, and congestion distribution maps. In large and complex chip designs, when calculating the congestion distribution map, EDA tools use advanced algorithms such as heuristic search, simulated annealing, and genetic algorithms to approximate the problem, which often requires longer time (approximately 200 seconds) and higher computing resources.

[0051] Based on this, an embodiment of the present invention provides a congestion prediction method for ultra-large-scale integrated circuits based on a neural network model with a U-Net structure. Through the output of the EDA tool, the unit distribution feature map, the wiring resource demand indicator rectangular area line density, and the rectangular area pin line density map are quickly calculated. Combined with the neural network based on the U-Net structure, a congestion hotspot map is obtained, thereby solving the time-consuming problem of accurately predicting the congestion results of integrated circuits and improving the result quality and execution efficiency of the layout and wiring tools.

[0052] According to an embodiment of the present invention, an embodiment of a congestion prediction method for a very large-scale integrated circuit based on a U-Net structure is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0053] In this embodiment, a congestion prediction method for a very large scale integrated circuit based on a U-Net structure is provided, which can be used for computer equipment such as computers, servers, etc. Figure 4 FIG. 1 is a flow chart of a method for predicting congestion of a very large scale integrated circuit based on a U-Net structure according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0054] Step S101: Model training of a fully convolutional neural network model.

[0055] During the training process, the original data is normalized and converted into a feature map based on two-dimensional tiles for model training. The steps of this embodiment are as follows:

[0056] Step S1011: Generation of data set

[0057] The open-source C906 project, based on the RISC-V architecture, was selected as the base RTL design. This base design consists of a series of RISC-V processing units, a virtual memory management unit (MMU), and corresponding communication interface units. For the digital front-end, the dataset was expanded by adding 1-3 additional SRAM memory cells and macros. Clock constraints were set at 100MHz, 200MHz, and 500MHz. Furthermore, a DC library based on a 55nm process was used for synthesis. To further expand the dataset, three core utilizations (70%, 80%, and 90%) were set during the back-end design process. Five macro placement methods were set using EDA tools, and 16 parameter combinations were selected to generate the corresponding power meshes. Finally, pre-route and post-route fill were performed to expand the dataset. As shown in the summary, the 4*2*3*3*5*16*2 expansion yielded a total of 11,520 sets of back-end placement and routing data. After removing some failed placement combinations, 9,978 sets remained for routing feature extraction, as shown in Table 1.

[0058] Table 1

[0059]

[0060] Step S1012: Feature extraction

[0061] In this project, we mainly extract RUDY, pinRUDY, and macro_map data from each data set, as well as the corresponding congestion status. The entire layout is divided into 256*256 regions, and the extracted feature data is normalized and mapped to the corresponding regions to form a corresponding two-dimensional feature map, which reflects the congestion level of the corresponding region. As is common knowledge in the field, macro_map reflects the distribution of the corresponding logic modules, RUDY reflects the occupancy of the wiring resources of each rectangular block, which is referred to as line density in the following text, and pinRUDY reflects the wiring resources required by the pins, which is referred to as pin line density in the following text.

[0062] The three features of the model are extracted from the output of the corresponding stage of the EDA tool, such as Figure 1 As shown in the figure, the unit distribution feature map (macro_map) is obtained after the layout (floorplan) is completed, and RUDY and pinRUDY come from the wiring (placement) stage. The macro area map (macro_map) reflects the distribution of relative routing resources, such as Figure 2 As shown in .a, the macro coverage area and uncovered area are represented by different grayscale values. RUDY reflects the routing resources of the area, which is related to the routing congestion part. It has a fast acquisition speed and can be directly encoded into a two-dimensional feature map, such as Figure 2As shown in .b. pinRUDY can also be converted into the corresponding two-dimensional feature map, such as Figure 2 .c.

[0063] In addition, if Figure 2 As shown in Figure .d, the congestion labels generated by Cadence Innovus clearly identify potential congestion areas. The red solid boxes highlight the locations where congestion is likely to occur. These locations are Figure 2 The densely populated macros, indicated by the dashed boxes in (a), are highly consistent, demonstrating a trend of congestion clustering in the small gaps between adjacent macros. The remaining few hotspots, as indicated by the purple circles in the figure, are sparsely distributed at the edges of certain macros.

[0064] Step S1013: Model building and training

[0065] The dataset obtained from s1012 was divided into two parts: the first 8,000 groups were used as the training set, and the last 1,978 groups were used as the test set. The training set data was fed into a U-Net model with a variable convolution kernel and trained for 100,000 iterations. In addition, the corresponding model weights were saved every 100 iterations of training.

[0066] The basic structure of U-Net is as follows:

[0067] The encoder module consists of the first custom convolutional layer, the first maximum pooling layer, the first hybrid convolutional layer, the second custom convolutional layer, the second maximum pooling layer, the second hybrid convolutional layer, and the first output layer. The decoder module consists of the third custom convolutional layer, the third hybrid convolutional layer, the first custom upsampling layer, the fourth custom convolutional layer, the fourth hybrid convolutional layer, the second custom upsampling layer, and the second output layer. This model is a fully convolutional neural network model.

[0068] The first custom convolutional layer and the second custom convolutional layer inherit from nn.Module and use the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolutional layer, an instance normalization layer, and a Leaky ReLU activation function;

[0069] The first output layer, inherited from nn.Module, uses the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolutional layer, a batch normalization layer (BatchNorm2d), and a Tanh activation function;

[0070] The third custom convolutional layer has the same structure as the custom convolutional layer in the fourth custom convolutional layer encoder;

[0071] The first and second custom upsampling layers use the nn.Sequential splicing network structure, which consists of a two-dimensional deconvolution layer nn.ConvTranspose2d, a normalization layer, and a nn.LeakyReLU activation layer.

[0072] The third and fourth hybrid convolutional layers have the same structure as the hybrid convolutional layers in the encoder;

[0073] The second output layer consists of a 2D convolutional layer and a sigmoid activation function.

[0074] The encoder and decoder are connected by a jumper, connecting the output of the first custom convolutional layer in the encoder to the second output layer of the decoder, and the output of the second custom convolutional layer in the encoder to the fourth custom convolutional layer of the decoder. The jumper structure splices the feature map of the corresponding encoding layer into the decoding layer to extract and retain detail information and promote feature reuse.

[0075] Four mixed convolution layers perform multi-branch convolution operations, each with 4 convolution kernels, and perform feature learning according to channel averaging. They flexibly learn features under different channels and enhance feature extraction capabilities, such as Figure 10 shown.

[0076] Step S1014: Model prediction

[0077] The weights obtained from model training are called, and the remaining 1978 sets of two-dimensional feature data are used as the output of the model to obtain the congestion hotspot map of each set of congestion data. Compared with the corresponding congestion label map, the corresponding evaluation indicators SSIM, NRMSE, and peakNRMSE are calculated.

[0078] The structural similarity index SSIM is defined as follows:

[0079]

[0080] Among them, μ X and μ Y are the mean values ​​of image X and Y respectively, and are the variances of X and Y respectively, is the covariance between two images. It is based on a k×k sliding window and comprehensively measures the similarity of images from dimensions such as brightness, contrast, and structure. The higher the SSIM value, the higher the structural similarity of the two images, that is, the more similar the images are.

[0081] The normalized mean square error NRMSE is defined as follows:

[0082]

[0083] Among them, y max and y min is the maximum and minimum value of the true value of the image, which is used to normalize the mean square error.

[0084] The peak mean square error (peak NRMSE) is calculated based on the ranking of congestion values ​​in the real congestion map, selecting the top 0.5%, 1%, and 5% of the elements.

[0085] The model parameters obtained after repeated debugging are as follows:

[0086] The number of input channels of the first custom convolutional layer is the input feature number 3, and the number of output channels is 32; the number of input channels of the second custom convolutional layer is 32, and the number of output channels is 64; the number of input channels of the first output layer is 64, and the number of output channels is 32; the number of input channels of the third custom convolutional layer is 32, and the number of output channels is 32; the number of input channels of the fourth custom convolutional layer is 80, and the number of output channels is 16; the number of input channels of the second output layer is 36, and the number of output channels is 1.

[0087] In the four mixed convolution layers, the channels are divided into four equal parts, and each channel uses four convolution kernels of 3, 5, 7, and 9 respectively; the stride is 1, and the padding is determined by the convolution kernel size, padding = (kernel_size-1) / 2, such as Figure 10 shown.

[0088] The first and second max pooling layers both use a 2x2 pooling window. The 2D deconvolution layer has a kernel size of 4, a stride of 2, and a padding of 1.

[0089] To ensure the fairness of the comparison and reflect the advanced nature of the model, we tested it on the open source dataset CircuitNet-N28 and obtained the following results: Figure 5 The ROC indicator diagram shown in the figure shows a significant improvement over the existing model. Considering points with congestion values ​​exceeding 20% ​​as hotspots, the prediction accuracy can exceed 80%. In addition, as shown in Table 2 for the SSIM, NRMSE, and peakNRMSE indicators, the SSIM is improved by more than 2% compared to the existing model. Further testing on the open source dataset ISPD2015 shows that the model's prediction indicators are shown in Table 3, showing a performance improvement of more than 19% compared to the existing model. Figure 11 As shown in the figure, compared with the traditional EDA simulation time, the average acceleration ratio reaches 1231557x, and compared with the traditional model, the acceleration ratio of Congest-Net is 1.8x.

[0090] Table 2

[0091]

[0092] Table 3

[0093]

[0094] Step S102: VLSI congestion prediction based on U-Net structure

[0095] Step S1021: using existing EDA tools to extract a unit distribution feature map, a rectangular uniform line density map, and a rectangular area pin uniform line density map from the floorplan and placement data respectively;

[0096] The rectangular area line density (RUDY) that reflects the wiring resources is as follows: Figure 7 The specific definitions are as follows:

[0097] s k =(min(x k,max ,x i,max )-max(x k,min ,x i,min ))×(min(y k,max ,y i,max )-max(y k,min ,y j,min ));

[0098] s ij =(x i,max -x i,min )×(y j,max -y j,min );

[0099] w k =x k,max -x k,min ;

[0100] h k =y k,max -y k,min ;

[0101]

[0102] Among them, {x k,min ,x k,max ,y k,min ,y k,max} is the bounding box of the given k-th network. Meanwhile, the bounding box of the (i,j)-th tile is given by {x i,min ,x i,max ,y i,min ,y i,max Here, s i,jrepresents the area of ​​cell (i, j), while sk represents the area occupied by network k when covering tile (i, j). Furthermore, RUDY(x, y) is the cumulative RUDY of all nets in the tile.

[0103] The cell distribution feature map macro_map is represented by different grayscale values ​​depending on whether the corresponding tile is covered by the macro. The area covered by the macro in the layout shows the relative wiring resource distribution, such as Figure 6 shown.

[0104] The pin density of the rectangular area, pinRUDY, is calculated based on the individual characteristics of the pins and the network they are connected to, as an analogy for pin density. Specifically, for cell (i, j), the pinRUDY of the pins belonging to network k is calculated as follows:

[0105]

[0106] Among them, w k and h k As shown in the definition of RUDY above, it is the width and height of the k-th network.

[0107] Step S102: Input the unit distribution feature map, rectangular uniform line density map, and rectangular uniform pin line density map into the congestion prediction model to obtain the congestion distribution map. The predicted value and the actual value are as follows: Figure 8 As shown in Figure 2, the congestion hotspots are highly overlapped.

[0108] As common technical means in this field, this project can further utilize methods such as flipping, rotating, scaling, and cropping to expand the dataset, preventing overfitting and improving model generalization. Specifically, a gradient clipping layer is provided in the encoder and / or decoder, positioned between any layers. The gradient clipping layer uses the torch.nn.utils.clip_grad_value_() function in the Python library to perform gradient clipping on the model. And / or a drop layer is provided in the encoder and / or decoder, positioned between any layers. The drop layer uses a random dropout function. In an embodiment of the present invention, network pruning, gradient pruning, and random dropout are used to remove unimportant jumps. Only three jumps are retained: from the first pooling layer in the encoder to the first upsampling layer in the decoder layer, from the second convolutional layer in the encoder layer to the second convolutional layer in the decoder, and from the pooling layer in the second encoder to the second upsampling layer in the decoder. A gradient cap of 1 is set, and the torch.nn.utils.clip_grad_value_() function in Python is used to perform gradient clipping on the model, controlling the gradient within a certain range and making training more stable. Finally, the random dropout function nn.Dropout() is used in the decoder and decoder, and a random dropout layer is added to set the output of some neurons to 0 to increase the generalization ability of the model.

[0109] This embodiment provides a VLSI congestion prediction device based on a U-Net structure. Figure 9 Shown, including:

[0110] Acquisition module A is used to obtain the unit distribution feature map, rectangular uniform line density, and rectangular uniform pin line density of the integrated circuit under test. This module relies on EDA design tools to quickly generate the unit distribution feature map, rectangular uniform line density distribution map, and rectangular uniform pin line density map of the integrated circuit under test.

[0111] Prediction module B is used to calculate the macro_map, RUDY, and pinRUDY graphs using a pre-trained U-Net-based network model, and efficiently output the congestion result graph.

[0112] The embodiment of the present invention also provides a computer device having the above Figure 9The U-Net structure-based ultra-large-scale integrated circuit congestion prediction device shown. The computer device generally includes: one or more processors, memories, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0113] The processor may be a central processing unit, a network processor, or a combination thereof. The processor may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0114] The memory stores instructions that can be executed by at least one processor, so that the at least one processor executes the method shown in the above embodiment.

[0115] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory may include a high-speed random access memory and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory may optionally include a memory remotely located relative to the processor, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0116] The memory may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid state drive; the memory may also include a combination of the above types of memory.

[0117] The computer device also includes an input device and an output device. The processor, memory, input device and output device can be connected via a bus or other means.

[0118] The input device can receive input digital or character information and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touch pad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device can include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0119] The computer device further includes a communication interface for the computer device to communicate with other devices or a communication network.

[0120] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0121] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for predicting congestion in a very large scale integrated circuit, characterized in that: include: Inputting the unit distribution characteristic map, the rectangular uniform line density distribution map and the rectangular area pin uniform line density of the integrated circuit to be tested into the congestion prediction model to obtain a congestion distribution map; The congestion prediction model adopts a neural network model based on a U-Net structure, including an encoder and a decoder; An encoder module, comprising: a first custom convolutional layer, a first maximum pooling layer, a first hybrid convolutional layer, a second custom convolutional layer, a second maximum pooling layer, a second hybrid convolutional layer, and a first output layer; The first custom convolutional layer and the second custom convolutional layer inherit from nn.Module and use the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolutional layer, an instance normalization layer, and a Leaky ReLU activation function; The first mixed convolution layer and the second mixed convolution layer perform multi-branch convolution operations, each with 4 convolution kernels, and perform feature learning according to channel averaging; The first output layer, inherited from nn.Module, uses the nn.Sequential module to generate a serialized convolutional neural network layer; the serialized convolutional neural network layer includes a two-dimensional convolutional layer, a batch normalization layer (BatchNorm2d), and a Tanh activation function; A decoder, comprising: a third custom convolutional layer, a third hybrid convolutional layer, a first custom upsampling layer, a fourth custom convolutional layer, a fourth hybrid convolutional layer, a second custom upsampling layer, and a second output layer; The encoder and decoder are connected by connecting the output of the first custom convolutional layer in the encoder to the second output layer of the decoder, and the output of the second custom convolutional layer in the encoder to the fourth custom convolutional layer in the decoder. The third and fourth custom convolutional layers have the same structure as the custom convolutional layers in the encoder; The first and second custom upsampling layers use the nn.Sequential splicing network structure, which consists of a two-dimensional deconvolution layer nn.ConvTranspose2d, a normalization layer, and a nn.LeakyReLU activation layer. The third and fourth hybrid convolutional layers have the same structure as the hybrid convolutional layers in the encoder; The second output layer consists of a 2D convolutional layer and a sigmoid activation function.

2. A method for predicting congestion of a very large scale integrated circuit according to claim 1, characterized in that: The custom convolution layer adopts the network structure of nn.Sequential splicing, which includes the following 6 layers in sequence: two-dimensional convolution layer 1, instance normalization layer 1, leaky ReLU activation layer 1, two-dimensional convolution layer 2, instance normalization layer 2, and leaky ReLU activation layer 2; the input channel of the two-dimensional convolution layer 1 is the same as the input channel of the custom convolution layer, and the output channel is determined by the output channel of the custom convolution layer. The convolution kernel size of the convolution layer is 3, the stride is 1, and the padding1 is 1; the only difference between the two-dimensional convolution layer 2 and the two-dimensional convolution layer 1 is that the input and output channels of the convolution layer are both the number of output channels of the custom convolution layer; the affine parameters of the two instance normalization layers are both True, and a learnable linear transformation will be applied to each channel after normalization; the negative_slope and inplace parameters of the two leaky ReLU activation layers are both set to 0.2 and true.

3. The method for predicting congestion of a very large scale integrated circuit according to claim 1, wherein: The encoder and / or decoder further includes a drop layer, which is arranged between any layers, and the drop layer adopts a random deactivation function nn.Dropout().

4. The method for predicting congestion of a very large scale integrated circuit according to claim 1, wherein: The encoder and / or decoder further includes a gradient clipping layer, which is provided between any layers. The gradient clipping layer uses the torch.nn.utils.clip_grad_value_() function in the python library to perform gradient clipping on the model.

5. The method for predicting congestion of a very large scale integrated circuit according to claim 1, wherein: The number of input channels of the first custom convolutional layer is the input feature number 3, and the number of output channels is 32; the number of input channels of the second custom convolutional layer is 32, and the number of output channels is 64; the number of input channels of the first output layer is 64, and the number of output channels is 32; the number of input channels of the third custom convolutional layer is 32, and the number of output channels is 32; the number of input channels of the fourth custom convolutional layer is 80, and the number of output channels is 16; the number of input channels of the second output layer is 36, and the number of output channels is 1.

6. The method for predicting congestion of a very large scale integrated circuit according to claim 1, wherein: The first and second maximum pooling layers both use a 2*2 pooling window.

7. The method for predicting congestion of a very large scale integrated circuit according to claim 1, wherein: Four mixed convolution layers divide the channel into four equal parts, and each channel uses four convolution kernels of 3, 5, 7, and 9 respectively; the stride is 1, and the padding is determined by the convolution kernel size, padding = (kernel_size-1) / 2.

8. The method for predicting congestion of a very large scale integrated circuit according to claim 1, wherein: The 2D deconvolution layer has a kernel size of 4, a stride of 2, and a padding of 1, and is normalized using the nn.InstanceNorm2d layer.

9. The method for predicting congestion of a very large scale integrated circuit according to claim 1, wherein: The neural network model based on the U-Net structure is trained based on open source data, including the unit distribution feature map of the open source integrated circuit obtained using the EDA tool, the rectangular uniform line density distribution map and the rectangular area pin uniform line density as the input features of the neural network, and the congestion distribution map of the open source integrated circuit obtained using the EDA tool as the input label of the neural network.

10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 9 by executing the computer instructions.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 9.

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