A method and system for efficient extraction and layout optimization of parasitic inductance parameters

Abstract

This invention belongs to the field of inductance parameter extraction technology, and discloses an efficient method and system for extracting and optimizing the layout of parasitic inductance parameters of power semiconductor modules. Based on the powerful simulation capabilities and co-simulation interfaces of commercial software ANSYS and MATLAB, it achieves efficient interaction of simulation data between software, facilitating the extraction of module parasitic inductance parameters and current sharing characteristics. Utilizing effective algorithms for analyzing parasitic inductance parameters and current sharing characteristics, it provides scientific guidance for optimizing module layout. This invention has the following significant advantages: Compared to the method of "human experience + hardware debugging," this invention adopts efficient simulation development methods, avoiding frequent hardware iterations in the manufacturing and verification stages, reducing development costs, thereby improving the R&D efficiency of multi-chip silicon carbide power modules and better supporting their higher-quality and more flexible development.

Description

Technical Field

[0001] This invention belongs to the field of inductance parameter extraction technology, and particularly relates to an efficient method for extracting and optimizing the layout of parasitic inductance parameters of power semiconductor modules. Background Technology

[0002] Driven by the strategic goals of carbon peaking and carbon neutrality, my country has been vigorously developing a green economy and actively promoting the innovative development of energy-saving and emission-reduction technologies in recent years. Improving energy efficiency and upgrading power conversion technologies are crucial components of this effort. Power semiconductor devices are core components for power conversion, control, and utilization, and their characteristics directly affect the efficiency and reliability of power electronic systems. With the increasing maturity of silicon carbide power devices, represented by SiC MOSFETs, continuous advancements in integrated packaging technology, and the ever-expanding demands for power conversion, silicon carbide power modules have become an important pathway for developing ultra-high power density converter equipment. However, due to the complexity of multi-chip parallel power module design, lengthy process flows, and cumbersome manufacturing verification, development models relying on manual experience and hardware testing are insufficient to meet the design requirements of power devices in terms of parasitic parameter extraction and current sharing characteristics. Furthermore, the use of ANSYS for power semiconductor simulation design suffers from drawbacks such as long simulation times, uncertainties, and complex design processes, making the process equally time-consuming and labor-intensive. Therefore, an accurate and efficient current sharing method for power modules is currently lacking.

[0003] Based on the above analysis, the problems and shortcomings of the existing technology are as follows:

[0004] Traditionally, methods for obtaining the parasitic inductance and current sharing characteristics of power modules have relied heavily on designers' experience combined with hardware testing, or on manually using various finite element and time-domain circuit analysis software. While these methods can accurately obtain the required module parasitic inductance and current sharing characteristics, they are generally insufficient to meet the increasing performance and development time demands of power modules, exhibiting the following problems:

[0005] (1) The initial design and iterative direction selection mainly depend on the designer's experience. Due to the high degree of freedom in power module design, the module layout and electrical parameters are not a simple linear relationship, making it difficult for humans to approach the design limits manually;

[0006] (2) Parameter evaluation requires manual use of various finite element and time-domain circuit analysis software, which involves a large amount of calculation, long time consumption, and high human resource costs. Summary of the Invention

[0007] To address the problems existing in the prior art, this invention provides an efficient method for extracting and optimizing the layout of parasitic inductance parameters of power semiconductor modules.

[0008] This invention provides an efficient method for extracting and optimizing the parasitic inductance parameters of power semiconductor modules. It achieves efficient and accurate design optimization through four main steps. First, in step 1, initial parameters are defined and parasitic inductance is extracted. Advanced simulation tools such as ANSYS Q3D are used to automatically identify the circuit network and initially extract inductance values. Then, in step 2, this simulation data is transferred to the MATLAB environment for further analysis and processing. Step 3 uses an automated ANSYS script to perform re-analysis based on optimization suggestions provided by MATLAB; this automation significantly improves analysis efficiency. Finally, in step 4, the re-analysis results are fed back and iteratively optimized. Advanced optimization techniques such as genetic algorithms are used to adjust the circuit layout to minimize parasitic inductance and improve module performance. This process integrates the latest computing technologies and algorithms, significantly improving the accuracy and efficiency of circuit design and ensuring the high performance and reliability of the final product.

[0009] Furthermore, the initial parameter definition and parasitic inductance extraction method are as follows:

[0010] (1) Design the basic circuit layout;

[0011] (2) Determine the material properties of the power module;

[0012] (3) Arrange the circuit and automatically identify the network;

[0013] First, select the excitation source (SOURCE) and ground (SINK). The specific meaning of each port has been determined during the circuit diagram creation process.

[0014] The automatic network identification function of ANSYS Q3D is used to identify and display the unique electrical path of the model;

[0015] (4) Extract parasitic inductance;

[0016] The circuit is simulated, and its resistance and inductance parameters are extracted.

[0017] Furthermore, the basic circuit layout of the design is as follows:

[0018] 1) Calculation model of packaged parasitic inductance - accumulation method;

[0019] The inductance of a cuboid conductor is:

[0020]

[0021] In the formula, L σ For inductance, H; l R b R h R Let be the length, width, and thickness of the conductor, respectively, in mm; μ0 = 4π × 10⁻⁶ -7H / m is the free permeability;

[0022] The inductance of a long straight conductor is:

[0023]

[0024] In the formula, l L and d L These are the length and diameter of the wire, respectively, in mm; if d L <<l L Then the inductance of a long straight conductor can be expressed as:

[0025]

[0026] When multiple bond wires are connected in parallel, the parasitic inductance of a cluster of bond wires is equivalent to:

[0027]

[0028] In the formula, N is the number of bond lines;

[0029] 2) Parasitic inductance calculation model for rectangular loop encapsulation—magnetic field cancellation method;

[0030] Inductance coefficient λ σ The derivation is as follows:

[0031] The inductance of the closed-loop rectangular circuit is:

[0032]

[0033] In the formula, a C and b C These are the length and width of the rectangle, d. C Let d be the diameter of the conductor, in mm; if d C <<a C and b C It can be simplified to:

[0034]

[0035] In the formula, C C =2(a C +b C ) and S C =a C b C Let be the perimeter and area of ​​the rectangular conductor, respectively; therefore, the open-loop rectangular circuit inductance is:

[0036]

[0037] Inductance coefficient λ of open-loop rectangular circuit σ It can be defined as:

[0038] λσ =C C ln S C -b C [ln(2b C )-1].

[0039] Furthermore, the material properties of the power module are determined as follows:

[0040] The preliminary model generated using SOLIDWORKS is imported into ANSYS. During the simulation, the materials of each part of the circuit are determined, including the bonding wires, DBC, power chip, and busbar.

[0041] Furthermore, the simulation data transmission:

[0042] After extracting the parasitic inductance, the simulation data from ANSYS Q3D is imported into the MATLAB environment by generating a detailed simulation report.

[0043] Furthermore, the ANSYS scripts are automated and reanalyzed:

[0044] Based on the new layout scheme provided by the MATLAB genetic algorithm, ANSYS scripts are automatically written, and these scripts are used to guide ANSYS software to perform a new round of parasitic inductance analysis.

[0045] Another objective of this invention is to provide a highly efficient system for extracting and optimizing the layout of parasitic inductance parameters of power semiconductor modules, comprising:

[0046] The extraction module is used for initial parameter definition and parasitic inductance extraction;

[0047] The data transmission module is used to simulate data transmission.

[0048] Analysis module, used for ANSYS script automation and reanalysis;

[0049] The feedback module is used to feed the results back to MATLAB after the parasitic inductance analysis under the new layout is completed using ANSYS software.

[0050] Another object of the present invention is to provide a computer device, the computer device including a memory and a processor, the memory storing a computer program, the computer program being executed by the processor causing the processor to perform the steps of the method for efficiently extracting and optimizing the parasitic inductance parameters of the power semiconductor module.

[0051] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the method for efficiently extracting and optimizing the parasitic inductance parameters of the power semiconductor module.

[0052] Another objective of this invention is to provide an information data processing terminal, which is used to realize an efficient extraction and layout optimization system for the parasitic inductance parameters of the power semiconductor module.

[0053] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:

[0054] First, this invention leverages the powerful simulation capabilities and co-simulation interfaces of commercial software ANSYS and MATLAB to achieve efficient interaction of simulation data between software programs, facilitating the extraction of parasitic inductance parameters and current sharing characteristics of modules. By employing effective algorithms for analyzing parasitic inductance parameters and current sharing characteristics, it provides scientific guidance for optimizing module layout. This invention has the following significant advantages:

[0055] Compared to the "human experience + hardware debugging" method, this invention adopts efficient simulation development methods, which can avoid frequent hardware iterations in the manufacturing and verification stages, reduce development costs, thereby improving the R&D efficiency of multi-chip silicon carbide power modules and better supporting their higher quality and more flexible development.

[0056] Compared to manually calling analysis software, the real-time interaction between ANSYS and MATLAB not only ensures the accuracy of ANSYS finite element analysis but also leverages MATLAB's ease of use in programming intelligent optimization algorithms and writing objective functions for mathematical models. This real-time interaction saves significant time and manpower, greatly reduces manual intervention, and significantly improves the level of automation and intelligence.

[0057] Secondly, this invention proposes an efficient method for extracting and optimizing the parasitic inductance parameters of power semiconductor modules, solving the problems of low efficiency and insufficient accuracy in the extraction and optimization of parasitic inductance parameters in existing technologies. This method allows for more accurate and efficient extraction and optimization of the parasitic inductance parameters of power semiconductor modules, thereby improving the electrical performance and reliability of the modules.

[0058] The definition of initial parameters and the extraction of parasitic inductance lay the foundation for the entire process. By designing the basic circuit layout, clarifying the material properties of the power module, and automatically identifying the circuit network using simulation software, this stage ensures the targetedness and efficiency of subsequent optimizations. In particular, the calculation of parasitic inductances of conductors with different geometries using the accumulation method and the magnetic field cancellation method provides accurate initial data and theoretical basis.

[0059] The integration of simulation data transfer, automated execution of ANSYS scripts, and reanalysis makes the entire process highly automated, reducing manual intervention and improving the speed and accuracy of data processing. In particular, the use of ANSYS makes the simulation closer to reality, providing more accurate inductance parameter evaluation.

[0060] The results feedback and iterative optimization phase not only optimizes and adjusts the system based on simulation results, but also continuously refines model parameters through iterative processes until the optimal design is achieved. This feedback-based iterative optimization method can significantly improve design efficiency, reduce trial-and-error costs, and accelerate product development cycles.

[0061] This invention significantly improves the accuracy and efficiency of power semiconductor module design by combining a precise parasitic inductance calculation model, an efficient data processing flow, and an intelligent iterative optimization strategy, providing an effective means to enhance the performance and reliability of power semiconductor modules. This not only helps reduce power loss and improve energy efficiency but also promotes the application and development of power semiconductor technology in energy, electronics, and other fields.

[0062] Third, as supplementary evidence of the inventive step of the claims of this invention, it is also reflected in the following important aspects:

[0063] (1) The technical solution of this invention fills a technical gap in the industry both domestically and internationally:

[0064] After more than 40 years of research and development in power devices, the physical properties of Si power modules have approached their physical limits. In recent years, research on SiC advanced semiconductor materials has become a hot research area. SiC advanced semiconductor materials possess superior properties such as higher bandgap, breakdown field strength, and thermal conductivity, bringing hope and opportunities for the development of high-voltage, high-temperature, and high-frequency power devices, and providing technical support for efficient, high-power-density, and high-reliability power conversion. With the increasing maturity of silicon carbide power devices represented by SiC MOSFETs, the continuous progress in integrated packaging technology, and the ever-expanding demand for power conversion, SiC power modules have become an important way to develop ultra-high power-density converter equipment. However, SiC power devices represent a significant breakthrough in the technical system compared to Si power devices, especially in areas such as packaging integration and transient testing, where there is a lack of fundamental theoretical and key technical support. Furthermore, due to the complex design, long process flow, and cumbersome manufacturing verification of multi-chip parallel power modules, the development model relying on manual experience and hardware testing is difficult to meet the design requirements of SiC power devices in terms of parasitic parameter extraction and current sharing characteristics. Regarding simulation systems, considering the drawbacks of using ANSYS to simulate the design of power semiconductors, such as long simulation time, complex design process, and large uncertainty of simulation results, the simulation process is also time-consuming and labor-intensive. Therefore, there is still a lack of accurate and efficient current sharing methods for power modules.

[0065] Based on the current state of technology and research challenges in the domestic and international industry, this invention aims to develop a fast, accurate, efficient, and automated co-simulation system to fill the gap in the simulation of parasitic parameters in SiC multi-chip parallel power semiconductors. This invention leverages the powerful simulation capabilities and co-simulation interfaces of two major commercial software programs, ANSYS and MATLAB. It researches and develops real-time interactive functions between ANSYS and MATLAB, fully utilizing ANSYS's script recording and script simulation capabilities. This allows for the establishment of an ANSYS-MATLAB interactive simulation bridge through readable script code, significantly improving the directionality, controllability, and readability of simulation control. Developers can easily communicate simulation objectives to ANSYS via MATLAB using this invention. Parameter extraction and layout optimization schemes for power modules can be controlled through concise MATLAB code. The entire simulation system iterates until the functional requirements of the module are met. This invention fully utilizes the precision of ANSYS in the field of finite element analysis and the ease of programming intelligent optimization algorithms and writing mathematical model objective functions in MATLAB. The real-time interaction between the two greatly improves the automation and intelligence of power module parasitic parameter extraction, avoids frequent hardware iterations in the power module manufacturing and verification process, significantly reduces development costs, saves a lot of time and human resources, and significantly reduces manual intervention.

[0066] Based on this invention, the research on parameter extraction and layout optimization of power modules will be supported by a more efficient, convenient, high-quality and flexible simulation method. This provides important basic technical support for research directions such as obtaining the current sharing characteristics of power modules and improving the layout of power modules in more advanced and highly applicable fields.

[0067] (2) The technical solution of the present invention solves a technical problem that people have long wanted to solve but have never been able to solve successfully:

[0068] Previous development methods could also achieve virtual iterative design of power modules with the help of digital software, but they still relied heavily on the designer's experience and had the following limitations:

[0069] 1) Parameter evaluation requires manual use of various finite element simulation analysis software, which involves a large amount of calculation, is time-consuming, and has high human resource costs.

[0070] 2) Both the initial design and the choice of iterative direction depend on the designer's experience. Due to the high degree of freedom in power module design and the influence of high-frequency switching excitation and coupling effects, the module layout and parameters are not a simple linear relationship, making it difficult for humans to approach the design limits.

[0071] 3) Traditional simulation methods struggle to handle multi-objective problems and produce limited results. Because there are various trade-offs between power module design objectives, and different applications have different requirements for parasitic parameter trade-offs, traditional simulation methods typically require iterative updates when updating design objectives, resulting in low design flexibility.

[0072] In summary, developers have traditionally relied on a combination of manual experience and hardware testing, or manually using various finite element and time-domain circuit analysis software, to obtain the parasitic inductance and current sharing characteristics of power modules. While these methods can accurately obtain the required module parasitic inductance and current sharing characteristics, they are generally insufficient to meet the ever-increasing performance and development time demands of power modules. The industry urgently needs flexible, efficient, and comprehensive digital design tools.

[0073] This invention solves the above-mentioned technical problems in the following three aspects:

[0074] 1) Power module parameter evaluation and layout optimization no longer require manual invocation of multiple finite element simulation analysis software. The ANSYS-MATLAB co-simulation method developed in this invention can achieve fully automatic simulation analysis in a directional manner after specifying the power module layout optimization target, until the developer's design requirements are met, which greatly saves experimental links, experimental time and human resources.

[0075] 2) The ANSYS-MATLAB co-simulation method developed in this invention can rely entirely on digital algorithms to select the direction of module layout iteration, achieving fully digital design and eliminating reliance on the designer's experience. Digital algorithms have unparalleled advantages over human experience in high-degree-of-freedom and nonlinear problems. In fields such as power module layout design, where it is difficult to approach the design limits manually, developers can use digital algorithms to transform the design objectives into lines of visually readable digital algorithms (such as genetic algorithms, particle swarm optimization, or simulated annealing algorithms) in MATLAB. MATLAB can then guide ANSYS step by step according to the algorithm to extract parasitic parameters and improve the module layout. The two interact and iterate cyclically to ultimately solve high-degree-of-freedom nonlinear problems such as power module design.

[0076] 3) This invention can also effectively solve the multi-objective collaborative planning problem frequently encountered in power module parameter extraction and layout design. A major technological innovation of this invention is the use of MATLAB to write digital intelligent algorithms to guide the simulation process, especially in multi-objective collaborative planning problems, where its importance is particularly evident. For example, the application of the NSGA-II algorithm in the multi-objective collaborative design of power modules allows the computer to meticulously analyze the design objectives and mechanisms using digital algorithms, finding the appropriate design direction. Traditional design methods relying on human experience often suffer from problems such as long processing times, low efficiency, and rigid design processes when dealing with multi-objective collaborative design problems. The ANSYS-MATLAB co-simulation method developed in this invention significantly addresses the industry's predicament in simulation design due to its advantages of fewer steps, higher efficiency, and flexible development.

[0077] Fourth, the present invention provides an efficient method for extracting and optimizing the parasitic inductance parameters of power semiconductor modules, which solves the technical problems of low extraction efficiency, insufficient accuracy, and inadequate layout optimization in existing technologies, and has achieved significant technological progress in industrial applications. The core technical features of the present invention and its industrial application effectiveness are analyzed in detail below.

[0078] The existing technical problem to be solved:

[0079] 1. Low extraction efficiency:

[0080] In traditional methods, the extraction of parasitic inductance parameters often relies on manual measurement or simple circuit simulation, which is inefficient and cannot quickly adapt to the design requirements of complex circuits.

[0081] This invention improves efficiency by combining automated scripts with simulation tools (such as ANSYS Q3D) to automatically identify circuit networks and extract inductance parameters.

[0082] 2. Insufficient accuracy:

[0083] Traditional extraction methods fail to accurately simulate circuit behavior under actual working conditions, resulting in deviations between the extracted inductance parameters and actual application scenarios.

[0084] By implementing physical model-based simulations (using SOLIDWORKS and ANSYS to simulate material properties and geometry in detail), this invention ensures the accuracy and reliability of the extracted parameters.

[0085] 3. Insufficient layout optimization:

[0086] Traditional layout design often relies on the designer's experience and intuitive judgment, lacking a systematic optimization process.

[0087] This invention utilizes a genetic algorithm in MATLAB to automatically generate an optimized layout, which is then verified and analyzed again using ANSYS to ensure the optimal circuit layout and the lowest parasitic inductance.

[0088] Technological advancements in industrial applications:

[0089] 1. Automation and high efficiency:

[0090] Automated design and parameter extraction processes significantly reduce the time from design to verification, thereby greatly shortening the product development cycle and improving R&D efficiency and market responsiveness.

[0091] It is suitable for rapid iteration and optimization in high-volume production, and is especially important in the power electronics industry.

[0092] 2. Improve design accuracy and reliability:

[0093] Accurate simulation analysis helps designers understand and optimize the effects of inductance in circuits, thereby enabling the design of more efficient and stable power semiconductor modules.

[0094] This directly improves the performance and reliability of the final product, and reduces power loss and failure rate.

[0095] 3. Significant cost-effectiveness:

[0096] By optimizing circuit layout and reducing unnecessary design iterations, material and manufacturing costs were significantly reduced.

[0097] Automated and efficient design processes reduce labor and time costs, bringing greater economic benefits to enterprises.

[0098] 4. Scalability and flexibility:

[0099] The method provided by this invention can be widely applied to the design of different types of power semiconductor modules and has good scalability.

[0100] It supports rapid adaptation to and implementation of new design requirements and technological changes, enhancing the company's competitiveness in a highly competitive market.

[0101] This invention, by combining advanced simulation technology and automated scripts, not only solves the efficiency and accuracy problems of traditional methods, but also achieves significant technological progress in the power semiconductor industry, providing an efficient, accurate and economical solution for parasitic inductance parameter extraction and layout optimization. Attached Figure Description

[0102] Figure 1 This is a flowchart of a method for efficient extraction and layout optimization of parasitic inductance parameters of power semiconductor modules provided in an embodiment of the present invention.

[0103] Figure 2 This is a block diagram of the system structure for efficient extraction and layout optimization of parasitic inductance parameters of power semiconductor modules provided in this embodiment of the invention.

[0104] Figure 3 This is an optimized circuit blueprint provided in an embodiment of the present invention.

[0105] Figure 4 This is a SOILEWORKS model diagram provided in the embodiments of the present invention.

[0106] Figure 5 This is a material property diagram of the power module provided in an embodiment of the present invention.

[0107] Figure 6 The present invention provides a method for selecting excitation sources and grounds. Indication picture.

[0108] Figure 7 This is an automatically identified network diagram provided in an embodiment of the present invention.

[0109] Figure 8 This is the parasitic inductance extraction diagram provided in the embodiments of the present invention.

[0110] Figure 9 This is a power semiconductor model diagram provided in an embodiment of the present invention.

[0111] Figure 10 This is a diagram showing the preparation of ANSYS and MATLAB interaction provided in an embodiment of the present invention.

[0112] Figure 11 This is the first iteration diagram that begins after running the circle function, as provided in this embodiment of the invention.

[0113] Figure 12 This is a diagram showing the first iteration nearing completion, provided in an embodiment of the present invention.

[0114] Figure 13 This is a power semiconductor model diagram with 10 iterations provided in an embodiment of the present invention.

[0115] Figure 14 This is the method for generating the ACfiter.tab diagram provided in this embodiment of the invention.

[0116] Figure 15 This is a line graph generated according to an embodiment of the present invention.

[0117] Figure 16 This is a schematic diagram of the current sharing characteristics of the circuit provided in an embodiment of the present invention. Detailed Implementation

[0118] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0119] The efficient extraction and layout optimization method for parasitic inductance parameters of power semiconductor modules of the present invention can be widely applied to different types of power electronic devices. The following are two specific application examples illustrating how the present invention can be applied to practical industrial design.

[0120] Application Example 1: Power Module Design in Electric Vehicle Drive System

[0121] In the drive system of electric vehicles, the power module is one of the key components, and its performance directly affects the efficiency and reliability of the electric motor. Electric vehicle power modules need to handle high voltage and high current, therefore optimizing their internal parasitic inductance is crucial to reduce switching losses and improve response speed.

[0122] Implementation method:

[0123] 1. Design basic circuit layout: Use SOLIDWORKS to design the preliminary physical structure of the power module, including IGBTs, diodes, conductive paths, etc.

[0124] 2. Determine material properties: Select suitable materials (such as silicon carbide) to ensure the stability of the module under high temperature and high pressure environments.

[0125] 3. ANSYS Q3D Simulation: Import the design into ANSYS Q3D and use the software to automatically identify the circuit network and extract parasitic inductance.

[0126] 4. MATLAB Optimization: Import the extracted data into MATLAB and use a genetic algorithm to optimize the circuit layout, attempting to reduce parasitic inductance.

[0127] 5. Re-simulation and physical testing: Adjust the ANSYS model according to the suggestions after MATLAB optimization, perform simulation verification, manufacture a prototype, and conduct real vehicle testing.

[0128] The optimized power module demonstrated lower heat loss and higher power output efficiency in real vehicle testing, effectively extending the driving range and battery life of electric vehicles.

[0129] Application Example 2: Power Module Optimization of Solar Inverters

[0130] A solar inverter converts direct current (DC) from solar panels into alternating current (AC) that can be supplied to the power grid. Within the inverter, the efficiency and stability of the power modules determine the overall system performance and energy conversion efficiency.

[0131] 1. Circuit Design: Design a complex circuit that includes multiple switches and filters to ensure it can handle the large variations in DC input from the solar panel.

[0132] 2. Material selection and simulation: Select semiconductor materials suitable for high-frequency switching and set the corresponding physical properties in ANSYS.

[0133] 3. Automatic identification and parasitic inductance extraction: The parasitic inductance of the circuit is extracted using the automatic network identification function of ANSYS Q3D, and preliminary simulation is performed.

[0134] 4. Layout optimization: Utilize algorithms in MATLAB to analyze circuit layout, optimize wire layout and component positions to reduce parasitic inductance.

[0135] 5. Verification and Implementation: Adjust the design and re-simulate in ANSYS. After confirming the reduction in inductance, manufacture test units and conduct performance tests in actual solar energy systems.

[0136] Through optimization, the new solar inverter power module exhibits higher energy efficiency and lower heat loss, improving the reliability and economy of the entire system and reducing operating costs.

[0137] like Figure 1 As shown in the figure, the efficient extraction and layout optimization method for parasitic inductance parameters of a power semiconductor module provided by this embodiment of the invention includes the following steps:

[0138] S101, Initial parameter definition and parasitic inductance extraction;

[0139] S102, Simulation data transmission;

[0140] S103, ANSYS Script Automation and Reanalysis;

[0141] S104, Result Feedback and Iterative Optimization.

[0142] The initial parameter definition and parasitic inductance extraction method provided in this embodiment of the invention are as follows:

[0143] (1) Design the basic circuit layout;

[0144] (2) Determine the material properties of the power module;

[0145] (3) Arrange the circuit and automatically identify the network;

[0146] First, select the excitation source (SOURCE) and ground (SINK). The specific meaning of each port has been determined during the circuit diagram creation process.

[0147] The automatic network identification function of ANSYS Q3D is used to identify and display the unique electrical path of the model;

[0148] (4) Extract parasitic inductance;

[0149] The circuit is simulated, and its resistance and inductance parameters are extracted.

[0150] The basic circuit layout provided in this embodiment of the invention is as follows:

[0151] 1) Calculation model of packaged parasitic inductance - accumulation method;

[0152] The inductance of a cuboid conductor is:

[0153]

[0154] In the formula, L σ For inductance, H; l R b R h R Let be the length, width, and thickness of the conductor, respectively, in mm; μ0 = 4π × 10⁻⁶ -7 H / m is the free permeability;

[0155] The inductance of a long straight conductor is:

[0156]

[0157] In the formula, l L and d L These are the length and diameter of the wire, respectively, in mm; if d L <<l L Then the inductance of a long straight conductor can be expressed as:

[0158]

[0159] When multiple bond wires are connected in parallel, the parasitic inductance of a cluster of bond wires is equivalent to:

[0160]

[0161] In the formula, N is the number of bond lines;

[0162] 2) Parasitic inductance calculation model for rectangular loop encapsulation—magnetic field cancellation method;

[0163] Inductance coefficient λ σ The derivation is as follows:

[0164] The inductance of the closed-loop rectangular circuit is:

[0165]

[0166] In the formula, aC and b C These are the length and width of the rectangle, d. C Let d be the diameter of the conductor, in mm; if d C <<a C and b C It can be simplified to:

[0167]

[0168] In the formula, C C =2(a C +b C ) and S C =a C b C Let be the perimeter and area of ​​the rectangular conductor, respectively; therefore, the open-loop rectangular circuit inductance is:

[0169]

[0170] Inductance coefficient λ of open-loop rectangular circuit σ It can be defined as:

[0171] λ σ =C C lnS C -b C [ln(2b C )-1].

[0172] The invention provides methods for determining the material properties of a power module:

[0173] The preliminary model generated using SOLIDWORKS is imported into ANSYS. During the simulation, the materials of each part of the circuit are determined, including the bonding wires, DBC, power chip, and busbar.

[0174] The simulation data transmission provided in this embodiment of the invention:

[0175] After extracting the parasitic inductance, the simulation data from ANSYS Q3D is imported into the MATLAB environment by generating a detailed simulation report.

[0176] The ANSYS script automation and reanalysis provided in this embodiment of the invention:

[0177] Based on the new layout scheme provided by the MATLAB genetic algorithm, ANSYS scripts are automatically written, and these scripts are used to guide ANSYS software to perform a new round of parasitic inductance analysis.

[0178] like Figure 2 As shown in the figure, an efficient extraction and layout optimization system for parasitic inductance parameters of a power semiconductor module provided by an embodiment of the present invention includes:

[0179] The extraction module is used for initial parameter definition and parasitic inductance extraction;

[0180] The data transmission module is used to simulate data transmission.

[0181] Analysis module, used for ANSYS script automation and reanalysis;

[0182] The feedback module is used to feed the results back to MATLAB after the parasitic inductance analysis under the new layout is completed using ANSYS software.

[0183] An embodiment of the present invention provides a computer device, the computer device including a memory and a processor, the memory storing a computer program, and when the computer program is executed by the processor, the processor performs the steps of the method for efficient extraction and layout optimization of parasitic inductance parameters of the power semiconductor module.

[0184] The present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the method for efficiently extracting and optimizing the parasitic inductance parameters of the power semiconductor module.

[0185] This invention provides an information data processing terminal, which is used to realize an efficient extraction and layout optimization system for parasitic inductance parameters of the power semiconductor module.

[0186] In the field of electromagnetic simulation and optimization, effective parasitic inductance minimization strategies are crucial for improving the performance of electronic devices. This study employs a method combining ANSYS Q3D and MATLAB, using a genetic algorithm to optimize parasitic inductance, thereby achieving more efficient circuit design. The specific process is as follows:

[0187] Step 1: Initial Parameter Definition and Parasitic Inductance Extraction

[0188] First, in ANSYS Q3D, parasitic inductance is extracted based on the given initial layout. Through accurate simulation, the parasitic inductance value of the circuit under a specific configuration can be obtained.

[0189] The specific process for achieving this goal is as follows:

[0190] 1. Design the basic circuit layout

[0191] It should be noted that this algorithm optimizes an existing circuit layout; therefore, the reference circuit for optimization is essential. This project utilizes the following computational model to design the circuit:

[0192] 1.1 Calculation Model of Package Parasitic Inductance - Accumulation Method

[0193] When a power semiconductor module is operating, the current commutation path is irregular, and both the DBC copper layer and the bonding wires contribute parasitic inductance. A calculation model for the parasitic inductance of the DBC copper layer and bonding wires is derived, the inductance value of each region is calculated, and then summed to obtain the parasitic inductance value of the entire power circuit.

[0194] By treating the DBC copper layer as a cuboid conductor and the bonding wire as a long straight wire, a calculation model for packaged parasitic inductance can be established based on the parasitic inductance of a regular conductor.

[0195] The inductance of a cuboid conductor is

[0196]

[0197] In the formula, L σ For inductance, H; l R b R h R Let be the length, width, and thickness of the conductor, respectively, in mm; μ0 = 4π × 10⁻⁶ -7 H / m is the permeability of free space.

[0198] The inductance of a long straight conductor is

[0199]

[0200] In the formula, l L and d L Let d be the length and diameter of the wire, respectively, in mm. If d L <<l L Then the inductance of a long straight conductor can be expressed as:

[0201]

[0202] When multiple bond wires are connected in parallel, the parasitic inductance of a cluster of bond wires is equivalent to...

[0203]

[0204] In the formula, N is the number of bond lines.

[0205] The summation method uses simplifying assumptions and has poor accuracy, but it is fast and suitable for quickly evaluating the parasitic inductance of modules. The ANSYS Q3D finite element method, introduced later, offers the most accurate simulation, but its computation time is long, making it less suitable for rapid iteration in module design.

[0206] 1.2 Parasitic Inductance Calculation Model for Rectangular Loop Encapsulation—Magnetic Field Destruction Method

[0207] In power module design, sometimes it is only necessary to quickly assess the relative magnitude of parasitic inductance without calculating its specific value. Therefore, the inductance coefficient λ can be defined. σ The derivation is as follows:

[0208] The inductance of the closed-loop rectangular circuit is

[0209]

[0210] In the formula, a C and b C These are the length and width of the rectangle, d. C Let d be the diameter of the conductor, in mm. C <<a C and b C It can be simplified to

[0211]

[0212] In the formula, C C =2(a C +b C ) and S C =a C b C These are the perimeter and area of ​​the rectangular conductor, respectively. Therefore, the inductance of the open-loop rectangular circuit is...

[0213]

[0214] Inductance coefficient λ of open-loop rectangular circuit σ Can be defined as

[0215] λ σ =C C ln S C -b C [ln(2b C )-1]

[0216] This coefficient is proportional to the parasitic inductance. It is a practical and quick method for projects with many power loops where the actual inductance value is sometimes irrelevant.

[0217] Considering the two calculation methods above, our team referenced various methods for reducing inductance and sharing current, such as multiple commutation loops, symmetrical terminal layouts, and interconnection comparisons. After much deliberation, the final circuit diagram adopted a symmetrical two-terminal layout, symmetrically arranging DC power terminals to achieve two-terminal circulating current, thereby reducing the difference between parasitic inductance and parallel inductance. The circuit schematic used for optimization is shown below. Figure 3 As shown, the SOLIDWORKS model is as follows: Figure 4 As shown, SOLIDWORKS modeling will use this circuit schematic as a reference, and all subsequent algorithms will be based on the above circuit.

[0218] 2. Determine the material properties of the power module

[0219] The preliminary model generated using SOLIDWORKS is then imported into ANSYS. Figure 5 The process of determining the materials of each part of the circuit during simulation is shown. The parts that need to be determined can be mainly divided into bonding wires, DBCs, power chips, and busbars.

[0220] The bonding wire material can be selected from gold, copper, silver, and aluminum. Among them, gold wire has the best conductivity, but its high price makes it difficult to use in general applications and is not considered. Copper is more economical, but its rigidity is too strong, and a protective gas must be added during use. Its reliability is not as good as aluminum wire. Silver is mainly used in special parts such as LEDs. Under normal use, its other performance indicators are not as good as the other three metals. Aluminum wire has low consumable cost, short welding time, can withstand high current, and has low requirements for the surface of the welding metal. It has many advantages. Considering all these factors, aluminum was finally selected as the bonding wire material.

[0221] The material selection for the DBC (Digital Circuit Board) also involved careful consideration. Since aluminum was chosen for the bonding wires, adding aluminum to the DBC surface was the initial consideration. However, a review of typical power semiconductor material selection reveals a common three-layer structure: copper-ceramic-copper. The two metals have similar conductivity, copper has high hardness to ensure the mechanical strength of the DBC, and good thermal conductivity. Since the copper-covered DBC surface forms the core of the circuit, aluminum's heat dissipation performance is insufficient for high currents. The ceramic layer is added in the middle to increase electrical insulation and ensure normal circuit operation. Therefore, the model was modified, changing the bottom layer to three layers and selecting a copper-ceramic-copper material.

[0222] The choice of materials for busbars is very similar to that for DBCs. Because busbars are a major part of the circuit and need to carry large currents, both conductivity and thermal conductivity need to be carefully considered. At the same time, the position of the busbar requires it to have high rigidity. Therefore, copper is clearly more suitable than aluminum, and copper is chosen as the material for busbars.

[0223] The materials used in power chips are complex, and using only one material inevitably introduces errors. However, their internal structures are too intricate, and detailed modeling and simulation after a thorough understanding would be too laborious and impractical. Through literature review and extensive discussion, our team chose silver as the primary material for power chips because silver is mainly used for chip interconnects, and its electromagnetic distribution is similar to that of the chip itself.

[0224] 3. Arrange the circuit and automatically identify the network.

[0225] First, the excitation source (SOURCE) and ground (SINK) are selected. The specific meaning of each port has been determined during the circuit diagram creation process; here, it is simply represented on the model. Subsequently, ANSYS Q3D's automatic network identification function is used to identify and display the unique electrical path in the model, ensuring the model's correctness and preparing for subsequent simulation studies. The specific process is as follows: Figure 6 , 7 As shown, this step will not be repeated in subsequent loops.

[0226] 4. Extracting parasitic inductance

[0227] Based on the previous preparations, the circuit was simulated, and the resistance and inductance parameters of the circuit were extracted. The specific process is as follows: Figure 8 As shown.

[0228] Step 2: Simulation Data Transfer

[0229] After extracting the parasitic inductance, a detailed simulation report was generated, and the simulation data from ANSYS Q3D was imported into the MATLAB environment. This process ensured seamless data transfer and laid the foundation for further data analysis and processing.

[0230] Specifically, the extracted data is first exported from ANSYS Q3D. After exporting, the file is read using MATLAB to obtain the corresponding parasitic inductance data.

[0231] In the script,

[0232] oEditor.CreateRelativeCS Array("NAME:RelativeCSParameters","Mode:=","Axis / Position","OriginX:=",_"29.100000000mm","OriginY:=","0.000000000mm","OriginZ:=",_"14. 000000000mm","XAxisXvec:=","1mm","XAxisYvec:=","0mm","XAxisZvec:=", _"0mm","YAxisXvec:=","0mm","YAxisYvec:=","1mm","YAxisZvec:=","0mm"),

[0233] Array("NAME:Attributes","Name:=",_"RelativeCS27_1")

[0234] In actual ANSYS operation, the relative coordinate system origin RelativeCS is moved from the original origin by a distance of OriginX = 29.100000000mm in the X direction, a distance of OriginY = 0.000000000mm in the Y direction, and a distance of OriginZ = 14.000000000mm in the Z direction, and the new relative coordinate system is named RelativeCS27_1.

[0235] oEditor.Rotate Array("NAME:Selections", "Selections:=", "wirebond_MOSlower","NewPartsModelFlag:=", _"Model"),Array("NAME:RotateParameters","RotateAxis:=","Y","RotateAngle:=","2deg")

[0236] This corresponds to the actual operation in ANSYS: "Rotate the wirebond_MOSlower device by 2° with RelativeCS27_1 as the origin and the Y-axis as the rotation axis".

[0237] Set oModule=oDesign.GetModule("AnalysisSetup")

[0238] oModule.EditSetup"Setup1",Array("NAME:Setup1","AdaptiveFreq:=","1MHz","SaveFields:=",_false,"Enabled:=",true,Array("NAME:AC","MaxPass:=",10,"MinPass:=",1,"MinConvPass:=",_

[0239] 1,"PerError:=",1,"PerRefine:=",30),"EnableTransitionRegionSolve:=",false,"ErrorValue:=",_"0.1")

[0240] oModule.EditSetup"Setup1",Array("NAME:Setup1","AdaptiveFreq:=","1MHz","SaveFields:=",_false,"Enabled:=",true,Array("NAME:AC","MaxPass:=",10,"MinPass:=",1,"MinConvPass:=",_

[0241] 1,"PerError:=",1,"PerRefine:=",30),"EnableTransitionRegionSolve:=",false,"ErrorValue:=",_"0.1")

[0242] In actual ANSYS operation, this corresponds to "setting Setup1 to a simulation frequency of 1MHz, not retaining the field conditions, using AC simulation mode, with a maximum number of iterations of 10 and a minimum number of iterations of 1, etc."

[0243] oProject.Save

[0244] oDesign.Analyze"Setup1"

[0245] Set oModule=oDesign.GetModule("ReportSetup")

[0246] oModule.CreateReport"ACL Matrix Table 1","Matrix","Data Table",_"Setup1:LastAdaptive",Array("Context:=","Original"),Array("Freq:=",Array(_"All")),Array("X Component:=","Freq","YComponent:=",Array(_"abs(ACL(BusBar:Source1,BusBar:Source1))"))

[0247] In actual ANSYS operation, this corresponds to "creating a simulation report ACL Matrix Table 1, plotting with Freq (frequency) as the X-axis and abs(ACL(BusBar:Source1,BusBar:Source1) (absolute value of the obtained ACL) as the Y-axis".

[0248] oModule.ExportToFile"ACL Matrix Table 1",dir+fname,false

[0249] This corresponds to "Storing the results ACL Matrix Table 1 in dir+fname" in actual ANSYS operation.

[0250] The above analysis shows that ANSYS's script recording function provides a medium for ANSYS to interact with the outside world. These specific statements can be rewritten using software such as MATLAB and controlled by the MATLAB main function, thus enabling automated iteration of ANSYS.

[0251] Step 3: ANSYS Script Automation and Reanalysis

[0252] Based on the new layout scheme provided by the MATLAB genetic algorithm, ANSYS scripts were automatically written, and these scripts were used to guide ANSYS software in a new round of parasitic inductance analysis. This step not only demonstrates the powerful capabilities of cross-platform automated scripts, but also provides an experimental basis for further optimization.

[0253] Receiving data from ANSYS using MATLAB is a simple process, but controlling ANSYS with MATLAB is a relatively complex task. Specifically, it involves two steps: writing the script and executing the script. Writing the script is the most complex part. The script needs to consider the three main functions required of ANSYS: model modification, determination of simulation parameters, and starting the simulation. The steps of determining simulation parameters and starting the simulation are relatively simple to write; the content can be directly written into a script file.

[0254] In this model, modifications only involve rotating the model. To achieve this, all factors related to model rotation are considered: the object to be rotated, the reference coordinate axis, the direction of rotation, and the angle of rotation. To allow for flexible model modification based on the needs of the genetic algorithm, a `position_change` function is created, aiming to rotate the model using only the above parameters. Essentially, the `position_change` function translates the algorithm's requirements into a script. During its development, it was noted that the script uses displacement values ​​in the X, Y, and Z directions to determine the new coordinate position, the model name to identify the object to be rotated, the Y-axis orientation to determine the direction of rotation, and the `deg` value to determine the angle of rotation. After considering the above conditions, we first need to translate the two elements: the object to be rotated and the new coordinate position. To make the `position_change` function more concise, we first use the two parameters `bondLineX` and `bondLineY` to determine the name of the target to be rotated and the position of the rotation coordinate system, i.e., the actual coordinates in the X, Y, and Z directions. Determining the name of the target to be rotated using two parameters is achievable; we simply need to create a two-dimensional array and use the target name as the array content. Since bond line rotation always uses its vertical portion as the rotation axis, we can use the vertical portion as the Y-axis, while keeping the X and Z axes unchanged from the initial coordinate system. This achieves the determination of the position of the rotation coordinate system, a function implemented in the `trans` and `findparameters` functions. However, simply determining the position of the rotation coordinate system is insufficient; we also need to create the `Moving_RelativeCS` function to calculate the displacement values ​​in the X, Y, and Z directions. After completing this translation, the rotation angle can be directly input into the function, and the Y-axis direction can be determined according to the actual rotation requirements. It is worth mentioning that because the Y-axis direction has continuity, if the Y-axis direction is negative, it needs to be changed back to positive after the rotation operation.

[0255]

[0256]

[0257]

[0258]

[0259]

[0260]

[0261] The script is as follows:

[0262]

[0263]

[0264]

[0265]

[0266]

[0267]

[0268]

[0269] Step 4: Results Feedback and Iterative Optimization

[0270] After ANSYS software completes the parasitic inductance analysis under the new layout, it feeds the results back to MATLAB. Then, steps one through three are repeated to enter the next iteration loop. This functionality is achieved using the `circle` function. By opening the blueprint script and writing a new script by comparing strings, it's possible to rotate any one of the 18 bond wires of the power semiconductor at any angle. The newly written script is then run using the command `system("script.vbs")` to perform the iteration. Through continuous iterative optimization, the goal of minimizing parasitic inductance is gradually approached until the design requirements are met.

[0271] This entire process embodies an efficient cross-platform collaborative approach, combining Ansys Q3D's powerful electromagnetic field simulation capabilities with MATLAB's strengths in data processing and algorithm optimization, providing a new solution for the field of electromagnetic design. Through this method, researchers can more accurately optimize circuit layout, significantly improving the performance and reliability of electronic devices.

[0272] 1. Model and Algorithm Preparation

[0273] Figure 9 Power semiconductor model (open with ANSYS Q3D)

[0274] Figure 10 Preparation for ANSYS and MATLAB Interaction

[0275] 2. Run the circle function

[0276] This design iteration involved 10 iterations. The upper MOSFET chip bond wires (only those that will not overlap with other bond wires during rotation, 6 wires in total) were moved counterclockwise by 2, and the lower MOSFET chip bond wires (12 wires in total) were moved counterclockwise by 3. After running the circle function, as shown... Figure 15 , 16As shown, the extraction of parasitic parameters for the first iteration begins.

[0277] 3. Results Analysis

[0278] After 10 iterations, the parasitic inductance data generated during the process is stored in ACLiter.tab. The parasitic inductance values ​​for each of the 10 iterations are as follows (unit: nH): 23.2489724983880 23.2494181170317 23.2619612881619 23.2610695565155 23.2772267075122 23.2874682288847 23.2980907281830 23.3122255214713 23.3213010685666 23.3418138606642

[0289] The generated line graph shows that the power semiconductor module has the minimum parasitic inductance in the first iteration. Specifically, the minimum parasitic inductance (23.2489724983880 nH) is achieved when the upper MOSFET chip bond wires (only those that do not overlap with other bond wires during rotation, totaling 6 wires) move counterclockwise by 2 units, and the lower MOSFET chip bond wires (12 wires) move counterclockwise by 3 units. Furthermore, the parasitic inductance generally exhibits a monotonically increasing trend as the angle gradually increases. To further obtain the minimum parasitic inductance, the bond wires to be rotated each time can be actively selected, continuously refining the rotation angle until a better result is obtained.

[0290] Driven by the long-term dual-carbon strategy, carbon reduction applications such as new energy power generation, high-efficiency power supply, and electrified transportation are steadily growing, leading to a continuous transformation of next-generation high-capacity power conversion equipment towards greater compactness, efficiency, and reliability. With the increasing maturity of silicon carbide power devices represented by SiC MOSFETs, the continuous advancement of integrated packaging technology, and the ever-expanding demands for power conversion, silicon carbide power modules have become an important pathway for developing ultra-high power density converter equipment.

[0291] 1. New Energy Power Generation. Under the guidance of grid parity, photovoltaic power plants are cost-sensitive applications. Increasing the power density of inverters to reduce investment costs is a technological trend in photovoltaic power conversion. The ANSYS-MATLAB co-simulation method developed in this invention is highly efficient and accurate in electrical parameter extraction and layout optimization. Parameters such as power density can be optimized directionally using intelligent digital algorithms, which significantly reduces the investment cost of photovoltaic inverters.

[0292] 2. High-efficiency power supply. Power routing systems based on power electronic equipment can significantly improve power quality, efficiency, and reliability, and provide additional functions such as flexible power adjustment, power quality control, and backup power switching. This represents a significant development direction for data center power supply systems. The extensive use of power semiconductor modules inevitably increases equipment costs and footprint; highly integrated power modules are key to achieving compact designs for data center power systems.

[0293] 3. Electrified Transportation. Due to its advantages in switching speed, temperature characteristics, and withstand voltage, SiC power modules are increasingly being used in electric vehicle motor controllers. The motor controller is a core component of electric vehicles, placing high demands on the electrothermal characteristics of the power module, thus posing a significant challenge to SiC packaging. For electric vehicle applications, the requirements for motor controllers are high voltage, long lifespan, and high reliability. Correspondingly, the packaging design goals for automotive SiC power modules are: low parasitic inductance, low thermal resistance, and high reliability. By individually or collaboratively optimizing these packaging goals, the potential of SiC technology can be maximized. The ANSYS-MATLAB co-simulation method developed in this invention can effectively achieve the low parasitic inductance packaging design goal of SiC power modules through MATLAB's digital intelligent algorithms. For multi-objective collaborative optimization problems, related algorithms (such as NSGA-II) can also be combined to achieve the optimization goals.

[0294] This invention brings several positive results to power semiconductor layout optimization. Specifically, firstly, this technology uses finite element analysis (FEA), improving the accuracy and visualization of layout optimization. The layout optimization in this technology is based on ANSYS simulation, while currently disclosed optimization techniques are all based on rapid simulations such as discrete circuit analysis (DCA). Compared to DCA, ANSYS simulation has advantages in higher accuracy and visualization. Secondly, this technology can save significant manpower costs during the optimization process. Finite element analysis (FEA) is time-consuming and unpredictable, and manually controlling ANSYS simulation is laborious. This technology introduces automated processing, freeing up researchers' time and energy. Finally, this technology also has strong portability. The core of this technology lies in the automation of ANSYS simulation. Besides layout optimization, this technology can also guide the process of building rapid simulation models and extracting a large number of circuit parameters, thus possessing portability and versatility.

[0295] 1. Effectively improves the accuracy and visualization of layout optimization.

[0296] The layout optimization in this technique primarily focuses on electromagnetic field analysis, without delving into thermodynamics or structural mechanics. Therefore, the core task of layout optimization becomes the accurate extraction and analysis of parasitic inductance in the circuit. Traditionally, many techniques employ Discrete Circuit Analysis (DCA) as a fast simulation method to extract parasitic inductance. This method is widely used due to its high computational speed, demonstrating its irreplaceable advantages, especially in specific situations. However, ANSYS Finite Element Analysis (FEA) offers a more accurate and intuitive analysis method, which should not be overlooked when performing layout optimization.

[0297] The high accuracy of Finite Element Analysis (FEA) can be explained by the completeness of its mathematical model and the comprehensiveness of its simulation details. First, unlike discrete circuit methods based on simplified circuit models and Kirchhoff's laws, FEA focuses on the complete geometric layout and material properties of the circuit, using spatial discretization (mesh generation) to solve complex partial differential equations. This method allows FEA to accurately analyze the distribution of electromagnetic fields and the impact of circuit physical layout and non-ideal interactions between components (such as electromagnetic coupling and signal integrity issues) on the simulation results. Second, from the perspective of simulation details, discrete circuit methods often neglect factors such as electromagnetic coupling between wires and electromagnetic interference (EMI), especially when dealing with complex three-dimensional structures. This neglect often leads to imperceptible errors, thus adversely affecting the simulation results. In contrast, FEA, through precise field analysis and comprehensive consideration of multiple influencing factors, achieves higher accuracy.

[0298] Once the accuracy of finite element simulation has been proven, its advantages in visualization become self-evident. For example, in practical applications, such as... Figure 16 As shown, each new circuit layout optimized by the algorithm not only displays the specific parasitic inductance value but also presents the corresponding electric field distribution diagram. This visualization tool allows designers to intuitively evaluate the current-sharing characteristics of the circuit, further guiding the decision-making process for optimization design.

[0299] 2. Saves researchers' energy and time costs.

[0300] In developing this technology, the invention explored the unique advantages of finite element analysis (FEA) in terms of accuracy and visualization. Although FEA excels in simulating the behavior of complex physical systems, this invention found that FEA is rarely widely adopted as a mainstream simulation technique in published papers and patents. The main reason is the long and unpredictable time consumption of FEA simulations, which significantly limits its efficiency in applications such as layout optimization and numerical extraction.

[0301] The reason for this is that FEA simulates the computational principles of a complex physical system by subdividing it into thousands to millions of small elements (mesh) and analyzing the physical and material properties of each element as well as complex boundary conditions, thereby solving partial differential equations. While this method is accurate, the simulation time and its uncertainties are affected by various factors when dealing with large and complex models. Although high-performance computing (HPC) and cloud computing technologies support the handling of these computations, not all research institutions have these computing resources.

[0302] Therefore, this invention proposes an optimization strategy using a MATLAB and ANSYS integrated system to improve the automation level of simulation and layout optimization, thereby significantly saving researchers' time and economic costs. The advantages of automated integration are mainly reflected in the following four aspects:

[0303] It can significantly improve time efficiency: Automated programs can run continuously without human intervention, allowing simulation tasks to be started and stopped at any suitable time. For example, complex simulation tasks can be set to run automatically at night or on weekends, effectively avoiding taking up daily work time and significantly reducing the overall project cycle. An application example of this technology is that the program is set up and automatically executed on the weekend.

[0304] Reduced human error: Automated processes significantly reduce errors caused by manual operation, improving the reliability and repeatability of simulation results. When large-scale, repetitive simulations are required, automated scripts can precisely control every simulation parameter, ensuring that the simulation process adheres to strict consistency standards.

[0305] Optimizing computing resource utilization: Automation can allocate computing resources more efficiently, ensuring maximum utilization of high-performance computing resources. Furthermore, automation tools can monitor simulation progress and performance in real time, making timely resource adjustments to optimize computational efficiency.

[0306] Enhanced design iteration and optimization capabilities: Automated processing enables researchers to quickly test and compare multiple design configurations, accelerating the optimization iteration process. Researchers can leverage automated tools to adjust design parameters, run multiple simulation scenarios, and quickly obtain comparison results to identify the optimal design solution. This process... Figure 14 , Figure 15 , Figure 16 This was reflected in the program's execution.

[0307] 3. It is portable and versatile.

[0308] Finally, it is worth emphasizing that this technique demonstrates excellent portability and broad applicability. Although initially designed for circuit layout optimization considering only electromagnetic field analysis, its core advantage lies in leveraging the integration of MATLAB and ANSYS to rapidly extract circuit parameters. The application scope of this technique extends far beyond preliminary electromagnetic field considerations, and it can be widely used in various research projects related to power semiconductor layout optimization.

[0309] In research on power semiconductor layout optimization, ANSYS's finite element analysis (FEA) capabilities are indispensable, whether for building rapid simulation models or extracting large-scale circuit parameters. FEA technology provides in-depth insights and highly accurate analysis results through fine mesh generation and complex physical simulations. With this technology, researchers can significantly improve the speed of parameter extraction and model building through automated processes while maintaining the accuracy of ANSYS analysis.

[0310] More importantly, the automated processing of this technology not only improves work efficiency but also optimizes resource allocation and utilization, enabling computing resources to be used more efficiently. The automated program can perform complex data processing and simulation tasks in the background without supervision, greatly reducing the need for manual operation and lowering the risk of human error.

[0311] Furthermore, due to the widespread use of MATLAB and ANSYS, this technology is highly portable and can be easily adapted to different research and industrial environments. Researchers can adjust and customize automation scripts according to specific application needs, making them more suitable for specific projects. This flexibility and customizability further enhances the market appeal and practical value of this technology.

[0312] The optimization process provided in this invention can record the parameters of each model during the optimization process. By simply closing the optimization process and performing only the extraction, a large amount of circuit data can be quickly extracted and compared with the results of the rapid simulation model or other needs can be met.

[0313] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for efficient extraction of parasitic inductance parameters and layout optimization of power semiconductor modules, characterized in that, The method comprises the following steps: Step one, initial parameter definition and parasitic inductance extraction; Step two, simulation data transfer: after the extraction of parasitic inductance, the simulation data in ANSYS Q3D is imported into the MATLAB environment by generating a detailed simulation report, and the genetic algorithm optimization technology is used to adjust the circuit layout to minimize the parasitic inductance and improve the module performance; Step three: ANSYS script automation and reanalysis: according to the new layout scheme provided by the MATLAB genetic algorithm, ANSYS scripts are automatically written, and these scripts are used to guide ANSYS software to perform a new round of parasitic inductance analysis; Step four: result feedback and iterative optimization: after ANSYS software completes the parasitic inductance analysis under the new layout, the results are fed back to MATLAB; then, steps one to three are repeated to enter the next iteration cycle; The initial parameter definition and parasitic inductance extraction method is as follows: (1) Design a basic circuit layout; (2) Determine the material properties of the power module; (3) Arrange the circuit and automatically identify the network; First, select the excitation source SOURCE and the ground SINK, and the specific meaning of each port has been determined in the process of circuit diagram making; Determine and display the unique electrical path of the model through the automatic network identification function of ANSYS Q3D; (4) Extract the parasitic inductance; Simulate the circuit and extract the resistance and inductance parameters of the circuit; The design of the basic circuit layout is based on the following model: 1) Packaging parasitic inductance calculation model - accumulation method; The inductance of a rectangular prism conductor is: ； In the formula, H is the inductance, H; , L, W, and T are the length, width, and thickness of the conductor, respectively, mm; H / m, is the vacuum permeability; The inductance of a straight conductor is: ； wherein and are the length and diameter of the wire, mm; if then the inductance of the long straight wire can be expressed as: ； For the case of multiple parallel bonding wires, the parasitic inductance equivalent of a cluster of bonding wires is: ； In the formula, is the number of bonding wires; 2) Rectangular loop packaging parasitic inductance calculation model - magnetic field cancellation method; Inductance coefficient is derived as follows: The inductance of a closed rectangular loop is: ； wherein are the length and width, respectively, of the rectangle, is the diameter of the conductor, mm; if can be simplified to: ； where, and are the perimeter and area of the rectangular conductor, respectively; thus, the open-loop rectangular loop inductance is: ； Open loop rectangular loop inductance coefficient May be defined as: 。 2. The method of claim 1, wherein the parasitic inductance parameters of the power semiconductor module are extracted with high efficiency and the layout of the power semiconductor module is optimized, characterized in that, The material properties of the power module are determined: The initial model generated by SOLIDWORKS is imported into ANSYS, and the materials of each part of the circuit are determined during simulation. The determined parts include bonding wires, DBC, power chips, and bus bars.

3. A system for efficient extraction and layout optimization of parasitic inductance parameters of a power semiconductor module implementing the method of efficient extraction and layout optimization of parasitic inductance parameters of a power semiconductor module according to any one of claims 1 to 2, characterized in that The system for efficient extraction and layout optimization of parasitic inductance parameters of a power semiconductor module comprises: An extraction module for initial parameter definition and parasitic inductance extraction; A data transfer module for simulation data transfer; An analysis module for ANSYS script automation and reanalysis; A feedback module for feeding back the results to MATLAB after ANSYS software completes the parasitic inductance analysis under the new layout.

4. A computer device, comprising: The computer device comprises a memory and a processor, and the memory stores a computer program. When the computer program is executed by the processor, the processor executes the steps of the efficient extraction and layout optimization method of parasitic inductance parameters of a power semiconductor module as claimed in any one of claims 1-2.

5. A computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to execute the steps of the efficient extraction and layout optimization method of parasitic inductance parameters of a power semiconductor module as claimed in any one of claims 1-2.

6. An information data processing terminal, characterized by The information data processing terminal is used for realizing the efficient extraction and layout optimization system of the parasitic inductance parameter of the power semiconductor module as claimed in claim 3.

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