Iterative optimization method for quantum circuit mapping

Abstract

The invention provides an iterative optimization method for quantum circuit mapping, and belongs to the technical field of quantum circuit compiling. The technical problem of automatically compiling and running the quantum circuit on the NISQ equipment with limited physical quantum bit connectivity is solved. According to the technical scheme, the method comprises the following steps: S1, reading a quantum circuit from a source file, and preprocessing the quantum circuit; s2, exploring a neighborhood space of quantum bit initial mapping by adopting an iterative local search mode until the number of iterations reaches a preset value, and S3, outputting a physical quantum circuit. The method has the beneficial effects that the reversibility of the quantum circuit is utilized, the bidirectional mapping process is repeatedly carried out, and the target quantum circuit with a smaller number of quantum gates is continuously generated until the number of times of repetition specified in advance is reached.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum circuit compilation, and in particular to an iterative optimization method for quantum circuit mapping. Background Art

[0002] Current noisy intermediate-scale quantum (NISQ) computing devices provide an effective physical platform for actually running quantum algorithms. However, there are still some obstacles to using such quantum computing prototype devices to complete computing tasks. Among them, a more common obstacle is that the physical quantum bits in the device are susceptible to noise and the connectivity between them is limited. The restricted connectivity constraint between physical quantum bits requires that the two-bit quantum gate in the quantum circuit is only allowed to act on a pair of directly connected physical quantum bits.

[0003] Quantum circuits are a common model for describing quantum algorithms, usually containing several logical qubits and a sequence of quantum gate operations acting on them. When designing quantum circuits, in order to reduce the difficulty of design, it is usually assumed that there are no many physical limitations on the underlying physical devices, such as assuming that the logical qubits are fully connected, which means that two-bit quantum gates can act on any two qubits. The inconsistency between quantum circuits and NISQ quantum computing devices in qubit connectivity requires specific transformations of quantum circuits before they can be deployed on NISQ computing devices for execution. This transformation is called quantum circuit mapping.

[0004] Existing quantum circuit mapping methods generally lack the ability to continuously evolve the generated target quantum circuit. If the number of quantum gates of the generated target quantum circuit exceeds the capacity limit of the current NISQ computing equipment, the existing quantum circuit mapping methods cannot provide a quantum circuit with fewer quantum gates based on the generated circuit.

[0005] Existing NISQ computing devices are susceptible to noise interference. Each quantum gate operation applied to a quantum bit will inevitably introduce operational errors. The accumulation of such errors will make the operation results of the quantum circuit unreliable and meaningless. Therefore, reducing the number of auxiliary quantum gates inserted during the quantum circuit mapping process is the key to ensuring the success rate of quantum circuit execution.

[0006] Existing quantum circuit mapping methods generally adopt a single-pass mapping strategy, which converts quantum circuits into target quantum circuits that meet physical constraints by traversing and processing quantum circuits once. However, if the number of quantum gates in the target quantum circuit exceeds the effective computing capability of current NISQ devices, such methods cannot further provide target quantum circuits with fewer quantum gates.

[0007] How to solve the above technical problems is the subject faced by the present invention. Summary of the invention

[0008] The object of the present invention is to provide an iterative optimization method for quantum circuit mapping, which utilizes the reversibility of quantum circuits and continuously generates target quantum circuits with fewer quantum gates by repeatedly performing a bidirectional mapping process until a pre-specified number of repetitions is reached.

[0009] In order to better achieve the above-mentioned invention object, the following related concepts in the present invention are described:

[0010] Quantum bit: A quantum bit is the basic unit for storing and processing quantum information on a quantum computer. The state of a quantum bit is referred to as a quantum state. The quantum bits in a quantum circuit are called logical quantum bits; while the quantum bits in a NISQ computer are called physical quantum bits.

[0011] CNOT gate: CNOT gate is a commonly used two-bit quantum gate, also known as quantum controlled NOT gate. Its function is: when the quantum state of the control bit is 1, the quantum state of the target bit is inverted; Figure 1 An example diagram of a CNOT gate is given, where q0 is the control bit and q1 is the target bit. The gate can be written as g(q0,q1).

[0012] SWAP gate: SWAP gate is a commonly used two-bit quantum gate, also known as quantum exchange gate, which is used to exchange the quantum states of two related physical quantum bits, and can also be equivalently regarded as exchanging the logical quantum bits corresponding to two physical quantum bits. A SWAP gate can be decomposed into three consecutive CNOT gates, such as Figure 2 shown.

[0013] Quantum circuit: A quantum circuit usually consists of a logical qubit and a sequence of quantum gate operations acting on the qubit. Figure 3 The example quantum circuit shown includes five logical qubits {q0, q1, q2, q3, q4} and five two-bit quantum gates {g0(q0, q3), g1(q0, q2), g2(q3, q4), g3(q1, q4), g4(q2, q0)}.

[0014] Physical quantum circuit: The target quantum circuit generated by the quantum circuit mapping method and satisfying the physical constraints of the NISQ device is called a physical quantum circuit.

[0015] Physical qubit coupling graph of the NISQ computer: The coupling graph describes the physical qubits in the NISQ computer and the two-bit quantum gate operations they directly support, where nodes represent physical qubits and edges between nodes represent the two-bit quantum gates that are allowed to be applied. Figure 4An example of a coupling graph containing five physical qubits {v0,v1,v2,v3,v4} is given.

[0016] Quantum bit mapping relationship: refers to the one-to-one correspondence between logical quantum bits and physical quantum bits, which can be represented by the injective function π:Q→V, where Q={q0,q1,…,q n-1} is the set of logical qubits, n is the number of logical qubits, V = {v0,v1,…,v m-1} is a set of physical quantum bits, m is the number of physical quantum bits; if π(q i )=v j , which means that the logical quantum bit q i Assigned to physical qubit v j superior.

[0017] Initial qubit mapping: The qubit mapping relationship before the quantum circuit mapping begins is called the initial mapping.

[0018] The physical distance of a two-bit quantum gate refers to the shortest path length of the two physical quantum bits acted on by the two-bit quantum gate on the coupling graph under a specific quantum bit mapping relationship. Figure 4 The physical quantum bit coupling diagram shown in Figure 1 and the quantum bit mapping relationship π:Q→V, where π(q i )=v i , i = {0,1,2,3,4}, if a CNOT gate acts on logical qubits q0 and q4, then the two corresponding physical qubits under the mapping relationship π are v0 and v4. Since the shortest path length between v0 and v4 on the coupling graph is 2, the physical distance of the CNOT gate is equal to 2.

[0019] Nearest neighbor interaction constraint: The restricted connectivity of physical qubits on NISQ computing devices requires that only two directly connected physical qubits can interact with each other, that is, a two-bit quantum gate is only allowed to act on two directly connected physical qubits. This constraint applicable to two-bit quantum gates is called the nearest neighbor interaction constraint. When the physical distance of a two-bit quantum gate is 1 under a specific qubit mapping, the gate satisfies the nearest neighbor interaction constraint; otherwise, it does not satisfy the interaction constraint. For example, given Figure 4 The physical quantum bit coupling diagram shown in Figure 1 and the quantum bit mapping relationship π:Q→V, where π(q i )=v i , i = {0,1,2,3,4}, if a CNOT gate acts on logical qubits q0 and q1, then the two corresponding physical qubits under the mapping relationship π are v0 and v1, indicating that the physical distance of the CNOT gate is equal to 1. Therefore, the CNOT gate meets the nearest neighbor interaction constraint.

[0020] In order to make all quantum gates of the quantum circuit satisfy the nearest neighbor interaction constraints of the NISQ device, the quantum circuit mapping process usually includes the following two steps:

[0021] (1) Quantum bit allocation

[0022] Determine the initial mapping relationship between logical qubits and physical qubits, that is, uniquely specify for each logical qubit the physical qubit that stores its information on the NISQ device.

[0023] (2) Quantum bit routing

[0024] Under the initial mapping relationship obtained by the quantum bit allocation, there may still be two-bit quantum gates in the quantum circuit that do not satisfy the nearest neighbor interaction constraint. In this case, the quantum gates must be scheduled and processed in sequence according to the dependency relationship of the quantum gates. If a two-bit quantum gate satisfies the nearest neighbor interaction constraint under the current mapping relationship, it is directly scheduled. Otherwise, the mapping relationship between the logical quantum bit and the physical quantum bit must be updated by inserting a SWAP gate until the two-bit quantum gate satisfies the nearest neighbor interaction constraint, and then the quantum gate is scheduled. Since the operation of updating the quantum bit mapping relationship through the SWAP gate is essentially equivalent to routing and moving the logical quantum bit on the physical quantum bit coupling graph, this process is usually called quantum bit routing.

[0025] The research motivation and basic principle of the method described in the present invention are as follows:

[0026] The initial qubit mapping generated by the qubit allocation process has an important impact on the quantum circuit mapping cost, that is, the number of auxiliary quantum gates inserted. Existing quantum circuit mapping usually uses heuristic rules to determine an initial qubit mapping, then performs a traversal of the quantum circuit based on the initial mapping, and performs qubit routing on demand during the traversal. Therefore, the mapping cost of existing quantum circuit mapping methods, that is, the number of auxiliary quantum gates inserted, is heavily dependent on the given initial qubit mapping; however, which initial mapping can bring the lowest mapping cost is a difficult problem that is difficult to predict in advance. In addition, for a NISQ computing device with n physical qubits, there may be at most n! different qubit initial mappings; therefore, the problem solution space with O(n!) complexity makes the exhaustive search strategy infeasible. Existing quantum circuit mapping methods generally use heuristic quantum bit allocation strategies to obtain an initial quantum bit mapping. In most cases, this initial mapping does not bring the lowest mapping cost, and is even far from it. In addition, when the number of quantum gates contained in the physical quantum circuit exceeds the capacity limit of the available NISQ computing equipment, the existing quantum circuit mapping methods do not have any method or means to provide a physical quantum circuit with better quality.

[0027] The basic principle of the method described in the present invention is as follows: the quantum circuit mapping process is regarded as a discrete function, whose domain is the set composed of all legal quantum bit initial mappings, and the range is the number of quantum gates contained in the physical quantum circuit finally generated. Thus, the optimization problem of determining the minimum mapping cost is transformed into the problem of solving the minimum value of the discrete function. Since the function is a discrete function, it is difficult to accurately characterize it by a mathematical formula, and in order to cope with the O (n!) problem solution space complexity, the quantum circuit mapping method described in the present invention adopts an iterative local search strategy. Its characteristics are as follows: starting from a specific quantum bit initial mapping, an iterative local search is performed on its neighborhood space, and when the number of explorations in the neighborhood space exceeds a specified threshold, in order to prevent falling into a local optimum, a new initial mapping is randomly generated again, and the next round of iterative search is started based on the initial mapping until the number of iterations reaches a predetermined value. In each round of iterative search process, the quantum bit routing process is continuously performed on the quantum circuit in a bidirectional, i.e. forward and reverse, traversal manner, and the high-quality neighborhood of the current quantum bit initial mapping is continuously explored, so as to find an initial mapping with a lower mapping cost.

[0028] Specifically, in each round of iterative search, the quantum bit routing process is first performed in a forward traversal manner based on the current quantum bit initial mapping, and the number of auxiliary quantum gates inserted in the routing process, namely the number of SWAP gates, is used as the performance evaluation index of the current initial mapping. The quantum bit mapping relationship at the end of the routing process is used as the quantum bit initial mapping neighborhood for the next exploration, and when the next neighborhood exploration is performed, quantum bit routing is performed in a reverse traversal manner.

[0029] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is specifically: an iterative optimization method for quantum circuit mapping, comprising the following steps:

[0030] S1, read the quantum circuit from the source file and preprocess the quantum circuit;

[0031] S2. Use iterative local search to explore the neighborhood space of the initial mapping of the quantum bit until the number of iterations reaches a predetermined value. In each round of iterative search, the quantum bit routing process is continuously performed on the quantum circuit in a bidirectional traversal manner to continuously explore the high-quality neighborhood of the current initial mapping of the quantum bit, thereby finding an initial mapping with a lower mapping cost;

[0032] S3, physical quantum circuit output

[0033] The single-bit quantum gate deleted during quantum circuit preprocessing is restored to the optimal physical quantum circuit output by the iterative optimization process according to its recorded original position information, and the final physical quantum circuit is output.

[0034] Furthermore, in step S1, the quantum circuit reading and preprocessing specifically includes the following steps:

[0035] S11. The source file of the quantum circuit is provided by a third party, generated by other quantum circuit pre-compilation tools, or a custom quantum circuit description file based on any quantum basic gate library. There is no special requirement for the format of the quantum circuit source file, and its format is a text file, a database file, or any other valid quantum circuit file format;

[0036] S12, deleting the single-bit quantum gate irrelevant to the quantum bit mapping from the quantum circuit, and recording its original position in the quantum circuit;

[0037] S13, constructing a directed acyclic graph for the original quantum circuit to express the execution dependency of quantum gates, wherein the nodes in the directed acyclic graph of quantum gate dependency represent quantum gates, and the directed edges between quantum gates represent the direct dependency between the two quantum gates, where the output of the previous quantum gate will be directly used as the input of the next quantum gate. The construction process of the quantum gate dependency graph is as follows: read each quantum gate g in the quantum circuit in turn. i , add a corresponding node to the quantum gate dependency graph. If the quantum gate g i and a quantum gate g just added to the diagram j Sharing the same logical qubit, we can establish a quantum gate g j Start to the quantum gate g i ;

[0038] S14, constructing a quantum gate dependency graph for the reverse quantum circuit of the original quantum circuit, called a reverse quantum gate dependency graph;

[0039] The construction process of the reverse quantum gate dependency graph is as follows: read each quantum gate g in the quantum circuit in sequence from back to front i , add a corresponding node to the quantum gate dependency graph. If the quantum gate g i and a quantum gate g that was recently added to the diagram j Sharing the same logical qubit, we can establish a quantum gate g j Start to the quantum gate g i ;

[0040] S15. According to the device information of the NISQ computer, a physical quantum bit coupling diagram is constructed, and the distance between any two physical quantum bits on the coupling diagram is calculated. The distance refers to the shortest path length between the two physical quantum bits on the coupling diagram. The shortest path length between any two physical quantum bits on the coupling diagram is saved by a two-dimensional array D[][], where D[i][j] saves the physical quantum bit v i and v j The distance between

[0041] The physical quantum bit coupling graph, wherein the nodes represent physical quantum bits, and the edges between the nodes represent the two-bit quantum gates that are allowed to be applied.

[0042] Furthermore, the step S2 specifically includes the following steps:

[0043] S21, initialization operation;

[0044] S22, a new round of local search process based on bidirectional mapping is carried out, starting from the quantum bit initial mapping π0, by continuously performing the quantum bit routing process on the quantum circuit in a bidirectional traversal manner, constantly exploring the high-quality neighborhood of the current quantum bit initial mapping, and outputting the optimal physical quantum circuit C1 and its corresponding quantum bit initial mapping π1 obtained in this process, the optimal physical quantum circuit refers to the physical quantum circuit with the least quantum gates;

[0045] S23, updating the best physical quantum circuit C2 so far and its corresponding initial quantum bit mapping π2;

[0046] Compare the optimal physical quantum circuit C1 returned by the most recent local search process with the optimal physical quantum circuit C2 so far. If the latter is empty or the number of quantum gates of the former is less than that of the latter, update the latter with the former and update the initial mapping accordingly, setting C2 = C1 and π2 = π1.

[0047] S24, randomly perturb the optimal quantum bit initial mapping π2 so far, and use the perturbed result as the quantum bit initial mapping π0 for starting the next round of local search process;

[0048] The random perturbation process is carried out by performing a random perturbation on the physical quantum bit sequence [π2(q1),π2(q2),…,π2(q n-1 )] is randomly reordered, and the reordered array is set to plist[], then the initial mapping relationship π0 of the next round of quantum bits is constructed, so that π0(q i ) = plist[i], where i = {0, 1, 2, ..., n-1};

[0049] S25, add 1 to the value of the iteration round counter i, and determine whether to start the next round of local search. If the value of i does not exceed the round number threshold I max , then the next round of local search is started, that is, jumping to step S22 for execution; otherwise, the operation is terminated and the optimal physical quantum bit circuit C2 and its corresponding quantum bit initial mapping π2 are returned.

[0050] Furthermore, in step S21, the initialization operation specifically includes the following steps:

[0051] S211, set the initial value of the iteration round counter i to 0, and set the round number threshold I at the same time max The iteration round counter i is used to record the number of rounds currently iterated in real time, and the round number threshold I max Used to set the maximum number of iterations allowed;

[0052] S212, randomly generate a quantum bit mapping relationship, and use it as the quantum bit initial mapping π0, the method of randomly generating the quantum bit initial mapping, for the array Arr = [v0, v1, ..., v m-1 ] are randomly reordered, where m is the total number of physical qubits in the NISQ device; if the quantum circuit contains n logical qubits, where n≤m, then the first n elements of the Arr array are taken to construct a qubit mapping relationship π0 such that π0(q i )=Arr[i], where i={0,1,2,…,n-1};

[0053] S213. Initialize the optimal physical quantum bit circuit C2 and its corresponding quantum bit initial mapping π2 to be empty. The optimal physical quantum circuit refers to the physical quantum circuit with the least quantum gates found in multiple rounds of local search.

[0054] Furthermore, in step S22, the local search process based on bidirectional mapping specifically includes the following steps:

[0055] S221, initialization operation

[0056] S2211, set the maximum number of times L that each round of local search allows for traversal of the quantum circuit max , and set the initial value of the traversal counter l to 0, the traversal times calculator l is used to record the current traversal times in real time;

[0057] S2212, initializing the optimal physical quantum bit circuit C1 and its corresponding quantum bit initial mapping π1 that can be found in this round of local search to empty, wherein the optimal physical quantum circuit refers to the physical quantum circuit with the least quantum gates found in this round of local search;

[0058] S2213, the quantum gate dependency graph G c Initialize to the quantum gate dependency graph corresponding to the original quantum circuit, the quantum gate dependency graph is obtained by the quantum circuit preprocessing step;

[0059] S222, based on the initial mapping of quantum bits π0, and according to the quantum gate dependency graph G c The traversal order is defined, the qubit routing process is called, and the physical quantum circuit C3 generated by the qubit routing process and the qubit mapping relationship π3 after qubit routing are returned;

[0060] S223, update the optimal physical quantum bit circuit C1 of this round of local search and its corresponding quantum bit initial mapping π1, compare the physical quantum circuit C3 generated by the most recent quantum bit routing with the optimal physical quantum bit circuit C1 of this round so far, if C1 is empty, or the number of quantum gates in C3 is less than the number of quantum gates in C1, then update C1 to C3, that is, set C1=C3, and update the initial mapping accordingly, that is, set π1=π3;

[0061] S224, update the quantum bit initial mapping π0 and the quantum gate dependency graph G c , thus preparing for the next call to the quantum bit routing process, which specifically includes the following steps:

[0062] S2241, updating the initial quantum bit mapping π0 to the quantum bit mapping π3 returned by the most recent quantum bit routing process, i.e. setting π0=π3;

[0063] S2242, the quantum gate dependency graph G c Switch between the original and reverse quantum gate dependency graphs. c If it is the original quantum gate dependency graph, it is switched to the reverse quantum gate dependency graph; otherwise, it is switched to the original quantum gate dependency graph;

[0064] S225, add 1 to the value of the traversal counter l, and determine whether it is necessary to start the next quantum bit routing process. If the value of l does not exceed the round number threshold L max , then the next quantum bit routing process is started, that is, jumping to step S222 for execution; otherwise, the operation is terminated and the optimal physical quantum bit circuit C1 of this round and its corresponding quantum bit initial mapping π1 are returned.

[0065] Furthermore, in step S222, the quantum bit routing process specifically includes the following steps:

[0066] The first step is to start from the quantum gate dependency graph G c Read the quantum gate operations in the active state to form an active quantum gate set;

[0067] The quantum gate operation in the active state has no predecessor node in the quantum gate dependency graph, that is, the quantum gates it depends on have been deleted from the quantum gate dependency graph;

[0068] The second step is to check whether there is an executable quantum gate in the active quantum gate set. If not, proceed to the next step. Otherwise, delete this row of executable gates from the active quantum gate set and the quantum gate dependency graph, and add it to the physical quantum circuit C3. Then check whether the quantum gate dependency graph after the deletion operation is empty. If not, return to the first step. Otherwise, end the operation and return to the physical quantum circuit C3 and the final quantum bit mapping relationship π3.

[0069] The executable gate refers to an active quantum gate that satisfies the nearest neighbor interaction constraint, and the physical quantum circuit refers to a target quantum circuit that satisfies the nearest neighbor interaction constraint on a NISQ quantum computing device;

[0070] The third step is to generate a set of candidate SWAP gates. The candidate SWAP gates must meet the following conditions:

[0071] (1) The SWAP gate shares the same physical qubit with at least one quantum gate in the active quantum gate set;

[0072] (2) Executing the SWAP gate will bring non-negative effects to the execution of every quantum gate in the set of active quantum gates;

[0073] (3) The SWAP gate complies with the nearest neighbor interaction constraint, that is, it acts on two directly connected physical qubits in the coupling graph;

[0074] The non-negative effect of the SWAP gate on an active quantum gate means that after the execution of the SWAP gate, the physical distance of the active quantum gate on the coupling graph decreases or remains unchanged. The physical distance of the quantum gate refers to the shortest path length of the two physical quantum bits acted on by the two-bit quantum gate on the coupling graph under the current quantum bit mapping relationship, which can be directly accessed through the distance array D[][] obtained in the preprocessing stage.

[0075] In the fourth step, for each SWAP gate in the candidate SWAP gate set, a look-ahead window W is constructed for it. The look-ahead window includes the X-layer sub-circuit to be executed. The look-ahead window is constructed according to the following steps:

[0076] 1) Construct the quantum gate dependency graph G c A copy of G d ;

[0077] 2) The G d All quantum gates in the first layer are added to the look-ahead window W, and these quantum gates are removed from G d Delete, the first layer of quantum gates refers to, in G d All quantum gates without predecessor nodes in the , that is, the aforementioned active quantum gates;

[0078] 3) Repeat step (2) until the look-ahead window W contains the first X layers of sub-lines;

[0079] Step 5: For each SWAP gate in the candidate SWAP gate set, calculate the profit function of the SWAP gate in its look-ahead window W, and insert the SWAP gate with the largest function value into the physical quantum circuit, update the current quantum bit mapping relationship according to the inserted SWAP gate, and then return to the first step to continue execution;

[0080] For a SWAP gate, under the quantum bit mapping relationship π, the form of the profit function is: Where W represents the look-ahead window corresponding to the SWAP, g represents each quantum gate in the look-ahead window W, and eff(g) represents the reduction in the physical distance of the quantum gate g after the SWAP gate is applied, which is equal to the original physical distance of the g gate minus the physical distance after the SWAP gate is applied;

[0081] The physical distance of the quantum gate refers to the shortest path length of the two physical quantum bits acted on by the dual-bit quantum gate on the coupling graph under the current quantum bit mapping relationship, which can be directly accessed through the distance array D[][] obtained in the preprocessing stage.

[0082] The updating of the current quantum bit mapping relationship according to the inserted SWAP gate has the following characteristics: if the current quantum bit mapping relationship is π, and satisfies π(q i )=v x ,π(q j )=v y , then in the physical quantum bit v x and v y After applying the SWAP gate, the mapping relationship π is updated to And in the new mapping relationship Next, the logical quantum bit q i and q j The positions of will be exchanged, that is, π(q i )=v y ,π(q j )=v x .

[0083] Compared with the prior art, the present invention has the following beneficial effects:

[0084] (1) The quantum circuit mapping iterative optimization method of the present invention utilizes the reversibility of quantum circuits. By continuously executing the forward and reverse quantum bit routing processes on the quantum circuits, the high-quality neighborhood of the current quantum bit mapping relationship is explored. Compared with the existing method 1 [1] which uses simulated annealing technology to completely randomly explore the quantum bit mapping field, the method of the present invention has obvious advantages in both the optimization amplitude of the number of quantum gates and the optimization stability. The following Table 1 shows the experimental results of the method of the present invention and the existing method 1 [1] in terms of quantum gate optimization amplitude and stability. We run the existing method 1 and the method of the present invention 10 times on each benchmark quantum circuit, and record the minimum value (min), maximum value (max), average value (avg), and stability coefficient (cov) of the auxiliary quantum gates used. The stability coefficient is equal to the quotient of the standard deviation and mean of the ten running results. The smaller the value, the more stable the corresponding method. As can be seen from the table below, the method of the present invention is significantly better than the existing method 1 in terms of optimization stability. The stability coefficient values ​​of the method on all benchmark circuits are all lower than 0.1, while the stability coefficient values ​​of the existing method 1 are generally higher. In addition, the method described in the present invention is also better than the existing method 1 in terms of the average optimization effect of the number of quantum gates. Except for a few small-scale benchmark circuits that do not require auxiliary gates, the average number of quantum gates of the method described in the present invention on other benchmark circuits is also significantly reduced compared with the existing method 1.

[0085] Table 1

[0086]

[0087] (2) The method of the present invention adopts an iterative local search technology, so that the method does not rely heavily on the initial mapping of quantum bits like the existing methods, and can further reduce the number of quantum gates required for quantum circuit mapping by increasing the number of iterations, thereby providing an "evolutionary" ability that is generally not available in existing quantum circuit mapping methods, so that when the physical quantum circuit generated by the mapping process exceeds the limit of the physical device in terms of the number of gates, it can continue to provide physical quantum circuits with fewer quantum gates. The following Table 2 gives the experimental comparison results of the method of the present invention and the two existing methods [1,2] on multiple benchmark quantum circuits. Compared with the existing method 1 [1], the number of auxiliary quantum gates required by the method of the present invention on all benchmark circuits is reduced by an average of 28.80%, and by a maximum of 42.86%; compared with the existing method 2 [2], the number of auxiliary quantum gates required by the method of the present invention is reduced by an average of 41.25%, and by a maximum of 66.67%.

[0088] Table 2

[0089] BRIEF DESCRIPTION OF THE DRAWINGS

[0090] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0091] Figure 1 This is an example of a CNOT gate in the present invention, where q0 is the control bit and q1 is the target bit. The gate can be recorded as g(q0,q1), and its function is: when the quantum state of the control bit q0 is 1, the quantum state of the target bit q1 is inverted.

[0092] Figure 2 This is an example of a SWAP gate in the present invention, an example of a SWAP gate, which is used to exchange logical quantum bits q0 and q1, and can be further decomposed into 3 consecutive CNOT gates.

[0093] Figure 3 This is an example of a quantum circuit in the present invention, which includes five logical quantum bits {q0, q1, q2, q3, q4} and five CNOT quantum gates {g0(q0, q3), g1(q0, q2), g2(q3, q4), g3(q1, q4), g4(q2, q0)}.

[0094] Figure 4 This is an example of a coupling graph including five physical quantum bits {v0, v1, v2, v3, v4} in the present invention, wherein a two-bit quantum gate is allowed to act on any two directly connected physical quantum bits.

[0095] Figure 5 The figure is a schematic diagram of the overall process of the quantum circuit mapping iterative optimization method corresponding to the present invention.

[0096] Figure 6 Schematic diagram of the quantum circuit mapping iterative optimization device corresponding to the present invention.

[0097] Figure 7 for Figure 1 Quantum gate dependency diagram corresponding to the quantum circuit shown.

[0098] Figure 8 for Figure 1 Reverse quantum gate dependency diagram corresponding to the quantum circuit shown.

[0099] Fig. 9 The figure is a flow chart of performing multiple rounds of iterative local searches on the initial mapping neighborhood of quantum bits corresponding to the present invention.

[0100] Fig.10 It is a flowchart of each round of local search process corresponding to the present invention.

[0101] Fig.11It is a flowchart of the quantum bit routing process corresponding to the present invention.

[0102] Fig.12 A physical quantum circuit diagram of an embodiment of the quantum circuit mapping iterative optimization method corresponding to the present invention Figure 1 .

[0103] Fig.13 A physical quantum circuit diagram of an embodiment of the quantum circuit mapping iterative optimization method corresponding to the present invention Figure 2 .

[0104] Fig.14 Schematic diagram of physical quantum circuits for other quantum bit mapping technology embodiments. DETAILED DESCRIPTION

[0105] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Of course, the specific embodiments described here are only used to explain the present invention and are not used to limit the present invention.

[0106] Example 1

[0107] This embodiment provides a technical solution, which is an iterative optimization method for quantum circuit mapping, such as Fig.12 When mapping the quantum circuit shown in the left figure to Figure 4 When the physical quantum bit coupling diagram is shown, the method of this embodiment obtains an initial quantum bit mapping (wherein, π(q0)=v1), π(q1)=v0), π(q2)=v3), π(q3)=v2), π(q4)=v4)) by iterative local search of the randomly generated quantum bit initial mapping neighborhood. Under this initial mapping, the quantum circuit can be directly executed without inserting any SWAP gates. This embodiment verifies the efficiency of the method described in the present invention in exploring the quantum bit mapping neighborhood.

[0108] Example 2

[0109] This embodiment provides a technical solution, which is an iterative optimization method for quantum circuit mapping, such as Fig.13 As shown. Figure 3 The quantum circuit shown is mapped to Figure 4 The physical quantum circuit and its corresponding quantum bit mapping are shown in the physical quantum bit coupling diagram. Fig.13 As shown. The final physical quantum circuit contains only one SWAP gate, which has reached the optimal number of SWAP gates. This example verifies the effectiveness of the iterative optimization method described in this article.

[0110] Example 3

[0111] This embodiment provides a technical solution for generating physical quantum circuits that may be generated by other quantum bit mapping methods. Figure 3 The quantum circuit shown is mapped to Figure 4 In the physical quantum bit coupling diagram shown in Fig.14 As shown, only three SWAP gates are included, which exceeds the number of SWAP gates required by the technology described in the present invention in Example 2.

[0112] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An iterative optimization method for quantum circuit mapping, characterized in that: The following steps are involved: S1, read the quantum circuit from the source file and preprocess the quantum circuit; S2. Use iterative local search to explore the neighborhood space of the initial mapping of the quantum bit until the number of iterations reaches a predetermined value. In each round of iterative search, the quantum bit routing process is continuously performed on the quantum circuit in a bidirectional traversal manner to continuously explore the high-quality neighborhood of the current initial mapping of the quantum bit, thereby finding an initial mapping with a lower mapping cost; S3, physical quantum circuit output The single-bit quantum gate deleted during quantum circuit preprocessing is restored to the optimal physical quantum circuit output by the iterative optimization process according to its recorded original position information, and the final physical quantum circuit is output.

2. The iterative optimization method for quantum circuit mapping according to claim 1, characterized in that: In step S1, quantum circuit reading and preprocessing specifically include the following steps: S11. The source file of the quantum circuit is provided by a third party, generated by other quantum circuit pre-compilation tools, or a custom quantum circuit description file based on any quantum basic gate library. There is no special requirement for the format of the quantum circuit source file, and its format is a text file, a database file, or any other valid quantum circuit file format; S12, deleting the single-bit quantum gate irrelevant to the quantum bit mapping from the quantum circuit, and recording its original position in the quantum circuit; S13, constructing a directed acyclic graph for the original quantum circuit to express the execution dependency of quantum gates, wherein the nodes in the directed acyclic graph of quantum gate dependency represent quantum gates, and the directed edges between quantum gates represent the direct dependency between the two quantum gates, where the output of the previous quantum gate will be directly used as the input of the next quantum gate. The construction process of the quantum gate dependency graph is as follows: read each quantum gate g in the quantum circuit in turn. i , add a corresponding node to the quantum gate dependency graph. If the quantum gate g i and a quantum gate g just added to the diagram j Sharing the same logical qubit, we can establish a quantum gate g j Start to the quantum gate g i The directed edges of S14, constructing a quantum gate dependency graph for the reverse quantum circuit of the original quantum circuit, called a reverse quantum gate dependency graph; The construction process of the reverse quantum gate dependency graph is as follows: read each quantum gate g in the quantum circuit in sequence from back to front i , add a corresponding node to the quantum gate dependency graph. If the quantum gate g i and a quantum gate g that was recently added to the diagram j Sharing the same logical qubit, we can establish a quantum gate g j Start to the quantum gate g i The directed edges of S15. According to the device information of the NISQ computer, a physical quantum bit coupling diagram is constructed, and the distance between any two physical quantum bits on the coupling diagram is calculated. The distance refers to the shortest path length between the two physical quantum bits on the coupling diagram. The shortest path length between any two physical quantum bits on the coupling diagram is saved by a two-dimensional array D[][], where D[i][j] saves the physical quantum bit v i and v j The distance between The physical quantum bit coupling graph, wherein the nodes represent physical quantum bits, and the edges between the nodes represent the two-bit quantum gates that are allowed to be applied.

3. The iterative optimization method for quantum circuit mapping according to claim 1, characterized in that: The step S2 specifically includes the following steps: S21, initialization operation; S22, a new round of local search process based on bidirectional mapping is carried out, starting from the quantum bit initial mapping π0, by continuously performing the quantum bit routing process on the quantum circuit in a bidirectional traversal manner, constantly exploring the high-quality neighborhood of the current quantum bit initial mapping, and outputting the optimal physical quantum circuit C1 and its corresponding quantum bit initial mapping π1 obtained in this process, the optimal physical quantum circuit refers to the physical quantum circuit with the least quantum gates; S23, updating the best physical quantum circuit C2 so far and its corresponding initial quantum bit mapping π2; Compare the optimal physical quantum circuit C1 returned by the most recent local search process with the optimal physical quantum circuit C2 so far. If the latter is empty or the number of quantum gates of the former is less than that of the latter, update the latter with the former and update the initial mapping accordingly, setting C2 = C1 and π2 = π1. S24, randomly perturb the optimal quantum bit initial mapping π2 so far, and use the perturbed result as the quantum bit initial mapping π0 for starting the next round of local search process; The random perturbation process is carried out by performing a random perturbation on the physical quantum bit sequence [π2(q1),π2(q2),…,π2(q n-1 )] is randomly reordered, and the reordered array is set to plist[], then the initial mapping relationship π0 of the next round of quantum bits is constructed, so that π0(q i ) = plist[i], where i = {0, 1, 2, ..., n-1}; S25, add 1 to the value of the iteration round counter i, and determine whether to start the next round of local search. If the value of i does not exceed the round number threshold I max , then the next round of local search is started, that is, jumping to step S22 for execution; otherwise, the operation is terminated and the optimal physical quantum bit circuit C2 and its corresponding quantum bit initial mapping π2 are returned.

4. The iterative optimization method for quantum circuit mapping according to claim 3, characterized in that: In step S21, the initialization operation specifically includes the following steps: S211, set the initial value of the iteration round counter i to 0, and set the round number threshold I at the same time max The iteration round counter i is used to record the number of rounds currently iterated in real time, and the round number threshold I max Used to set the maximum number of iterations allowed; S212, randomly generate a quantum bit mapping relationship, and use it as the quantum bit initial mapping π0, the method of randomly generating the quantum bit initial mapping, for the array Arr = [v0, v1, ..., v m-1 ] are randomly reordered, where m is the total number of physical qubits in the NISQ device; if the quantum circuit contains n logical qubits, where n≤m, then the first n elements of the Arr array are taken to construct a qubit mapping relationship π0 such that π0(q i )=Arr[i], where i={0,1,2,…,n-1}; S213. Initialize the optimal physical quantum bit circuit C2 and its corresponding quantum bit initial mapping π2 to be empty. The optimal physical quantum circuit refers to the physical quantum circuit with the least quantum gates found in multiple rounds of local search.

5. The iterative optimization method for quantum circuit mapping according to claim 3, characterized in that: In step S22, the local search process based on bidirectional mapping specifically includes the following steps: S221, initialization operation S2211, set the maximum number of times L that each round of local search allows for traversal of the quantum circuit max , and set the initial value of the traversal counter l to 0, the traversal times calculator l is used to record the current traversal times in real time; S2212, initializing the optimal physical quantum bit circuit C1 and its corresponding quantum bit initial mapping π1 that can be found in this round of local search to empty, wherein the optimal physical quantum circuit refers to the physical quantum circuit with the least quantum gates found in this round of local search; S2213, the quantum gate dependency graph G c Initialize to the quantum gate dependency graph corresponding to the original quantum circuit, the quantum gate dependency graph is obtained by the quantum circuit preprocessing step; S222, based on the initial mapping of quantum bits π0, and according to the quantum gate dependency graph G c The traversal order is defined, the qubit routing process is called, and the physical quantum circuit C3 generated by the qubit routing process and the qubit mapping relationship π3 after qubit routing are returned; S223, update the optimal physical quantum bit circuit C1 of this round of local search and its corresponding quantum bit initial mapping π1, compare the physical quantum circuit C3 generated by the most recent quantum bit routing with the optimal physical quantum bit circuit C1 of this round so far, if C1 is empty, or the number of quantum gates in C3 is less than the number of quantum gates in C1, then update C1 to C3, that is, set C1=C3, and update the initial mapping accordingly, that is, set π1=π3; S224, update the quantum bit initial mapping π0 and the quantum gate dependency graph G c , so as to prepare for the next call to the quantum bit routing process, which specifically includes the following steps: S2241, updating the initial quantum bit mapping π0 to the quantum bit mapping π3 returned by the most recent quantum bit routing process, i.e. setting π0=π3; S2242, the quantum gate dependency graph G c Switch between the original and reverse quantum gate dependency graphs. c If it is the original quantum gate dependency graph, it is switched to the reverse quantum gate dependency graph; otherwise, it is switched to the original quantum gate dependency graph; S225, add 1 to the value of the traversal counter l, and determine whether it is necessary to start the next quantum bit routing process. If the value of l does not exceed the round number threshold L max , then the next quantum bit routing process is started, that is, jumping to step S222 for execution; otherwise, the operation is terminated and the optimal physical quantum bit circuit C1 of this round and its corresponding quantum bit initial mapping π1 are returned.

6. The iterative optimization method for quantum circuit mapping according to claim 5, characterized in that: In step S222, the quantum bit routing process is specifically The following steps are involved: The first step is to start from the quantum gate dependency graph G c Read the quantum gate operations in the active state to form an active quantum gate set; The quantum gate operation in the active state has no predecessor node in the quantum gate dependency graph, that is, the quantum gates it depends on have been deleted from the quantum gate dependency graph; The second step is to check whether there is an executable quantum gate in the active quantum gate set. If not, proceed to the next step. Otherwise, delete this row of executable gates from the active quantum gate set and the quantum gate dependency graph, and add it to the physical quantum circuit C3. Then check whether the quantum gate dependency graph after the deletion operation is empty. If not, return to the first step. Otherwise, end the operation and return to the physical quantum circuit C3 and the final quantum bit mapping relationship π3. The executable gate refers to an active quantum gate that satisfies the nearest neighbor interaction constraint, and the physical quantum circuit refers to a target quantum circuit that satisfies the nearest neighbor interaction constraint on a NISQ quantum computing device; The third step is to generate a set of candidate SWAP gates. The candidate SWAP gates must meet the following conditions: (1) The SWAP gate shares the same physical qubit with at least one quantum gate in the active quantum gate set; (2) Executing the SWAP gate will bring non-negative effects to the execution of every quantum gate in the set of active quantum gates; (3) The SWAP gate complies with the nearest neighbor interaction constraint, that is, it acts on two directly connected physical qubits in the coupling graph; In the fourth step, for each SWAP gate in the candidate SWAP gate set, a look-ahead window W is constructed for it. The look-ahead window includes the X-layer sub-circuit to be executed. The look-ahead window is constructed according to the following steps: 1) Construct the quantum gate dependency graph G c A copy of G d ; 2) The G d All quantum gates in the first layer are added to the look-ahead window W, and these quantum gates are removed from G d Delete, the first layer of quantum gates refers to, in G d All quantum gates without predecessor nodes in the , that is, the aforementioned active quantum gates; 3) Repeat step 2) until the look-ahead window W contains the first X layers of sub-lines; Step 5: For each SWAP gate in the candidate SWAP gate set, calculate the profit function of the SWAP gate in its look-ahead window W, and insert the SWAP gate with the largest function value into the physical quantum circuit, update the current quantum bit mapping relationship according to the inserted SWAP gate, and then return to the first step to continue execution; For a SWAP gate, under the quantum bit mapping relationship π, the form of the profit function is: h(π)=∑eff(g)+N exe , where W represents the look-ahead window corresponding to the SWAP, g represents each quantum gate in the look-ahead window W, and eff(g) represents the reduction in the physical distance of the quantum gate g after the SWAP gate is applied, which is equal to the original physical distance of the g gate minus the physical distance after the SWAP gate is applied; The updating of the current quantum bit mapping relationship according to the inserted SWAP gate has the following characteristics: If the current quantum bit mapping relationship is π, and satisfies π(q i )=v x ,π(q j )=v y , then in the physical quantum bit v x and v y After applying the SWAP gate, the mapping relationship π is updated to And in the new mapping relationship Next, the logical quantum bit q i and q j The positions of will be exchanged, that is, π(q i )=v y ,π(q j )=v x .

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