Shifting register unit, driving method thereof, display substrate and display device

Abstract

The invention discloses a shift register unit and a driving method thereof, a display substrate and a display device, and the shift register unit comprises a node control sub-circuit which is configured to provide a signal of a signal input end or a first power supply end for a first node under the signal control of a first clock signal end and a second clock signal end, providing a signal of a second power supply end or a first clock signal end for a second node; the pull-down sub-circuit is configured to provide a signal of a third power supply end to the first node; the output sub-circuit is configured to provide a signal of the first power supply end or the second clock signal end to the first signal output end under the control of signals of the first node, the second node and the second power supply end, and the absolute value of the voltage value of the signal of the third power supply end is larger than that of the voltage value of the signal of the second power supply end.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and specifically to a shift register unit and a driving method thereof, a display substrate, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting elements and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a shift register unit, comprising: a node control subcircuit, an output subcircuit, and a pull-down subcircuit;

[0005] The node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, and the second node, respectively, and is configured to provide a signal from the signal input terminal or the first power supply terminal to the first node, and provide a signal from the second power supply terminal or the first clock signal terminal to the second node under the control of the signal from the first clock signal terminal and the second clock signal terminal;

[0006] The pull-down sub-circuit is electrically connected to the first node and the third power supply terminal, respectively, and is configured to provide a signal of the third power supply terminal to the first node;

[0007] The output subcircuit is electrically connected to the second clock signal terminal, the first power terminal, the second power terminal, the first signal output terminal, the first node and the second node respectively, and is configured to provide a signal from the first power terminal or the second clock signal terminal to the first signal output terminal under the control of the signals from the first node, the second node and the second power terminal;

[0008] An absolute value of a voltage value of a signal at the third power supply terminal is greater than an absolute value of a voltage value of a signal at the second power supply terminal.

[0009] In an exemplary embodiment, the pull-down sub-circuit includes: an eleventh transistor;

[0010] A first electrode of the eleventh transistor is electrically connected to the third power supply terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

[0011] In an exemplary embodiment, a control electrode of the eleventh transistor is electrically connected to the first node.

[0012] In an exemplary embodiment, the node control subcircuit includes: a first transistor, a second transistor, a third transistor, a sixth transistor, and a seventh transistor;

[0013] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0014] The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0015] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node;

[0016] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fourth node;

[0017] The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first node.

[0018] In an exemplary embodiment, the output subcircuit includes: a fourth transistor, a fifth transistor, and an eighth transistor;

[0019] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first signal output terminal;

[0020] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first signal output terminal;

[0021] The control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node.

[0022] In an exemplary embodiment, the pull-down sub-circuit includes: an eleventh transistor;

[0023] The eleventh transistor control electrode is electrically connected to the third node.

[0024] In an exemplary embodiment, the output subcircuit further includes: at least one of a first capacitor and a second capacitor;

[0025] The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power supply terminal;

[0026] The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first signal output terminal.

[0027] In an exemplary embodiment, the output subcircuit is also electrically connected to the third clock signal terminal and the second signal output terminal, respectively, and is configured to provide a signal from the second power supply terminal or the third clock signal terminal to the second signal output terminal under the control of the signals of the first node and the second node.

[0028] In an exemplary embodiment, the output subcircuit includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0029] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first signal output terminal;

[0030] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first signal output terminal;

[0031] The control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node;

[0032] The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is connected to the third clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the second signal output terminal;

[0033] The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the second signal output terminal.

[0034] In an exemplary embodiment, the output sub-circuit further includes: a twelfth transistor; the control electrode of the ninth transistor is electrically connected to the first node through the twelfth transistor;

[0035] The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the control electrode of the ninth transistor.

[0036] In an exemplary embodiment, the output subcircuit further includes: at least one of a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

[0037] The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power supply terminal;

[0038] The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first signal output terminal;

[0039] A first electrode plate of the third capacitor is electrically connected to the control electrode of the ninth transistor, and a second electrode plate of the third capacitor is connected to the second signal output terminal;

[0040] The first plate of the fourth capacitor is electrically connected to the second node, and the second plate of the fourth capacitor is connected to the second power supply terminal.

[0041] In an exemplary embodiment, the signal at the third clock signal terminal and the signal at the second clock signal terminal are inverted signals.

[0042] In an exemplary embodiment, it further includes: an output control subcircuit;

[0043] The output control subcircuit is electrically connected to the first power supply terminal and the first signal output terminal respectively, and is configured to store a voltage difference between the signal at the first signal output terminal and the signal at the first power supply terminal.

[0044] In an exemplary embodiment, the output control subcircuit includes: a fifth capacitor;

[0045] The first electrode of the fifth capacitor is electrically connected to the first power supply terminal, and the second electrode of the fifth capacitor is electrically connected to the first signal output terminal.

[0046] In an exemplary embodiment, the signal at the first clock signal terminal and the signal at the second clock signal terminal are not active level signals at the same time.

[0047] In a second aspect, the present disclosure further provides a display substrate, comprising: a substrate, and sub-pixels, gate lines, and a gate driving circuit arranged on the substrate, wherein the substrate is provided with a display area and a non-display area, the gate driving circuit is located in the non-display area, the sub-pixels and the gate lines are located in the display area, and the gate lines are electrically connected to the sub-pixels and the gate driving circuit, respectively;

[0048] The gate driving circuit includes: a plurality of cascaded shift register units, wherein the first signal output terminal of the i-th shift register unit is connected to the signal input terminal of the (i + 1)-th shift register unit, 1 ≤ i < N, and N is the total number of stages of the shift register units.

[0049] In an exemplary embodiment, the first signal output terminal of the shift register unit is electrically connected to the gate line.

[0050] In an exemplary embodiment, it further includes: an initial signal line, a first clock signal line, a second clock signal line, a first power supply line, a second power supply line, and a third power supply line disposed on the substrate and located in the non-display area;

[0051] Any one of the initial signal line, the first clock signal line, the second clock signal line, the first power supply line, the second power supply line, and the third power supply line extends along a first direction, the gate line extends along a second direction, and the first direction intersects the second direction.

[0052] In an exemplary embodiment, the initial signal line, the first clock signal line, the second clock signal line, and the first power supply line are arranged in sequence along the direction close to the display area and are located on the side of the shift register unit away from the display area.

[0053] In an exemplary embodiment, the shift register unit includes: a plurality of transistors, the second power supply line is located on the side of the first power supply line close to the display area and is located between the plurality of transistors of the shift register unit.

[0054] In an exemplary embodiment, the third power supply line is located on the side of the second power supply line close to the display area, and the orthographic projection on the substrate overlaps with the orthographic projection of the shift register unit on the substrate partially.

[0055] In an exemplary embodiment, the shift register unit includes: a first transistor, a second transistor, a third transistor, a sixth transistor, and a seventh transistor;

[0056] At least a part of any one of the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor is located between the first power supply line and the second power supply line.

[0057] In an exemplary embodiment, the shift register unit includes: a fourth transistor, a fifth transistor, an eighth transistor, an eleventh transistor, and a twelfth transistor, and the number of the second power supply lines is at least one;

[0058] At least a portion of any one of the fourth transistor, the fifth transistor, the eighth transistor, the eleventh transistor and the twelfth transistor is located on a side of the second power line close to the display area.

[0059] In an exemplary embodiment, the shift register unit includes: a second capacitor;

[0060] The second capacitor is located on a side of the third power line close to the display area.

[0061] In an exemplary embodiment, the invention further comprises: a third clock signal line and a fourth clock signal line disposed on the substrate and located in the non-display area, wherein any one of the third clock signal line and the fourth clock signal line extends along the first direction;

[0062] There are two second power lines. The second power line close to the display area is located on a side of any one of the third clock signal line and the fourth clock signal line close to the display area, and the second power line far from the display area is located between the first power line and the third power line.

[0063] In an exemplary embodiment, the shift register unit includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a fourth capacitor;

[0064] The fourth transistor, the fifth transistor, the eighth transistor, the eleventh transistor and the twelfth transistor are located between the second power line and any one of the third clock signal line and the fourth clock signal line far from the display area, and the ninth transistor and the tenth transistor are located on a side of the second power line close to the display area;

[0065] The orthographic projection of the second power line close to the display area on the substrate partially overlaps with the orthographic projection of the fourth capacitor on the substrate.

[0066] In an exemplary embodiment, the first clock signal terminal of the i-th stage shift register unit is electrically connected to one of the first clock signal line and the second clock signal line, and the second clock signal terminal of the i-th stage shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line;

[0067] The first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines.

[0068] In an exemplary embodiment, the shift register unit includes: a fourth transistor and a fifth transistor;

[0069] An orthographic projection of the third power line on the substrate partially overlaps with orthographic projections of the fourth transistor and the fifth transistor on the substrate.

[0070] In an exemplary embodiment, the active layer of the eighth transistor extends along the second direction, any one of the first electrode and the second electrode of the eighth transistor extends along the first direction, and the gate electrode of the eighth transistor at least partially extends along the first direction.

[0071] In an exemplary embodiment, the gate electrode of the eleventh transistor is an integral structure with the gate electrode of the fifth transistor, the orthographic projection of the first electrode of the eleventh transistor on the substrate partially overlaps with the orthographic projection of the third power line on the substrate, and is electrically connected to the third power line, and the second electrode of the eleventh transistor is an integral structure with the first electrode of the eighth transistor and the first electrode of the twelfth transistor.

[0072] In an exemplary embodiment, a width of any one of the first power line, the second power line, and the third power line along the second direction is smaller than a width of any one of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line along the second direction.

[0073] In an exemplary embodiment, the third clock signal terminal of the i-th stage shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line, and the third clock signal terminal of the i+1-th stage shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.

[0074] In an exemplary embodiment, a channel width of an active layer of the tenth transistor is greater than a channel width of an active layer of the fourth transistor.

[0075] In an exemplary embodiment, a channel width of an active layer of the tenth transistor is not less than 90 micrometers.

[0076] In an exemplary embodiment, a channel width of an active layer of the fourth transistor is no greater than 50 micrometers.

[0077] In an exemplary embodiment, a channel width of an active layer of the ninth transistor is greater than a channel width of an active layer of the fifth transistor.

[0078] In an exemplary embodiment, a channel width of an active layer of the ninth transistor is not less than 90 micrometers.

[0079] In an exemplary embodiment, a channel width of an active layer of the fifth transistor is no greater than 50 micrometers.

[0080] In an exemplary embodiment, the second signal output terminal of the shift register unit is electrically connected to the gate line.

[0081] In a third aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0082] In a fourth aspect, the present disclosure further provides a driving method of a shift register unit, which is configured to drive the above-mentioned shift register unit, and the method includes:

[0083] The node control subcircuit provides a signal from the signal input terminal or the first power supply terminal to the first node and provides a signal from the second power supply terminal or the first clock signal terminal to the second node under the control of the signals from the first clock signal terminal and the second clock signal terminal;

[0084] The pull-down sub-circuit provides a signal of the third power supply terminal to the first node;

[0085] The output subcircuit provides a signal from the first power supply terminal or the second clock signal terminal to the first signal output terminal under the control of the signals from the first node and the second node.

[0086] In an exemplary embodiment, the shift register unit further includes: an output control subcircuit;

[0087] The method further comprises: the output subcircuit provides a signal from a second power supply terminal or a third clock signal terminal to a second signal output terminal under the control of the signals from the first node and the second node;

[0088] The output control subcircuit stores a voltage difference between the signal at the first signal output terminal and the signal at the first power supply terminal.

[0089] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0091] Figure 1 A schematic diagram of the structure of the shift register unit provided in the embodiment of the present disclosure Figure 1 ;

[0092] Figure 2 is an equivalent circuit diagram of a pull-down subcircuit;

[0093] Figure 3 is an equivalent circuit diagram of another pull-down subcircuit;

[0094] Figure 4 is the equivalent circuit diagram of the node control subcircuit;

[0095] Figure 5 The equivalent circuit of the output subcircuit is Figure 1 ;

[0096] Figure 6 is the equivalent circuit diagram of the output subcircuit;

[0097] Figure 7 A schematic diagram of the structure of the shift register unit provided in the embodiment of the present disclosure Figure 2 ;

[0098] Figure 8 The equivalent circuit of the output subcircuit is Figure 3 ;

[0099] Fig. 9 The equivalent circuit of the output subcircuit is Figure 4 ;

[0100] Fig.10 A schematic diagram of the structure of the shift register unit provided in the embodiment of the present disclosure Figure 3 ;

[0101] Fig.11 is the equivalent circuit diagram of the output control subcircuit;

[0102] Fig.12 The equivalent circuit of the shift register unit is Figure 1 ;

[0103] Fig.13 The equivalent circuit of the shift register unit is Figure 2 ;

[0104] Fig.14 The equivalent circuit of the shift register unit is Figure 3 ;

[0105] Fig.15 The equivalent circuit of the shift register unit is Figure 4 ;

[0106] Fig.16 The equivalent circuit of the shift register unit is Figure 5 ;

[0107] Fig.17 The equivalent circuit of the shift register unit is Figure 6 ;

[0108] Fig.18 The equivalent circuit of the shift register unit is Figure 7 ;

[0109] Fig.19 for Fig.12 and Fig.13 The signal timing simulation diagram of the shift register unit provided;

[0110] Fig. 20 for Figures 14 to 18 The signal timing simulation diagram of the shift register provided;

[0111] Fig.21 is a comparison diagram of signals at the first node and the second signal output terminal of different shift register units;

[0112] Fig. 22 is a structural schematic diagram of a display device;

[0113] Fig.23 A schematic diagram of a planar structure of a display substrate Figure 1 ;

[0114] Fig.24 A schematic diagram of a planar structure of a display substrate Figure 2 ;

[0115] Fig.25 A schematic diagram of a planar structure of a display substrate Figure 3 ;

[0116] Fig.26A is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0117] Fig.26B for Fig.26A The working timing diagram of the pixel driving circuit provided;

[0118] Fig.27A is a schematic diagram of an equivalent circuit of another pixel driving circuit;

[0119] Fig.27B for Fig.27A The working timing diagram of the pixel driving circuit provided;

[0120] Fig.28 Schematic diagram of the cascade connection of the gate drive circuit Figure 1 ;

[0121] Fig.29 Schematic diagram of the cascade connection of the gate drive circuit Figure 2 ;

[0122] Fig.30 Schematic diagram of the structure of the display substrate Figure 1 ;

[0123] Fig.31 Schematic diagram of the structure of the display substrate Figure 2 ;

[0124] Fig.32 for Fig.30 A schematic diagram after forming a semiconductor layer pattern;

[0125] Fig.33 for Fig.31 A schematic diagram after forming a semiconductor layer pattern;

[0126] Fig.34 for Fig.30 A schematic diagram of a first conductive layer pattern in FIG.

[0127] Fig.35 for Fig.30 A schematic diagram after forming a first conductive layer pattern;

[0128] Fig.36 for Fig.31 A schematic diagram of a first conductive layer pattern in FIG.

[0129] Fig.37 for Fig.31 A schematic diagram after forming a first conductive layer pattern;

[0130] Fig.38 for Fig.30 A schematic diagram of a second conductive layer pattern in FIG.

[0131] Fig.39 for Fig.30 A schematic diagram after forming a second conductive layer pattern;

[0132] Fig.40 for Fig.31 A schematic diagram of a second conductive layer pattern in FIG.

[0133] Fig.41 for Fig.31 A schematic diagram after forming a second conductive layer pattern;

[0134] Fig.42 for Fig.30 A schematic diagram after forming a third insulating layer pattern;

[0135] Fig.43 for Fig.31 A schematic diagram after forming a third insulating layer pattern;

[0136] Fig.44 for Fig.30 A schematic diagram of a third conductive layer pattern in FIG.

[0137] Fig.45 for Fig.30 A schematic diagram after forming a third conductive layer pattern;

[0138] Fig.46 for Fig.31 A schematic diagram of a third conductive layer pattern in FIG.

[0139] Fig.47 for Fig.31 A schematic diagram after forming a third conductive layer pattern;

[0140] Fig.48 for Fig.30 A schematic diagram after forming a fourth insulating layer pattern;

[0141] Fig.49 for Fig.31 A schematic diagram after forming a fourth insulating layer pattern;

[0142] Fig.50 for Fig.30 and Fig.31 A schematic diagram of a fourth conductive layer pattern in FIG.

[0143] Fig.51 for Fig.30 A schematic diagram after forming a fourth conductive layer pattern;

[0144] Fig.52 for Fig.31 Schematic diagram after forming the fourth conductive layer pattern. DETAILED DESCRIPTION

[0145] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the usual design.

[0146] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0147] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0148] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0149] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0150] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0151] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0152] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0153] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0154] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0155] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.

[0156] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0157] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0158] The display substrate includes: a pixel driving circuit, a light-emitting element and a gate driving circuit, wherein the gate driving circuit is configured to provide a gate signal to the transistor in the pixel driving circuit so that the pixel driving circuit can drive the light-emitting element to emit light. The display substrate uses low-temperature polysilicon (LTPS) technology, which has advantages such as high resolution, high response speed, high brightness, and high aperture ratio. Although it is popular in the market, LTPS technology also has some defects, such as high production cost and high power consumption. At this time, the low-temperature polycrystalline oxide (LTPO) technology solution came into being. Compared with LTPS technology, the pixel driving circuit includes low-temperature polysilicon transistors. The pixel driving circuit in LTPO technology includes low-temperature polysilicon transistors and metal oxide transistors. The metal oxide transistor has a smaller leakage current, which makes the pixel point respond faster. The display substrate adds an extra layer of oxide, which can reduce the energy consumption required to excite the pixel point, thereby reducing the power consumption when the screen is displayed. The display product using LTPO technology includes a set of driving circuits to control the metal oxide transistors in the display product. As the size, resolution and refresh rate of display substrates increase, the compensation time of pixel driving circuits in one frame is getting shorter and shorter. What's worse, the driving circuit used to control metal oxide transistors in the display substrate usually fails to reach a predetermined voltage due to insufficient voltage at some nodes, that is, the driving ability of the driving circuit controlling the metal oxide transistor is weak, which leads to a low conduction degree of the metal oxide transistor, affecting the performance of the pixel driving circuit, thereby reducing the display effect of the display substrate.

[0159] Figure 1 A schematic diagram of the structure of the shift register unit provided in the embodiment of the present disclosure Figure 1 .like Figure 1 As shown, the shift register unit provided by the embodiment of the present disclosure may include: a node control subcircuit, an output subcircuit and a pull-down subcircuit.

[0160] like Figure 1As shown, the node control sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK1, the second clock signal terminal CK2, the first power supply terminal V1, the second power supply terminal V2, the first node N1 and the second node N2, respectively, and is configured to provide the signal of the signal input terminal IN or the first power supply terminal V1 to the first node N1, and provide the signal of the second power supply terminal V2 or the first clock signal terminal CK1 to the second node N2 under the control of the signal of the first clock signal terminal CK1 and the second clock signal terminal CK2; the pull-down sub-circuit is electrically connected to the first node N1 and the third power supply terminal V3, respectively, and is configured to provide the signal of the third power supply terminal V3 to the first node N1; the output sub-circuit is electrically connected to the second clock signal terminal CK2, the first power supply terminal V1, the second power supply terminal V2, the first signal output terminal OUT1, the first node N1 and the second node N2, respectively, and is configured to provide the signal of the first power supply terminal V1 or the second clock signal terminal CK2 to the first signal output terminal OUT1 under the control of the signal of the second power supply terminal V2, the first node N1 and the second node N2.

[0161] In an exemplary embodiment, the first power terminal V1 continuously provides a high level signal, and the second power terminal V2 and the third power terminal V3 continuously provide a low level signal.

[0162] In an exemplary embodiment, the absolute value of the voltage value of the signal at the third power supply terminal V3 is greater than the absolute value of the voltage value of the signal at the second power supply terminal V2. Exemplarily, the width of the signal line connected to the second power supply terminal V2 is different from the width of the signal line connected to the third power supply terminal V3.

[0163] In an exemplary embodiment, a signal at any one of the first clock signal terminal CK1 and the second clock signal terminal CK2 may be a periodic pulse signal.

[0164] In an exemplary embodiment, the signal at the signal output terminal IN is a single pulse signal.

[0165] The shift register unit provided by the embodiment of the present disclosure includes: a node control subcircuit, an output subcircuit and a pull-down subcircuit, wherein the node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node and the second node, respectively, and is configured to provide the signal of the signal input terminal or the first power supply terminal to the first node, and provide the signal of the second power supply terminal or the first clock signal terminal to the second node under the control of the signal of the first clock signal terminal and the second clock signal terminal; the pull-down subcircuit is electrically connected to the first node and the third power supply terminal, respectively, and is configured to provide the signal of the third power supply terminal to the first node; the output subcircuit is electrically connected to the second clock signal terminal, the first power supply terminal, the first signal output terminal, the first node and the second node, respectively, and is configured to provide the signal of the first power supply terminal or the second clock signal terminal to the first signal output terminal under the control of the signal of the first node and the second node, and the absolute value of the voltage value of the signal of the third power supply terminal is greater than the absolute value of the voltage value of the signal of the second power supply terminal. The shift register unit provided in the present disclosure can pull down the signal of the first node to a low-level signal with a lower voltage value by setting a pull-down sub-circuit, so that some transistors in the shift register unit can be fully turned on, and then the voltage of the output signal of the shift register unit can reach a predetermined voltage, thereby improving the driving capability of the shift register unit, and can ensure the conduction capability of the transistors in the pixel driving circuit, thereby improving the performance of the pixel driving circuit and the display effect of the display substrate.

[0166] In an exemplary embodiment, Figure 2 is an equivalent circuit diagram of a pull-down subcircuit, Figure 3 is the equivalent circuit diagram of another pull-down subcircuit. Figure 2 and Figure 3 As shown, the pull-down sub-circuit may include: an eleventh transistor T11. A first electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal V3, and a second electrode of the eleventh transistor T11 is electrically connected to the first node N1.

[0167] In an exemplary embodiment, Figure 4 is the equivalent circuit diagram of the node control subcircuit. Figure 4As shown, the node control subcircuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6 and a seventh transistor T7. Among them, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the first power supply terminal V1, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh transistor T7 is connected to the fourth node, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0168] In an exemplary embodiment, Figure 5 The equivalent circuit of the output subcircuit is Figure 1 .like Figure 5 As shown, the output subcircuit may include: a fourth transistor T4, a fifth transistor T5 and an eighth transistor T8. The control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3.

[0169] In an exemplary embodiment, Figure 2 As shown, the control electrode of the eleventh transistor T11 may be electrically connected to the first node N1.

[0170] In an exemplary embodiment, Figure 3 As shown, the control of the eleventh transistor may be electrically connected to the third node N3.

[0171] In an exemplary embodiment, Figure 6 The equivalent circuit of the output subcircuit is Figure 2 .like Figure 6As shown, the output subcircuit may include: at least one of a first capacitor C1 and a second capacitor C2. The first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the first power supply terminal V1; the first plate of the second capacitor C2 is electrically connected to the third node, and the second plate of the second capacitor C2 is electrically connected to the first signal output terminal OUT1. Figure 6 The description is made by taking the output sub-circuit further including the first capacitor C1 and the second capacitor C2 as an example.

[0172] In an exemplary embodiment, Figure 7 A schematic diagram of the structure of the shift register unit provided in the embodiment of the present disclosure Figure 2 .like Figure 7 As shown, the output sub-circuit is electrically connected to the second clock signal terminal CK2, the first power supply terminal V1, the first signal output terminal OUT1, the first node N1, the second node N2, the third clock signal terminal CK3, the second power supply terminal V2 and the second signal output terminal OUT2, respectively, and is configured to provide a signal from the first power supply terminal V1 or the second clock signal terminal CK2 to the first signal output terminal OUT1, and provide a signal from the second power supply terminal V2 or the third clock signal terminal CK3 to the second signal output terminal OUT2 under the control of the signals of the first node N1 and the second node N2.

[0173] In an exemplary embodiment, the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are single pulse signals, and the signal at the first signal output terminal OUT1 and the signal at the second signal output terminal OUT2 are inverted signals to each other, that is, when the signal at the first signal output terminal OUT1 is a high-level signal, the signal at the second signal output terminal OUT2 is a low-level signal, and when the signal at the first signal output terminal OUT1 is a low-level signal, the signal at the second signal output terminal OUT2 is a high-level signal.

[0174] In an exemplary embodiment, the first signal output terminal OUT1 is configured to output a cascade signal, which is a low level signal, and the second signal output terminal OUT2 is configured to output a gate scan signal. Exemplarily, the gate scan signal is a high level signal or a low level signal.

[0175] In an exemplary embodiment, Figure 8 The equivalent circuit of the output subcircuit is Figure 3 .like Figure 8As shown, the output sub-circuit may include: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10. Among them, the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the third clock signal terminal CK3, and the second electrode of the ninth transistor T9 is electrically connected to the second signal output terminal OUT2; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the second signal output terminal OUT2.

[0176] In an exemplary embodiment, Fig. 9 The equivalent circuit of the output subcircuit is Figure 4 .like Fig. 9As shown, the output subcircuit may include: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10 and a twelfth transistor T12, wherein the control electrode of the ninth transistor T9 is electrically connected to the first node N1 through the twelfth transistor T12. Among them, the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the ninth transistor T 9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the third clock signal terminal CK3, and the second electrode of the ninth transistor T9 is electrically connected to the second signal output terminal OUT2; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the second power supply terminal V2, the second electrode of the tenth transistor T10 is electrically connected to the second signal output terminal OUT2, the control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2, the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, and the second electrode of the twelfth transistor T12 is electrically connected to the control electrode of the ninth transistor T9.

[0177] In an exemplary embodiment, the twelfth transistor T12 is a continuously turned-on transistor, which can ensure the stability of the signal at the control electrode of the ninth transistor T9, avoid large deviation of the output signal of the shift register unit, and ensure the stability of the output signal of the shift register unit.

[0178] In an exemplary embodiment, Figure 8 and Fig. 9 As shown, the output sub-circuit may further include: at least one of a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4.

[0179] In an exemplary embodiment, Figure 8 and Fig. 9As shown, the first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the first power supply terminal V1; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate of the second capacitor C2 is connected to the first signal output terminal OUT1; the first plate of the third capacitor C3 is electrically connected to the control electrode of the ninth transistor T9, and the second plate of the third capacitor C3 is connected to the second signal output terminal OUT2; the first plate of the fourth capacitor C4 is electrically connected to the second node N2, and the second plate of the fourth capacitor C4 is connected to the second power supply terminal V2.

[0180] In an exemplary embodiment, the output subcircuit may include: a second capacitor C2 and a fourth capacitor C4, or may include: a second capacitor C2, or may include: a first capacitor C1 and a third capacitor C3, or may include: a third capacitor C3, or may include: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. Figure 8 and Fig. 9 The output subcircuit includes: a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4. The first capacitor C1 can ensure the stability of the second node N2, the second capacitor C2 can ensure the voltage difference between the third node N3 and the signal of the first signal output terminal OUT1, the third capacitor can ensure the voltage difference between the first node N1 and the signal of the second signal output terminal OUT2, and the fourth capacitor C4 can ensure the stability of the signal of the second node N2.

[0181] In an exemplary embodiment, Fig.10 A schematic diagram of the structure of the shift register unit provided in the embodiment of the present disclosure Figure 3 .like Fig.10 As shown, the shift register unit may further include: an output control subcircuit, wherein the output control subcircuit is electrically connected to the first power supply terminal V1 and the first signal output terminal OUT1 respectively, and is configured to store the voltage difference between the signal of the first signal output terminal OUT1 and the first power supply terminal V1. Fig.10 The output subcircuit of the shift register unit in can be electrically connected to the second clock signal terminal CK2, the first power supply terminal V1, the first node N1, the second node N2 and the first signal output terminal OUT1, or can be electrically connected to the second clock signal terminal CK2, the third clock signal line CK3, the first power supply terminal V1, the second power supply terminal V2, the first node N1, the second node N2, the first signal output terminal OUT1 and the second signal output terminal OUT2.

[0182] In the present disclosure, since the signal outputted by the first signal output terminal OUT1 is a cascade signal, that is, the signal line connected to the first signal output terminal OUT1 will not flow through the display area where the pixel driving circuit is located, that is, the load of the signal line connected to the first signal output terminal OUT1 is small, and it is easily affected by the parasitic capacitance of some transistors in the output subcircuit, thereby causing the signal of the first signal output terminal OUT1 to fluctuate. However, the present disclosure can make the signal outputted by the first signal output terminal OUT1 more stable by setting the output control subcircuit, thereby improving the performance of the shift register unit.

[0183] In an exemplary embodiment, Fig.11 is the equivalent circuit diagram of the output control subcircuit. Fig.11 As shown, in an exemplary embodiment, the output control subcircuit includes: a fifth capacitor C5, wherein a first electrode of the fifth capacitor C5 is electrically connected to the first power supply terminal V1, and a second electrode of the fifth capacitor C5 is electrically connected to the first signal output terminal OUT1.

[0184] In an exemplary embodiment, Fig.10 and Fig.11 The dotted line in the figure indicates that the connection may be made or not made.

[0185] In an exemplary embodiment, Fig.12 The equivalent circuit of the shift register unit is Figure 1 , Fig.13 The equivalent circuit of the shift register unit is Figure 2 .like Fig.12 and Fig.13 As shown, the shift register unit can also output a control subcircuit, wherein the node control subcircuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6 and a seventh transistor T7, the output subcircuit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, and at least one of the first capacitor C1 and the second capacitor C2, the pull-down subcircuit includes: an eleventh transistor T11, and the output control subcircuit includes: a fifth capacitor C5. Fig.12 The shift register unit includes: a second capacitor C2, Fig.13 The description is made by taking the shift register unit including: a first capacitor C1 and a second capacitor C2 as an example. Fig.12 The description is made by taking the example that the control electrode of the eleventh transistor is electrically connected to the third node N3. Fig.13 The description is made by taking the example that the control electrode of the eleventh transistor is electrically connected to the first node N1.

[0186] In an exemplary embodiment, Fig.12 and Fig.13As shown, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, and the first electrode of the sixth transistor T6 is electrically connected to the second node N2. A control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, a first electrode of the seventh transistor T7 is connected to the fourth node, and a second electrode of the seventh transistor T7 is electrically connected to the first node N1; a control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, a first electrode of the eighth transistor T8 is connected to the first node N1, and a second electrode of the eighth transistor T8 is electrically connected to the third node N3; a control electrode of the eleventh transistor T11 is electrically connected to the first node N1 or the third node N3 The first electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal V3, and the second electrode of the eleventh transistor T11 is electrically connected to the first node N1; the first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the first power supply terminal V1; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate of the second capacitor C2 is connected to the first signal output terminal OUT1; the first plate of the fifth capacitor C5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth capacitor C5 is electrically connected to the first signal output terminal OUT1. Fig.12 The control electrode of the eleventh transistor T11 is electrically connected to the third node N3 as an example for explanation. Fig.13 The description is made by taking the case where the control electrode of the eleventh transistor T11 is electrically connected to the first node N1 as an example.

[0187] In an exemplary embodiment, the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).

[0188] In an exemplary embodiment, the first to eighth transistors T1 to T8 and the eleventh transistor T11 may all be P-type transistors.

[0189] In an exemplary embodiment, Fig.14 The equivalent circuit of the shift register unit is Figure 3 , Fig.15 The equivalent circuit of the shift register unit is Figure 4 .like Fig.14 and Fig.15 As shown, the shift register unit also includes: an output control subcircuit, the node control subcircuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6 and a seventh transistor T7, the output subcircuit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10 and at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4, the pull-down subcircuit includes: an eleventh transistor T11, and the output control subcircuit includes: a fifth capacitor C5. Fig.14 and Fig.15 The description is made by taking the shift register unit including: a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4 as an example. Fig.14 The description is made by taking the example that the control electrode of the eleventh transistor is electrically connected to the third node N3. Fig.15 The description is made by taking the example that the control electrode of the eleventh transistor is electrically connected to the first node N1.

[0190] In an exemplary embodiment, Fig.14 and Fig.15As shown, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, and the first electrode of the fourth transistor T4 is electrically connected to the second node N2. a control electrode of the fifth transistor T5 is electrically connected to the third node N3, a first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and a second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; a control electrode of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is connected to the first power supply terminal V1, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node; a control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, a first electrode of the seventh transistor T7 is connected to the fourth node, and a second electrode of the seventh transistor T7 is electrically connected to the first node N1 The control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the third clock signal terminal CK3, and the second electrode of the ninth transistor T9 is electrically connected to the second signal output terminal OUT2; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the second signal output terminal OUT2; the control electrode of the eleventh transistor T11 is electrically connected to the first node N1 or the third node N 3, a first electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal V3, and a second electrode of the eleventh transistor T11 is electrically connected to the first node N1; a first plate of the first capacitor C1 is electrically connected to the second node N2, and a second plate of the first capacitor C1 is electrically connected to the first power supply terminal V1; a first plate of the second capacitor C2 is electrically connected to the third node N3, and a second plate of the second capacitor C2 is connected to the first signal output terminal OUT1; a first plate of the third capacitor C3 is electrically connected to the control electrode of the ninth transistor T9, and a second plate of the third capacitor C3 is connected to the second signal output terminal OUT2; a first plate of the fourth capacitor C4 is electrically connected to the second node N2, and a second plate of the fourth capacitor C4 is connected to the second power supply terminal V2;The first electrode of the fifth capacitor C5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth capacitor C5 is electrically connected to the first signal output terminal OUT1. Fig.14 The control electrode of the eleventh transistor T11 is electrically connected to the third node N3 as an example for explanation. Fig.15 The description is made by taking the case where the control electrode of the eleventh transistor T11 is electrically connected to the first node N1 as an example.

[0191] In an exemplary embodiment, the first to eleventh transistors T1 to T11 may all be P-type transistors.

[0192] In an exemplary embodiment, Fig.16 The equivalent circuit of the shift register unit is Figure 5 , Fig.17 The equivalent circuit of the shift register unit is Figure 6 , Fig.18 The equivalent circuit of the shift register unit is Figure 7 .like Figures 16 to 18 As shown, it also includes: an output control subcircuit, the node control subcircuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6 and a seventh transistor T7, the output subcircuit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a twelfth transistor T12 and at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, the pull-down subcircuit includes: an eleventh transistor T11, and the output control subcircuit includes: a fifth capacitor C5. Fig.16 and Fig.17 The shift register unit includes: a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4. Fig.18 The description is made by taking the shift register unit including the second capacitor C2 and the fourth capacitor C4 as an example. Fig.16 and Fig.18 The description is made by taking the example that the control electrode of the eleventh transistor T11 is electrically connected to the third node N3. Fig.17 The description is made by taking the example that the control electrode of the eleventh transistor T11 is electrically connected to the first node N1.

[0193] In an exemplary embodiment, if Figures 16 to 18As shown, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, and the first electrode of the fourth transistor T4 is electrically connected to the The first power supply terminal V1 is connected, the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the first power supply terminal V1, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh transistor T7 is connected to the fourth node, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; The control electrode of the transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the control electrode of the ninth transistor T9 is electrically connected to the second electrode of the twelfth transistor T12, the first electrode of the ninth transistor T9 is connected to the third clock signal terminal CK3, and the second electrode of the ninth transistor T9 is electrically connected to the second signal output terminal OUT2; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the second signal output terminal OUT2; the control electrode of the eleventh transistor T11 is electrically connected to the first node N1 or the third node N3 The first electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal V3, and the second electrode of the eleventh transistor T11 is electrically connected to the first node N1; the control electrode of the twelfth transistor T12 is electrically connected to the second power supply line, and the first electrode of the twelfth transistor T12 is electrically connected to the first node N1; the first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the first power supply terminal VGH; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate of the second capacitor C2 is connected to the first signal output terminal OUT1; the first plate of the third capacitor C3 is electrically connected to the control electrode of the ninth transistor T9, and the second plate of the third capacitor C3 is connected to the second signal output terminal OUT2;The first plate of the fourth capacitor C4 is electrically connected to the second node N2, and the second plate of the fourth capacitor C4 is connected to the second power supply terminal V2; the first plate of the fifth capacitor C5 is electrically connected to the first power supply terminal V1, and the second plate of the fifth capacitor C5 is electrically connected to the first signal output terminal OUT1.

[0194] In an exemplary embodiment, the first to eleventh transistors T1 to T11 may all be P-type transistors.

[0195] In an exemplary embodiment, the signal of the first clock signal terminal CK1 and the signal of the second clock signal terminal CK2 are not valid level signals at the same time. Exemplarily, when the signal of the first clock signal terminal CK1 is at a valid level signal, the signal of the second clock signal terminal CK2 is an invalid level signal, and when the signal of the second clock signal terminal CK2 is at a valid level signal, the signal of the first clock signal terminal CK1 is an invalid level signal.

[0196] In an exemplary embodiment, the signal of the third clock signal terminal CK3 and the signal of the second clock signal terminal CK2 may be inverted signals or may not be inverted signals. When the signal of the third clock signal terminal CK3 and the signal of the second clock signal terminal CK2 are inverted signals, when the signal of the third clock signal terminal CK3 is a valid level signal, the signal of the second clock signal terminal CK2 is an invalid level signal, and when the signal of the third clock signal terminal CK3 is an invalid level signal, the signal of the second clock signal terminal CK2 is a valid level signal.

[0197] In an exemplary embodiment, the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are inverted signals to each other.

[0198] Fig.19 for Fig.12 and Fig.13 The signal timing simulation diagram of the shift register unit is provided. Fig.19 The description is made by taking the case where all transistors in the shift register unit are P-type transistors as an example.

[0199] In an exemplary embodiment, for Fig.12 and Fig.13 In the provided shift register unit, since the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the eighth transistor T8 is continuously turned on.

[0200] Combination Fig.12 and Fig.19 As shown, Fig.12 The working process of the provided control shift register unit includes the following stages:

[0201] In the first stage S1, i.e., the input stage, the signals of the signal input terminal IN and the first clock signal terminal CK1 are low-level signals, and the signal of the second clock signal terminal GCK2 is a high-level signal. The signal of the first clock signal terminal CK1 is a low-level signal, the first transistor T1 and the third transistor T3 are turned on, the low-level signal of the signal input terminal IN is written into the first node N1, and the low-level signal of the second power supply terminal V2 is written into the second node N2. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both low-level signals. The signal of the first node N1 is a low-level signal, the second transistor T2 is turned on, and the low-level signal of the first clock signal terminal CK1 is written into the second node N2, ensuring that the signal of the second node N2 continues to be a low-level signal. The signal of the second node N2 is a low-level signal, the fourth transistor T4 and the sixth transistor T6 are turned on, the high-level signal of the first power supply terminal V1 is written into the first signal output terminal OUT1 and the fourth node N4, and the low-level signal of the second power supply terminal V2 is written into the second signal output terminal OUT2. The signal of the third node N3 is a low-level signal, the fifth transistor T5 and the eleventh transistor T11 are turned on, and the signal of the third power supply terminal V3 is written to the first node N1, further pulling down the level signal of the first node N1, so that the signal of the first node N1 continues to be a low-level signal. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is turned off, the high-level signal of the fourth node N4 will not be written to the first node N1, and the signal of the first node N1 will not be pulled high. In this stage, the signals of the first node N1, the second node N2 and the third node N3 are low-level signals, the signal of the fourth node N4 is a high-level signal, the signal of the first power supply terminal V1 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high-level signal.

[0202] In the second stage S2, i.e., the output stage, the signals of the signal input terminal IN and the first clock signal terminal CK1 are high-level signals, and the signal of the second clock signal terminal GCK2 is a low-level signal. The signal of the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are turned off, and the signal of the first node N1 remains a low-level signal. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both low-level signals. The signal of the first node N1 is a low-level signal, the second transistor T2 is turned on, the high-level signal of the first clock signal terminal CK1 is written into the second node N2, the signal of the second node N2 is a high-level signal, the signal of the second node N2 is a high-level signal, the fourth transistor T4 and the sixth transistor T6 are turned off, and the high-level signal of the first power supply terminal V1 cannot be written into the first signal output terminal OUT1. The signal of the third node N3 is a low-level signal, the fifth transistor T5 and the eleventh transistor T11 are turned on, the signal of the third power supply terminal V3 is written into the first node N1, the signal of the first node N1 is kept continuously as a low-level signal, and the low-level signal of the second clock signal terminal CK2 is written into the first signal output terminal OUT1. Since the signal at the second clock signal terminal CK2 is a low level signal, the seventh transistor T7 is turned on, and the signal at the fourth node N4 is pulled down by the signal at the first node N1, and the signal at the fourth node N4 is a low level signal. In this stage, the signals at the first node N1, the third node N3, and the fourth node N4 are low level signals, the signal at the second node N2 is a high level signal, the low level signal at the second clock signal terminal CK2 is written to the first signal output terminal OUT1, and the output signal at the first signal output terminal OUT1 is a low level signal.

[0203] In the third stage S3, the signals of the signal input terminal IN and the second clock signal terminal GCK2 are high-level signals, and the signal of the first clock signal terminal CK1 is a low-level signal. The signal of the first clock signal terminal CK1 is a low-level signal, the first transistor T1 and the third transistor T3 are turned on, the high-level signal of the signal input terminal IN is written into the first node N1, and the low-level signal of the second power supply terminal V2 is written into the second node N2. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both high-level signals. The signal of the first node N1 is a high-level signal, and the second transistor T2 is turned off. The signal of the second node N2 is a low-level signal, the fourth transistor T4 and the sixth transistor T6 are turned on, and the high-level signal of the first power supply terminal V1 is written into the first signal output terminal OUT1 and the fourth node N4. The signal of the third node N3 is a high-level signal, the fifth transistor T5 and the eleventh transistor T11 are turned off, the signal of the third power supply terminal V3 cannot be written into the first node N1, the signal of the first node N1 is kept as a high-level signal, and the high-level signal of the second clock signal terminal CK2 cannot be written into the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a high level signal, the seventh transistor T7 is turned off. In this stage, the signal of the second node N2 is a low level signal, the signals of the first node N1, the third node N3 and the fourth node N4 are high level signals, the signal of the first power supply terminal V1 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high level signal.

[0204] In the fourth stage S4, the signal input terminal IN and the first clock signal terminal CK1 are high-level signals, and the signal of the second clock signal terminal CK2 is a low-level signal. The signal of the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are disconnected, and the signal of the first node N1 remains a high-level signal. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both high-level signals. The signal of the first node N1 is a high-level signal, and the second transistor T2 is disconnected. The signal of the second node N2 continues to be a low-level signal, the fourth transistor T4 and the sixth transistor T6 are turned on, and the high-level signal of the first power supply terminal V1 is written to the first signal output terminal OUT1 and the fourth node N4. The signal of the third node N3 is a high-level signal, the fifth transistor T5 and the eleventh transistor T11 are disconnected, the signal of the third power supply terminal V3 cannot be written to the first node N1, the signal of the first node N1 is kept as a high-level signal, and the high-level signal of the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is disconnected. In this stage, the signal of the second node N2 is a low level signal, the signals of the first node N1, the third node N3 and the fourth node N4 are high level signals, the signal of the first power supply terminal V1 is written into the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high level signal.

[0205] The working process of the shift register unit further includes: a plurality of third stages S3 and fourth stages S4, and the third stage S3 and the fourth stage S4 work alternately.

[0206] Fig.13 The shift register unit provided with Fig.12 The shift register unit provided is different in that the control electrode of the eleventh transistor is connected to a different node, Fig.12 The control electrode of the eleventh transistor is connected to the third node as an example. Fig.13 The control electrode of the eleventh transistor is connected to the first node. Since the signals of the first node N1 and the third node N3 are both high level signals or both low level signals, that is, Fig.12 and Fig.13 The eleventh transistors in the shift register unit provided are turned on or off at the same time, so that Fig.13 The working process of the shift register unit provided is similar to Fig.12 The shift register unit provided operates in the same manner.

[0207] Fig. 20 for Figures 14 to 18 The signal timing simulation diagram of the shift register is provided. Fig. 20 The description is given by taking the case where all transistors in the shift register are P-type transistors as an example.

[0208] In an exemplary embodiment, for Fig.14 and Fig.15 In the shift register unit provided, since the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the eighth transistor T8 is continuously turned on. Figures 16 to 18 In the provided shift register unit, the control electrodes of the eighth transistor T8 and the twelfth transistor T12 are both electrically connected to the second power supply terminal V2, and the eighth transistor T8 and the twelfth transistor T12 are continuously turned on.

[0209] Combination Fig.14 and Fig. 20 As shown, Fig.14 The working process of the provided control shift register unit includes the following stages:

[0210] In the first stage S1, i.e., the input stage, the signals of the signal input terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 are low-level signals, and the signal of the second clock signal terminal GCK2 is a high-level signal. The signal of the first clock signal terminal CK1 is a low-level signal, the first transistor T1 and the third transistor T3 are turned on, the low-level signal of the signal input terminal IN is written into the first node N1, and the low-level signal of the second power supply terminal V2 is written into the second node N2. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both low-level signals. The signal of the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the low-level signal of the first clock signal terminal CK1 is written into the second node N2, ensuring that the signal of the second node N2 continues to be a low-level signal, and the low-level signal of the third clock signal terminal CK3 is written into the second signal output terminal OUT2. The signal of the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6 and the tenth transistor T10 are turned on, the high-level signal of the first power supply terminal V1 is written into the first signal output terminal OUT1 and the fourth node N4, and the low-level signal of the second power supply terminal V2 is written into the second signal output terminal OUT2. The signal of the third node N3 is a low-level signal, the fifth transistor T5 and the eleventh transistor T11 are turned on, and the signal of the third power supply terminal V3 is written into the first node N1, further pulling down the level signal of the first node N1, so that the signal of the first node N1 continues to be a low-level signal. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is turned off, the high-level signal of the fourth node N4 will not be written into the first node N1, and the signal of the first node N1 will not be pulled high. In this stage, the signals of the first node N1, the second node N2 and the third node N3 are low-level signals, the signal of the fourth node N4 is a high-level signal, the signal of the first power supply terminal V1 is written into the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high-level signal, the signal of the third clock signal terminal CK3 and the signal of the second power supply terminal V2 are written into the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is a low-level signal.

[0211] In the second stage S2, i.e., the output stage, the signals of the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK3 are high-level signals, and the signal of the second clock signal terminal GCK2 is a low-level signal. The signal of the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are disconnected, and the signal of the first node N1 remains a low-level signal. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both low-level signals. The signal of the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal of the first clock signal terminal CK1 is written into the second node N2, the signal of the second node N2 is a high-level signal, the high-level signal of the third clock signal terminal CK3 is written into the second signal output terminal OUT2, the signal of the second node N2 is a high-level signal, the fourth transistor T4, the sixth transistor T6 and the tenth transistor T10 are disconnected, the high-level signal of the first power supply terminal V1 cannot be written into the first signal output terminal OUT1, and the low-level signal of the first low-level signal terminal VGL1 cannot be written into the second signal output terminal OUT2. The signal of the third node N3 is a low-level signal, the fifth transistor T5 and the eleventh transistor T11 are turned on, the signal of the third power supply terminal V3 is written to the first node N1, the signal of the first node N1 is kept as a low-level signal, and the low-level signal of the second clock signal terminal CK2 is written to the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a low-level signal, the seventh transistor T7 is turned on, the signal of the fourth node N4 is pulled down by the signal of the first node N1, and the signal of the fourth node N4 is a low-level signal. In this stage, the signals of the first node N1, the third node N3 and the fourth node N4 are low-level signals, the signal of the second node N2 is a high-level signal, the low-level signal of the second clock signal terminal CK2 is written to the first signal output terminal OUT1, the output signal of the first signal output terminal OUT1 is a low-level signal, the signal of the third clock signal terminal CK3 is written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is a high-level signal.

[0212] In the third stage S3, the signals of the signal input terminal IN and the second clock signal terminal GCK2 are high-level signals, and the signals of the first clock signal terminal CK1 and the third clock signal terminal CK3 are low-level signals. The signal of the first clock signal terminal CK1 is a low-level signal, the first transistor T1 and the third transistor T3 are turned on, the high-level signal of the signal input terminal IN is written into the first node N1, and the low-level signal of the second power supply terminal V2 is written into the second node N2. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both high-level signals. The signal of the first node N1 is a high-level signal, and the second transistor T2 and the ninth transistor T9 are turned off. The signal of the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6 and the tenth transistor T10 are turned on, the high-level signal of the first power supply terminal V1 is written into the first signal output terminal OUT1 and the fourth node N4, and the low-level signal of the second power supply terminal V2 is written into the second signal output terminal OUT2. The signal of the third node N3 is a high-level signal, the fifth transistor T5 and the eleventh transistor T11 are disconnected, the signal of the third power supply terminal V3 cannot be written to the first node N1, the signal of the first node N1 is kept as a high-level signal, and the high-level signal of the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is disconnected. In this stage, the signal of the second node N2 is a low-level signal, the signals of the first node N1, the third node N3 and the fourth node N4 are high-level signals, the signal of the first power supply terminal V1 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high-level signal, the signal of the second power supply terminal V2 is written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is a low-level signal.

[0213] In the fourth stage S4, the signals of the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK3 are high-level signals, and the signal of the second clock signal terminal CK2 is a low-level signal. The signal of the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are disconnected, and the signal of the first node N1 remains a high-level signal. Since the eighth transistor T8 is continuously turned on, the signal of the third node N3 and the signal of the first node N1 are both high-level signals. The signal of the first node N1 is a high-level signal, the second transistor T2 and the ninth transistor T9 are disconnected, and the high-level signal of the third clock signal terminal CK3 cannot be written into the second output signal terminal. The signal of the second node N2 continues to be a low-level signal, the fourth transistor T4, the sixth transistor T6 and the tenth transistor T10 are turned on, the high-level signal of the first power supply terminal V1 is written into the first signal output terminal OUT1 and the fourth node N4, and the low-level signal of the second power supply terminal V2 is written into the second signal output terminal OUT2. The signal of the third node N3 is a high-level signal, the fifth transistor T5 and the eleventh transistor T11 are disconnected, the signal of the third power supply terminal V3 cannot be written to the first node N1, the signal of the first node N1 is kept as a high-level signal, and the high-level signal of the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is disconnected. In this stage, the signal of the second node N2 is a low-level signal, the signals of the first node N1, the third node N3 and the fourth node N4 are high-level signals, the signal of the first power supply terminal V1 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high-level signal, the signal of the second power supply terminal V2 is written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is a low-level signal.

[0214] The working process of the shift register unit includes: a plurality of third stages S3 and fourth stages S4, and the third stage S3 and the fourth stage S4 work alternately.

[0215] Fig.15 The shift register unit provided with Fig.14 The shift register unit provided is different in that the control electrode of the eleventh transistor is connected to a different node, Fig.14 The control electrode of the eleventh transistor is connected to the third node as an example. Fig.15 The control electrode of the eleventh transistor is connected to the first node. Since the signals of the first node N1 and the third node N3 are both high level signals or both low level signals, that is, Fig.14 and Fig.15 The eleventh transistors in the shift register unit provided are turned on or off at the same time, so that Fig.15 The working process of the shift register unit provided is similar to Fig.14The shift register unit provided operates in the same manner.

[0216] Fig.16 The shift register unit provided with Fig.14 The shift register units provided differ in that Fig.16 The provided shift register unit also includes: a twelfth transistor T12. Since the twelfth transistor T12 is turned on, the second transistor T12 can be equivalent to a wire and will not affect the working process of other transistors of the shift register unit. Therefore, Fig.16 The working process of the shift register unit provided is similar to Fig.14 The shift register unit provided operates in the same manner.

[0217] Fig.17 and Fig.18 The shift register unit provided with Fig.15 The shift register units provided differ in that Fig.17 and Fig.18 The provided shift register unit also includes: a twelfth transistor T12. Since the twelfth transistor T12 is turned on, the second transistor T12 can be equivalent to a wire and will not affect the working process of other transistors of the shift register unit. Therefore, Fig.17 and Fig.18 The working process of the shift register unit provided is similar to Fig.15 The shift register unit provided operates in the same manner.

[0218] The setting of the eleventh transistor T11 in the present disclosure can pull the first node N1 down to the signal of the third power supply terminal V3 with a lower voltage value, thereby improving the conduction degree of the ninth transistor T9, so that the fifth transistor T5 and the ninth transistor T9 can be fully turned on.

[0219] Fig.21 3 is a comparison diagram of signals at the first node and the second signal output terminal of different shift register units. Fig.21 N1-1 and OUT2-1 refer to the Figures 14 to 18 The first node and the second signal output terminal in any one of the shift register units, N1-2 and OUT2-2 respectively refer to the first node and the second signal output terminal in the shift register unit whose transistors only include the first transistor to the tenth transistor. Fig.21 As shown, in the output stage and part of the output stage, the voltage value of the signal N1-1 is less than the voltage value of the signal N1-2, and the duration of the rising edge of the signal OUT2-1 is less than the duration of the rising edge of the signal OUT2-2, that is, the shift register unit provided in the present disclosure can increase the voltage value of the output signal of the second signal output terminal, thereby improving the performance of the shift register unit.

[0220] The embodiment of the present disclosure further provides a driving method of a shift register unit, which is configured to drive the shift register unit. The driving method of the shift register unit may include the following steps:

[0221] Step 100: Under the control of the first clock signal terminal and the second clock signal terminal, the node control subcircuit provides a signal from the signal input terminal or the first power terminal to the first node, and provides a signal from the second power terminal or the first clock signal terminal to the second node.

[0222] Step 200: The pull-down sub-circuit provides a signal of the third power terminal to the first node.

[0223] Step 300: The output sub-circuit provides a first power supply terminal or a second clock signal terminal to a first signal output terminal under the control of signals at a first node and a second node.

[0224] The shift register unit is the shift register unit provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0225] In an exemplary embodiment, the driving method of the shift register unit may further include: the output subcircuit provides a signal from the second power supply terminal or the third clock signal terminal to the second signal output terminal under the control of the signals from the first node and the second node.

[0226] In an exemplary embodiment, the shift register unit may further include: an output control subcircuit; and the driving method of the shift register unit may further include: the output control subcircuit storing a voltage difference between a signal at the first signal output terminal and a signal at the first power supply terminal.

[0227] The embodiment of the present disclosure also provides a display device. Fig. 22 FIG. 1 is a schematic diagram of the structure of a display device. Fig. 22As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a display substrate. The display substrate includes: a pixel array, a timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal line, the light emitting signal line and the data signal line. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register unit, and may sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal, where m may be a natural number. The light emitting driver may generate an emission signal to be provided to the light emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be constructed in the form of a shift register unit, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.

[0228] In an exemplary embodiment, the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device may be a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, or any other product or component having a display function.

[0229] Fig.23 A schematic diagram of a planar structure of a display substrate Figure 1 , Fig.24 A schematic diagram of a planar structure of a display substrate Figure 2 , Fig.25 A schematic diagram of a planar structure of a display substrate Figure 3 .like Figure 23 to Figure 25 As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, the plurality of pixel units P include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and at least one third sub-pixel P3 emitting a third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each including a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.

[0230] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in horizontal parallel, vertical parallel or in a herringbone manner, which is not limited in the present disclosure.

[0231] In an exemplary embodiment, Fig.23 and Fig.25As shown, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a herringbone pattern, which is not limited in the present disclosure. Fig.23 The horizontal parallel arrangement is used as an example to illustrate. Fig.25 The explanation is given by taking the herringbone arrangement as an example.

[0232] In an exemplary embodiment, Fig.24 As shown, a pixel unit may include four sub-pixels, and the four sub-pixels may be a first sub-pixel, a second sub-pixel, and two third sub-pixels. The four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure. Fig.24 The description is given by taking the arrangement of four sub-pixels in a square as an example.

[0233] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a stacked electrode (anode), an organic light emitting layer, and a second electrode (cathode).

[0234] In an exemplary embodiment, the organic light emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0235] In an exemplary embodiment, the display substrate is a LTPO display substrate.

[0236] Fig.26AFIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Fig.26A As shown, the pixel driving circuit may include 7 transistors (a first transistor M1 to a seventh transistor M7) and 1 capacitor C.

[0237] like Fig.26A As shown, the gate electrode of the first transistor M1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the gate electrode of the second transistor M2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor M2 is electrically connected to the first node N1, and the second electrode of the second transistor M2 is electrically connected to the third node N3; the gate electrode of the third transistor M3 is electrically connected to the first node N1, the first electrode of the third transistor M3 is electrically connected to the second node N2, and the second electrode of the third transistor M3 is electrically connected to the third node N3; the gate electrode of the fourth transistor M4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor M4 is electrically connected to the data signal line Data, and the fourth transistor The second electrode of the transistor M4 is electrically connected to the second node N2; the gate electrode of the fifth transistor M5 is electrically connected to the light emitting signal line EM, the first electrode of the fifth transistor M5 is electrically connected to the high level power line VDD, and the second electrode of the fifth transistor M5 is electrically connected to the second node N2; the gate electrode of the sixth transistor M6 is electrically connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is electrically connected to the third node N3, and the second electrode of the sixth transistor M6 is electrically connected to the fourth node N4; the gate electrode of the seventh transistor M7 is electrically connected to the first scanning signal line Gate1, the first electrode of the seventh transistor M7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is electrically connected to the fourth node N4; the first plate of the capacitor C is electrically connected to the first node N1, and the second plate of the capacitor C is electrically connected to the high level power line VDD.

[0238] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form an LTPO display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0239] In an exemplary embodiment, the first transistor M1 and the second transistor M2 are opposite to the third transistor M3 to the seventh transistor M7 in transistor type. Exemplarily, the first transistor M1 and the second transistor M2 may be N-type transistors, and the third transistor M3 to the seventh transistor M7 may be P-type transistors.

[0240] In an exemplary embodiment, the first transistor M1 and the second transistor M2 may be oxide transistors, and the third to seventh transistors M3 to M7 may be low temperature polysilicon transistors.

[0241] In an exemplary embodiment, the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal. The voltage value of the signal of the first initial signal line INIT1 may be -3V.

[0242] In an exemplary embodiment, the voltage value of the signal of the second initial signal line INIT2 is constant and is a DC signal. The voltage value of the signal of the second initial signal line INIT2 may be 0V.

[0243] In an exemplary embodiment, the light emitting device L′ may be electrically connected to the fourth node N4 and the low-level power line VSS, respectively.

[0244] In an exemplary embodiment, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0245] Fig.26B for Fig.26A The working timing diagram of the pixel driving circuit provided is as follows. Fig.26A The operation process of the exemplary pixel driving circuit in the display phase illustrates an exemplary embodiment of the present disclosure. Fig.26BThe description is made by taking the first transistor M1 and the second transistor M2 as N-type transistors and the third transistor M3 to the seventh transistor M7 as P-type transistors as an example. Fig.26B The pixel driving circuit includes the first transistor M1 to the seventh transistor M7, a capacitor C and 8 signal lines (data signal line Data, a first scanning signal line Gate1, a second scanning signal line Gate2, a reset signal line Reset, a first initial signal line INIT1, a second initial signal line INIT2, a light emitting signal line EM and a high-level power line VDD).

[0246] Combination Fig.26A and Fig.26B , the working process of the pixel driving circuit may include:

[0247] The first stage P1 is called the initialization stage. The signal of the reset signal line Reset is a high-level signal, the first transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written into the first node N1 through the turned-on first transistor M1, and the first node N1 is initialized (resettled), and the pre-stored voltage inside it is cleared to complete the initialization.

[0248] The second stage P2 is called the data writing stage or the threshold compensation stage, the first scanning signal line Gate1 is a low level signal, the second scanning signal line Gate2 is a low level signal, and the data signal line Data outputs a data voltage. In this stage, since the first node N1 is a low level signal, the third transistor M3 is turned on. The signal of the first scanning signal line Gate1 is a low-level signal, the fourth transistor M4 is turned on and the seventh transistor M7 is turned on, the signal of the second scanning signal line Gate2 is a high-level signal, the second transistor M2 is turned on, and the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor M3, the seventh transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4 through the turned-on seventh transistor M7, the first electrode of the light-emitting device L is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.

[0249] The third stage P3 is called the light-emitting stage. The signal of the light-emitting signal line EM is a low-level signal. The fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, thereby driving the light-emitting device L to emit light.

[0250] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is:

[0251] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0252] Among them, I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0253] In an exemplary embodiment, Fig.27A FIG. 1 is a schematic diagram of an equivalent circuit of another pixel driving circuit. Fig.27A As shown, the pixel driving circuit may include 8 transistors (first transistor M1 to eighth transistor M8), 1 capacitor C and 9 signal lines (data signal line Data, control signal line Scan, scan signal line Gate, reset signal line Reset, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, high level power line VDD and low level power line VSS).

[0254] In an exemplary embodiment, a first electrode of the capacitor C is connected to a high-level power supply line VDD, and a second electrode of the capacitor C is connected to a first node N1. A control electrode of the first transistor M1 is connected to a reset signal line Reset, a first electrode of the first transistor M1 is connected to a first initial signal line INIT1, and a second electrode of the first transistor is connected to a fourth node N4. A control electrode of the second transistor M2 is connected to a scan signal line Gate, a first electrode of the second transistor M2 is connected to a fourth node N4, and a second electrode of the second transistor M2 is connected to a second node N2. A control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to a second node N2, and a second electrode of the third transistor M3 is connected to a third node N3. A control electrode of the fourth transistor M4 is connected to a scan signal line Gate, a first electrode of the fourth transistor M4 is connected to a data signal line Data, and a second electrode of the fourth transistor M4 is connected to a third node N3. A control electrode of the fifth transistor M5 is connected to a light-emitting signal line EM, a first electrode of the fifth transistor M5 is connected to a high-level power supply line VDD, and a second electrode of the fifth transistor M5 is connected to a third node N3. The control electrode of the sixth transistor M6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the second node N2, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device L. The control electrode of the seventh transistor M7 is connected to the reset signal line Reset, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device L is connected to the low level power line VSS. The control electrode of the eighth transistor M8 is connected to the control signal line Scan, the first electrode of the eighth transistor M8 is connected to the first node N1, and the second electrode of the eighth transistor M8 is connected to the fourth node N4.

[0255] In an exemplary embodiment, the control electrode of the seventh transistor M7 can also be connected to the scan signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and the second electrode of the light emitting device L is connected to the low level power line VSS.

[0256] In an exemplary embodiment, the signal of the high-level power line VDD is a continuously provided high-level signal, and the signal of the low-level power line VSS is a low-level signal.

[0257] In an exemplary embodiment, the eighth transistor M8 is a metal oxide transistor and is an N-type transistor, and the first to seventh transistors M1 to M7 are low temperature polysilicon transistors and are P-type transistors.

[0258] In an exemplary embodiment, the eighth transistor M8 is an oxide transistor, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.

[0259] Fig.27B for Fig.27A The working timing diagram of the pixel driving circuit provided is as follows. Fig.27B The operation process of the pixel driving circuit of the example illustrates an exemplary embodiment of the present disclosure. The operation process of the pixel driving circuit may include:

[0260] The first stage A1 is called the reset stage. The signals of the control signal line Scan, the light emitting signal line EM and the scanning signal line Gate are all high-level signals, and the signal of the reset signal line Reset is a low-level signal. The signal of the reset signal line Reset is a low-level signal, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is provided to the fourth node N4, the seventh transistor M7 is turned on, and the initial voltage of the second initial signal line INIT2 is provided to the first electrode of the light emitting device L, and the first electrode of the light emitting device L is initialized (reset), for example: the pre-stored voltage inside it is cleared, the initialization is completed, and the light emitting device L is ensured not to emit light. The signal of the control signal line Scan is a high-level signal, the eighth transistor M8 is turned on, the signal of the fourth node N4 is provided to the first node N1, the capacitor C is initialized, and the original data voltage in the capacitor C is cleared. The signals of the scanning signal line Gate and the light emitting signal line EM are high-level signals, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are turned off, and in this stage, the light emitting device L does not emit light.

[0261] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the scanning signal line Gate is a low level signal, the signals of the reset signal line Reset, the luminous signal line EM and the control signal line Scan are high level signals, and the data signal line Data outputs a data voltage. In this stage, since the first node N1 is a low level signal, the third transistor M3 is turned on. The signal of the scanning signal line Gate is a low level signal, the second transistor M2 and the fourth transistor M4 are turned on, the signal of the control signal line Scan is a high level signal, and the eighth transistor M8 is turned on. The second transistor M2, the fourth transistor M4 and the eighth transistor M8 are turned on so that the data voltage output by the data signal line Data is provided to the first node N1 through the third node N3, the turned-on third transistor M3, the second node N2, the turned-on second transistor M2, the fourth node N4 and the turned-on eighth transistor M8, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3. The signal of the reset signal line Reset is a low-level signal, and the first transistor M1 and the seventh transistor M7 are turned off. The signal of the luminous signal line EM is a high-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off.

[0262] The third stage A3 is called the light-emitting stage. The signals of the control signal line Scan and the light-emitting signal line EM are both low-level signals, and the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals. The signal of the reset signal line Reset is a low-level signal, and the first transistor M1 and the seventh transistor M7 are turned off. The control signal line Scan is a low-level signal, the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals, and the second transistor M2, the fourth transistor M4 and the eighth transistor M8 are turned off. The signal of the light-emitting signal line EM is a low-level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, driving the light-emitting device L to emit light.

[0263] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is:

[0264] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd)2

[0265] Among them, I is the driving current flowing through the third transistor M3, which is also the driving current for driving the light-emitting device L. K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0266] The display substrate provided by the embodiments of the present disclosure may include: a substrate, and sub-pixels, gate lines, and a gate driving circuit provided on the substrate. The substrate is provided with a display area and a non-display area. The gate driving circuit is located in the non-display area, and the sub-pixels and gate lines are located in the display area. The gate lines are electrically connected to the sub-pixels and the gate driving circuit respectively.

[0267] In an exemplary embodiment, the sub-pixel includes: a pixel driving circuit and a light-emitting device. When the pixel driving circuit is Fig.26A the provided pixel driving circuit, the gate line may include at least one of a reset signal line, a first scan signal line, a second scan signal line, and a light-emitting signal line.

[0268] In an exemplary embodiment, the sub-pixel includes: a pixel driving circuit and a light-emitting device. When the pixel driving circuit is Fig.27A the provided pixel driving circuit, the gate line may include at least one of a reset signal line, a first scan signal line, a second scan signal line, a control signal line, and a light-emitting signal line.

[0269] The shift register unit is the shift register unit provided in any of the foregoing embodiments, and the implementation principle and implementation effect are similar, and will not be described in detail herein.

[0270] Fig.28 Schematic diagram of the cascade of the gate driving circuit Figure 1 , Fig.29 Schematic diagram of the cascade of the gate driving circuit Figure 2 . As Fig.28 and Fig.29 shown, the first signal output terminal OUT1 of the i-th stage shift register unit GOA(i) is connected to the signal input terminal IN of the (i + 1)-th stage shift register unit GOA(i + 1), 1 ≤ i < N, and N is the total number of stages of the shift register unit. Among them, Fig.28 is described by taking the shift register unit provided in Fig.12 and Fig.13 as an example, Fig.29 is described by taking the shift register unit provided in Figures 14 to 18 as an example.

[0271] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and a conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0272] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0273] In an exemplary embodiment, if Fig.28 As shown, the first signal output terminal OUT1 of the shift register unit can be electrically connected to the gate line.

[0274] In an exemplary embodiment, if Fig.29 As shown, the second signal output terminal OUT2 of the shift register unit can be electrically connected to the gate line.

[0275] In an exemplary embodiment, Fig.30 Schematic diagram of the structure of the display substrate Figure 1 , Fig.31 Schematic diagram of the structure of the display substrate Figure 2 . Fig.30 So Fig.12 The shift register unit provided is used as an example for explanation. Fig.31 So Fig.18The shift register unit provided is used as an example for explanation. Figure 28 to Figure 31 As shown, the display substrate may further include: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, a second power line VGL1 and a third power line VGL2 disposed on the substrate and located in the non-display area.

[0276] In an exemplary embodiment, the signal input terminal IN of the first-stage shift register unit GOA(1) is electrically connected to the initial signal line STV, the first power terminal of the i-th stage shift register unit is electrically connected to the first power line VGH, the second power terminal of the i-th stage shift register unit is electrically connected to the second power line VGL1, and the third power terminal of the i-th stage shift register unit is electrically connected to the third power line VGL2.

[0277] In an exemplary embodiment, any one of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the second power line VGL1 and the third power line VGL2 extends along the first direction D1, the gate line extends along the second direction D2, and the first direction D1 intersects the second direction D2.

[0278] In an exemplary embodiment, if Fig.30 and Fig.31 As shown, the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2 and the first power line VGH are sequentially arranged in a direction close to the display area and are located at a side of the shift register unit away from the display area.

[0279] In an exemplary embodiment, if Fig.30 and Fig.31 As shown, the shift register unit includes: a plurality of transistors, and the second power line VGL1 is located on a side of the first power line VGH close to the display area and is located between the plurality of transistors of the shift register unit.

[0280] In an exemplary embodiment, if Fig.30 and Fig.31 As shown, the third power line VGL2 is located at a side of the second power line VGL1 close to the display area, and its orthographic projection on the substrate partially overlaps with the orthographic projection of the shift register unit on the substrate.

[0281] In an exemplary embodiment, if Fig.30 and Fig.31As shown, the shift register unit includes: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6 and a seventh transistor T7. At least a portion of any one of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 is located between the first power line VGH and the second power line VGL1.

[0282] In an exemplary embodiment, Fig.31 As shown, the shift register unit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, an eleventh transistor T11 and a twelfth transistor T12, and the number of the second power line VGL1 is at least one, wherein at least a portion of any one of the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the eleventh transistor T11 and the twelfth transistor T12 is located on a side of the second power line VGL1 close to the display area.

[0283] In an exemplary embodiment, Fig.30 and Fig.31 As shown, the shift register unit includes: a second capacitor C2; the second capacitor C2 is located at a side of the third power line VGL2 close to the display area.

[0284] In an exemplary embodiment, Fig.31 As shown, the display substrate may further include: a third clock signal line CLK3 and a fourth clock signal line CLK4 disposed on the base and located in the non-display area, and any one of the third clock signal line CLK3 and the fourth clock signal line CLK4 extends along the first direction D1.

[0285] In an exemplary embodiment, Fig.31 As shown, there are two second power lines VGL1. The second power line VGL1 close to the display area is located on one side of the third clock signal line CLK3 and the fourth clock signal line CLK4 close to the display area, and the second power line VGL1 away from the display area is located between the first power line VGH and the third power line VGL2.

[0286] In an exemplary embodiment, Fig.31As shown, the shift register unit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a fourth capacitor C4. The fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the eleventh transistor T11 and the twelfth transistor T12 are located between the second power line VGL1 and any one of the third clock signal line CLK3 and the fourth clock signal line CLK4 away from the display area, and the ninth transistor T9 and the tenth transistor T10 are located on the side of the second power line VGL1 close to the display area close to the display area.

[0287] In an exemplary embodiment, Fig.31 As shown, the orthographic projection of the second power line VGL1 close to the display area on the substrate partially overlaps with the orthographic projection of the fourth capacitor C4 on the substrate.

[0288] In an exemplary embodiment, Figure 28 to Figure 31 As shown, the first clock signal terminal CK1 of the i-th stage shift register unit is electrically connected to one of the first clock signal line CLK1 and the second clock signal line CLK2, and the second clock signal terminal CK2 of the i-th stage shift register unit is electrically connected to the other of the first clock signal line CLK1 and the second clock signal line CLK2; the first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines. Exemplarily, exemplary, the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1, the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2, the first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2, and the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1, or, the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2, the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1, the first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1, and the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2, Fig.28 and Fig.29The explanation is given by taking the example that the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1, the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2, the first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2, and the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1.

[0289] In an exemplary embodiment, if Fig.29 and Fig.31 As shown, the third clock signal terminal CK3 of the i-th shift register unit is electrically connected to one of the third clock signal line CLK3 and the fourth clock signal line CLK4, and the third clock signal terminal CK3 of the i+1-th shift register unit is electrically connected to the other of the third clock signal line CLK3 and the fourth clock signal line CLK4. Exemplarily, the third clock signal terminal CK3 of the odd-numbered shift register unit is electrically connected to the third clock signal line CLK3, and the third clock signal terminal CK3 of the even-numbered shift register unit is electrically connected to the fourth clock signal line CLK4, or the third clock signal terminal CK3 of the odd-numbered shift register unit is electrically connected to the fourth clock signal line CLK4, and the third clock signal terminal CK3 of the even-numbered shift register unit is electrically connected to the third clock signal line CLK3. Fig.29 The description is made by taking the example that the third clock signal terminal CK3 of the odd-numbered shift register unit is electrically connected to the third clock signal line CLK3, and the third clock signal terminal CK3 of the even-numbered shift register unit is electrically connected to the fourth clock signal line CLK4.

[0290] In an exemplary embodiment, if Fig.30 and Fig.31 As shown, the orthographic projection of the third power line VGL2 on the substrate partially overlaps with the orthographic projections of the fourth transistor T4 and the fifth transistor T5 on the substrate.

[0291] In an exemplary embodiment, if Fig.30 and Fig.31 As shown, the active layer T81 of the eighth transistor T8 extends along the second direction D2, any one of the first electrode T83 and the second electrode T84 of the eighth transistor T8 extends along the first direction D1, and the gate electrode T82 of the eighth transistor T8 at least partially extends along the first direction D1.

[0292] In an exemplary embodiment, if Fig.30 and Fig.31As shown, the gate electrode T112 of the eleventh transistor is an integral structure with the gate electrode T52 of the fifth transistor, the orthographic projection of the first electrode T113 of the eleventh transistor on the substrate partially overlaps with the orthographic projection of the third power line VGL2 on the substrate, and is electrically connected to the third power line VGL2, and the second electrode T114 of the eleventh transistor is an integral structure with the first electrode T83 of the eighth transistor and the first electrode T123 of the twelfth transistor.

[0293] In an exemplary embodiment, Fig.31 As shown, the width of any one of the first power line VGH, the second power line VGL1 and the third power line VGL2 along the second direction D2 is smaller than the width of any one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 along the second direction D2.

[0294] In an exemplary embodiment, since the signals of the clock signal lines are AC signals, the width of any one of the first clock signal line CLK1 , the second clock signal line CLK2 , the third clock signal line CLK3 and the fourth clock signal line CLK4 along the second direction D2 is wider to reduce the load of the clock signal lines.

[0295] In an exemplary embodiment, a channel width of an active layer of the tenth transistor is greater than a channel width of an active layer of the fourth transistor.

[0296] In an exemplary embodiment, the channel width of the active layer of the tenth transistor is not less than 90 micrometers. Exemplarily, the channel width of the active layer of the tenth transistor may be about 100 micrometers.

[0297] In example embodiments, a channel length of the active layer of the tenth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the tenth transistor may be approximately 100 / 3.5.

[0298] In an exemplary embodiment, the channel width of the active layer of the fourth transistor is no greater than 50 micrometers. Exemplarily, the channel width of the active layer of the fourth transistor may be approximately 25 micrometers.

[0299] In an exemplary embodiment, a channel length of the active layer of the fourth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the fourth transistor may be approximately 25 / 3.5.

[0300] In an exemplary embodiment, a channel width of an active layer of the ninth transistor is greater than a channel width of an active layer of the fifth transistor.

[0301] In an exemplary embodiment, the channel width of the active layer of the ninth transistor is not less than 90 micrometers. Exemplarily, the channel width of the active layer of the ninth transistor may be about 100 micrometers.

[0302] In an exemplary embodiment, a channel length of the active layer of the ninth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the ninth transistor may be approximately 100 / 3.5.

[0303] In an exemplary embodiment, the channel width of the active layer of the fifth transistor is no greater than 50 micrometers. Exemplarily, the channel width of the active layer of the fifth transistor may be approximately 25 micrometers.

[0304] In an exemplary embodiment, a channel length of the active layer of the fifth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the fifth transistor may be approximately 25 / 3.5.

[0305] In an exemplary embodiment, the display substrate may further include: a driving structure layer disposed on the substrate; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate; the shift register unit includes: a plurality of transistors and a plurality of capacitors, any one of the capacitors includes: a first plate and a second plate;

[0306] The semiconductor layer includes at least: an active layer of a plurality of transistors located in at least one shift register unit;

[0307] The first conductive layer at least includes: control electrodes of a plurality of transistors located in at least one shift register unit and first plates of a plurality of capacitors;

[0308] The second conductive layer includes at least: second plates of a plurality of capacitors located in at least one shift register unit;

[0309] The third conductive layer at least includes: an initial signal line, a first clock signal line, a second clock signal line, a first power line, a second power line, a third clock signal line, a fourth clock signal line, and first and second electrodes of a plurality of transistors located in at least one shift register unit;

[0310] The fourth conductive layer at least includes: a third power line.

[0311] In an exemplary embodiment, the driving structure layer may further include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer and a flat layer, wherein the first insulating layer is located between the semiconductor layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, the fourth insulating layer is located between the third conductive layer and the fourth conductive layer, the fifth insulating layer is located on a side of the fourth conductive layer away from the substrate, and the flat layer is located on a side of the fifth insulating layer away from the substrate.

[0312] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0313] (1) Forming a semiconductor layer pattern on a substrate, including: depositing a semiconductor film on the substrate, and patterning the semiconductor film through a patterning process to form a semiconductor layer pattern. Fig.32 and Fig.33 As shown, Fig.32 for Fig.30 Schematic diagram after forming a semiconductor layer pattern, Fig.33 for Fig.31 Schematic diagram after patterning the semiconductor layer.

[0314] In an exemplary embodiment, Fig.32 As shown, the semiconductor layer pattern may include: an active layer T11 of a first transistor to an active layer T81 of an eighth transistor, an active layer T111 of an eleventh transistor, and an active connection block AL located in at least one shift register unit.

[0315] In an exemplary embodiment, Fig.33 As shown, the semiconductor layer pattern may include: an active layer T11 of a first transistor to an active layer T121 of a twelfth transistor located in at least one shift register unit and an active connection block AL.

[0316] In an exemplary embodiment, Fig.32 and Fig.33As shown, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor are an integrated structure, and the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are an integrated structure. The active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T31 of the third transistor, the active layer T81 of the eighth transistor, the active layer T111 of the eleventh transistor, and the active connection block AL can be provided separately.

[0317] In an exemplary embodiment, if Fig.33 As shown, the active layer T91 of the ninth transistor and the active layer T101 of the fourth transistor are an integrated structure, and the active layer T121 of the twelfth transistor can be provided separately.

[0318] In an exemplary embodiment, if Fig.32 and Fig.33 As shown, the active layer T11 of the first transistor and the active layer T61 of the sixth transistor (also the active layer T71 of the seventh transistor) are arranged along the second direction D2, and the active layer T11 of the first transistor of the shift register unit at this level is located on the side of the active layer T61 of the sixth transistor (also the active layer T71 of the seventh transistor) of the shift register unit at this level close to the shift register unit at the previous level. The active layer T21 of the second transistor is located on the side of the active layer T11 of the first transistor close to the display area. The active layer T31 of the third transistor and the active connection block AL are arranged along the second direction D2, and are located on the side of the active layer T21 of the second transistor close to the display area. The active layer T81 of the eighth transistor, the active layer T111 of the eleventh transistor and the active layer T41 of the fourth transistor (also the active layer T51 of the fifth transistor) are arranged in sequence along the second direction D2, and are located on the side of the active layer T31 of the third transistor close to the display area, wherein the active layer T111 of the eleventh transistor of the shift register unit at this level is located on the side of the active layer T81 of the eighth transistor of the shift register unit at this level close to the shift register unit of the next level, and the active layer T41 of the fourth transistor of the shift register unit at this level (also the active layer T51 of the fifth transistor) is located on the side of the active layer T111 of the eleventh transistor of the shift register unit at this level close to the shift register unit of the next level.

[0319] In an exemplary embodiment, if Fig.33 As shown, the active layer T121 of the twelfth transistor of the shift register unit at this level is located on the side of the active layer T81 of the eighth transistor of the shift register unit at this level close to the shift register unit at the previous level, and the active layer of the ninth transistor of the shift register unit at this level (also the active layer of the fourth transistor) is located on the side of the active layer T41 of the fourth transistor (also the active layer T51 of the fifth transistor) close to the display area.

[0320] In an exemplary embodiment, if Fig.32 and Fig.33 As shown, the active layer T11 of the first transistor to the active layer T71 of the seventh transistor are in the shape of strips and extend along the first direction D1. The active layer T81 of the eighth transistor and the active layer T11 of the eleventh transistor are in the shape of strips and extend along the second direction D2. The shape of the active connection block AL can be a block.

[0321] In an exemplary embodiment, if Fig.32 and Fig.33 As shown, the active layer of the ninth transistor (also the active layer of the fourth transistor) is in a strip shape and extends along the first direction D1. The active layer T121 of the twelfth transistor is in a strip shape and extends along the second direction D2.

[0322] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. The first region and the second region will be conductorized after the subsequent first conductive layer is formed, and therefore may also be referred to as a conductive region. In an exemplary embodiment, the second region T61-2 of the active layer T61 of the sixth transistor may simultaneously serve as the first region T71-2 of the active layer T31 of the seventh transistor, the second region T41-2 of the active layer T41 of the fourth transistor may simultaneously serve as the second region T51-2 of the active layer T51 of the fifth transistor, and the second region T91-2 of the active layer T91 of the ninth transistor may simultaneously serve as the second region T101-2 of the active layer T101 of the fourth transistor. The first region T11-1 and the second region T11-2 of the active layer T11 of the first transistor, the first region T21-1 and the second region T21-2 of the active layer T21 of the second transistor, the first region T31-1 and the second region T31-2 of the active layer T31 of the third transistor, the first region T41-1 of the active layer T41 of the fourth transistor, the first region T51-1 of the active layer T51 of the fifth transistor, the first region T61-1 of the active layer T61 of the sixth transistor, and the first region T61-2 of the active layer T61 of the seventh transistor. The second region T71-2 of the layer T71, the first region T81-1 and the second region T81-2 of the active layer T81 of the eighth transistor, the first region T91-1 of the active layer T91 of the ninth transistor, the first region T101-1 of the active layer T101 of the fourth transistor, the first region T111-1 and the second region T111-2 of the active layer T111 of the eleventh transistor, and the first region T121-1 and the second region T121-2 of the active layer T121 of the twelfth transistor can be set separately.

[0323] (2) forming a first conductive layer pattern, comprising: depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern, patterning the first insulating film and the first conductive film by a patterning process to form a first insulating layer pattern and a first conductive layer pattern disposed on the first insulating layer pattern, such as Figure 34 to Figure 37 As shown, Fig.34 for Fig.30 A schematic diagram of the first conductive layer pattern in FIG. Fig.35 for Fig.30 A schematic diagram after forming the first conductive layer pattern, Fig.36 for Fig.31 A schematic diagram of the first conductive layer pattern in FIG. Fig.37 for Fig.31 Schematic diagram after forming a first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0324] In an exemplary embodiment, Fig.34 and Fig.35 As shown, the first conductive layer pattern may include: the control electrode T12 of the first transistor to the control electrode T82 of the eighth transistor located in at least one shift register unit, the control electrode T112 of the eleventh transistor, the first electrode plate C21 of the second capacitor and the first connecting line L1.

[0325] In an exemplary embodiment, Fig.36 and Fig.37 As shown, the first conductive layer pattern may include: control electrodes T12 to T122 of the first transistor to the twelfth transistor located in at least one shift register unit, the first plate C21 of the second capacitor, the first plate C41 of the fourth capacitor and the first connecting line L1.

[0326] In an exemplary embodiment, Figure 34 to Figure 37 As shown, the control electrode T12 of the first transistor and the control electrode T32 of the third transistor are an integrated structure. The control electrode T52 of the fifth transistor, the control electrode T112 of the eleventh transistor and the first electrode plate C21 of the second capacitor are an integrated structure. The control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor are an integrated structure. The control electrode T22 of the second transistor, the control electrode T72 of the seventh transistor, the control electrode T82 of the eighth transistor and the first connecting line L1 can be set separately

[0327] In an exemplary embodiment, Fig.36 and Fig.37As shown, the control electrode T42 of the fourth transistor, the control electrode T62 of the sixth transistor, the control electrode T102 of the fourth transistor and the first electrode plate C41 of the fourth capacitor are an integrated structure. The control electrode T82 of the eighth transistor and the control electrode T122 of the twelfth transistor are an integrated structure. The control electrode T92 of the ninth transistor can be set separately.

[0328] In an exemplary embodiment, Figure 34 to Figure 37 As shown, the control electrode T12 of the first transistor includes: a first connection portion T12A and a second connection portion T12B, the first connection portion T12A extends along the first direction D1, the second connection portion T12B is in a "┐" shape, and the second connection portion T12B is connected to the middle of the first connection portion T12A. The control electrode T32 of the third transistor can be in a strip shape and extends along the second direction D2. The control electrode T32 of the third transistor is connected to the end of the second connection portion T12B.

[0329] In an exemplary embodiment, Figure 34 to Figure 37 As shown, the shape of the first electrode C21 of the second capacitor can be square, the shape of the control electrode T52 of the fifth transistor is strip-shaped and extends along the second direction D2, the shape of the control electrode T112 of the eleventh transistor is "┌", and the control electrode T52 of the fifth transistor and the control electrode T112 of the eleventh transistor are located on the side of the first electrode C21 of the second capacitor away from the display area.

[0330] In an exemplary embodiment, Fig.34 and Fig.35 As shown, the control electrode T42 of the fourth transistor (also the control electrode T62 of the sixth transistor) is in a strip shape and extends along the second direction D2.

[0331] In an exemplary embodiment, Fig.36 and Fig.37 As shown, the shape of the first electrode C41 of the fourth capacitor can be square, and the control electrode T102 of the fourth transistor includes: a plurality of first branch segments T102A, the first branch segments T102A extend along the second direction D2, and the plurality of first branch segments T102A are arranged along the first direction D1. The control electrode T62 of the sixth transistor and the control electrode T42 of the fourth transistor are located on the side of the first electrode C41 of the fourth capacitor away from the display area, and the control electrode T102 of the fourth transistor is located on the side of the first electrode C41 of the fourth capacitor close to the display area. Fig.36 and Fig.37 The description is made by taking two first branch segments T102A as an example.

[0332] In an exemplary embodiment, Figure 34 to Figure 37 As shown, the shape of the control electrode T82 of the eighth transistor can be a groove with an opening facing upward.

[0333] In an exemplary embodiment, Fig.36 and Fig.37 As shown, the control electrode T122 of the twelfth transistor is in a strip shape and extends along the first direction D1.

[0334] In an exemplary embodiment, Fig.36 and Fig.37 As shown, the control electrode T92 of the ninth transistor includes: a second connection segment T92A and a plurality of second branch segments T92B. The second connection segment T92A is in the shape of a “┐”, the second branch segment T92B extends along the second direction D2, and the plurality of second branch segments T92B are arranged along the first direction D1. The second connection segment T92A is equivalent to a “comb back”, and the plurality of second branch segments T92B are equivalent to “comb teeth”.

[0335] In an exemplary embodiment, Figure 34 to Figure 37 As shown, the control electrode T22 of the second transistor, the control electrode T72 of the seventh transistor and the first connection line L1 may be in the shape of strips, and at least partially extend along the second direction D2.

[0336] In an exemplary embodiment, the first connection segment T12A and the second connection segment T12B of the control electrode T12 of the first transistor are respectively arranged across the active layer of the first transistor, the control electrode T22 of the second transistor is arranged across the active layer of the second transistor, the control electrode T32 of the third transistor is arranged across the active layer of the third transistor, the control electrode T42 of the fourth transistor is arranged across the active layer of the fourth transistor, the control electrode T52 of the fifth transistor is arranged across the active layer of the fifth transistor, the control electrode T62 of the sixth transistor is arranged across the active layer of the sixth transistor, and the control electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor. On the active layer of the transistor, the control electrode T82 of the eighth transistor is arranged across the active layer of the eighth transistor, the multiple second branch segments T92B of the control electrode T92 of the ninth transistor are arranged across the active layer of the ninth transistor, the multiple first branch segments T102A of the control electrode T102 of the fourth transistor are arranged across the active layer of the fourth transistor, the control electrode T112 of the eleventh transistor is arranged across the active layer of the eleventh transistor, and the control electrode T122 of the twelfth transistor is arranged across the active layer of the twelfth transistor, that is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0337] In an exemplary embodiment, this process also includes a conductorization process. The conductorization process is to use the semiconductor layer in the control electrode shielding area of ​​multiple transistors (i.e., the area where the semiconductor layer and the control electrode overlap) as the channel area of ​​the transistor after forming the first conductive layer, and the semiconductor layer in the area not shielded by the first conductive layer is processed into a conductorization layer to form the electrode connection part of the transistor. Fig.24As shown, the active connecting line AL in the present disclosure is processed into a conductor layer to form a conductorized active connecting line AL, and the second area of ​​the active layer of the sixth transistor after conductorization (which is also the first area of ​​the active layer of the seventh transistor) can be reused as the second electrode T64 of the sixth transistor and the first electrode T73 of the seventh transistor.

[0338] (3) forming a second conductive layer pattern, comprising: depositing a second insulating film and a second conductive film on the substrate having the aforementioned pattern, patterning the second insulating film and the second conductive film by a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer pattern, such as Figures 38 to 41 As shown, Fig.38 for Fig.30 A schematic diagram of a second conductive layer pattern in FIG. Fig.39 for Fig.30 A schematic diagram after forming the second conductive layer pattern, Fig.40 for Fig.31 A schematic diagram of a second conductive layer pattern in FIG. Fig.41 for Fig.31 Schematic diagram after forming a second conductive layer pattern. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0339] In an exemplary embodiment, Fig.38 and Fig.39 As shown, the second conductive layer pattern may include: a second electrode C22 of a second capacitor located in at least one shift register unit and a second connection line L2.

[0340] In an exemplary embodiment, Fig.40 and Fig.41 As shown, the second conductive layer pattern may include: a second plate C22 of a second capacitor located in at least one shift register unit, a second plate C42 of a fourth capacitor, a second connection line L2, a third connection line L3 and a fourth connection line L4.

[0341] In an exemplary embodiment, Figures 38 to 41 As shown, the second plate C22 of the second capacitor is in a square shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate of the second capacitor on the substrate.

[0342] In an exemplary embodiment, Fig.40 and Fig.41 As shown, the second electrode plate C42 of the fourth capacitor is in a square shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the fourth capacitor on the substrate.

[0343] In an exemplary embodiment, Figures 38 to 41As shown, the second connection line L2 may be in a strip shape, and at least partially extends along the second direction D2.

[0344] In an exemplary embodiment, if Fig.40 and Fig.41 As shown, the third connection line L3 may be in a strip shape and at least partially extend along the second direction D2. The fourth connection line L4 may be in a strip shape and at least partially extend along the first direction D1.

[0345] (4) forming a third insulating layer pattern, comprising: depositing a third insulating film on the substrate having the aforementioned pattern, and patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via hole patterns, such as Fig.42 and Fig.43 As shown, Fig.42 for Fig.30 A schematic diagram after forming the third insulating layer pattern, Fig.43 for Fig.31 Schematic diagram after forming the third insulation layer pattern.

[0346] In an exemplary embodiment, if Fig.42 As shown, the plurality of via patterns may include first to thirteenth vias V13 , seventeenth to eighteenth vias V17 , twenty-first to twenty-seventh vias V21 to V27 , twenty-ninth to V29 , thirtieth to V30 , and thirty-second to V32 .

[0347] In an exemplary embodiment, if Fig.43 As shown, the plurality of via hole patterns may include: a first via hole V1 to a thirty-fourth via hole V34 .

[0348] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate, the first insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the active layer of the first transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor to the first region of the active layer of the first transistor through the via hole.

[0349] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first transistor on the substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the second region of the active layer of the first transistor, and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor (also the second electrode of the seventh transistor) to the second region of the active layer of the first transistor through the via.

[0350] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the second transistor on the substrate, the first insulating layer and the second insulating layer in the third via V3 are etched away to expose the surface of the first area of ​​the active layer of the second transistor, and the third via V3 is configured to connect the first electrode of the subsequently formed second transistor to the first area of ​​the active layer of the second transistor through the via.

[0351] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the second transistor on the substrate, the first insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the active layer of the second transistor, and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor) to the second region of the active layer of the second transistor through the via hole.

[0352] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the third transistor on the substrate, the first insulating layer and the second insulating layer in the fifth via V5 are etched away to expose the surface of the first area of ​​the active layer of the third transistor, and the fifth via V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of ​​the active layer of the third transistor through the via.

[0353] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the third transistor on the substrate, the first insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the second region of the active layer of the third transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed third transistor (also the second electrode of the second transistor) to the second region of the active layer of the third transistor through the via.

[0354] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the first area of ​​the active layer of the fourth transistor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active layer of the fourth transistor through the via.

[0355] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the fourth transistor (also the second area of ​​the active layer of the fifth transistor) on the substrate, the first insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the second area of ​​the active layer of the fourth transistor (also the second area of ​​the active layer of the fifth transistor), and the eighth via V8 is configured to connect the second electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second area of ​​the active layer of the fourth transistor (also the second area of ​​the active layer of the fifth transistor) through the via.

[0356] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the first area of ​​the active layer of the fifth transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active layer of the fifth transistor through the via.

[0357] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the sixth transistor on the substrate, the first insulating layer and the second insulating layer in the tenth via V10 are etched away to expose the surface of the first area of ​​the active layer of the sixth transistor, and the tenth via V10 is configured to connect the first electrode of the subsequently formed sixth transistor to the first area of ​​the active layer of the sixth transistor through the via.

[0358] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the seventh transistor on the substrate, the first insulating layer and the second insulating layer in the eleventh via V11 are etched away to expose the surface of the second region of the active layer of the seventh transistor, and the eleventh via V11 is configured to connect the second electrode of the subsequently formed seventh transistor (which is also the second electrode of the first transistor) to the second region of the active layer of the seventh transistor through the via.

[0359] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the eighth transistor on the substrate, the first insulating layer and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the first area of ​​the active layer of the eighth transistor, and the twelfth via V12 is configured to connect the first electrode of the subsequently formed eighth transistor (which is also the second electrode of the eleventh transistor and the first electrode of the twelfth transistor) to the first area of ​​the active layer of the eighth transistor through the via.

[0360] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth transistor on the substrate, the first insulating layer and the second insulating layer in the thirteenth via V13 are etched away to expose the surface of the first region of the active layer of the eighth transistor, and the thirteenth via V13 is configured to connect the second electrode of the subsequently formed eighth transistor to the second region of the active layer of the eighth transistor through the via.

[0361] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the ninth transistor on the substrate, the first insulating layer and the second insulating layer in the fourteenth via V14 are etched away to expose the surface of the first area of ​​the active layer of the ninth transistor, and the fourteenth via V14 is configured to connect the first electrode of the subsequently formed ninth transistor to the first area of ​​the active layer of the ninth transistor through the via.

[0362] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the ninth transistor (also the second area of ​​the active layer of the fourth transistor) on the substrate, the first insulating layer and the second insulating layer in the fifteenth via V15 are etched away to expose the surface of the second area of ​​the active layer of the ninth transistor (also the second area of ​​the active layer of the fourth transistor), and the fifteenth via V15 is configured to connect the second electrode of the subsequently formed ninth transistor (also the second electrode of the fourth transistor) to the second area of ​​the active layer of the ninth transistor (also the second area of ​​the active layer of the fourth transistor) through the via.

[0363] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the sixteenth via V16 are etched away to expose the surface of the first area of ​​the active layer of the fourth transistor, and the sixteenth via V16 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active layer of the fourth transistor through the via.

[0364] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the eleventh transistor on the substrate, the first insulating layer and the second insulating layer in the seventeenth via V17 are etched away to expose the surface of the first area of ​​the active layer of the eleventh transistor, and the seventeenth via V17 is configured to connect the first electrode of the subsequently formed eleventh transistor to the first area of ​​the active layer of the eleventh transistor through the via.

[0365] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eleventh transistor on the substrate, the first insulating layer and the second insulating layer in the eighteenth via V18 are etched away to expose the surface of the first region of the active layer of the eleventh transistor, and the eighteenth via V18 is configured to connect the second electrode of the subsequently formed eleventh transistor (which is also the first electrode of the eighth transistor and the first electrode of the twelfth transistor) to the second region of the active layer of the eleventh transistor through the via.

[0366] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the twelfth transistor on the substrate, the first insulating layer and the second insulating layer in the nineteenth via V19 are etched away to expose the surface of the first area of ​​the active layer of the twelfth transistor, and the nineteenth via V19 is configured to connect the first electrode of the subsequently formed twelfth transistor (which is also the second electrode of the eleventh transistor and the first electrode of the eighth transistor) to the first area of ​​the active layer of the twelfth transistor through the via.

[0367] In an exemplary embodiment, the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the twelfth transistor on the substrate, the first insulating layer and the second insulating layer in the twentieth via V20 are etched away to expose the surface of the first region of the active layer of the twelfth transistor, and the twentieth via V20 is configured to connect the second electrode of the subsequently formed twelfth transistor to the second region of the active layer of the twelfth transistor through the via.

[0368] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the active connection portion on the substrate, the first insulating layer and the second insulating layer in the twenty-first via V21 are etched away to expose the surface of the active connection portion, and the twenty-first via V21 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor) to the active connection portion through the via.

[0369] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the control electrode of the first transistor (also the control electrode of the third transistor) on the substrate, the second insulating layer in the twenty-second via V22 is etched away to expose the surface of the control electrode of the first transistor (also the control electrode of the third transistor), and the twenty-second via V22 is configured to connect one of the subsequently formed first clock signal line and the second clock signal line and the first electrode of the second transistor to the control electrode of the first transistor (also the control electrode of the third transistor) through the via.

[0370] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the control electrode of the second transistor on the substrate, the second insulating layer in the twenty-third via V23 is etched away to expose the surface of the control electrode of the second transistor, and the twenty-third via V23 is configured to connect the second electrode of the first transistor (also the first electrode of the seventh transistor) and the first electrode of the eighth transistor (also the second electrode of the eleventh transistor and the first electrode of the twelfth transistor) formed subsequently to the control electrode of the second transistor through the via.

[0371] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the control electrode of the fourth transistor (also the control electrode of the sixth transistor, the control electrode of the fourth transistor, and the first electrode plate of the fourth capacitor) on the substrate, the second insulating layer in the twenty-fourth via V24 is etched away to expose the surface of the control electrode of the fourth transistor (also the control electrode of the sixth transistor, the control electrode of the fourth transistor, and the first electrode plate of the fourth capacitor), and the twenty-fourth via V24 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor) to the control electrode of the fourth transistor (also the control electrode of the sixth transistor, the control electrode of the fourth transistor, and the first electrode plate of the fourth capacitor) through the via.

[0372] In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the control electrode of the fifth transistor (also the control electrode of the eleventh transistor and the first plate of the second capacitor) on the substrate, the second insulating layer in the twenty-fifth via V25 is etched away to expose the surface of the control electrode of the fifth transistor (also the control electrode of the eleventh transistor and the first plate of the second capacitor), and the twenty-fifth via V25 is configured to connect the second electrode of the subsequently formed eighth transistor to the control electrode of the fifth transistor (also the control electrode of the eleventh transistor and the first plate of the second capacitor) through the via.

[0373] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the control electrode of the seventh transistor on the substrate, the second insulating layer in the twenty-sixth via V26 is etched away to expose the surface of the control electrode of the seventh transistor, and the twenty-sixth via V26 is configured to connect the subsequently formed first clock signal line and another of the second clock signal lines and the first electrode of the fifth transistor to the control electrode of the seventh transistor through the via.

[0374] In an exemplary embodiment, the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) on the substrate, the second insulating layer in the twenty-seventh via V27 is etched away to expose the surface of the control electrode of the eighth transistor (also the control electrode of the twelfth transistor), and the twenty-seventh via V27 is configured to connect a subsequently formed first second power line to the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) through the via.

[0375] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 on the substrate is located within the range of the orthographic projection of the control electrode of the ninth transistor on the substrate, the second insulating layer in the twenty-eighth via V28 is etched away to expose the surface of the control electrode of the ninth transistor, and the twenty-eighth via V28 is configured to connect the second electrode of the subsequently formed twelfth transistor to the control electrode of the ninth transistor through the via.

[0376] In an exemplary embodiment, the orthographic projection of the twenty-ninth via V29 on the substrate is within the range of the orthographic projection of the first connecting line on the substrate, the second insulating layer in the twenty-ninth via V29 is etched away to expose the surface of the first connecting line, and the twenty-ninth via V29 is configured to connect the second electrode of the fourth transistor of the shift register unit of the current level (also the second electrode of the fifth transistor) and the first electrode of the first transistor of the shift register unit of the next level to the first connecting line through the via.

[0377] In an exemplary embodiment, the orthographic projection of the thirtieth via V30 on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate, the thirtieth via V30 exposes the surface of the second plate of the second capacitor, and the thirtieth via V30 is configured to connect the second electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second plate of the second capacitor through the via.

[0378] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the second plate of the fourth capacitor on the substrate, the thirty-first via V31 exposes the surface of the second plate of the fourth capacitor, and the thirty-first via V31 is configured to connect a subsequently formed second second power line to the second plate of the fourth capacitor through the via.

[0379] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the second connecting line on the substrate, the thirty-second via V32 exposes the surface of the second connecting line, and the thirty-second via V32 is configured to connect the first electrode of the subsequently formed sixth transistor and the first electrode of the fourth transistor to the second connecting line through the via.

[0380] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the third connecting line on the substrate, the thirty-third via V33 exposes the surface of the third connecting line, and the thirty-third via V33 is configured to connect the first electrode of the subsequently formed ninth transistor and one of the third clock signal line and the fourth clock signal line to the third connecting line through the via.

[0381] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the fourth connecting line on the substrate, the thirty-fourth via V34 exposes the surface of the fourth connecting line, and the thirty-fourth via V34 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the fourth transistor) to the fourth connecting line through the via.

[0382] (5) forming a third conductive layer pattern, comprising: depositing a third metal film on the substrate formed with the aforementioned pattern, and patterning the third metal film by a patterning process to form a third metal layer pattern, such as Figures 44 to 47 As shown, Fig.44 for Fig.30 A schematic diagram of a third conductive layer pattern in FIG. Fig.45 for Fig.30 Schematic diagram after forming the third conductive layer pattern, Fig.46 for Fig.31 A schematic diagram of the third conductive layer pattern in FIG. Fig.47 for Fig.31 Schematic diagram after forming the third conductive layer pattern. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0383] In an exemplary embodiment, if Fig.44 and Fig.45 As shown, the third conductive layer pattern may include: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, a second power line VGL1, and a first electrode T13 and a second electrode T14 of a first transistor located in at least one shift register unit to a first electrode T83 and a second electrode T83 of an eighth transistor, and a first electrode T113 and a second electrode 114 of an eleventh transistor.

[0384] In an exemplary embodiment, if Fig.46 and Fig.47As shown, the third conductive layer pattern may include: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a first power line VGH, two second power lines VGL1, and a first electrode T13 and a second electrode T14 of a first transistor to a first electrode T123 and a second electrode 124 of a twelfth transistor located in at least one shift register unit.

[0385] In an exemplary embodiment, Figures 44 to 47 As shown, the second electrode T14 of the first transistor and the second electrode T74 of the seventh transistor are an integrated structure. The second electrode T24 of the second transistor and the second electrode T34 of the third transistor are an integrated structure. The second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor are an integrated structure. The first power line VGH and the first electrode T63 of the sixth transistor are an integrated structure. The first second power line VGL1 and the first electrode T33 of the third transistor are an integrated structure. The second second power line VGL1 and the first electrode T103 of the fourth transistor are an integrated structure.

[0386] In an exemplary embodiment, Fig.44 and Fig.45 As shown, the first electrode T83 of the eighth transistor and the second electrode T114 of the eleventh transistor are an integrated structure. The second power line VGL1 and the first electrode T33 of the third transistor are an integrated structure.

[0387] In an exemplary embodiment, Fig.46 and Fig.47 As shown, the first electrode T83 of the eighth transistor, the second electrode T114 of the eleventh transistor and the first electrode T123 of the twelfth transistor are an integrated structure. The second electrode T94 of the ninth transistor and the second electrode T104 of the fourth transistor are an integrated structure. The first second power line VGL1 and the first electrode T33 of the third transistor are an integrated structure. The second second power line VGL1 and the first electrode T103 of the fourth transistor are an integrated structure.

[0388] In an exemplary embodiment, Fig.44 and Fig.45 As shown, the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH and the second power line VGL1 are arranged in sequence along a side close to the display area. Any one of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH and the second power line VGL1 extends along the first direction D1.

[0389] In an exemplary embodiment, Fig.46 and Fig.47As shown, the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the first second power line VGL1, the third clock signal line CLK3, the fourth clock signal line CLK4 and the second second power line VGL1 are sequentially arranged along a side close to the display area. Any one of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the first second power line VGL1, the third clock signal line CLK3, the fourth clock signal line CLK4 and the second second power line VGL1 extends along the first direction D1.

[0390] In an exemplary embodiment, if Figures 44 to 47 As shown, the first electrode T13 of the first transistor may be in a square shape and extend along the first direction D1. The first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through the first via hole, and is connected to the first connection line located in the previous shift register unit through the twenty-ninth via hole of the previous shift register unit. Fig.44 and Fig.45 As shown, the first electrode T13 of the first transistor is located between the first power line VGH and the second power line VGL1. Fig.46 and Fig.47 As shown, the first electrode T13 of the first transistor is located between the first power line VGH and the first second power line VGL1.

[0391] In an exemplary embodiment, if Figures 44 to 47 As shown, the second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) can be in the shape of a “┌”. The second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) is connected to the second region of the active layer of the first transistor through the second via hole, to the second region of the active layer of the seventh transistor through the eleventh via hole V11, and to the control electrode of the second transistor through the twenty-third via hole. Fig.44 and Fig.45 As shown, the second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) is located between the first power line VGH and the second power line VGL1. Fig.46 and Fig.47 As shown, the second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) is located between the first power line VGH and the first second power line VGL1.

[0392] In an exemplary embodiment, if Figures 44 to 47As shown, the first electrode T23 of the second transistor may be in the shape of a strip and extend along the first direction D1. The first electrode T23 of the second transistor is connected to the first region of the active layer of the second transistor through the third via hole, and is connected to the control electrode of the first transistor (also the control electrode of the third transistor) through the twenty-second via hole. Fig.44 and Fig.45 As shown, the first electrode T23 of the second transistor is located between the first power line VGH and the second power line VGL1. Fig.46 and Fig.47 As shown, the first electrode T23 of the second transistor is located between the first power line VGH and the first second power line VGL1.

[0393] In an exemplary embodiment, Figures 44 to 47 As shown, the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) may be in the shape of a zigzag line, and at least partially extends along the first direction D1. Fig.44 and Fig.45 As shown, the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) is located between the first power line VGH and the second power line VGL1. The second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) is connected to the second region of the active layer of the second transistor through the fourth via hole, connected to the second region of the active layer of the third transistor through the sixth via hole, connected to the active connection portion through the twenty-first via hole, and connected to the control electrode of the fourth transistor (also the control electrode of the sixth transistor) through the twenty-fourth via hole. Fig.46 and Fig.47 As shown, the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) is located between the first power line VGH and the first second power line VGL1. The second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) is connected to the second region of the active layer of the second transistor through the fourth via hole, connected to the second region of the active layer of the third transistor through the sixth via hole, connected to the active connection portion through the twenty-first via hole, and connected to the control electrode of the fourth transistor (also the control electrode of the sixth transistor, the control electrode of the fourth transistor, and the first electrode plate of the fourth capacitor) through the twenty-fourth via hole.

[0394] In an exemplary embodiment, Figures 44 to 47 As shown, the first electrode T33 of the third transistor may be in a strip shape and extend along the second direction D2. The first electrode T33 of the third transistor is connected to the first region of the active layer of the third transistor through a fifth via hole. Fig.44 and Fig.45 As shown, the first electrode T33 of the third transistor is located between the first power line VGH and the second power line VGL1. Fig.46 and Fig.47As shown, the first electrode T33 of the third transistor is located between the first power line VGH and the first second power line VGL1.

[0395] In an exemplary embodiment, Figures 44 to 47 As shown, the first electrode T43 of the fourth transistor may be in the shape of a strip and extend along the second direction D2. The first electrode T43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through the seventh via hole and is connected to the second connection line through the thirty-second via hole. Fig.44 and Fig.45 As shown, the first electrode T43 of the fourth transistor is located on a side of the second power line VGL1 close to the display area. Fig.46 and Fig.47 As shown, the first electrode T43 of the fourth transistor is located between the first second power line VGL1 and the third clock signal line CLK3.

[0396] In an exemplary embodiment, Figures 44 to 47 As shown, the second electrode T44 of the fourth transistor (also the second electrode T54 of the fifth transistor) can be in the shape of a “┨”. The second electrode T44 of the fourth transistor (also the second electrode T54 of the fifth transistor) is connected to the second region of the active layer of the fourth transistor (also the second region of the active layer of the fifth transistor) through the eighth via hole, connected to the first connection line through the twenty-ninth via hole, and connected to the second electrode plate of the second capacitor through the thirtieth via hole. Fig.44 and Fig.45 As shown, the second electrode T44 of the fourth transistor (also the second electrode T54 of the fifth transistor) is located on a side of the second power line VGL1 close to the display area. Fig.46 and Fig.47 As shown, the second electrode T44 of the fourth transistor (also the second electrode T54 of the fifth transistor) is located between the first second power line VGL1 and the third clock signal line CLK3.

[0397] In an exemplary embodiment, Figures 44 to 47 As shown, the first electrode T53 of the fifth transistor may be in a strip shape and extend along the second direction D2. The first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the ninth via hole and is connected to the control electrode of the seventh transistor through the twenty-sixth via hole. Fig.44 and Fig.45 As shown, the first electrode T53 of the fifth transistor is located on a side of the second power line VGL1 close to the display area. Fig.46 and Fig.47 As shown, the first electrode T53 of the fifth transistor is located between the first second power line VGL1 and the third clock signal line CLK3.

[0398] In an exemplary embodiment, Figures 44 to 47 As shown, the first electrode T63 of the sixth transistor may be in a strip shape and extend along the second direction D2. The first electrode T63 of the sixth transistor is connected to the first region of the active layer of the sixth transistor through the tenth via hole and is connected to the second connection line through the thirty-second via hole. Fig.44 and Fig.45 As shown, the first electrode T63 of the sixth transistor is located between the first power line VGH and the second power line VGL1. Fig.46 and Fig.47 As shown, the first electrode T63 of the sixth transistor is located between the first power line VGH and the first second power line VGL1.

[0399] In an exemplary embodiment, if Fig.44 and Fig.45 As shown, the shape of the first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor) can be "L" shaped. The first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor) is located on the side of the second power line VGL1 close to the display area. The first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor) is connected to the first area of ​​the active layer of the eighth transistor through the twelfth via hole, and is connected to the second area of ​​the active layer of the eleventh transistor through the eighteenth via hole, and is connected to the control electrode of the second transistor through the twenty-third via hole.

[0400] In an exemplary embodiment, if Fig.46 and Fig.47 As shown, the shape of the first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor and the first electrode T123 of the twelfth transistor) can be "L" shaped. The first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor and the first electrode T123 of the twelfth transistor) is located between the first second power line VGL1 and the third clock signal line CLK3. The first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor and the first electrode T123 of the twelfth transistor) is connected to the first area of ​​the active layer of the eighth transistor through the twelfth via hole, and is connected to the second area of ​​the active layer of the eleventh transistor through the eighteenth via hole, is connected to the first area of ​​the active layer of the twelfth transistor through the nineteenth via hole, and is connected to the control electrode of the second transistor through the twenty-third via hole.

[0401] In an exemplary embodiment, if Figures 44 to 47As shown, the second electrode T84 of the eighth transistor may be in a strip shape and extend along the first direction D1. The second electrode T84 of the eighth transistor is connected to the second region of the active layer of the eighth transistor through the thirteenth via hole, and is connected to the control electrode of the fifth transistor (also the control electrode of the eleventh transistor and the first electrode plate of the second capacitor) through the twenty-fifth via hole. Fig.44 and Fig.45 As shown, the second electrode T84 of the eighth transistor is located on the side of the second power line VGL1 close to the display area. Fig.46 and Fig.47 As shown, the second electrode T84 of the eighth transistor is located between the first second power line VGL1 and the third clock signal line CLK3.

[0402] In an exemplary embodiment, if Fig.46 and Fig.47 As shown, the shape of the first electrode T93 of the ninth transistor may be a "[" shape. The first electrode T93 of the ninth transistor is located on the side of the second second power line VGL1 close to the display area. The first electrode T93 of the ninth transistor is connected to the first area of ​​the active layer of the ninth transistor through the fourteenth via hole, and is connected to the third connection line through the thirty-third via hole.

[0403] In an exemplary embodiment, if Fig.46 and Fig.47 As shown, the first electrode T103 of the fourth transistor may be in a strip shape and extend along the first direction D1. The first electrode T103 of the fourth transistor is located on a side of the second second power line VGL1 close to the display area. The first electrode T103 of the fourth transistor is connected to the first area of ​​the active layer of the fourth transistor through the sixteenth via hole.

[0404] In an exemplary embodiment, if Fig.46 and Fig.47 As shown, the shape of the first electrode 94 of the ninth transistor (also the second electrode T104 of the fourth transistor) can be comb-shaped, wherein the teeth of the comb are located on the side of the comb back away from the display area. The first electrode 94 of the ninth transistor (also the second electrode T104 of the fourth transistor) is located on the side of the second second power line VGL1 close to the display area. The first electrode 94 of the ninth transistor (also the second electrode T104 of the fourth transistor) is connected to the second area of ​​the active layer of the ninth transistor (also the second area of ​​the active layer of the fourth transistor) through the fifteenth via hole, and is connected to the fourth connection line through the thirty-fourth via hole.

[0405] In an exemplary embodiment, if Figures 44 to 47 As shown, the first electrode T113 of the eleventh transistor may be in a strip shape and extend along the first direction D1. The first electrode T113 of the eleventh transistor is connected to the first region of the active layer of the eleventh transistor through the seventeenth via hole. Fig.44 and Fig.45 As shown, the first electrode T113 of the eleventh transistor is located on a side of the second power line VGL1 close to the display area. Fig.46 and Fig.47 As shown, the first electrode T113 of the eleventh transistor is located between the first second power line VGL1 and the third clock signal line CLK3.

[0406] In an exemplary embodiment, Figures 44 to 47 As shown, the second electrode T124 of the twelfth transistor may be in a strip shape and extend along the second direction D2. The second electrode T124 of the twelfth transistor is located between the first second power line VGL1 and the third clock signal line CLK3. The second electrode T124 of the twelfth transistor is connected to the second region of the active layer of the twelfth transistor through the twentieth via hole, and is connected to the control electrode of the ninth transistor through the twenty-eighth via hole.

[0407] In an exemplary embodiment, as 44 to Fig.47 As shown, the control electrode of the first transistor (also the control electrode of the third transistor) is connected to one of the first clock signal line CLK1 and the second clock signal line CLK2 through the twenty-second via hole. Fig.45 and Fig.47 The description is made by taking the example that the control electrode of the first transistor (also the control electrode of the third transistor) is connected to the first clock signal line CLK1 through the twenty-second via hole.

[0408] In an exemplary embodiment, Figures 44 to 47 As shown, the control electrode of the seventh transistor is connected to the other of the first clock signal line CLK1 and the second clock signal line CLK2 through the twenty-sixth via hole. Fig.45 and Fig.47 The description is made by taking the example that the control electrode of the seventh transistor is connected to the second clock signal line CLK2 through the twenty-sixth via hole.

[0409] In an exemplary embodiment, Fig.44 and Fig.45 As shown, the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) is connected to the second power line VGL1 through the twenty-seventh via hole.

[0410] In an exemplary embodiment, Fig.46 and Fig.47 As shown, the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) is connected to the first second power line VGL1 through the twenty-seventh via hole.

[0411] In an exemplary embodiment, Fig.46 and Fig.47As shown, the second electrode plate of the fourth capacitor is connected to the second second power line VGL1 through the thirty-first via hole.

[0412] In an exemplary embodiment, if Fig.46 and Fig.47 As shown, the third connection line is connected to one of the third clock signal line CLK3 and the fourth clock signal line CLK4 through a thirty-third via hole. Fig.47 The description is made by taking the example that the third connecting line is connected to the third clock signal line CLK3 through the thirty-third via hole.

[0413] In an exemplary embodiment, if Fig.47 As shown, the orthographic projection of the second power line VGL1 on the substrate partially overlaps with the orthographic projection of the fourth capacitor on the substrate.

[0414] (6) forming a fourth insulating layer pattern, comprising: depositing a fourth insulating film on the substrate having the aforementioned pattern, patterning the fourth insulating film by a patterning process to form a fourth insulating layer pattern covering the aforementioned structure, wherein the fourth insulating layer is provided with a via pattern, such as Fig.48 and Fig.49 As shown, Fig.48 for Fig.30 A schematic diagram after forming a fourth insulating layer pattern, Fig.49 for Fig.31 Schematic diagram after forming the fourth insulation layer pattern.

[0415] In an exemplary embodiment, if Fig.48 and Fig.49 As shown, the via hole pattern may include: a thirty-fifth via hole V35.

[0416] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the first electrode of the eleventh transistor on the substrate, the thirty-fifth via V35 exposes the surface of the first electrode of the eleventh transistor, and the thirty-fifth via V35 is configured to connect a subsequently formed third power line to the first electrode of the eleventh transistor through the via.

[0417] (7) forming a fourth conductive layer pattern, comprising: depositing a fourth metal film on the substrate formed with the aforementioned pattern, and patterning the fourth metal film by a patterning process to form a fourth metal layer pattern, such as Figure 50 to Figure 52 As shown, Fig.50 for Fig.30 and Fig.31 A schematic diagram of a fourth conductive layer pattern in FIG. Fig.51 for Fig.30 A schematic diagram after forming the fourth conductive layer pattern, Fig.52 for Fig.31Schematic diagram after forming a fourth conductive layer pattern. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0418] In an exemplary embodiment, Figure 50 to Figure 52 As shown, the fourth conductive layer pattern may include: a third power line VGL2.

[0419] In an exemplary embodiment, Figure 50 to Figure 52 As shown, the shape of the third power line VGL2 can be a line shape and extend along the first direction D1. The third power line VGL2 is connected to the first electrode of the eleventh transistor through the thirty-fifth via hole. The orthographic projection of the third power line VGL2 on the substrate partially overlaps with the orthographic projections of the fourth transistor and the fifth transistor on the substrate.

[0420] In an exemplary embodiment, Fig.51 As shown, the positive projection of the third power line VGL2 on the substrate is located on the side of the positive projection of the second power line on the substrate close to the display area. Fig.52 As shown, the orthographic projection of the third power line VGL2 on the substrate is located between the orthographic projection of the first second power line on the substrate and the orthographic projection of the third clock signal line on the substrate.

[0421] (8) forming a planar layer pattern, comprising: depositing a fifth insulating film on a substrate having the aforementioned pattern, coating a second planar film, and patterning the fifth insulating film and the second planar film through a patterning process to form a fifth insulating layer pattern and a planar layer pattern covering the aforementioned pattern.

[0422] At this point, the drive structure layer is prepared on the substrate. In a plane parallel to the display substrate, the drive structure layer may include a plurality of shift register units, and the drive structure layer may be arranged on the substrate. The drive structure layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a flat layer sequentially arranged on the substrate.

[0423] In an exemplary embodiment, the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0424] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0425] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0426] In an exemplary embodiment, the planar layer may employ an organic material such as resin or the like.

[0427] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0428] On the substrate formed with the aforementioned pattern, an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode conductive layer pattern arranged on the flat layer; on the substrate formed with the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned by a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern; on the substrate formed with the pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned by a patterning process to form an organic structure layer pattern; on the substrate formed with the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned by a patterning process to form a cathode conductive layer.

[0429] At this point, the light-emitting structure layer is prepared on the substrate.

[0430] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0431] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anode patterns.

[0432] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0433] In an exemplary embodiment, the organic structure layer may include at least: an organic light emitting layer of a light emitting device.

[0434] In an exemplary embodiment, the cathode conductive layer may include at least: cathodes of a plurality of light emitting devices.

[0435] In an exemplary embodiment, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum and titanium.

[0436] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0437] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0438] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0439] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A shift register unit, characterized in that: include: a node control subcircuit, an output subcircuit, and a pull-down subcircuit; The node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, and the second node, respectively, and is configured to provide a signal from the signal input terminal or the first power supply terminal to the first node, and provide a signal from the second power supply terminal or the first clock signal terminal to the second node under the control of the signal from the first clock signal terminal and the second clock signal terminal; The pull-down sub-circuit is electrically connected to the first node and the third power supply terminal, respectively, and is configured to provide a signal of the third power supply terminal to the first node; The output subcircuit is electrically connected to the second clock signal terminal, the first power terminal, the second power terminal, the first signal output terminal, the first node and the second node respectively, and is configured to provide a signal from the first power terminal or the second clock signal terminal to the first signal output terminal under the control of the signals from the first node, the second node and the second power terminal; An absolute value of a voltage value of a signal at the third power supply terminal is greater than an absolute value of a voltage value of a signal at the second power supply terminal.

2. The shift register unit according to claim 1, characterized in that: The pull-down sub-circuit comprises: an eleventh transistor; A first electrode of the eleventh transistor is electrically connected to the third power supply terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

3. The shift register unit according to claim 2, characterized in that: The control electrode of the eleventh transistor is electrically connected to the first node.

4. The shift register unit according to claim 1, characterized in that: The node control subcircuit includes: a first transistor, a second transistor, a third transistor, a sixth transistor and a seventh transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fourth node; The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first node.

5. The shift register unit according to claim 1, characterized in that: The output sub-circuit comprises: a fourth transistor, a fifth transistor and an eighth transistor; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first signal output terminal; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first signal output terminal; The control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node.

6. The shift register unit according to claim 5, characterized in that: The pull-down sub-circuit comprises: an eleventh transistor; The eleventh transistor control electrode is electrically connected to the third node.

7. The shift register unit according to claim 5, characterized in that: The output subcircuit further includes: at least one of a first capacitor and a second capacitor; The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power supply terminal; The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first signal output terminal.

8. The shift register unit according to claim 1, characterized in that: The output subcircuit is also electrically connected to the third clock signal terminal and the second signal output terminal respectively, and is configured to provide a signal from the second power supply terminal or the third clock signal terminal to the second signal output terminal under the control of the signals of the first node and the second node.

9. The shift register unit according to claim 8, characterized in that: The output sub-circuit comprises: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor and a tenth transistor; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first signal output terminal; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first signal output terminal; The control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is connected to the third clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the second signal output terminal; The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the second signal output terminal.

10. The shift register unit according to claim 9, characterized in that: The output sub-circuit further includes: a twelfth transistor; the control electrode of the ninth transistor is electrically connected to the first node through the twelfth transistor; The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the control electrode of the ninth transistor.

11. The shift register unit according to claim 9 or 10, characterized in that: The output subcircuit further includes: at least one of a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power supply terminal; The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first signal output terminal; A first electrode plate of the third capacitor is electrically connected to the control electrode of the ninth transistor, and a second electrode plate of the third capacitor is connected to the second signal output terminal; The first plate of the fourth capacitor is electrically connected to the second node, and the second plate of the fourth capacitor is connected to the second power supply terminal.

12. The shift register unit according to claim 8, characterized in that: The signal at the third clock signal end and the signal at the second clock signal end are inverted signals to each other.

13. The shift register unit according to claim 1, characterized in that: Also includes: output control subcircuit; The output control subcircuit is electrically connected to the first power supply terminal and the first signal output terminal respectively, and is configured to store a voltage difference between the signal at the first signal output terminal and the signal at the first power supply terminal.

14. The shift register unit according to claim 13, characterized in that: The output control subcircuit comprises: a fifth capacitor; The first electrode of the fifth capacitor is electrically connected to the first power supply terminal, and the second electrode of the fifth capacitor is electrically connected to the first signal output terminal.

15. The shift register unit according to claim 1, characterized in that: The signals of the first clock signal terminal and the second clock signal terminal are not simultaneously valid level signals.

16. A display substrate, characterized in that: It includes: a substrate, and sub-pixels, gate lines, and a gate driving circuit disposed on the substrate. The substrate is provided with a display area and a non-display area. The gate driving circuit is located in the non-display area. The sub-pixels and the gate lines are located in the display area. The gate lines are electrically connected to the sub-pixels and the gate driving circuit respectively. The gate driving circuit includes: a plurality of cascaded shift register units as described in any one of claims 1 to 15. Wherein, the first signal output terminal of the i-th stage shift register unit is connected to the signal input terminal of the (i + 1)-th stage shift register unit, 1 ≤ i < N, and N is the total number of stages of the shift register units.

17. The display substrate according to claim 16, characterized in that: The first signal output terminal of the shift register unit is electrically connected to the gate line.

18. The display substrate according to claim 16, characterized in that: It further includes: An initial signal line, a first clock signal line, a second clock signal line, a first power supply line, a second power supply line, and a third power supply line that are disposed on the substrate and located in the non-display area; Any one of the initial signal line, the first clock signal line, the second clock signal line, the first power supply line, the second power supply line, and the third power supply line extends along a first direction, the gate line extends along a second direction, and the first direction intersects with the second direction.

19. The display substrate according to claim 18, characterized in that: The initial signal line, the first clock signal line, the second clock signal line, and the first power supply line are arranged in sequence along the direction close to the display area and are located on the side of the shift register unit away from the display area.

20. The display substrate according to claim 18, characterized in that: The shift register unit includes: a plurality of transistors. The second power supply line is located on the side of the first power supply line close to the display area and is located between the plurality of transistors of the shift register unit.

21. The display substrate according to claim 18, characterized in that The third power supply line is located on the side of the second power supply line close to the display area, and the orthographic projection of the third power supply line on the substrate partially overlaps with the orthographic projection of the shift register unit on the substrate.

22. The display substrate according to claim 18, characterized in that: The shift register unit includes: a first transistor, a second transistor, a third transistor, a sixth transistor, and a seventh transistor; At least a part of any one of the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor is located between the first power supply line and the second power supply line.

23. The display substrate according to claim 18, characterized in that: The shift register unit includes: a fourth transistor, a fifth transistor, an eighth transistor, an eleventh transistor, and a twelfth transistor. The number of the second power supply lines is at least one; At least a part of any one of the fourth transistor, the fifth transistor, the eighth transistor, the eleventh transistor, and the twelfth transistor is located on the side of the second power supply line close to the display area.

24. The display substrate according to claim 18, characterized in that: The shift register unit includes: a second capacitor; The second capacitor is located on the side of the third power supply line close to the display area.

25. The display substrate according to claim 18 or 19, characterized in that: It further includes: A third clock signal line and a fourth clock signal line that are disposed on the substrate and located in the non-display area. Any one of the third clock signal line and the fourth clock signal line extends along the first direction; There are two second power lines. The second power line close to the display area is located on a side of any one of the third clock signal line and the fourth clock signal line close to the display area, and the second power line far from the display area is located between the first power line and the third power line.

26. The display substrate according to claim 25, characterized in that: The shift register unit includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a fourth capacitor; The fourth transistor, the fifth transistor, the eighth transistor, the eleventh transistor and the twelfth transistor are located between the second power line and any one of the third clock signal line and the fourth clock signal line far from the display area, and the ninth transistor and the tenth transistor are located on a side of the second power line close to the display area; The orthographic projection of the second power line close to the display area on the substrate partially overlaps with the orthographic projection of the fourth capacitor on the substrate.

27. The display substrate according to claim 18, characterized in that: The first clock signal terminal of the i-th shift register unit is electrically connected to one of the first clock signal line and the second clock signal line, and the second clock signal terminal of the i-th shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line; The first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines.

28. The display substrate according to claim 21, characterized in that: The shift register unit comprises: a fourth transistor and a fifth transistor; An orthographic projection of the third power line on the substrate partially overlaps with orthographic projections of the fourth transistor and the fifth transistor on the substrate.

29. The display substrate according to claim 23, characterized in that: The active layer of the eighth transistor extends along the second direction, any one of the first electrode and the second electrode of the eighth transistor extends along the first direction, and the gate electrode of the eighth transistor at least partially extends along the first direction.

30. The display substrate according to claim 23, characterized in that The gate electrode of the eleventh transistor is an integral structure with the gate electrode of the fifth transistor, the orthographic projection of the first electrode of the eleventh transistor on the substrate partially overlaps with the orthographic projection of the third power line on the substrate, and is electrically connected to the third power line, and the second electrode of the eleventh transistor is an integral structure with the first electrode of the eighth transistor and the first electrode of the twelfth transistor.

31. The display substrate according to claim 25, characterized in that A width of any one of the first power line, the second power line and the third power line along the second direction is smaller than a width of any one of the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line along the second direction.

32. The display substrate according to claim 25, characterized in that: The third clock signal terminal of the i-th stage shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line, and the third clock signal terminal of the i+1-th stage shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.

33. The display substrate according to claim 26, characterized in that: A channel width of an active layer of the tenth transistor is greater than a channel width of an active layer of the fourth transistor.

34. The display substrate according to claim 33, characterized in that: The channel width of the active layer of the tenth transistor is not less than 90 micrometers.

35. The display substrate according to claim 33, characterized in that: The channel width of the active layer of the fourth transistor is not greater than 50 micrometers.

36. The display substrate according to claim 26, characterized in that: A channel width of an active layer of the ninth transistor is greater than a channel width of an active layer of the fifth transistor.

37. The display substrate according to claim 36, characterized in that: The channel width of the active layer of the ninth transistor is not less than 90 micrometers.

38. The display substrate according to claim 36, characterized in that: The channel width of the active layer of the fifth transistor is not greater than 50 micrometers.

39. The display substrate according to claim 26, characterized in that: The second signal output terminal of the shift register unit is electrically connected to the gate line.

40. A display device, characterized in that: include: A display substrate as claimed in any one of claims 16 to 39.

41. A method for driving a shift register unit, characterized in that: is configured to drive the shift register unit according to any one of claims 1 to 15, the method comprising: The node control subcircuit provides a signal from the signal input terminal or the first power supply terminal to the first node and provides a signal from the second power supply terminal or the first clock signal terminal to the second node under the control of the signals from the first clock signal terminal and the second clock signal terminal; The pull-down sub-circuit provides a signal of the third power supply terminal to the first node; The output subcircuit provides a signal from the first power supply terminal or the second clock signal terminal to the first signal output terminal under the control of the signals from the first node and the second node.

42. The method according to claim 41, characterized in that The shift register unit further includes: an output control subcircuit; The method further comprises: the output subcircuit provides a signal from a second power supply terminal or a third clock signal terminal to a second signal output terminal under the control of the signals from the first node and the second node; The output control subcircuit stores a voltage difference between the signal at the first signal output terminal and the signal at the first power supply terminal.

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