Feedback circuit, memory device and method for operating memory device

Abstract

The invention provides a feedback circuit, a memory device and a method for operating the memory device. The invention particularly provides a method for limiting a leakage current of a memory device. A readout current is generated, the readout current being a representation of a leakage current of a memory cell array of a memory device. Generating a reference current with a preset value; the read current is compared with the reference current. An enable signal is generated based on the comparison. A bias voltage applied to a plurality of word lines of the memory cell array is adjusted based on the enable signal. The method provided by the invention is favorable for reducing the test cost and increasing the efficiency of the memory device.

Description

Technical Field

[0001] An embodiment of the present disclosure relates to a memory device and an operating method thereof, and more particularly to a leakage current controlled memory device and an operating method thereof. Background Art

[0002] Semiconductor memory is widely used as a storage medium for digital devices such as personal computers, cellular phones, personal data assistants, and other similar products. Digital information in units of one bit is stored in a two-dimensional array of bit cells or memory cells. Typically, a memory device includes one or more memory arrays that include memory cells and peripheral circuits that are used to perform functions such as addressing the memory cells, storing data in the memory cells, and retrieving data from the memory cells. The memory array can be any suitable type of memory, such as dynamic random-access memory (DRAM) or static random-access memory (SRAM). In SRAM, data is maintained as long as power is supplied to it. On the other hand, DRAM is volatile, meaning that it needs to be constantly rewritten to maintain its contents. DRAM is small and inexpensive, so it is used for most system memory. Summary of the invention

[0003] An embodiment of the present disclosure provides a feedback circuit, including a reference cell array, a reference current generator, a comparator, and a negative voltage generator. The reference cell array is operable to generate a read current representing a leakage current of a memory device. The reference current generator is operable to generate a reference current having a preset value. The comparator is operable to compare the reference current with the read current and provide an enable signal based on the comparison. The negative voltage generator is operable to generate a bias voltage based on the enable signal, wherein the bias voltage is applied to a plurality of word lines of the memory device in a standby mode.

[0004] An embodiment of the present disclosure provides a memory device, including a memory cell array and a first feedback circuit. The memory cell array includes a matrix of a plurality of rows and a plurality of columns, wherein each of the rows includes a plurality of first memory cells connected to a word line of a plurality of word lines, and wherein each of the columns includes a plurality of second memory cells connected to a bit line of a plurality of bit lines. The first feedback circuit is operable to provide a bias voltage to the word lines during a standby mode, wherein the feedback circuit limits a leakage current of the memory cell array to a preset value.

[0005] An embodiment of the present disclosure provides a method for operating a memory device, the method comprising the following steps: generating a read current, the read current being representative of a leakage current of a memory cell array of the memory device; generating a reference current having a preset value; comparing the read current with the reference current; generating an enable signal based on the comparison; and adjusting bias voltages applied to a plurality of word lines of the memory cell array based on the enable signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the disclosed embodiments may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. In addition, the drawings are illustrative as examples of embodiments of the disclosed embodiments and are not intended to be limiting.

[0007] Figure 1 is a diagram of a memory device according to some embodiments;

[0008] Figure 2 A diagram illustrating a memory cell of a memory device according to some embodiments;

[0009] Figure 3 is a diagram of a first feedback circuit for controlling leakage current of a memory device according to some embodiments;

[0010] Figure 4 is a diagram of a reference cell array of a first feedback circuit according to some embodiments;

[0011] Figure 5 is a diagram of a first example circuit diagram of a first feedback circuit according to some embodiments;

[0012] Figure 6 is a diagram of a second example circuit diagram of a first feedback circuit according to some embodiments;

[0013] Figure 7 is a diagram of a second feedback circuit for providing a pumped word line voltage according to some embodiments;

[0014] Figure 8 is a flow chart of a method for limiting leakage current of a memory device according to some embodiments.

[0015]

Explanation of symbols

[0016] 100:Memory device

[0017] 102: memory cell array

[0018] 104: Address decoder

[0019] 106: Readout amplifier

[0020] 108: Flip-flop

[0021] 112: Controller

[0022] 114:Timer

[0023] 116: Feedback circuit

[0024] 120: memory unit

[0025] 122: Access transistor

[0026] 124:Energy storage device

[0027] 200: first feedback circuit

[0028] 202: Reference cell array

[0029] 204, 602, 714: Comparator

[0030] 206: Gain and compensation block

[0031] 208: Negative voltage generator

[0032] 210: Reference current generator

[0033] 212, 726: output node

[0034] 500: First Example Circuit Diagram

[0035] 502, 604, 702: first transistor

[0036] 504, 606, 704: second transistor

[0037] 506, 608: third transistor

[0038] 508: fourth transistor

[0039] 510: fifth transistor

[0040] 512: sixth transistor

[0041] 514: Seventh transistor

[0042] 516: The eighth transistor

[0043] 518: The ninth transistor

[0044] 520: The tenth transistor

[0045] 522: Eleventh Transistor

[0046] 524:Energy storage element

[0047] 526: First current mirror

[0048] 528: Second current mirror

[0049] 530, 612, 720: first node

[0050] 600: Second Example Circuit Diagram

[0051] 610, 718: Current mirror

[0052] 614, 722: Second node

[0053] 700: word line voltage generating circuit

[0054] 706: first resistance element

[0055] 708: Second resistance element

[0056] 710: third resistance element

[0057] 712: fourth resistor element

[0058] 716: Charge Pump

[0059] 724: Third Node

[0060] 800: Method

[0061] 810, 820, 830, 840, 850: Block

[0062] A, B, C, D: Unit

[0063] BL, BL1, BL2, BL3, BL4: bit lines

[0064] CBL: Common Bit Line

[0065] CMP: Comparator

[0066] CPL: Common Panel Line

[0067] CSL: Common Source Line

[0068] CWL: Common Word Line

[0069] FF: Flip-flop

[0070] I LEAK :Leakage Current

[0071] I REF : Reference current

[0072] I R :Current

[0073] I SENSE :Read current

[0074] M4: Metal layer 4

[0075] M6: Metal layer six

[0076] PL: Plate Line

[0077] PUMP_EN: Pump enable signal

[0078] SA: Sense Amplifier

[0079] SL: Source Line

[0080] VBL: bit line voltage

[0081] VDD: supply voltage

[0082] VPP: Pumping word line voltage

[0083] VSS: Reference voltage

[0084] VSSN: Negative bias voltage

[0085] WL, WL1, WL2, WL3, WL4: character line DETAILED DESCRIPTION

[0086] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of components and configurations described below are for simplifying the embodiments of the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0087] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0088] Memory devices, such as Dynamic Random Access Memory (DRAM) devices, are used to store data in semiconductor devices and systems. Data stored in memory devices may be corrupted due to various reasons. One possible cause of corruption is due to environmental events inside the memory device and outside the memory device. In addition to environmental events, there are other reasons that lead to data corruption (failure). Data errors that are non-permanent or do not represent physical damage to the memory device (such as soft errors) can be caused by interference errors, radiation effects, or thermal effects. When bits are corrupted, the stored data is lost, resulting in system failure or data loss.

[0089] Therefore, memory devices are refreshed via a memory refresh operation to maintain the accuracy of the stored information. A memory refresh operation, or simply a refresh operation, is a process of periodically reading data from a region of a memory device, checking the data for errors, correcting the errors (if errors are detected), and rewriting the data to the memory device. Each memory refresh cycle refreshes subsequent regions of the memory device, thereby repeatedly refreshing all memory cells in consecutive cycles. Generally speaking, while a refresh operation is occurring, the memory device may not be available for read and write operations.

[0090] In one example, the frequency of refresh operations is determined based on the data corruption rate, which depends on the leakage current of the memory device. The leakage current may vary over the life of the memory device based on various factors such as environmental events (e.g., temperature changes), usage (i.e., aging), manufacturing defects (i.e., missing corners), etc. Therefore, the frequency of refresh operations may need to be continuously updated or set to match the worst case. Such refresh operations may result in a waste of resources because the memory device may not be available for normal read and write operations while the refresh operation is occurring.

[0091] Embodiments of the present disclosure provide circuits and methods for controlling or limiting the leakage current of a memory device to a preset value. Limiting the leakage current to a preset value can result in a constant frequency of refresh operations regardless of manufacturing defects, temperature variations, or usage patterns. In addition, embodiments of the present disclosure provide circuits and methods for providing a pumped word line voltage for a memory device. The pumped word line voltage is closer to the maximum limit of the word line voltage of the memory device and depends on the preset value of the leakage current. Therefore, the circuits and methods described herein eliminate the need for a temperature sensor or a leakage current sensor in the memory device. In addition, the circuits and methods described herein improve read and write operations and refresh operations in the memory device.

[0092] Figure 1A memory device 100 according to some embodiments is described. In some examples, the memory device 100 is a volatile memory device, such as a DRAM device. However, it will be apparent to one of ordinary skill in the art after reading the disclosed embodiments that other types of memory devices are within the scope of the disclosed embodiments. The memory device 100 may be used to store data and may require memory refresh to maintain the accuracy of the stored data.

[0093] like Figure 1 As shown in FIG. 1 , the memory device 100 includes a memory cell array 102, an address decoder 104, a sense amplifier 106, a flip-flop 108, and a controller 112. The controller 112 further includes a timer 114 and a feedback circuit 116. After reading the embodiments of the present disclosure, it will be apparent to those skilled in the art that the memory device 100 is similar to the memory cell array 102 of FIG. 1 . Figure 1 The memory device 100 may include additional components compared to the components shown in FIG. 1 . In addition, it will be apparent to those skilled in the art after reading the embodiments of the present disclosure that the memory device 100 may include additional components compared to the components shown in FIG. Figure 1 Fewer components than shown in the .

[0094] The memory cell array 102 includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. For example, a one-million-bit memory device includes a cell array having 1024 rows and 1024 columns, and thus having 1024×1024 memory cells. Each memory cell in the plurality of memory cells is used to store a bit logic “0” or “1” value of data therein.

[0095] Figure 2 An example memory cell 120 of the memory cell array 102 of the memory device 100 is illustrated according to some embodiments. The memory cell 120 stores one bit of information, such as a bit value of 1 and a bit value of 0. Figure 2 As shown in FIG. 1 , the memory cell 120 includes an access transistor 122 and an energy storage device 124 (also referred to as a capacitor 124). The source of the access transistor 122 is connected to a bit line (BL), and the drain of the access transistor 122 is connected to a source line (SL) and a first terminal of the capacitor 124. The second terminal of the capacitor 124 is connected to a plate line (PL). The gate of the access transistor 122 is connected to a word line (WL).

[0096] Since the memory cell 120 includes a transistor and a capacitor, it is also referred to as a 1T1C memory cell. However, other types of memory cells (e.g., 1T2C, 1T2C, 2T1C, 3T1C, etc.) are within the scope of the embodiments of the present disclosure. In an example, the bit line (BL) may be formed in metal layer four (M4), and the source line (SL) may be formed in metal layer six (M6). However, both the bit line (BL) and the source line (SL) may be formed in different metal layers.

[0097] A charged capacitor 124 represents a bit value of 1, while a discharged capacitor 124 represents a bit value of 0. A word line (WL) controls access to the capacitor 124 via an access transistor 122. For example, the word line (WL) is charged to a predetermined voltage level to turn on the access transistor 122 that connects the bit line (BL) to the capacitor 124. The charge on the capacitor 124 is measured via the bit line (BL) to determine the storage value in the memory cell 120. When the memory cell 120 is not used to read or write data, the leakage current (I LEAK ) may flow through the memory unit 120.

[0098] In an example, the access transistor 122 is an n-channel Metal Oxide Semiconductor (NMOS) transistor. However, other types of transistors are also within the scope of the embodiments of the present disclosure, such as a Complementary Metal Oxide Semiconductor (CMOS) transistor, a p-channel Metal Oxide Semiconductor (PMOS) transistor, a Field Effect Transistor (FET), a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), etc. In addition, the access transistor 122 is symmetrical. That is, the drain of the access transistor 122 can be the source, and the source of the access transistor 122 can be the drain.

[0099] return Figure 1, each of the plurality of rows of the memory cell array 102 is associated with a word line (e.g., WL1, WL2, WL3, WL4, etc.). In addition, each of the plurality of rows includes a first plurality of cells (cell A, cell B, cell C, cell D, etc.) of the plurality of cells. Each of the first plurality of cells of a row of the plurality of rows is connected to an associated word line (i.e., one of WL1, WL2, WL3, WL4, etc.). Similarly, each of the plurality of columns of the memory cell array 102 is associated with a bit line (i.e., BL1, BL2, BL3, BL4, etc.). In addition, each of the plurality of columns includes a second plurality of bit cells of the plurality of bit cells. Each of the second plurality of bit cells of a column of the plurality of columns is connected to an associated bit line (i.e., one of BL1, BL2, BL3, BL4, etc.).

[0100] The address decoder 104 is connected to the memory cell array 102. The address decoder 104 is operable to select one of a plurality of word lines (i.e., one of WL1, WL2, WL3, WL4, etc.) and charge the selected word line to a predetermined voltage level for read and write operations on a first plurality of cells associated with the selected word line. A single memory cell within an example one million-bit memory device having 1024×1024 cells may be selected by a 10-bit row address and a 10-bit column address. In some examples, the address decoder 104 is also referred to as a word line driver.

[0101] The sense amplifier 106 is connected to the memory cell array 102 and is operable to read data from the memory cell array 102 or write data into the memory cell array 102. For example, the sense amplifier 106 is operable to sense the current in the bit line and compare the sensed current with a reference current to read data from the memory cell array 102 or write data into the memory cell array 102. The sense amplifier 106 may be associated with a predetermined number of bit lines (e.g., four bit lines, eight bit lines, etc.). The predetermined number of bit lines associated with each sense amplifier 106 is also referred to as a word. The flip-flop 108 is connected to the sense amplifier 106 and is operable to temporarily store data read from the memory cell array 102 or data to be written into the memory cell array 102. Although Figure 1 The memory device 100 is shown as including only one sense amplifier, but it will be apparent to one of ordinary skill in the art that the memory device 100 may include more than one sense amplifier and flip-flop.

[0102] The controller 112 is connected to the memory cell array 102 and is operable to perform a refresh operation of the memory cell array 102. For example, the controller 112 initiates and performs a refresh operation on the memory cell array 102 at a set frequency. That is, the controller 112 repeats the refresh operation after a predetermined time period (e.g., every 20 milliseconds, 200 milliseconds, 2 seconds, etc.). The predetermined time period or frequency of the refresh operation is provided by the timer 114.

[0103] The feedback circuit 116 provides a bias voltage to the plurality of word lines during the standby mode to limit the leakage current of the memory cell array 102 to a preset value during the standby mode. Limiting the leakage current to the preset value helps to maintain a constant frequency of refresh operations of the memory device 100. In addition, the feedback circuit 116 provides a pumped word line voltage to the plurality of word lines for read and write operations. The pumped word line voltage improves the read and write efficiency of the memory device 100 by providing a better voltage margin for the read and write operations. The feedback circuit 116 will be discussed in more detail in the following sections of the present disclosure.

[0104] Controller 112 may include a storage device for storing instructions for refresh operations and one or more processors for executing the stored instructions to perform and manage refresh operations. The storage device for storing instructions may include a non-transistor computer readable medium.

[0105] In an example embodiment, the controller 112 may be in the form of a separate chip or circuit. In one example, the controller 112 is integrated with the memory device 100. In another example, the controller 112 is implemented on a motherboard or from an integrated memory controller (IMC) on a microprocessor to potentially reduce memory latency. Among other factors, the controller 112 also includes an error correction code (ECC) circuit (not shown). The ECC circuit is used to perform error checking on data stored in the memory cell array 102. For example, the ECC circuit is used to detect and correct errors in data stored in multiple cells of the memory cell array 102. In some examples, the ECC circuit may include an error detection module for detecting errors and an error correction module for correcting detected errors.

[0106] According to an example embodiment of the present disclosure, the predetermined time period or frequency of the refresh operation depends on the leakage current (I LEAK ). By setting the leakage current (I LEAK) is limited or controlled to a preset value, and the refresh frequency of the memory device 100 can be fixed. The feedback circuit 116 applies a negative bias voltage (VSSN) to multiple word lines of the memory device 100 to adjust the leakage current (I LEAK ) is controlled or limited to a preset value.

[0107] Figure 3 The present invention is used to control the leakage current (I) of the memory cell array 102 of the memory device 100 according to some embodiments of the present invention. LEAK ) of the first feedback circuit 200. The first feedback circuit 200 can LEAK ) is controlled at a target value (i.e., a preset value) to achieve a constant refresh frequency regardless of process corners, voltage variations, and operating temperatures. For example, when the memory device 100 is in standby mode, the first feedback circuit 200 provides a negative bias voltage (VSSN) applied to the gates of a plurality of memory cells of the memory cell array 102. Applying a negative bias voltage (VSSN) at the gates of the plurality of memory cells reduces or limits leakage caused by a high electric field effect in the drain junction by suppressing the creation of a depletion region under the gate. In addition, applying a negative bias voltage (VSSN) at the gates of the plurality of memory cells reduces dielectric leakage between the bit line contact (BLC) and the source node contact (SNC) by creating a larger barrier layer for electrons to flow through the metal and dielectric regions. The first feedback circuit 200 adjusts the negative bias voltage (VSSN) so that the leakage current (I LEAK ) is lower than the preset value.

[0108] like Figure 3 As shown in FIG. 1 , the first feedback circuit 200 includes a reference cell array 202, a comparator 204, a gain and compensation block 206, a negative voltage generator 208, and a reference current generator 210. The output of the reference cell array 202 is connected to a first input of the comparator 204. The output of the reference current generator is connected to a second input of the comparator 204.

[0109] The output of the first comparator 204 is connected to a first input of the gain and compensation block 206. The output of the negative voltage generator 208 is connected to a second input of the gain and compensation block 206. The output of the gain and compensation block 206 provides a negative bias voltage (VSSN) for a plurality of word lines of the memory device 100. The input of the reference cell array 202 is connected to the output of the gain and compensation block 206 at the output node 212. Therefore, the reference cell array 202, the first comparator 104, and the gain and compensation block 206 are connected in a feedback mode or a negative feedback mode.

[0110] The reference cell array 202 reads out the current (I SENSE ) is provided to the first input terminal of the comparator 204. The read current (I SENSE ) is the leakage current (I LEAK ), which represents the leakage current (I LEAK ). Figure 4 An example reference cell array 202 is illustrated in accordance with some embodiments of the present disclosure.

[0111] like Figure 4 As shown in , the reference cell array 202 includes a plurality of reference cells arranged in a matrix of a plurality of rows and a plurality of columns. The plurality of reference cells of the reference cell array 202 are similar to the memory cells 120 of the memory cell array 102. The gate of each reference cell of the reference cell array 202 in a row is connected to a word line. The source / drain of each reference cell in a row is connected to a bit line, and the drain / source of each reference cell in a row is connected to a source line. In addition, the plate of the capacitor of each reference cell in a row is connected to the plate line. However, all the bit lines of the reference cell array 202 are connected together as a common bit line (CBL). Similarly, all the word lines of the reference cell array 202 are connected together as a common word line (CWL). In addition, all the source lines of the reference cell array 202 are connected together as a common source line (CSL). Similarly, all the plate lines of the reference cell array 202 are connected together as a common plate line (CPL). The read current (I SENSE ) is the total drain-source current flowing from the common bit line (CBL) to the common source line (CSL), that is, the sum of the drain-source currents of the N reference bit cells.

[0112] The reference cell array 202 may be in the range of 100 kilobits to 1 million bits. However, other values ​​are within the scope of the disclosed embodiments. According to an example embodiment, the reference cell array 202 may include two or more reference cell sub-arrays located at different locations on the cell die. For example, one or more reference cell sub-arrays may be located at the center, edge, corner, etc. of the memory cell 100. Placing the reference cell sub-arrays at different locations on the cell die may provide a measure of the leakage current (I LEAK) and can take into account temperature variations at different locations on the unit die. In addition, placing the reference cell subarray at different locations on the unit die can take into account manufacturing defects at different locations on the unit die.

[0113] return Figure 3 The reference current generator 210 generates a reference current (I REF ). Reference current (I REF ) is the leakage current (I LEAK For example, the reference current (I REF ). Reference current (I REF ) can be constant and temperature compensated. For example, the reference current (I REF ) may vary with the temperature of the memory device 100. The reference current generator 210 generates a reference current (I REF ) is provided to the second input terminal of the comparator 204.

[0114] The comparator 204 receives the read current (I SENSE ) and the reference current (I REF ) to compare and provide an output signal at the output terminal. In an example, comparator 204 can be a digital comparator with a clock or an analog comparator without a clock. In some examples, comparator 204 can be a current or voltage comparator. In an example, if both inputs are connected to a resistor element, a voltage comparator can be used.

[0115] The output signal of the comparator 204 controls the negative voltage generator 208 via the gain and compensation block 206. The negative voltage generator 208 is used to limit the leakage current (I LEAK ) provides a negative bias voltage (VSSN) at the output terminal. For example, when the read current (I SENSE ) is higher than the reference current (I REF ), the gain and compensation block 206 may generate a pump enable signal (PUMP_EN) for the negative voltage generator 208. The negative voltage generator 208 decreases the negative bias voltage (VSSN) in response to receiving the pump enable signal (PUMP_EN). Since the negative bias voltage (VSSN) is applied to the gates of the plurality of memory cells of the memory cell array 102, the decrease in the negative bias voltage (VSSN) reduces the leakage current (I LEAK ). The negative bias voltage (VSSN) is lowered or decreased until the read current (I SENSE ) is equal to or lower than the reference current (I REF). Therefore, the first feedback circuit 200 converts the leakage current (I LEAK ) is limited to be equal to or lower than the reference current (I REF ) (i.e., the default value).

[0116] Figure 5 According to some embodiments of the present disclosure Figure 3 The first example circuit diagram 500 of the first feedback circuit 200 is shown. The feedback circuit 200 of the first circuit diagram 500 provides a negative bias voltage (VSSN) to the gates of a plurality of memory cells of the memory cell array 102 of the memory device 100 to reduce the leakage current (I LEAK ) is limited to the preset value. Figure 5 As shown in the figure, the first circuit diagram 500 includes a reference cell array 202, a first transistor 502, a second transistor 504, a third transistor 506, a fourth transistor 508, a fifth transistor 510, a sixth transistor 512, a seventh transistor 514, an eighth transistor 516, a ninth transistor 518, a tenth transistor 520, an eleventh transistor 522 and an energy storage element 524 (also referred to as a capacitor 524).

[0117] The first transistor 502 and the second transistor 504 form a first current mirror 526. The first current mirror 526 senses the read current (I SENSE ). The third transistor 506 and the fourth transistor 508 form a second current mirror 528, and the second current mirror 528 mirrors the mirror current provided by the first current mirror 526. The second current mirror 528 provides a read current (I SENSE The first current mirror 526 and the second current mirror 528 read out the current (I SENSE ) is changed from flowing into the reference cell array 202 to flowing into the first node 530. The gates of the tenth transistor 520 and the eleventh transistor 522 are connected to the first node 530.

[0118] The fifth transistor 510 and the seventh transistor 514 form a third current mirror, which generates a reference current (I REF ) is mirrored. The third current mirror provides a reference current (I REF ). A first terminal of the capacitor 524 is connected to a supply voltage (VDD), and a second terminal of the capacitor 524 is connected to a first node 530. The capacitor 524 forms a main pole to avoid certain fluctuations in current or voltage at the first node 530.

[0119] At the first node 530, the read current (ISENSE ) and the reference current (I REF ) is compared. For example, if the read current (I SENSE ) is greater than the reference current (I REF ), the first node 530 is pulled down or reduced to the voltage level of the negative voltage generator 208 (e.g., -2*VDD). This causes the negative bias voltage (VSSN) to further decrease, which is due to the voltage of the eleventh transistor 522 following its gate (i.e., the first node 530) to its source connected to the output node 212. When the negative bias voltage (VSSN) is provided to the gates of the plurality of memory cells of the memory cell array 102, the decrease or reduction of the negative bias voltage (VSSN) causes the leakage current (I LEAK ) is reduced. The negative bias voltage (VSSN) can be reduced until the read current (I SENSE ) is equal to or lower than the reference current (I REF )until.

[0120] When the read current (I SENSE ) is lower than the reference current (I REF ), the ninth transistor 518 can draw current into the first node 530. This causes the ninth transistor 518 to find the source of the current in the reference cell array 202 and the memory cell array 102. Therefore, the fifth transistor 510, the sixth transistor 512, the eighth transistor 516, the ninth transistor 518, the tenth transistor 520 and the eleventh transistor 522 together form a push-pull buffer.

[0121] like Figure 5As shown in FIG. 1 , the source of each of the first transistor 502, the second transistor 504, the fifth transistor 510, the seventh transistor 514, and the ninth transistor 518 is connected to the supply voltage (VDD). The drain of each of the third transistor 506, the fourth transistor 508, and the eleventh transistor 522 is connected to the output node of the negative voltage generator 208. The drain and gate of the first transistor 502 are connected to the common bit line (CBL) of the reference cell array 202. The gate of the second transistor 504 is connected to the gate of the first transistor 502. The drain of the second transistor 504 is connected to the source and gate of the third transistor 506. The gate of the fourth transistor 508 is connected to the gate of the third transistor 506. The gate of each of the fifth transistor 510, the sixth transistor 512, and the seventh transistor 514 is connected to the output terminal of the reference current generator 210. The source of the fourth transistor 508 is connected to the first node 530. The drain of the fifth transistor 510 is also connected to the first node 530. In addition, the gate of each of the tenth transistor 520 and the eleventh transistor 522 is also connected to the first node 530. The drain of the sixth transistor 512 is connected to the source and gate of the eighth transistor 516. The drain of the eighth transistor 516 is connected to the source of the tenth transistor 520. The gate of the ninth transistor 518 is connected to the gate of the eighth transistor 516. The drain of the ninth transistor 518 is connected to the source of the eleventh transistor 522. The drain of the seventh transistor is connected to the output terminal of the reference current generator 210.

[0122] It will be apparent to those skilled in the art that each of the first transistor 502, the second transistor 504, the third transistor 506, the fourth transistor 508, the fifth transistor 510, the sixth transistor 512, the seventh transistor 514, the eighth transistor 516, the ninth transistor 518, the tenth transistor 520, and the eleventh transistor 522 is symmetrical (i.e., the source and drain are interchangeable). In an example, each of the first transistor 502, the second transistor 504, the fifth transistor 510, the sixth transistor 512, the seventh transistor 514, the tenth transistor 520, and the eleventh transistor 522 is a PMOS transistor. In addition, each of the third transistor 506, the fourth transistor 508, the eighth transistor 516, and the ninth transistor 518 is an NMOS transistor. However, other types of transistors are also within the scope of the embodiments of the present disclosure.

[0123] Figure 6 According to some embodiments of the present disclosure Figure 2The feedback circuit 200 of the second circuit diagram 600 provides a negative bias voltage (VSSN) to the memory cell array 102 of the memory device 100 to reduce the leakage current (I LEAK ) is limited to the preset value. Figure 6 As shown in FIG. 6 , the second circuit diagram 600 includes the reference cell array 202 , the comparator 602 , the first transistor 604 , the second transistor 606 , the third transistor 608 , the negative voltage generator 208 , and the reference current source 210 . The second transistor 606 and the third transistor 608 form a current mirror 610 .

[0124] The comparator 602 adjusts the voltage of the common bit line (CBL) of the reference cell array 202 to the same voltage as the voltage of the bit line of the memory cell array 102 (i.e., the bit line voltage (VBL)). In the feedback mode or the negative feedback mode, the comparator 602 is connected to the common bit line (CBL) of the reference cell array 202. For example, the first input of the comparator 602 is connected to the common bit line (CBL) of the reference cell array 202 at the first node 612. The second input of the comparator 602 is connected to the bit line voltage (VBL) node. The output of the comparator 602 is connected to the gate of the first transistor 604. The comparator 602 and the first transistor 604 together bias the common bit line (CBL) of the reference cell array 202 to the same voltage as the voltage of the bit line of the memory cell array 102 (i.e., the bit line voltage (VBL)). For example, the comparator 602 compares the voltage received at the first input terminal of the common bit line (CBL) of the reference cell array 202 with the voltage received at the second input terminal of the bit line of the memory cell array 102, and adjusts the voltage of the common bit line (CBL) of the reference cell array 202 to be equal to the voltage of the bit line (VBL) based on the comparison.

[0125] The current mirror 610 senses the read current (I SENSE ) is mirrored and provided to the second node 614. The reference current generator 210 generates a reference current (I REF ) is provided to the second node 614. At the second node 614, the read current (I SENSE ) and the reference current (I REF) is compared, and a pump enable signal (PUMP_EN) is generated based on the comparison. The pump enable signal (PUMP_EN) activates the negative voltage generator 208 to reduce the negative bias voltage (VSSN). For example, if the read current (I SENSE ) is greater than the reference current (I REF ), a pump enable signal (PUMP_EN) is generated to enable the negative voltage generator 208 to reduce the negative bias voltage (VSSN). The reduction of the negative bias voltage (VSSN) suppresses leakage current in the reference cell array 202 and the memory cell array 102.

[0126] The gate of the first transistor 604 is connected to the output terminal of the comparator 602. The drain of the first transistor 604 is connected to the common bit line (CBL) of the reference cell array 202. The source of the first transistor 604 is connected to the drain of the second transistor 606. The gate of the second transistor 606 is connected to its drain and the gate of the third transistor 608. The source of each of the second transistor 606 and the third transistor 608 is connected to the supply voltage (VDD). The drain of the third transistor 608 is connected to the second node 614. Each of the first transistor 604, the second transistor 606 and the third transistor 608 is symmetrical. In addition, each of the first transistor 604, the second transistor 606 and the third transistor 608 is an NMOS transistor. However, other types of transistors are also within the scope of the embodiments of the present disclosure.

[0127] Figure 7 FIG. 7 is an example circuit diagram of a word line voltage generation circuit 700 according to some embodiments of the present disclosure. The word line voltage generation circuit 700 provides a predefined pumped word line voltage (VPP) for a word line of the memory device 100 for read and write operations. The pumped word line voltage is closer to the maximum limit of the word line voltage of the memory device 100 and depends on the leakage current (I LEAK Pumping the word line voltage improves the read and write efficiency of the memory device 100 by providing a better voltage margin between the word line voltage and the bit line voltage for read and write operations.

[0128] As discussed in more detail in the following sections of the present disclosure, the pumped word line voltage (VPP) provided by the word line voltage generation circuit 700 is relative to the negative bias voltage (VSSN) plus the reference current (I REF) is determined by the set voltage level determined by the negative bias voltage (VSSN). In addition, the pumped word line voltage (VPP) is preset at a level higher than the negative bias voltage (VSSN) so that it is as close as possible, but within the tolerance of the maximum allowed word line voltage of the memory device 100. For example, if the word line voltage (VPP) is -0.5 volts, the word line voltage (VPP) can be 1.5 volts (i.e., -0.5+2.0). This increases the voltage margin between the word line voltage and the bit line voltage for read and write operations.

[0129] like Figure 7 As shown in FIG. 1 , the word line voltage generating circuit 700 includes a first transistor 702, a second transistor 704, a first resistor 706, a second resistor 708, a third resistor 710, a fourth resistor 712, a comparator 714, and a charge pump 716. The first transistor 702 and the second transistor 704 form a current mirror 718. The current mirror 718 generates a reference current (I REF ) is mirrored and the mirror reference current (I REF ) is provided to the second node 722.

[0130] The first terminal of the first resistor element 706 is connected to the output node 726, and the second terminal of the first resistor element 706 is connected to the second node 722. The first terminal of the second resistor element 708 is connected to the output node 726, and the second terminal of the second resistor element 708 is connected to the third node 724. The first terminal of the third resistor element 710 is connected to the third node 724, and the second terminal of the third resistor element 710 is connected to the first terminal of the fourth resistor element 712. The second terminal of the fourth resistor element 712 is connected to the first node 720. In an example, the resistance value of each of the first resistor element 706, the second resistor element 708, the third resistor element 710, and the fourth resistor element 712 is the same and is approximately between 100 kilo-ohms and 1 million ohms. However, other values ​​are also possible. In some other examples, the third resistor element 710 and the fourth resistor element 712 can be combined and provided as a single resistor element.

[0131] The first input terminal of the comparator 714 is connected to the second node 722, and the second input terminal of the comparator 714 is connected to the third node 724. The output terminal of the comparator 714 is connected to the charge pump 716. Therefore, the comparator 714 is connected to the charge pump 716 in a feedback mode. That is, the comparator 714 compares the instantaneous voltage of the second node 722 with the instantaneous voltage of the third node 724 and provides an output signal based on the comparison. The output signal from the comparator 714 is provided to the charge pump 716, and the charge pump 716 increases or decreases the pumped word line voltage (VPP) based on the output signal.

[0132] The output signal of the comparator 714 represents the voltage difference between the second node 722 and the third node 724. The instantaneous voltage of the second node 722 can be expressed as:

[0133] VPP-I REF *R

[0134] If the instantaneous voltage of the second node 722 is less than the instantaneous voltage of the third node 724, the charge pump 716 increases the pumped word line voltage (VPP). Conversely, if the instantaneous voltage of the second node 722 is greater than the instantaneous voltage of the third node 724, the charge pump 716 increases the pumped word line voltage (VPP).

[0135] The pumped word line voltage (VPP) can be expressed as:

[0136] VPP=VSSN+3*I REF *R

[0137] Therefore, the pumped word line voltage (VPP) depends on the negative bias voltage (VSSN), the reference current (I REF ) and the resistance values ​​of resistors 706, 708, 710 and 712. The reference current (I REF ) and the resistance values ​​of resistors 706, 708, 710 and 712 are preset to a preset pumped word line voltage (VPP). REF ) becomes temperature dependent, allowing the pumped word line voltage (VPP) to be temperature compensated to optimize reliability requirements. In addition, the pumped word line voltage (VPP) can track PVT variations, thereby reducing the power consumption of the chip due to its dependence on the reference current (I REF ) to achieve constant stress conditions to improve chip yield.

[0138] Figure 8 is a method for limiting the leakage current (I LEAK ) is a flowchart of a method 800. LEAK ) is limited to a preset value to provide a constant frequency for the refresh operation. In some examples, the method 800 is performed by the controller 112 or the processing system. In other examples, the method 800 may be stored as instructions in a storage device accessible by the controller 112 or the processor. The stored instructions may be executed by the controller 112 or the processor to perform the method 800. The storage device for storing instructions may include a non-transitory computer-readable medium.

[0139] At block 810 of method 800, a read current (I SENSE ), which is the leakage current (I LEAK). For example, as referenced above Figures 1 to 7 As discussed, a read current (I SENSE ). Readout current (I SENSE ) is the sum of the drain-source currents of the reference cells in the reference cell array 202. In other words, the read current (I SENSE ) is the current flowing between the common bit line (CBL) and the common source line (CSL) of the reference cell array 202.

[0140] In block 820 of method 800, a reference current (I REF As discussed above, the reference current (I REF ) is generated by the reference current generator 210. For example, the reference current (I REF ). Reference current (I REF ) can be constant and temperature compensated. REF ) defines the leakage current (I LEAK )’s preset limit.

[0141] At block 830 of method 800, the read current (I SENSE ) and the reference current (I REF ). For example, by Figure 3 The comparator 204 of the feedback circuit 200 will sense the current (I SENSE ) and the reference current (I REF ) for comparison. In addition, as mentioned above Figure 5 As discussed, Figure 5 The first node 530 of the first circuit diagram 500 reads the current (I SENSE ) and the reference current (I REF ) for comparison. In addition, as mentioned above Figure 6 As discussed, Figure 6 The second node 614 of the second circuit diagram 600 reads the current (I SENSE ) and the reference current (I REF ) for comparison.

[0142] In block 840 of method 800, an enable signal is generated based on the comparison. For example, if the read current (I SENSE ) is greater than the reference current (I REF ), a pump enable signal (PUMP_EN) is generated. In some examples, the pump enable signal (PUMP_EN) is generated by the gain and compensation block 206.

[0143] In block 850 of method 800, bias voltages applied to a plurality of word lines of memory cell array 102 are adjusted based on the enable signal. For example, the pump enable signal (PUMP_EN) activates negative voltage generator 208 to reduce the negative bias voltage (VSSN). For example, if the read current (I SENSE ) is greater than the reference current (I REF ), a pump enable signal (PUMP_EN) is generated to enable the negative voltage generator 208 to reduce the negative bias voltage (VSSN). The reduction of the negative bias voltage (VSSN) suppresses leakage current in the reference cell array 202 and the memory cell array 102.

[0144] According to an example embodiment, a feedback circuit for limiting leakage current of a memory device includes: a reference cell array operable to generate a read current representing the leakage current of the memory device; a reference current generator operable to generate a reference current having a preset value; a comparator operable to compare the reference current with the read current and provide an enable signal based on the comparison; and a negative voltage generator operable to generate a bias voltage based on the enable signal, wherein the bias voltage is applied to a plurality of word lines of the memory device in a standby mode.

[0145] In some embodiments, a bias voltage is also applied to a common word line of the reference cell array.

[0146] In some embodiments, the bias voltage is a negative voltage and decreases when the read current is greater than the reference current.

[0147] In some embodiments, the reference cell array includes one or more reference cell sub-arrays disposed at one or more locations on the die of the memory device.

[0148] In some embodiments, the read current is a sum of a plurality of drain-source currents of a plurality of reference cells of the reference cell array.

[0149] In some embodiments, multiple word lines of the reference cell array are connected together as a common word line, wherein multiple bit lines of the reference cell array are connected together as a common bit line, and wherein multiple source lines of the reference cell array are connected together as a common source line.

[0150] In some embodiments, the negative voltage generator is a charge pump.

[0151] In an example embodiment of the present disclosure, a memory device includes a memory cell array and a first feedback circuit, the memory cell array including a matrix of multiple rows and multiple columns, wherein each of the multiple rows includes a multiple first memory cells connected to a word line of a multiple word lines, and wherein each of the multiple columns includes a multiple second memory cells connected to a bit line of a multiple bit lines, the first feedback circuit is operable to provide a bias voltage to the multiple word lines during a standby mode, wherein the feedback circuit limits a leakage current of the memory cell array to a preset value.

[0152] In some embodiments, the first feedback circuit includes a reference cell array, a reference current generator, a comparator, and a negative voltage generator. The reference cell array is operable to generate a read current representing a leakage current of the memory device. The reference current generator is operable to generate a reference current having a preset value. The comparator is operable to compare the reference current with the read current and provide an enable signal based on the comparison. The negative voltage generator is operable to generate a bias voltage based on the enable signal, wherein the bias voltage is applied to these word lines of the memory device in the standby mode.

[0153] In some embodiments, the negative voltage generator is a charge pump.

[0154] In some embodiments, a plurality of word lines of the reference cell array are connected together as a common word line, wherein a plurality of bit lines of the reference cell array are connected together as a common bit line, and wherein a plurality of source lines of the reference cell array are connected together as a common source line.

[0155] In some embodiments, the read current is a sum of a plurality of drain-source currents of a plurality of reference cells of the reference cell array.

[0156] In some embodiments, the memory device further comprises a second feedback circuit, wherein the second feedback circuit is operable to provide a pumped word line voltage to one of the word lines of the memory device for a read operation or a write operation.

[0157] In some embodiments, the pumped word line voltage is relative to the bias voltage plus a set voltage level.

[0158] According to an example embodiment, a method of limiting leakage current of a memory device includes the steps of generating a read current that is representative of leakage current of a memory cell array of the memory device; generating a reference current having a preset value; comparing the read current with the reference current; generating an enable signal based on the comparison; and adjusting bias voltages applied to a plurality of word lines of the memory cell array based on the enable signal.

[0159] In some embodiments, the step of generating a readout current includes the step of generating a readout current via a reference cell array.

[0160] In some embodiments, the step of adjusting the bias voltage includes the step of decreasing the bias voltage in response to receiving the enable signal.

[0161] In some embodiments, the step of generating an enable signal includes the step of generating an enable signal when the read current is greater than a reference current.

[0162] In some embodiments, adjusting the bias voltage applied to the plurality of word lines of the memory cell array based on the enable signal includes the following steps: reducing the bias voltage in response to receiving the enable signal.

[0163] In some embodiments, the bias voltage is a negative bias voltage.

[0164] The present disclosure summarizes various embodiments so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A feedback circuit, characterized in that: include: a reference cell array operable to generate a read current representative of a leakage current of a memory device; a reference current generator operable to generate a reference current having a preset value; a comparator operable to compare the reference current with the sense current and provide an enable signal based on the comparison; and A negative voltage generator is operable to generate a bias voltage based on the enable signal, wherein the bias voltage is applied to a plurality of word lines of the memory device in a standby mode.

2. The feedback circuit according to claim 1, characterized in that: The bias voltage is a negative voltage and decreases when the read current is greater than the reference current.

3. The feedback circuit according to claim 1, characterized in that The reference cell array includes one or more reference cell sub-arrays disposed at one or more locations on a die of the memory device.

4. The feedback circuit according to claim 1, wherein: The readout current is a sum of drain-source currents of a plurality of reference cells in the reference cell array.

5. A memory device, characterized in that: include: A memory cell array comprising a matrix of a plurality of rows and a plurality of columns, wherein each of the plurality of rows comprises a plurality of first memory cells connected to a word line of a plurality of word lines, and wherein each of the plurality of columns comprises a plurality of second memory cells connected to a bit line of a plurality of bit lines; and A first feedback circuit is operable to provide a bias voltage to the word lines during a standby mode, wherein the feedback circuit limits a leakage current of the memory cell array to a predetermined value.

6. The memory device according to claim 5, wherein: The first feedback circuit comprises: a reference cell array operable to generate a read current representative of the leakage current of the memory device; a reference current generator operable to generate a reference current having a preset value; a comparator operable to compare the reference current with the sense current and provide an enable signal based on the comparison; and A negative voltage generator is operable to generate a bias voltage based on the enable signal, wherein the bias voltage is applied to the plurality of word lines of the memory device in a standby mode.

7. The memory device according to claim 6, wherein: The negative voltage generator is a charge pump.

8. The memory device according to claim 6, wherein: The multiple word lines of the reference cell array are connected together as a common word line, the multiple bit lines of the reference cell array are connected together as a common bit line, and the multiple source lines of the reference cell array are connected together as a common source line.

9. The memory device according to claim 5, wherein: further comprising a second feedback circuit, wherein the second feedback circuit is operable to provide a pumped word line voltage to one of the plurality of word lines of the memory device for a read operation or a write operation, The pumped word line voltage is a voltage obtained by adding a set voltage level to the bias voltage.

10. A method for operating a memory device, characterized in that: The following steps are involved: generating a read current that is representative of a leakage current of a memory cell array of a memory device; generating a reference current having a preset value; comparing the read current with the reference current; generating an enable signal based on the comparison; and A bias voltage applied to a plurality of word lines of the memory cell array is adjusted based on the enable signal.

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