Electronic device and testing method thereof

Abstract

The invention provides an electronic device and a testing method thereof, including a method of providing one or more signals to the electronic device to execute a test program involving programming a one-time programmable (OTP) memory in the electronic device. Whether the connection of one or more signals to the electronic device is stable is verified by executing a series of one or more iteration programs, each iteration including (i) performing from a set of temporarily stored addresses in the OTP memory, determining an address available for programming, (ii) writing a test value to the address, and then (iii) reading the test value from the address. If the read test value differs from the written test value, retuning of the one or more signal connections is initiated. Only when the connection is verified to be stable through a series of iterative programs, the OTP memory is programmed according to the test program.

Description

Technical Field

[0001] The present invention relates to an electronic device, and in particular to a programming method and system for a one-time programmable (OTP) memory. Background Art

[0002] An electronic device may include a one-time programmable (OTP) memory for storing various device parameters. The parameters stored in the OTP memory may include, for example, the life cycle (LC) state of the device. Since programming of the OTP memory is irreversible, the programming procedure should be highly reliable. Summary of the invention

[0003] Embodiments of the present invention described herein provide a method for testing an electronic device. The method includes providing one or more signals to the electronic device by a test system for executing a test program, which involves programming a one-time programmable (OTP) memory in the electronic device. Whether the connection between one or more signals and the electronic device is stable is verified by performing a series of one or more iterations, each iteration including (i) determining an address that can be used for programming from a set of temporary addresses in the OTP memory, (ii) writing a test value to the address, and then (iii) reading the test value from the address. If the test value read is different from the test value written, re-tuning of one or more signal connections is initiated. Only when the connection is verified to be stable through the series of iterations, the OTP memory of the electronic device is programmed according to the test program.

[0004] In some embodiments, the test method further includes outputting a fault indication when it is found that all temporary addresses have been programmed but the connection is unstable. In an embodiment, the one or more signals include a clock signal for timing at least a portion of the electronic device. Or or more, the one or more signals include a power supply signal for powering at least a portion of the electronic device.

[0005] In a disclosed embodiment, programming the OTP memory includes updating a life cycle (LC) state of the electronic device according to a test procedure. In an exemplary embodiment, determining an address available for programming includes scanning a temporary address of the OTP memory for an address holding an all-zeros value. In an alternative embodiment, determining an address available for programming includes maintaining the state of the OTP memory in a memory different from the OTP memory.

[0006] According to the embodiments described herein, a method for testing an electronic device is further provided. The method includes, in an electronic device including a one-time programmable (OTP) memory, receiving one or more signals from a test system for executing a test program involving programming of the OTP memory. Verifying whether the connection between the one or more signals and the electronic device is stable by (i) determining an address that can be used for programming from a set of temporary addresses in the OTP memory, (ii) writing a test value to the address, (iii) reading the test value from the address, and (iv) verifying whether the read test value is equal to the written test value. If the connection is verified to be stable, the OTP memory of the electronic device is programmed according to the test program. If it is determined that the connection is unstable, a fault indication is output.

[0007] According to the embodiments described herein, there is also provided an electronic device including a one-time programmable (OTP) memory and control hardware. The control hardware is configured to receive one or more signals from a test system for executing a test program involving programming of the OTP memory, and verify whether the connection between the one or more signals and the electronic device is stable by: determining an address that can be used for programming from a set of temporary addresses in the OTP memory, (ii) writing a test value to the address, (iii) reading the test value from the address, and (iv) verifying whether the read test value is equal to the written test value. The control hardware is configured to program the OTP memory according to the test program if the connection is verified to be stable, and output a fault indication if it is determined that the connection is unstable.

[0008] The present invention will be more fully understood through the detailed description of the embodiments of the present invention in conjunction with the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a system for testing an electronic device, including reliable programming of an OTP memory, according to an embodiment of the present invention;

[0010] Figure 2 is a schematic flow chart of a method for reliably programming an OTP memory during testing according to an embodiment of the present invention.

[0011] Reference numerals:

[0012] 20: Test system

[0013] 22: Chip

[0014] 24: Electronic devices

[0015] 28: Control Hardware

[0016] 32: Memory

[0017] 36:OTP memory

[0018] 40:LC Zone

[0019] 44: Probe Machine

[0020] 46: Tester

[0021] 48: Computer

[0022] 52: Operator

[0023] 54:Test Head

[0024] 56: Test substrate

[0025] 60: Spring ring

[0026] 64:Probe Card

[0027] 68: Probe

[0028] 72: Temporary storage area

[0029] 80,84,88,92,96,100,104,108: Operation DETAILED DESCRIPTION

[0030] Various electronic devices use one-time programming (OTP) memory to store device parameters. For example, the serial number or calibration parameters of some devices are usually only programmed once, while other parameters, such as the device's life cycle (LC) status, can be updated during the life cycle. When a parameter is updated or needs to be reprogrammed due to programming failure, the original OTP address can no longer be used. Failure to program the OTP may eventually render the device unusable, so OTP memory is a sensitive device that needs to be used with caution.

[0031] Special problems occur when the electronic device receives external signals, such as power and / or clock signals from a test system, so that the OTP memory is programmed. For example, a chip-level test system that tests electronic devices manufactured on a chip may use needles contacting pads to supply power and / or clock signals to the device. Any instability in the electrical connection to the device and / or the connection between the internal components of the probe may cause instability in the power and / or clock signals, thereby causing OTP programming failure.

[0032] This problem is exacerbated by the fact that line operators typically start the test process with the probe at a relatively weak connection and try to improve incrementally to avoid damaging the device. This trial-and-error process increases the likelihood of OTP programming failure, which greatly shortens the life of the device.

[0033] Embodiments of the present invention as described herein provide methods and systems for reliable programming of OTP memories. The techniques disclosed herein may be used in the context of a test system, or more generally, when providing signals to a device being programmed over a potentially unstable connection.

[0034] In certain disclosed embodiments, a pre-programmed connectivity test is used to test the stability of the electrical connection to the device before programming the OTP memory with the actual device parameters. The pre-programmed connectivity test (referred to herein as a "connectivity test" or "test" for brevity) utilizes a set of addresses assigned in the OTP memory, namely "scratchpad addresses".

[0035] In the example flow, the operator establishes electrical connections between the test system and one or more devices (usually multiple devices in parallel) and starts the test program. After receiving a signal indicating the start of the test, each device scans the temporary address of its OTP memory to find an address that can be used for programming. The device writes a test value to the address and then reads the test value from the address.

[0036] If the programming of the test value is successful, i.e. the test value read is equal to the test value written, the connection is considered stable and the test procedure continues, which includes programming the OTP memory with the applicable LC state. If the programming of the test value fails, i.e. the test value read is different from the test value written, the connection is considered unstable and the device outputs a fault indication. In response to this fault indication, the operator will readjust the connection to try to improve its stability and restart the test procedure.

[0037] The above iterative process can continue until the electrical connection to the device becomes stable and the LC state is successfully programmed. If all the temporary addresses have been written before the connection is stable, the iterative process may fail. In this case, the device usually outputs a fatal failure indication. In a typical implementation, a sufficient number of temporary addresses are allocated to support the number of LC updates expected during the life cycle of the device.

[0038] In alternative embodiments, the disclosed "tests" may be implemented using a different "division-of-labor" between the test system and the device under test. For example, more test logic may be implemented on the test system side.

[0039] The techniques described herein ensure that critical information (e.g., LC state or other device parameters) is programmed into the OTP memory only when the connection of the external signal to the device is stable. Thus, the disclosed techniques enhance the reliability of OTP programming and improve the reliability and yield of the entire device production process.

[0040] System Description

[0041] Figure 1 2 is a schematic diagram of a test system 20 according to an embodiment of the present invention, wherein the test system 20 is used to test a chip 22 having an electronic device 24 thereon. The electronic device 24 may include, for example, a non-volatile memory (NVM) device, a microcontroller, or any other suitable electronic device. The electronic device 24 is also referred to herein as a "device under test" (DUTs).

[0042] Figure 1 The inset in the lower right corner shows a simplified internal structure of an electronic device 24 according to an exemplary embodiment. As shown, the electronic device 24 includes control hardware (HW) 28, memory 32 (which may be volatile or non-volatile), and OTP memory 36. The control hardware 28 is responsible for programming the OTP memory 36 using the techniques described herein.

[0043] The OTP memory 36 is used to store various parameters of the electronic device 24. At least some of the information stored in the OTP memory 36 is considered critical and should be programmed with very high reliability. The following description mainly uses the LC state of the electronic device 24 as an example of such critical information. However, this choice is purely for clarity, and the technology disclosed herein can be applied in a similar manner to any other suitable information (critical information or other information) stored in the OTP memory 36.

[0044] exist Figure 1 In an exemplary embodiment, the LC area 40 is allocated in the OTP memory for storing the current LC state of the electronic device. Examples of LC states include "preset", "test", "development", "operational", "return merchandise authorization (RMA)", etc. For operational and security reasons, the LC state is an extremely sensitive parameter, and an error or difference in the LC state may render the device unusable or convert the device to an illegal state.

[0045] The LC state of a given electronic device 24 may change several times during the life cycle of the device, for example, during production testing before shipment, or even when transferred between different stations during production and testing. To allow for multiple updates of the LC state, the LC region 40 contains multiple addresses. The size of the LC region 40 is typically selected to allow for a sufficient number of updates to the LC state during the life cycle of the device.

[0046] exist Figure 1 In the embodiment of the present invention, the test system 20 includes a tester 46 connected to a prober 44, and the tester 46 and the prober 44 are controlled by a computer 48 operated by an operator 52. The chip 22 is installed in the prober 44 for executing a test program. The prober 44 includes a test head 54, a test substrate (load board) 56, a spring ring (pogo ring) 60 and a probe card 64. A plurality of probes 68 extend from the probe card 64 to the chip 22. In some applicable test programs, the plurality of probes 68 are configured to make electrical contact with selected pads of the electronic device 24. For example, the probes 68 can be used to provide power signals and clock signals to the electronic device 24, and to inject test signals into and extract test signals from the electronic device 24. Typically, the prober 44 tests a group of electronic devices 24 at a time, and one electronic device 24 is usually connected by a plurality of probes 68.

[0047] In practice, the quality of the electrical connection between the probe machine 44 and the electronic device 24 may vary. In this example, the connection between (i) the test head 54 and the test substrate 56, (ii) the connection between the test substrate 56 and the spring ring 60, and (iii) the connection between the spring ring 60 and the probe card 64 all contain springs (pogos), i.e., spring-loaded contacts, which may cause problems with the stability of the electrical connection. Problems with the stability of the electrical connection may also occur between the probe 68 and the electronic device 24. In this context, phrases such as "connection between the probe machine and the electronic device" and "stability of the connection" expressed in various grammatical terms refer to the above-mentioned various connections, as well as any other related connections between the components of the probe machine 44 in the test system 20, or between the probe machine 44 and the electronic device 24.

[0048] Conventionally, the operator 52 typically begins the test procedure by setting a relatively weak connection between the probe 68 and the electronic device 24 to minimize the risk of damaging the device. If the initial connection is not stable enough, the operator 52 typically makes one or more attempts to improve it until a good enough connection is achieved for conducting the test procedure.

[0049] The above trial-and-error set-up process is problematic if the test procedure involves updating critical information, such as LC status. If the LC status is updated at the same time as each attempt to reposition the probe 68, erroneous data may be written into the OTP memory. For example, erroneous programming of the LC status may irreversibly lock up the electronic device or render it unusable.

[0050] Therefore, in some embodiments, the test system 20 performs a pre-programming connectivity test (hereinafter referred to as a "test"), which can verify the stability of the electrical connection between the probe 68 and the electronic device 24. Generally speaking, only when the test is successfully completed, the real information (e.g., LC state) in the OTP memory 36 is allowed to be programmed, that is, the electronic device is considered ready for OTP programming.

[0051] The disclosed test uses a set of addresses allocated in the OTP memory 36, referred to as a scratchpad region 72. The scratchpad region 72 may be contiguous or non-contiguous. In an exemplary embodiment, the scratchpad region 72 includes 32 addresses, allowing 32 programming attempts, each address storing a 16-bit word. In some embodiments, although not necessary, for convenience, the scratchpad region 72 is located at the beginning of the OTP memory 36, i.e., at offset 0. When accessing the scratchpad region 72, the built-in self-test (BIST) and error correction coding (ECC) are disabled. The pre-programmed connection test and the use of the scratchpad region 72 are described in detail below.

[0052] like Figure 1 The configuration of the test system 20 and the electronic device 24 shown is an example configuration selected purely for the purpose of clarifying the concept. Any other suitable configuration may be used in alternative embodiments. For example, the probe machine 44 may be any other suitable contact for contacting the electronic device 24, not necessarily a probe. As an example, Figure 1 The configuration involves chip-level wafer probe (CP) testing. In an alternative embodiment, the disclosed technology can be used for final testing (FT) of packaged devices. In FT implementation, the electronic device 24 is a packaged device, and the electrical connection being verified includes the connection between the probe machine 44 and the selected pins of the packaged device.

[0053] The various elements of the test system 20 and the electronic device 24 may be implemented using any suitable hardware, such as in one or more application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs), using software, or a combination of software and hardware. In some embodiments, the computer 48 includes one or more general purpose processors that are programmed with software to perform the functions described herein. For example, the software may be downloaded to any processor in electronic form over a network, or may alternatively or additionally be provided and / or stored on non-transitory tangible media, such as magnetic, optical, or electronic memory.

[0054] Reliable programming of OTP memory during testing

[0055] For various reasons, in some test procedures, the probe machine 44 provides one or more power signals and / or one or more clock signals to the electronic device 24 during the test. For example, some tests require a clock signal with higher accuracy than the internal clock of the electronic device 24. In another example, some tests require a high power supply voltage that the internal power supply circuit of the electronic device 24 cannot generate. In a non-limiting example, the test must be performed at an elevated temperature, at which the internal power supply of the device cannot generate the required voltage level.

[0056] It is understood that it is very dangerous to program the OTP memory 36 with actual device parameters (e.g., LC state) when the electronic device 24 is powered and / or clocked externally. Therefore, in some embodiments, the control hardware 28 of the electronic device 24 performs a pre-programming connectivity test (hereinafter referred to as "test") before programming the OTP memory 36 with actual device parameters.

[0057] Figure 2 8 is a schematic flow chart of a method for reliably programming the OTP memory 36 of the electronic device 24 during testing according to an embodiment of the present invention. The method begins with an operation (tuning phase) 80, in which the operator 52 tunes the contacts for transmitting signals between the probe machine 44 and the electronic device 24. After tuning the contacts, the operator 52 initiates the test by issuing a "start" command.

[0058] In response to the "start" command, in a given electronic device 24, the control hardware 28 determines the next address in the temporary storage area 72 that can be used for programming during operation (free address selection phase) 84. In the exemplary embodiment, the control hardware 28 determines the next available address by sequentially scanning the temporary storage area 72. For each scanned address, the control hardware 28 reads the address and checks whether the read value is an all-zeros word. If so, the address is considered available for programming; if not, the address is considered to have been used, and the control hardware 28 advances to the next address in the temporary storage area 72.

[0059] After finding the next available address in the temporary storage area 72, the control hardware 28 writes the test value to the address in operation (test value programming phase) 88. In the exemplary embodiment, the test value is an all-ones word, or any other suitable test value can be used. However, the more bits set, the more reliable the connection can be. In operation (test value reading phase) 92, the control hardware 28 reads the address just programmed.

[0060] At operation (test value checking phase) 96, the control hardware 28 checks whether the read value is indeed an all-one word (or more broadly, whether the test value read at operation (test value reading phase) 92 is equal to the test value programmed at operation (test value programming phase) 88).

[0061] If the read test value is equal to the written test value (all ones in this example), the connection to the electronic device 24 is considered stable and the method stops at operation (successful termination phase) 100. The control hardware 28 (and the test system 20 as a whole) continues to execute the test procedure, including programming the appropriate LC state in the LC area 40 of the OTP memory 36.

[0062] On the other hand, if operation (test value check phase) 96 shows that the test value read is different from the test value written (all 1s in this example), the control hardware 28 considers the test to have failed. At operation (availability check phase) 104, the control hardware 28 checks whether there are any remaining free addresses in the temporary storage area 72, that is, addresses that can be used for programming. If there are no remaining free addresses in the temporary storage area 72, the method stops at operation (failure termination phase) 108. In this case, the control hardware 28 will usually output a serious error indication, signaling to the probe machine 44 that the electronic device 24 has an irrecoverable failure.

[0063] If operation (availability check phase) 104 indicates that there are one or more free addresses remaining in the buffer area 72, the control hardware 28 will typically output a failure indication to notify the probe machine 44 that the test has failed. However, this failure is not a serious failure, but is used to indicate that the operator 52 needs to re-tune the joints, after which the method loops back to operation (tuning phase) 80, and the operator 52 re-tunes the joints that transmit signals to the electronic device 24.

[0064] In the above example, the pre-programmed connectivity test is performed by the control hardware 28 in the electronic device 24 as part of the test procedure. In this implementation, the probe machine 44 and the operator 52 are not necessarily aware that the pre-programmed connectivity test is being performed. From the perspective of the probe machine 44 and the operator 52, the electronic device 24 is instructed to perform the test and report a pass / fail result. The failure result does not necessarily indicate a failure of the test itself or a failure of the pre-programmed connectivity test. In alternative embodiments, any other suitable implementation may be used.

[0065] above Figure 2 The process is an example process described purely for clarifying the concept. In alternative embodiments, the disclosed technology may be performed using any other suitable process.

[0066] For example, in an alternative embodiment, the state of OTP memory 36 is maintained in a memory different from OTP memory 36. For example, instead of scanning scratch pad 72 for the next available address, control hardware 28 may record the identity of the next available address in some memory other than OTP memory 36 (e.g., memory 32). During operation (free address selection phase) 84, control hardware 28 typically reads the value from the address to verify that it is indeed all zeros before proceeding to operation (test value programming phase) 88. After completing operation (test value programming phase) 88, control hardware 28 increments the identity of the next available address.

[0067] In one embodiment, the probe machine issues a command to start the test and reads the result by writing and reading one or more Joint Test Access Group (JTAG) registers of the electronic device 24. In alternative embodiments, any other suitable implementation may be used.

[0068] Generally speaking, measures should be taken to prevent other (hardware or software) entities from accessing the OTP memory 36 during testing.

[0069] Although the embodiments described herein primarily address programming applications involving OTP memories, the methods and systems described herein may also be employed in other applications, for example, in other systems and scenarios where it is desirable to avoid retesting.

[0070] It is therefore understood that the above embodiments are cited by way of example, and the present invention is not limited to what has been specifically shown and described above. On the contrary, the scope of the present invention includes combinations and sub-combinations of the various features described above, as well as changes and modifications that would occur to those skilled in the art after reading the foregoing description and that are not disclosed herein. The documents incorporated by reference into this patent application should be considered as an integral part of this application, unless any term is defined in these incorporated documents in a manner that conflicts with the explicit or implicit definition in this specification, then only the definition in this specification should be considered.

Claims

1. A method for testing an electronic device, characterized in that: include: Providing one or more signals to an electronic device through a test system to execute a test procedure involving programming of a one-time programmable (OTP) memory in the electronic device; Verifying whether the connection between the one or more signals and the electronic device is stable by performing one or more iterations, wherein each of the one or more iterations comprises: Determining an address available for programming from a set of temporary addresses in the OTP memory; writing a test value to the address and then reading the test value from the address; and retuning the connections to the one or more signals if the test value read is different from the test value written; and Only when the connection is verified to be stable through the one or more iterations, the OTP memory of the electronic device is programmed according to the test procedure.

2. The electronic device testing method according to claim 1, wherein: Also includes: When all temporary addresses in the group of temporary addresses have been programmed but the connection is unstable, a failure indication is output.

3. The electronic device testing method according to claim 1, wherein: The one or more signals include a clock signal that clocks at least a portion of the electronic device.

4. The electronic device testing method according to claim 1, wherein: The one or more signals include a power supply signal for powering at least a portion of the electronic device.

5. The electronic device testing method according to claim 1, wherein: The operation of programming the OTP memory includes updating the life cycle LC status of the electronic device according to the test program.

6. The electronic device testing method according to claim 1, wherein: The operation of determining the address available for programming includes scanning the set of temporary addresses of the OTP memory for an address holding an all-zero value.

7. The electronic device testing method according to claim 1, wherein: The operation of determining the address available for programming includes maintaining the state of the OTP memory in a memory different from the OTP memory.

8. A method for testing an electronic device, characterized in that: The test method includes: In an electronic device including a one-time programmable (OTP) memory, receiving one or more signals from a test system for executing a test procedure involving programming of the OTP memory; Verifying whether the connection between the one or more signals and the electronic device is stable through multiple operations, each of the multiple operations comprising: Determining an address available for programming from a set of temporary addresses in the OTP memory; writing a test value to the address, reading the test value from the address, and verifying whether the read test value is equal to the written test value; and If the connection is verified to be stable, programming the OTP memory of the electronic device according to the test procedure; and If the connection is determined to be unstable, a failure indication is output.

9. The electronic device testing method according to claim 8, wherein: The method further includes outputting a serious fault indication when all temporary addresses of the group of temporary addresses have been programmed but the connection is unstable.

10. The electronic device testing method according to claim 8, wherein: The one or more signals include a clock signal that clocks at least a portion of the electronic device.

11. The electronic device testing method according to claim 8, wherein: The one or more signals include a power supply signal for powering at least a portion of the electronic device.

12. The electronic device testing method according to claim 8, wherein: The operation of programming the OTP memory includes updating the life cycle LC status of the electronic device according to the test program.

13. The electronic device testing method according to claim 8, wherein: The operation of determining the address available for programming includes scanning the set of temporary addresses of the OTP memory for an address holding an all-zero value.

14. An electronic device, characterized in that: include: A one-time programmable OTP memory; as well as A control hardware, configured with: receiving one or more signals from a test system for executing a test procedure involving the OTP memory code; Verify whether the connection between the one or more signals and the electronic device is stable by multiple operations, each of the multiple operations comprising: Determining an address available for programming from a set of temporary addresses in the OTP memory; Writing a test value to the address, reading the test value from the address, and verifying whether the read test value is equal to the written test value; If the connection is verified to be stable, programming the OTP memory according to the test procedure; and If the connection is determined to be unstable, a failure indication is output.

15. The electronic device according to claim 14, wherein: The control hardware is also used to output a serious fault indication when all the temporary addresses of the group have been programmed but the connection is unstable.

16. The electronic device as claimed in claim 14, characterized in that: The one or more signals include a clock signal that clocks at least a portion of the electronic device.

17. The electronic device as claimed in claim 14, wherein: The one or more signals include a power supply signal for powering at least a portion of the electronic device.

18. The electronic device as claimed in claim 14, wherein: When programming the OTP memory, the control hardware is configured to update the life cycle LC status of the electronic device according to the test program.

19. The electronic device as claimed in claim 14, wherein: The control hardware is configured to determine an address available for programming by scanning the set of temporary addresses of the OTP memory for an address holding an all-zero value.

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