Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present disclosure relates to a method for manufacturing a semiconductor structure and a semiconductor structure, and relates to the field of integrated circuit technology. The manufacturing method includes: providing a target layer, forming a mask layer on the target layer, and patterning the mask layer to form a mask pattern; etching the target layer according to the mask pattern, forming a first groove in the target layer, and the sidewall of the first groove has a first tilt angle; performing the following steps at least once: etching the sidewall of the mask pattern, increasing the size of the mask pattern, and etching the target layer according to the etched mask pattern; etching the first groove into a target groove, and the sidewall of the target groove has a target tilt angle, the target tilt angle is less than the first tilt angle, and the target tilt angle is less than 30°. The present disclosure does not require cumbersome exposure and etching steps, simplifies the manufacturing process, reduces the difficulty of manufacturing, and saves manufacturing costs.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the field of semiconductor technology, especially in the manufacturing process of optoelectronic devices, low-angle tilted mesas are a challenging task. The angle of the tilted mesas made by traditional methods is relatively high, which cannot meet the needs of low-angle tilted mesas. In addition, the traditional method of making tilted mesas requires multiple exposure and development steps, which is complicated and has high production costs. Summary of the invention

[0003] Based on this, it is necessary to provide a method for manufacturing a semiconductor structure and a semiconductor structure to address the problems of difficulty, complex process and high manufacturing cost in the prior art of manufacturing a low-angle inclined table.

[0004] In a first aspect, the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0005] Providing a target layer, forming a mask layer on the target layer, and patterning the mask layer to form a mask pattern;

[0006] Etching the target layer according to the mask pattern to form a first trench in the target layer, wherein a sidewall of the first trench has a first inclination angle;

[0007] Perform the following steps at least once: etching the sidewalls of the mask pattern to increase the size of the mask pattern, and etching the target layer according to the etched mask pattern; etching the first groove into a target groove, the sidewalls of the target groove having a target inclination angle, the target inclination angle being less than the first inclination angle, and the target inclination angle being less than 30°.

[0008] Optionally, the mask layer is dry-etched using a first gas to form the mask pattern, and the target layer exposed by the mask pattern is continuously etched using the first gas to form the first groove.

[0009] Optionally, the first gas includes a fluorine-based gas and an oxidizing gas.

[0010] Optionally, a second gas is used to dry-etch the sidewall of the mask pattern to increase the size of the mask pattern, and the second gas includes at least one of O2, O3, N2, and N2H2.

[0011] Optionally, a third gas is used to etch the target layer according to the etched mask pattern, and the third gas includes a fluorine-based gas and an oxidizing gas.

[0012] Optionally, the manufacturing method comprises:

[0013] Providing a target layer, forming the mask layer on the target layer, and patterning the mask layer to form a first mask pattern;

[0014] Etching the target layer according to the first mask pattern to form the first trench in the target layer, wherein the sidewall of the first trench has the first inclination angle, and the first inclination angle is greater than 60°;

[0015] Etching the sidewall of the first mask pattern to increase the size of the first mask pattern to form a second mask pattern;

[0016] The target layer is etched according to the second mask pattern to etch the first groove into a second groove, the sidewall of the second groove has a second inclination angle, the second inclination angle is smaller than the first inclination angle, and the second inclination angle is smaller than 30°.

[0017] Optionally, the manufacturing method comprises:

[0018] Etching the sidewall of the second mask pattern to increase the size of the second mask pattern to form a third mask pattern;

[0019] The target layer is etched according to the third mask pattern to etch the second groove into a third groove, the sidewall of the third groove has a third inclination angle, the third inclination angle is smaller than the second inclination angle, and the third inclination angle is smaller than 20°.

[0020] Optionally, the manufacturing method comprises:

[0021] Etching the sidewall of the third mask pattern to increase the size of the third mask pattern to form a fourth mask pattern;

[0022] The target layer is etched according to the fourth mask pattern to etch the third groove into a fourth groove, the sidewall of the fourth groove has a fourth inclination angle, the fourth inclination angle is smaller than the third inclination angle, and the fourth inclination angle is 5-10°.

[0023] Optionally, the ratio of the depth of the first groove to the thickness of the target layer is 1:2-1:3.

[0024] In a second aspect, the present disclosure provides a semiconductor structure manufactured using the method for manufacturing the semiconductor structure as described in the first aspect.

[0025] The manufacturing method and semiconductor structure of the semiconductor structure disclosed in the present invention execute the step of patterning a mask layer once to form a mask pattern, etch a target layer according to the mask pattern to form a first groove whose side wall has a first inclination angle, then increase the size of the mask pattern by etching, and then etch the target layer with the etched mask pattern to reduce the inclination angle of the side wall of the groove, thereby forming a target groove with a side wall inclination angle less than 30°, thereby realizing the production of a slope with a small inclination angle, without the need for complicated exposure and etching steps, simplifying the production process, reducing the production difficulty, and saving the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 is a process flow chart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0028] Figure 2 A schematic diagram of a structure after a mask layer is formed on a target layer and the mask layer is patterned to form a mask pattern provided in an embodiment;

[0029] Figure 3 A schematic diagram of a structure after a target layer is etched according to a mask pattern and a first groove is formed in the target layer provided in an embodiment;

[0030] Figure 4 A schematic diagram of the structure of the sidewall of the etching mask pattern provided in one embodiment after the size of the mask pattern is increased;

[0031] Figure 5 A schematic diagram of a structure after etching a target layer according to an etched mask pattern and etching a first groove into a target groove provided in an embodiment;

[0032] Figure 6 A schematic diagram of a structure after etching the sidewall of a first mask pattern to form a second mask pattern provided in an embodiment;

[0033] Figure 7 A schematic diagram of a structure after etching the target layer according to the second mask pattern and etching the first trench into the second trench provided in an embodiment;

[0034] Figure 8 A schematic diagram of a structure after etching the sidewall of the second mask pattern to form a third mask pattern provided in an embodiment;

[0035] Fig. 9 A schematic diagram of a structure after etching the target layer according to a third mask pattern and etching the second trench into a third trench provided in an embodiment;

[0036] Fig.10 A schematic diagram of a structure after etching the sidewall of the third mask pattern to form a fourth mask pattern provided in an embodiment;

[0037] Fig.11 A schematic diagram of a structure after etching the target layer according to a fourth mask pattern and etching the third trench into a fourth trench provided in an embodiment;

[0038] Fig.12 A schematic diagram of a structure after etching a substrate according to a patterned target layer provided in an embodiment;

[0039] Fig.13 It is a schematic diagram of a structure after a doped substrate is doped using a patterned target layer as a barrier layer to form a doped region provided in an embodiment.

[0040] Description of reference numerals:

[0041] 10. Target layer; 20. Mask layer; 130. First mask pattern; 230. Second mask pattern; 330. Third mask pattern; 430. Fourth mask pattern; 141. First groove; 241. Second groove; 341. Third groove; 441. Fourth groove; 50. Substrate; 51. Doped region; α1. First tilt angle; α2. Second tilt angle; α3. Third tilt angle; α4. Fourth tilt angle. DETAILED DESCRIPTION

[0042] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0044] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0045] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0046] The inventors of the present application have discovered that in the related art, photoresist reflow is used to produce low-angle photoresist, and pattern transfer is performed based on the low-angle photoresist to form a low-angle table in the target layer. However, the effective photoresist angle obtained by the photoresist reflow method is also limited (usually between 40° and 60°), so the angle of the inclined table formed by the final pattern transfer in the target layer is also limited.

[0047] There is also a related technology that forms a low-angle table through a multi-step photolithography + etching method. Although this method can obtain a low-angle inclined table, it requires multiple exposures, significantly increases the number of steps, and is also costly.

[0048] According to an exemplary embodiment, the present disclosure provides a method for manufacturing a semiconductor structure, such as Figure 1 A process flow chart showing a method for manufacturing a semiconductor structure according to this exemplary embodiment is shown. Figure 1 As shown, the method for manufacturing a semiconductor structure comprises the following steps:

[0049] Step S11: providing a target layer 10, forming a mask layer 20 on the target layer 10, and patterning the mask layer 20 to form a mask pattern.

[0050] Step S12: etching the target layer 10 according to the mask pattern to form a first trench 141 in the target layer 10, wherein the sidewall of the first trench 141 has a first inclination angle α1.

[0051] Step S13: Execute the following steps at least once: etch the sidewalls of the mask pattern, increase the size of the mask pattern, and etch the target layer 10 according to the etched mask pattern; etch the first groove 141 into a target groove, the sidewalls of the target groove have a target inclination angle, the target inclination angle is less than the first inclination angle α1, and the target inclination angle is less than 30°.

[0052] The method for manufacturing the semiconductor structure of the present embodiment performs a step of patterning the mask layer 20 once to form a mask pattern, etches the target layer 10 according to the mask pattern to form a first groove 141 whose side wall has a first inclination angle α1, then increases the size of the mask pattern by etching, and then etches the target layer 10 with the etched mask pattern to reduce the inclination angle of the side wall of the groove, thereby forming a target groove with a side wall inclination angle less than 30°, thereby realizing the production of a slope with a small inclination angle, without the need for complicated exposure and etching steps, simplifying the production process, reducing the production difficulty, and saving the production cost.

[0053] Below, the embodiments of the present application are described in detail.

[0054] In step S11, refer to Figure 2 The target layer 10 can be a semiconductor substrate, which is made of semiconductor materials. The semiconductor materials can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials with semiconductor properties, such as III-V group compounds such as gallium arsenide.

[0055] Alternatively, the target layer 10 may be other material layers used to form semiconductor devices, such as a dielectric layer or a metal layer, etc. For example, the target layer 10 may be an amorphous carbon layer, an oxide layer, a nitride layer, a copper layer, a tungsten layer, an aluminum layer, etc., but is not limited thereto.

[0056] The target layer 10 may include one or more stacked semiconductor device layers, and the semiconductor device layers may be formed in a substrate or disposed on a substrate. In each semiconductor device layer, a variety of semiconductor devices and a variety of metal interconnect structures may be disposed. In the semiconductor device layer, the semiconductor device may include at least one of a metal oxide semiconductor field effect transistor, a bipolar junction transistor, a resistor, an inductor, a diode, and an optical device.

[0057] Photoresist may be coated on the target layer 10 and dried to form the mask layer 20. Then, the mask layer 20 is patterned according to a master having a design pattern, and the mask layer 20 is etched according to the master to transfer the design pattern to the mask layer 20 to form a mask pattern.

[0058] In step S12, refer to Figure 3 , the target layer 10 is etched according to the mask pattern. In this embodiment, the target layer 10 is etched by a dry process. By controlling the etching gas and etching parameters, a first groove 141 is formed in the target layer 10. The depth of the first groove 141 is less than the depth of the target layer 10. The projection of the first groove 141 on the plane perpendicular to the target layer 10 is a pattern that is wide at the top and narrow at the bottom. The sidewall of the first groove 141 is an inclined surface. The sidewall of the first groove 141 has a first inclination angle α1, wherein the first inclination angle α1 is the angle formed by the sidewall of the first groove 141 and the plane parallel to the target layer 10.

[0059] It can be understood that the sidewall of the first trench 141 in this embodiment is an inclined surface, which may be an inclined surface of at least one side of the sidewall of the first trench 141 , or multiple sidewalls of the first trench 141 may be inclined surfaces.

[0060] In this embodiment, the critical dimension of the first trench 141 is smaller than the critical dimension of the target trench to be formed. Figure 3As shown, the width of the first trench 141 is smaller than the width of the target trench to be formed.

[0061] In step S13, refer to Figure 4 , the mask pattern is etched using a dry process to expose a portion of the target layer 10 at the periphery of the first trench 141. Figure 5 , the target layer 10 is etched again according to the etched mask pattern, the size of the first trench 141 is increased and the inclination of the sidewall of the trench is reduced. In this embodiment, the steps of etching the mask pattern according to the target inclination and etching the target layer 10 again according to the etched mask pattern are performed one or more times until the first trench 141 is etched into a target trench, and the sidewall of the target trench has a target inclination of less than 30°.

[0062] The manufacturing method of the semiconductor structure of the present embodiment has a simple process. A bevel with a small inclination angle is manufactured through one patterning and two etchings. Only one mask layer 20 is consumed, and only one exposure and development is performed on the mask layer 20. This simplifies the manufacturing process, reduces the number of exposure and etching times, and reduces possible errors and defects, thereby improving the success rate and reliability of manufacturing, improving production efficiency, reducing manufacturing difficulty, and saving manufacturing costs.

[0063] The method for manufacturing the semiconductor structure of the present embodiment can adjust the critical dimensions of the mask pattern formed by the patterned mask layer 20 according to the critical dimensions, target inclination and depth of the target groove, and in the process of etching the target layer 10 for the first time, control the etching parameters to control the groove depth of the first groove 141 to have a reasonable ratio with the groove depth of the target groove, and then perform the step of etching the target layer 10 again after etching the mask pattern, so that the critical dimensions, target inclination and depth of the manufactured target groove meet the design requirements.

[0064] In some embodiments, reference Figure 2 , Figure 3 , the mask layer 20 is dry-etched using the first gas to form a mask pattern, and the target layer 10 exposed by the mask pattern is continuously etched using the first gas to form a first trench 141 .

[0065] Wherein, the first gas includes a fluorine-based gas and an oxidizing gas.

[0066] For example, the fluorine-based gas may be selected from at least one of SF6, NF3, CF4, C2F, C4F8, C5F8 or C4F6.

[0067] The oxidizing gas can be selected from at least one of oxidizing gases such as O2, N2, N2H2, etc.

[0068] The first gas may further include a carrier gas, and the carrier gas is selected from inert gases such as Ar and He.

[0069] In this embodiment, the target layer 10 after the mask layer 20 is formed is transferred to a process chamber, which can be a dry etching chamber. The pressure, bias power, and source power in the process chamber are adjusted, and a first gas is introduced into the dry etching chamber. After the mask layer 20 is patterned with the first gas to form a mask pattern, the target layer 10 exposed by the mask pattern is etched with the first gas to form a first groove 141.

[0070] In some embodiments, reference Figure 4 The second gas is used to dry-etch the sidewall of the mask pattern to increase the size of the mask pattern, and the second gas includes an oxygen-based gas or a nitrogen-based gas. The second gas may include at least one of O2, O3, N2, and N2H2.

[0071] In this embodiment, the step of etching the side wall of the mask pattern is continued in the process chamber. After the process chamber is evacuated, the process conditions of the process chamber are adjusted, the bias power is increased, the source power is reduced, and the second gas is introduced into the process chamber. The second gas is ionized to generate oxygen plasma and / or nitrogen plasma so that the plasma bombards the side wall of the mask pattern in a horizontal direction. After the size of the mask pattern is increased to a target size, the introduction of the second gas into the process chamber is stopped.

[0072] In some embodiments, reference Figure 5 , a third gas is used to etch the target layer 10 according to the etched mask pattern, and the third gas includes a fluorine-based gas and an oxidizing gas.

[0073] For example, the fluorine-based gas can be selected from at least one of SF6, NF3, CF4, C2F, C4F8, C5F8 or C4F6; the oxidizing gas can be selected from at least one of oxidizing gases such as O2, N2, N2H2, etc.

[0074] The third gas may also include a carrier gas, and the carrier gas is selected from inert gases such as Ar and He.

[0075] The third gas may be the same gas as the first gas, or may be a gas different from the first gas according to production requirements.

[0076] In this embodiment, the step of etching the target layer 10 according to the etched mask pattern using the third gas is continued in the process chamber. After the process chamber is evacuated, the process conditions of the process chamber are adjusted, the bias power is reduced, the source power is increased, and the third gas is introduced into the process chamber to etch the target layer 10 exposed by the etched mask pattern, thereby increasing the size of the first trench 141 and reducing the inclination of the sidewall of the trench.

[0077] In the method for manufacturing the semiconductor structure of the present embodiment, each step is performed in the same process chamber. The process flow can be completed without adding additional equipment, and there is no need to transfer the structure midway, which reduces equipment consumption and avoids product loss caused by structure transfer. This is beneficial to improving product yield, shortening the production cycle, and improving production efficiency.

[0078] According to an exemplary embodiment, the method for manufacturing a semiconductor structure of this embodiment includes the following steps:

[0079] Step S21 : providing a target layer 10 , forming a mask layer 20 on the target layer 10 , and patterning the mask layer 20 to form a first mask pattern 130 .

[0080] In this embodiment, refer to Figure 2 The target layer 10 is a material layer formed on the substrate 50. The target layer 10 may be a silicon oxide layer, a silicon nitride layer or a semiconductor layer. The target layer 10 may be used to directly form a semiconductor device, or the target layer 10 may also be used to form a mask or an isolation layer of a device on the substrate 50. The specific selection of the target layer 10 and the substrate 50 is the same as that in the above embodiment, and will not be repeated here.

[0081] Reference Figure 2 After forming a mask layer 20 on the target layer 10, the mask layer 20 is etched with a first gas, and the mask layer 20 is patterned to form a first mask pattern 130. The critical dimension of the first mask pattern 130 and the critical dimension of the target groove to be formed are in a ratio of 0.9-1.1: 1. For example, the critical dimension of the first mask pattern 130 and the critical dimension of the target groove to be formed can be 0.90:1, 0.91:1, 0.93:1, 0.95:1, 0.97:1, 0.99:1, 1.0:1, 1.01:1, 1.03:1, 1.04:1, 1.06:1, 1.08:1 or 1.1:1.

[0082] It can be understood that the critical dimension of the first mask pattern 130 can be smaller than or larger than the critical dimension of the target groove. After the first groove 141 is formed according to the first mask pattern 130 and the mask layer 20 is trimmed, the target layer 10 is continuously etched downward based on the first groove 141. The critical dimension of the target groove formed can be smaller than the critical dimension of the first groove 141.

[0083] The inventors of the present application have discovered that setting the ratio of the critical dimension of the first mask pattern 130 to the critical dimension of the target groove to be formed to 0.9-1.1:1, and setting the ratio of the critical dimension of the first groove 141 to the critical dimension of the target groove to 0.9-1.1:1, is beneficial to controlling the critical dimension of the target groove so that the critical dimension of the target groove meets expectations, and is beneficial to controlling the target tilt angle so that the target tilt angle is less than 30°.

[0084] Step S22: etching the target layer 10 according to the first mask pattern 130 to form a first trench 141 in the target layer 10, wherein the sidewall of the first trench 141 has a first inclination angle α1, and the first inclination angle α1 is greater than 60°.

[0085] Reference Figure 3 , the target layer 10 exposed by the first mask pattern 130 is etched by a first gas to form a first trench 141, and the sidewall of the first trench 141 has a first inclination angle α1 greater than 60°. In this embodiment, the ratio of the trench depth of the first trench 141 to the thickness of the target layer 10 is 1:2-1:3. For example, the ratio of the trench depth of the first trench 141 to the thickness of the target layer 10 can be 1:2, 1:2.2, 1:2.4, 1:2.5, 1:2.6, 1:2.8 or 1:3.

[0086] Step S23 : etching the sidewall of the first mask pattern 130 to increase the size of the first mask pattern 130 and form a second mask pattern 230 .

[0087] Reference Figure 6 In this embodiment, the second gas is used to etch the first mask pattern 130 to form the second mask pattern 230, and the critical dimension of the second mask pattern 230 is the same as the critical dimension of the target trench to be formed.

[0088] Step S24: etching the target layer 10 according to the second mask pattern 230 to etch the first trench 141 into a second trench 241, the sidewall of the second trench 241 having a second inclination angle α2, which is smaller than the first inclination angle α1 and smaller than 30°.

[0089] Reference Figure 7 In this embodiment, the target layer 10 exposed by the second mask pattern 230 is etched by a third gas, and the first groove 141 is etched into a second groove 241, and the second groove 241 is the target groove. The sidewall of the second groove 241 has a second inclination angle α2, and the second inclination angle α2 is less than 30°.

[0090] The method for manufacturing the semiconductor structure of the present embodiment reasonably designs the ratio of the critical dimension of the first mask pattern 130 to the critical dimension of the target groove to be formed, and the ratio of the groove depth of the first groove 141 to the thickness of the target layer 10. It only needs to perform one patterning step on the mask layer 20 and etch the target layer 10 twice to obtain the second groove 241 with an inclination angle less than 30°. The manufacturing process is simple, the manufacturing difficulty is low, and the manufacturing cost is saved.

[0091] In some embodiments, the critical dimension of the second mask pattern 230 is smaller than the critical dimension of the target trench to be formed. The method for manufacturing the semiconductor structure of this embodiment further includes the following steps:

[0092] Step S25 : etching the sidewall of the second mask pattern 230 to increase the size of the second mask pattern 230 and form a third mask pattern 330 .

[0093] Reference Figure 8 In this embodiment, the second mask pattern 230 is etched by the second gas to form the third mask pattern 330, and the critical dimension of the third mask pattern 330 is the same as the critical dimension of the target trench to be formed.

[0094] Step S26: etching the target layer 10 according to the third mask pattern 330 to etch the second trench 241 into a third trench 341, wherein the sidewall of the third trench 341 has a third inclination angle α3, which is smaller than the second inclination angle α2 and smaller than 20°.

[0095] Reference Fig. 9 The target layer 10 exposed by the second mask pattern 230 is etched with a third gas, and the second groove 241 is etched into a third groove 341, where the third groove 341 is the target groove, and the sidewall of the third groove 341 has a third inclination angle α3, which is less than 20°.

[0096] The method for manufacturing the semiconductor structure of the present embodiment increases the size of the mask pattern by repeatedly etching the mask pattern, and etches the target layer 10 according to the etched mask pattern until a target groove is etched to further reduce the inclination of the side wall of the target groove, so that the side wall of the target groove has a third inclination angle α3 less than 20°.

[0097] In some embodiments, the critical dimension of the third mask pattern 330 is smaller than the critical dimension of the target trench to be formed. The method for manufacturing the semiconductor structure of this embodiment further includes the following steps:

[0098] Step S27 : etching the sidewall of the third mask pattern 330 to increase the size of the third mask pattern 330 and form a fourth mask pattern 430 .

[0099] Step S28: etching the target layer 10 according to the fourth mask pattern 430, etching the third trench 341 into a fourth trench 441, the sidewall of the fourth trench 441 has a fourth inclination angle α4, the fourth inclination angle α4 is smaller than the third inclination angle α3, and the fourth inclination angle α4 is 5-10°.

[0100] Reference Fig.10 , Fig.11 In this embodiment, the size of the mask pattern is increased by etching the mask pattern multiple times, and the groove is etched according to the etched mask pattern. Each time the groove is etched according to the mask pattern, the inclination angle of the side wall of the groove can be further reduced to obtain a groove with a smaller inclination angle. In the process of manufacturing the semiconductor structure, the number of times the mask pattern is etched can be flexibly adjusted according to the expected inclination angle of the inclined surface. The manufacturing process of the semiconductor structure manufacturing method of this embodiment is more flexible, and inclined surfaces with different inclination angles can be manufactured.

[0101] In some embodiments, reference Fig.12 The substrate 50 is etched using the patterned target layer 10 as a mask, and the pattern of the patterned mask layer 20 is transferred to the substrate 50, forming a structure on the substrate 50 with a side surface having a slope and a slope angle less than 30°.

[0102] In some other embodiments, referring to Fig.13 , the first trench 141 is etched into a target trench, the sidewall of the target trench has a target tilt angle, the target tilt angle is less than the first tilt angle α1, and the target tilt angle is less than 30°. Afterwards, the patterned target layer 10 is used as a barrier layer to perform ion implantation into the substrate 50 exposed by the target trench, and a doping region 51 is formed on the substrate 50. The size of the doping region 51 gradually decreases along the direction from the top surface of the substrate 50 to the bottom surface of the substrate 50, so as to form a doping region 51 with a gradually changing size.

[0103] In a second aspect, the present disclosure provides a semiconductor structure manufactured using the semiconductor structure manufacturing method of the above embodiment.

[0104] Among them, the semiconductor structure of this embodiment can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM) or other types of memory.

[0105] In some embodiments, an electronic device is provided, including the semiconductor structure of the above embodiment or the semiconductor structure manufactured by the method for manufacturing the semiconductor structure of the above embodiment. The electronic device may be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0106] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a target layer, forming a mask layer on the target layer, and patterning the mask layer to form a mask pattern; wherein the target layer is a silicon nitride layer formed on a substrate; Etching the target layer according to the mask pattern to form a first trench in the target layer, wherein a sidewall of the first trench has a first inclination angle; Performing the following steps at least once: etching the sidewall of the mask pattern, increasing the size of the mask pattern, and etching the target layer according to the etched mask pattern; etching the first groove into a target groove, the sidewall of the target groove has a target tilt angle, the target tilt angle is less than the first tilt angle, and the target tilt angle is less than 30°; Wherein, the target layer is etched according to the etched mask pattern using a third gas, and the third gas includes a fluorine-based gas and an oxidizing gas; the fluorine-based gas is selected from at least one of SF6, NF3, CF4, C2F, C4F8, C5F8 or C4F6; the oxidizing gas is selected from at least one of oxidizing gases such as O2, N2, N2H2, etc.; The ratio of the depth of the first groove to the thickness of the target layer is 1:2-1:3; The ratio of the critical dimension of the first groove to the critical dimension of the target groove is 0.9-1.1:

1.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The mask layer is dry-etched using a first gas to form the mask pattern, and the target layer exposed by the mask pattern is continuously etched using the first gas to form the first groove.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The first gas includes a fluorine-based gas and an oxidizing gas.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The sidewall of the mask pattern is dry-etched using a second gas to increase the size of the mask pattern, and the second gas includes at least one of O2, O3, N2, and N2H2.

5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The production method comprises: Providing a target layer, forming the mask layer on the target layer, and patterning the mask layer to form a first mask pattern; Etching the target layer according to the first mask pattern to form the first trench in the target layer, wherein the sidewall of the first trench has the first inclination angle, and the first inclination angle is greater than 60°; Etching the sidewall of the first mask pattern to increase the size of the first mask pattern to form a second mask pattern; The target layer is etched according to the second mask pattern to etch the first groove into a second groove, the sidewall of the second groove has a second inclination angle, the second inclination angle is smaller than the first inclination angle, and the second inclination angle is smaller than 30°.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The production method comprises: Etching the sidewall of the second mask pattern to increase the size of the second mask pattern to form a third mask pattern; The target layer is etched according to the third mask pattern to etch the second groove into a third groove, the sidewall of the third groove has a third inclination angle, the third inclination angle is smaller than the second inclination angle, and the third inclination angle is smaller than 20°.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The production method comprises: Etching the sidewall of the third mask pattern to increase the size of the third mask pattern to form a fourth mask pattern; The target layer is etched according to the fourth mask pattern to etch the third groove into a fourth groove, the sidewall of the fourth groove has a fourth inclination angle, the fourth inclination angle is smaller than the third inclination angle, and the fourth inclination angle is 5-10°.

8. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the manufacturing method of any one of claims 1 to 7.

Images