Method of fabricating a semiconductor structure, semiconductor structure, device and apparatus

Abstract

The application provides a semiconductor structure preparation method, a semiconductor structure, a device and equipment. The method comprises the following steps: providing a substrate; the substrate comprises a lateral diffusion region and a core region; ion implantation is performed on the lateral diffusion region to form a P-type well region and an N-type drift region; the lateral diffusion region and the core region are etched to form a fin structure; the fin structure comprises a first fin structure and a second fin structure which are arranged in a stacking manner along a first direction; a first fin cutting process is performed on the first fin structure to form a first fin cutting groove; the first fin cutting groove is filled with oxide; a first transistor is formed based on the first fin structure; the substrate is inverted and removed; a second fin cutting process is performed on the second fin structure to form a second fin cutting groove; the second fin cutting groove is filled with oxide; and a second transistor is formed based on the second fin structure. Through the application, process compatibility between a lateral diffusion device and a stacked transistor can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and in particular to a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. BACKGROUND

[0002] With the performance of FinFET (fin field-effect transistor) approaching the limit, a laterally-diffused metal-oxide semiconductor (LDMOS) process based on a new structure needs to be developed, which helps further miniaturization of the transistor size. Transistor stacking is considered as a potential way of miniaturization. At present, how to realize process compatibility with stacked transistors is still a problem to be solved for FinFET LDMOS as a ring in a supporting circuit module. SUMMARY

[0003] The present application provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment to realize process compatibility between a laterally-diffused device and a stacked transistor.

[0004] In a first aspect, the embodiments of the present application provide a method for manufacturing a semiconductor structure, the semiconductor structure comprising a lateral diffused device and a core device, the core device comprising a first transistor and a second transistor stacked along a first direction; the semiconductor structure further comprising the lateral diffused device, the lateral diffused device being arranged side by side with the first transistor or being arranged side by side with the second transistor; the method comprising: providing a substrate; the substrate comprising a lateral diffusion region and a core region; the lateral diffusion region and the core region being arranged adjacent to each other along a second direction; the second direction being perpendicular to the first direction; performing ion implantation in the lateral diffusion region to form a P-type well region and an N-type drift region; etching the lateral diffusion region and the core region to form a fin structure; the fin structure comprising a first fin structure and a second fin structure stacked along the first direction; performing a first fin cut process on the first fin structure to form a first fin cut trench; the first fin cut trench being perpendicular to an extension direction of the first fin structure; the etching depth of the first fin cut process being half of a height of the fin structure; filling the first fin cut trench with an oxide; forming the first transistor based on the first fin structure; peeling off and removing the substrate; performing a second fin cut process on the second fin structure to form a second fin cut trench; the second fin cut trench being perpendicular to an extension direction of the second fin structure; the etching depth of the second fin cut process being equal to the height of the fin structure or being half of the height of the fin structure; filling the second fin cut trench with an oxide; forming the second transistor based on the second fin structure; wherein the method further comprises: forming a first recess in the N-type drift region corresponding to the first fin structure while performing the first fin cut process on the first fin structure, and forming the lateral diffused device based on the first recess, or forming a first recess in the N-type drift region corresponding to the second fin structure while performing the second fin cut process on the second fin structure, and forming the lateral diffused device based on the first recess; the first recess being used for filling the oxide.

[0005] In some possible implementations, the first fin cut process is performed on the first fin structure to form the first fin cut trench, comprising: performing the first fin cut process on the first fin structure to form the first fin cut trench in the core region corresponding to the first fin structure, and to form a first recess in the N-type drift region corresponding to the first fin structure; the filling of the oxide in the first fin cut trench comprises: depositing the oxide on the fin structure and the substrate to form a shallow trench isolation structure; the shallow trench isolation structure wrapping the fin structure and filling the first recess and the first fin cut trench.

[0006] In some possible implementation manners, forming the first transistor based on the first fin structure comprises: forming a first dummy gate structure in the first transistor and a second dummy gate structure in the lateral diffusion device based on the first fin structure; etching a portion of the first fin structure to form a first source-drain recess and a second source-drain recess; performing source-drain epitaxial growth in the first source-drain recess and the second source-drain recess to form a first source-drain structure in the first transistor and a second source-drain structure in the lateral diffusion device; removing the first dummy gate structure and the second dummy gate structure, and forming a first gate structure in the first transistor and a second gate structure in the lateral diffusion device; forming a first source-drain metal in the first transistor and a second source-drain metal in the lateral diffusion device on the first source-drain structure and the second source-drain structure; and performing a back-end-of-line process on the first gate structure, the second gate structure, the first source-drain metal, and the second source-drain metal to form a first metal interconnection layer in the first transistor and a second metal interconnection layer in the lateral diffusion device.

[0007] In some possible implementation manners, forming the second transistor based on the second fin structure comprises: forming a third dummy gate structure in the second transistor based on the second fin structure; etching a portion of the second fin structure to form a third source-drain recess; performing source-drain epitaxial growth in the third source-drain recess to form a third source-drain structure in the second transistor; removing the third dummy gate structure, and forming a third gate structure in the second transistor; forming a third source-drain metal in the second transistor on the third source-drain structure; and performing a back-end-of-line process on the third gate structure and the third source-drain metal to form a third metal interconnection layer in the second transistor and a back surface dielectric layer in the isolation device; and the lateral diffusion device and the isolation device are arranged in a stack along a first direction.

[0008] In some possible implementation manners, the second fin cutting processing on the second fin structure to form a second fin cutting trench comprises: performing the second fin cutting processing on the second fin structure to form a second fin cutting trench corresponding to a core region of the second fin structure, and form a first recess in an N-type drift region of the second fin structure; and filling oxide in the second fin cutting trench comprises: filling oxide in the second fin cutting trench and the first recess.

[0009] In some possible implementation manners, forming the first transistor based on the first fin structure comprises: forming a first dummy gate structure in the first transistor based on the first fin structure; etching a part of the first fin structure to form a first source-drain recess; performing source-drain epitaxial growth in the first source-drain recess to form a first source-drain structure in the first transistor; removing the first dummy gate structure and forming a first gate structure in the first transistor; forming a first source-drain metal in the first transistor on the first source-drain structure; performing a back-end-of-line process on the first gate structure and the first source-drain metal to form a first metal interconnection layer in the first transistor and a front surface dielectric layer in the isolation device; and the isolation device and the lateral diffusion device are arranged in a stack along the first direction.

[0010] In some possible implementation manners, forming the second transistor based on the second fin structure comprises: forming a third dummy gate structure in the second transistor and a second dummy gate structure in the lateral diffusion device based on the second fin structure; etching a part of the second fin structure to form a third source-drain recess and a second source-drain recess; performing source-drain epitaxial growth in the third source-drain recess and the second source-drain recess to form a third source-drain structure in the second transistor and a second source-drain structure in the lateral diffusion device; removing the third dummy gate structure and the second dummy gate structure and forming a third gate structure in the second transistor and a second gate structure in the lateral diffusion device; forming a third source-drain metal in the second transistor and a second source-drain metal in the lateral diffusion device on the third source-drain structure and the second source-drain structure; and performing a back-end-of-line process on the third gate structure, the second gate structure, the third source-drain metal and the second source-drain metal to form a third metal interconnection layer in the second transistor and a second metal interconnection layer in the lateral diffusion device.

[0011] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by the method in any of the foregoing embodiments, and the semiconductor structure comprises: a core device; the core device comprises a first transistor and a second transistor arranged in a stack along a first direction; a lateral diffusion device; the lateral diffusion device is arranged side by side with the first transistor or the second transistor; an isolation device; the isolation device is arranged in a stack with the lateral diffusion device along the first direction; wherein the lateral diffusion device comprises a P-type well region and an N-type drift region; a first recess is arranged in the N-type drift region in the lateral diffusion device, and the first recess is used for filling an oxide.

[0012] In a third aspect, an embodiment of the present application provides a semiconductor device, which comprises the semiconductor structure in any of the foregoing embodiments.

[0013] In a fourth aspect, an embodiment of the present application provides an electronic device, which comprises a circuit board and the semiconductor device in any of the foregoing embodiments, and the semiconductor device is arranged on the circuit board.

[0014] In the present application, by forming a first recess in the N-type drift region while performing a first fin cut process on the first fin-shaped structure or a second fin cut process on the second fin-shaped structure, and filling the first recess with oxide, the formed lateral diffusion device can withstand higher voltage while being compatible with the process of preparing the stacked transistors, thereby optimizing the preparation process of the semiconductor structure.

[0015] Further, since the second fin cut process is performed on the second fin-shaped structure, different etching depths can be selected according to actual needs, i.e., the etching depth of the second fin cut process is equal to the height of the fin-shaped structure or equal to half the height of the fin-shaped structure, so that the layout of the internal devices of the semiconductor structure is more flexible.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application.

[0018] Figure 1 An implementation flowchart of the preparation method of the semiconductor structure in the embodiments of the present application;

[0019] Figure 2 A design layout of the semiconductor structure in the embodiments of the present application;

[0020] Figure 3 A first structure schematic diagram of the semiconductor structure in the embodiments of the present application;

[0021] Figures 4A-4D A first preparation process schematic diagram of the semiconductor structure in the embodiments of the present application;

[0022] Figure 5 A second structure schematic diagram of the semiconductor structure in the embodiments of the present application;

[0023] Figure 6 A second preparation process schematic diagram of the semiconductor structure in the embodiments of the present application;

[0024] Figure 7 A third structure schematic diagram of the semiconductor structure in the embodiments of the present application;

[0025] The above figures:

[0026] 10, semiconductor structure; 11, first transistor; 111, first spacer; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate dielectric layer; 115, first gate structure; 116, first source-drain metal; 12, lateral diffused device; 121, second spacer; 122, second source-drain structure; 123, second interlayer dielectric layer; 124, second gate dielectric layer; 125, second gate structure; 126, second source-drain metal; 13, second transistor; 131, third spacer; 132, third source-drain structure; 133, third interlayer dielectric layer; 134, third gate dielectric layer; 135, third gate structure; 136, third source-drain metal; 14, isolation device; 143, fourth interlayer dielectric layer; 15, first insulating layer; 16, carrier wafer; 21, substrate; 22, fin structure; 221, first fin structure; 222, second fin structure; 231, first fin cut trench; 232, second fin cut trench; 24, first recess; 25, shallow trench isolation structure; 251, shallow trench isolation layer; 261, first gate oxide layer; 262, second gate oxide layer; 271, first contact layer; 272, second contact layer; 311, first dummy gate structure; 312, second dummy gate structure; 313, third dummy gate structure. DETAILED DESCRIPTION

[0027] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description below concerns the drawings, wherein the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0028] In some embodiments, LDMOS structures pursue higher breakdown voltage and lower on-resistance. To increase the breakdown voltage, there is a drift region between the source region and the drain region, which has a lower impurity concentration and presents a high resistance state, thus being able to withstand higher voltage. The LDMOS drift region uses STI (shallow trench isolation) / field oxide technology, so that the current path is blocked and lengthened, thereby further improving the voltage withstand capability. To further scale down the size, LDMOS based on FinFET (fin field-effect transistor) process has attracted widespread attention. Taking nLDMOS as an example, a P-well and an N-type drift region are implanted on a p-type substrate, wherein the source region is located in the P-well, the drain region and the STI are located in the N-type drift region, and the gate covers the channel region, part of the N-type drift region and part of the STI region.

[0029] As FinFET performance approaches the limit, LDMOS processes based on new structures need to be developed, which helps further miniaturization of transistors. Transistor stacking is considered as a promising way of miniaturization, for example, complementary field effect transistor (CFET) technology. However, there are also some problems, such as: (1) thermal stability of the bottom layer device when making the upper layer device; (2) performance of the top layer device under low thermal budget; (3) metal interconnection of transistors between layers.

[0030] At present, as a part of a supporting circuit module, how to realize process compatibility with stacked transistors for FinFET LDMOS is still a problem to be solved.

[0031] To solve the above technical problems, the embodiments of the present application provide a preparation method of a semiconductor structure to realize process compatibility between a lateral diffused device and a stacked transistor.

[0032] In the embodiments of the present application, the above semiconductor structure can be applied to semiconductor devices such as memories, processors, etc.

[0033] In some possible implementations, the semiconductor structure includes: a core device; the core device includes a first transistor and a second transistor stacked along a first direction; a lateral diffused device; the lateral diffused device is arranged side by side with the first transistor or arranged side by side with the second transistor; an isolation device; the isolation device is stacked with the lateral diffused device in the first direction; wherein the lateral diffused device includes a P-type well region and an N-type drift region; a first recess is arranged in the N-type drift region of the lateral diffused device, and the first recess is used for filling an oxide.

[0034] It can be understood that the semiconductor structure mentioned in the embodiments of the present application includes a lateral diffused device (i.e. LDMOS) and a core device. The lateral diffused device and the core device can be arranged adjacent to each other, can be arranged at intervals, or can be arranged in other forms, which are not limited in the embodiments of the present application. It should be noted that the semiconductor structure can include multiple lateral diffused devices and multiple core devices, and the lateral diffused devices and the core devices in the same semiconductor structure are prepared based on the same substrate (i.e. wafer), and for the convenience of description, the embodiments of the present application are described by taking the semiconductor structure including one lateral diffused device and one core device as an example.

[0035] In some embodiments, the lateral diffusion device in the semiconductor structure is disposed only on the front or back side of the semiconductor structure, that is, the lateral diffusion device is disposed side by side with the first transistor or side by side with the second transistor. The isolation device and the lateral diffusion device are stacked in a first direction. When the lateral diffusion device is disposed side by side with the first transistor, the isolation device is disposed side by side with the second transistor; when the lateral diffusion device is disposed side by side with the second transistor, the isolation device is disposed side by side with the first transistor.

[0036] In this embodiment, the core device includes a first transistor and a second transistor stacked back-to-back to form a stacked transistor. The first transistor and the second transistor can be the same type of transistor, such as a fin field-effect transistor.

[0037] Figure 2 It is a semiconductor structure composed of fin field-effect transistors and lateral diffusion devices. See [link / reference] Figure 2 As shown, the semiconductor structure includes a lateral diffusion device and a core device. The core device includes a first transistor and a second transistor stacked along a first direction. The semiconductor structure also includes a lateral diffusion device, which is arranged side-by-side with the first transistor or side-by-side with the second transistor. The following description, in conjunction with... Figure 2 The semiconductor structure shown illustrates the method for fabricating the semiconductor structure provided in the embodiments of this application.

[0038] Figure 1 This is a schematic diagram illustrating one implementation process of the semiconductor structure fabrication method in this application. See also... Figure 1 As shown, the method for fabricating the above-mentioned semiconductor structure may include:

[0039] S101 provides a substrate.

[0040] The substrate includes a lateral diffusion region and a core region; the lateral diffusion region and the core region are arranged adjacent to each other in a second direction; the second direction is perpendicular to the first direction.

[0041] Understandably, the substrate includes a lateral diffusion region for forming lateral diffusion devices and isolation devices, and a core region for forming core devices. The lateral diffusion region and the core region may be arranged adjacent to each other.

[0042] In some embodiments, the semiconductor structure is a stacked transistor, with lateral diffusion devices and isolation devices stacked accordingly; a first transistor and a second transistor in the core device are stacked.

[0043] In some embodiments, the substrate may be a Si substrate made of silicon (Si) material, or other types of substrates may be selected according to actual needs, such as silicon-on-insulator (SOI) substrates.

[0044] S102, ion implantation is performed on the lateral diffusion region to form a P-type well region and an N-type drift region.

[0045] It can be understood that, by using a mask plate process, ion implantation can be performed twice on the lateral diffusion region to form a high-concentration P-type well region and a low-concentration N-type drift region, respectively. During ion implantation, the P-type well region can be formed first, and then the N-type drift region can be formed. Alternatively, the N-type drift region can be formed first, and then the P-type well region can be formed. It should be noted that the implantation mode of the N-type drift region can be selected according to actual needs, and the application embodiments do not make specific limitations thereto; a PN junction in the horizontal direction (i.e., the second direction mentioned above) can be formed between the N-type drift region and the P well.

[0046] S103, etching the lateral diffusion region and the core region to form a fin structure.

[0047] The fin structure includes a first fin structure and a second fin structure stacked along the first direction.

[0048] It can be understood that, by etching the substrate, a fin structure (fin) can be formed. The fin structure in the lateral diffusion region is used to form a lateral diffusion device and an isolation device, and the fin structure in the core region is used to form a core device. The fin structure can be divided into an upper half and a lower half, the upper half being the first fin structure and the lower half being the second fin structure. The first fin structure located in the lateral diffusion region is used to form a lateral diffusion device or an isolation device, and the second fin structure located in the lateral diffusion region is used to form an isolation device or a lateral diffusion device; the first fin structure located in the core region is used to form a first transistor, and the second fin structure located in the core region is used to form a second transistor.

[0049] S104, performing a first fin cut process on the first fin structure to form a first fin cut trench. The first fin cut trench is perpendicular to the extension direction of the first fin structure; the etching depth of the first fin cut process is half the height of the fin structure.

[0050] It can be understood that, after the fin structure is formed, a fin cut process can be performed on the first fin structure by lithography to form a first fin cut trench; the etching depth is half the height of the fin structure, i.e., half the depth.

[0051] S105, filling the first fin cut trench with oxide.

[0052] It can be understood that after the first fin cut trench is formed, a shallow trench isolation (STI) structure can be formed by depositing an oxide on the substrate and the fin structure, and the first fin cut trench is filled with the oxide while the shallow trench isolation structure is formed.

[0053] S106, forming a first transistor based on the first fin structure.

[0054] It can be understood that after the first fin cut trench is filled with the oxide, the first transistor can be formed according to a standard process of preparing a transistor.

[0055] S107, peeling and removing the substrate.

[0056] It can be understood that after the first transistor is formed, in order to prepare a second transistor, the first transistor can be subjected to a peeling process and the substrate can be removed, so that the second fin structure is placed upward.

[0057] In some possible embodiments, before S107 described above, the method for preparing the semiconductor structure can further include: depositing an insulating material on an upper surface of the first transistor to form an insulating layer; and bonding the insulating layer with a carrier wafer.

[0058] In the embodiments of the present application, the carrier wafer after bonding can provide physical support for the flipped first transistor after peeling, effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

[0059] S108, performing a second fin cut on the second fin structure to form a second fin cut trench. The second fin cut trench is perpendicular to an extension direction of the second fin structure; and the etching depth of the second fin cut is equal to a height of the fin structure or equal to half of the height of the fin structure.

[0060] It can be understood that after the second fin structure is exposed, the second fin structure can be subjected to a fin cut process by photolithography to form a second fin cut trench. The etching depth can be half of the height of the fin structure or equal to the height of the fin structure, i.e., half-depth or full-depth.

[0061] In the embodiments of the present application, when the second fin structure is subjected to the fin cut process, the depth of the fin cut can be set according to actual requirements, such as half-depth or full-depth, which is not limited in the embodiments of the present application.

[0062] S109, filling the second fin cut trench with an oxide.

[0063] It can be understood that, after the second fin cut groove is formed, the oxide can be filled in the second fin cut groove. It should be noted that the oxide filled in the first fin cut groove and the second fin cut groove is the same.

[0064] S110, based on the second fin structure, forming a second transistor.

[0065] It can be understood that, after the second fin cut groove is filled with the oxide, the second transistor can be formed according to the standard process of preparing the transistor.

[0066] In some possible implementation manners, the method can further include: forming a first recess in an N-type drift region corresponding to the first fin structure while performing the first fin cutting process on the first fin structure, and forming a lateral diffusion device based on the first recess, or forming a first recess in an N-type drift region corresponding to the second fin structure while performing the second fin cutting process on the second fin structure, and forming a lateral diffusion device based on the first recess; the first recess is used for filling the oxide.

[0067] It can be understood that the N-type drift region can be divided into a first N-type drift region and a second N-type drift region, the first N-type drift region corresponds to the first fin structure, and the second N-type drift region corresponds to the second fin structure. The first recess can be arranged in the first N-type drift region or the second N-type drift region according to actual needs. In the case that the first recess is located in the first N-type drift region, the lateral diffusion device is arranged side by side with the first transistor; and the first recess is formed at the same time as the first fin cutting structure is formed, and then the first recess is filled with the oxide in the process of forming the shallow trench isolation structure. In the case that the first recess is located in the second N-type drift region, the lateral diffusion device is arranged side by side with the second transistor; and the first recess is formed at the same time as the second fin cutting structure is formed, and then the first recess is filled with the oxide.

[0068] In some possible implementation manners, in the case that the first recess is located in the first N-type drift region, S104 can include: performing the first fin cutting process on the first fin structure to form a first fin cut groove in a core region corresponding to the first fin structure, and forming the first recess in the N-type drift region corresponding to the first fin structure.

[0069] It can be understood that, in the case that the first recess is located in the first N-type drift region, the first fin cut groove and the first recess can be formed in the same etching process.

[0070] In some possible implementation manners, in the case that the first recess is located in the first N-type drift region, S105 can include: depositing the oxide on the fin structure and the substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the fin structure and fills the first recess and the first fin cut groove.

[0071] It can be understood that, in the case that the first recess is located in the first N-type drift region, the oxide is deposited on the substrate and the fin structure to form the shallow trench isolation structure. At the same time of depositing the oxide on the substrate and the fin structure, the oxide is also deposited in the first fin cut groove and the first recess, so that the shallow trench isolation structure formed wraps the fin structure while filling the first fin cut groove and the first recess.

[0072] In some possible embodiments, in the case that the first recess is located in the first N-type drift region, the S106 can include: based on the first fin structure, forming a first dummy gate structure in the first transistor and a second dummy gate structure in the lateral diffusion device; etching a part of the first fin structure to form a first source-drain recess and a second source-drain recess; performing source-drain epitaxial growth in the first source-drain recess and the second source-drain recess to form a first source-drain structure in the first transistor and a second source-drain structure in the lateral diffusion device; removing the first dummy gate structure and the second dummy gate structure, and forming a first gate structure in the first transistor and a second gate structure in the lateral diffusion device; forming a first source-drain metal in the first transistor and a second source-drain metal in the lateral diffusion device on the first source-drain structure and the second source-drain structure; performing a back-end-of-line process on the first gate structure, the second gate structure, the first source-drain metal and the second source-drain metal to form a first metal interconnection layer in the first transistor and a second metal interconnection layer in the lateral diffusion device.

[0073] It can be understood that, after filling the first recess, the lateral diffusion device can be formed based on the first fin structure in the lateral diffusion region, and the first transistor can be formed based on the first fin structure in the core region. Among them, the same device in the first transistor and the lateral diffusion device is formed in the same process, for example, the first dummy gate structure and the second dummy gate structure are formed in the same process, and the first source-drain structure and the second source-drain structure are formed in the same process.

[0074] In an example, after forming the shallow trench isolation structure, the shallow trench isolation structure of a preset height is etched so that the first fin structure is exposed. An oxide of a preset height is deposited on the surface of the first fin structure to form a first gate oxide layer covering the surface of the first fin structure. Then, a gate recess is opened on the first gate oxide layer by photolithography, and a polysilicon is deposited in the gate recess to form a first dummy gate structure in the first transistor and a second dummy gate structure in the lateral diffusion device. A dielectric material is deposited on the sidewall of the first dummy gate structure to form a first spacer in the first transistor, and a dielectric material is deposited on the sidewall of the second dummy gate structure to form a second spacer in the lateral diffusion device. A portion of the first fin structure is etched to form a first source / drain recess and a second source / drain recess. Source / drain epitaxial growth is performed in the first source / drain recess to form a first source / drain structure in the first transistor, and source / drain epitaxial growth is performed in the second source / drain recess to form a second source / drain structure in the lateral diffusion device. A dielectric material is deposited on the first source / drain structure, the second source / drain structure, and the etched shallow trench isolation structure to form a first interlayer dielectric layer in the first transistor and a second interlayer dielectric layer in the lateral diffusion device. It should be noted that the height of the first interlayer dielectric layer and the second interlayer dielectric layer is the same as the height of the first dummy gate structure and the second dummy gate structure. Then, the first dummy gate structure and the second dummy gate structure are removed to expose the gate recess, and a metal material is deposited in the gate recess to form a first gate structure in the first transistor and a second gate structure in the lateral diffusion device. An insulating material is deposited on the first interlayer dielectric layer and the second interlayer dielectric layer to form a first contact layer. By photolithography, the first contact layer, the first interlayer dielectric layer, and the second interlayer dielectric layer are etched to form a first via hole on the upper surface of the first source / drain structure and a second via hole on the upper surface of the second source / drain structure. A metal material is deposited in the first via hole and the second via hole to form a first source / drain metal and a second source / drain metal. Finally, a back-end-of-line process is performed on the first contact layer to form a first metal interconnection layer in the first transistor and a second metal interconnection layer in the lateral diffusion device.

[0075] In some possible implementations, in a case where the first recess is located in the first N-type drift region, the S110 can include: based on the second fin structure, forming a third dummy gate structure in a second transistor; etching a portion of the second fin structure to form a third source / drain recess; performing source / drain epitaxial growth in the third source / drain recess to form a third source / drain structure in the second transistor; removing the third dummy gate structure and forming a third gate structure in the second transistor; forming a third source / drain metal in the second transistor on the third source / drain structure; performing a back-end-of-line process on the third gate structure and the third source / drain metal to form a third metal interconnection layer in the second transistor and a back surface dielectric layer in the isolation device; and the lateral diffusion device and the isolation device are arranged in a stack along the first direction.

[0076] It can be understood that, in the case that the first recess is located in the first N-type drift region, the gate structure, the source-drain structure and the source-drain metal are not formed in the isolation device.

[0077] In an example, the shallow trench isolation structure of the preset height is etched so that the second fin structure is exposed, and the remaining shallow trench isolation structure is used as a shallow trench isolation layer. An oxide of the preset height is deposited on the surface of the second fin structure to form a second gate oxide layer covering the surface of the second fin structure. Then, a gate recess is opened on the second gate oxide layer by photolithography, and a polysilicon is deposited in the gate recess to form a third dummy gate structure in the second transistor; a dielectric material is deposited on the sidewall of the third dummy gate structure to form a third spacer in the second transistor. A part of the second fin structure is etched to form a third source-drain recess; source-drain epitaxial growth is performed in the third source-drain recess to form a third source-drain structure in the second transistor. A dielectric material is deposited on the third source-drain structure and the shallow trench isolation layer to form a third interlayer dielectric layer in the second transistor and a fourth interlayer dielectric layer in the isolation device. It should be noted that the height of the third interlayer dielectric layer and the fourth interlayer dielectric layer is the same as the height of the third dummy gate structure. Then, the third dummy gate structure is removed to expose the gate recess, and a metal material is deposited in the gate recess to form a third gate structure in the second transistor. An insulating material is deposited on the third interlayer dielectric layer and the fourth interlayer dielectric layer to form a second contact layer. By photolithography, the second contact layer and the third interlayer dielectric layer are etched to form a third via hole located on the upper surface of the third source-drain structure. A metal material is deposited in the third via hole to form a third source-drain metal. Finally, a back surface dielectric layer in the isolation device and a third metal interconnection layer in the second transistor are formed by performing a subsequent process on the second contact layer.

[0078] It should be noted that, in the case that the first recess is located in the first N-type drift region, since the gate structure and the source-drain structure are not formed in the isolation device, only a dielectric layer (i.e., the back surface dielectric layer) needs to be formed in the process of the subsequent process, and metal interconnection does not need to be performed in the back surface dielectric layer.

[0079] In some possible implementation manners, in the case that the first recess is located in the second N-type drift region, the S108 can include: performing a second fin cutting process on the second fin structure to form a second fin cutting groove in a core region corresponding to the second fin structure and form the first recess in the N-type drift region corresponding to the second fin structure.

[0080] It can be understood that, in the case that the first recess is located in the second N-type drift region, the second fin cutting groove and the first recess can be formed in the same etching process.

[0081] In some possible implementation, in the case that the first recess is located in the second N-type drift region, the S109 can include: filling the second fin cut trench and the first recess with oxide.

[0082] It can be understood that, in the case that the first recess is located in the second N-type drift region, after the second fin cut trench and the first recess are formed, the second fin cut trench and the first recess are filled with the same oxide as the shallow trench isolation structure.

[0083] In some possible implementation, in the case that the first recess is located in the second N-type drift region, the S106 can include: based on the first fin structure, forming a first dummy gate structure in the first transistor; etching a part of the first fin structure to form a first source-drain recess; performing source-drain epitaxial growth in the first source-drain recess to form a first source-drain structure in the first transistor; removing the first dummy gate structure and forming a first gate structure in the first transistor; forming a first source-drain metal in the first transistor on the first source-drain structure; performing a back-end-of-line process on the first gate structure and the first source-drain metal to form a first metal interconnection layer in the first transistor and a front surface dielectric layer in the isolation device; and the isolation device and the lateral diffusion device are arranged in a stack along a first direction.

[0084] It can be understood that, in the case that the first recess is located in the second N-type drift region, no gate structure, source-drain structure and source-drain metal are formed in the isolation device.

[0085] In an example, a shallow trench isolation structure with a preset height is etched so that the first fin structure is exposed. An oxide with a preset height is deposited on the surface of the first fin structure to form a first gate oxide layer covering the surface of the first fin structure. Then a gate recess is opened on the first gate oxide layer by photolithography, and a polysilicon is deposited in the gate recess to form a first dummy gate structure in the first transistor. A dielectric material is deposited on the sidewall of the first dummy gate structure to form a first spacer in the first transistor. A portion of the first fin structure is etched to form a first source-drain recess. Source-drain epitaxial growth is performed in the first source-drain recess to form a first source-drain structure in the first transistor. A dielectric material is deposited on the first source-drain structure and the etched shallow trench isolation structure to form a first interlayer dielectric layer in the first transistor and a fourth interlayer dielectric layer in the isolation device. It should be noted that the height of the first interlayer dielectric layer and the fourth interlayer dielectric layer is the same as the height of the first dummy gate structure. Then, the first dummy gate structure is removed to expose the gate recess, and a metal material is deposited in the gate recess to form a first gate structure in the first transistor. An insulating material is deposited on the first interlayer dielectric layer and the fourth interlayer dielectric layer to form a first contact layer. By photolithography, the first contact layer and the first interlayer dielectric layer are etched to form a first via hole on the upper surface of the first source-drain structure. A metal material is deposited in the first via hole to form a first source-drain metal. Finally, a back-end-of-line process is performed on the first contact layer to form a first metal interconnection layer in the first transistor and a front surface dielectric layer in the isolation device.

[0086] It should be noted that in the case where the first recess is located in the second N-type drift region, no gate structure and source-drain structure are formed in the isolation device, so in the process of the back-end-of-line process, only a dielectric layer (i.e. the front surface dielectric layer) needs to be formed, and no metal interconnection needs to be performed in the front surface dielectric layer.

[0087] In some possible implementations, in the case where the first recess is located in the second N-type drift region, the S110 can include: based on the second fin structure, forming a third dummy gate structure in a second transistor and a second dummy gate structure in a lateral diffusion device; etching a portion of the second fin structure to form a third source-drain recess and a second source-drain recess; performing source-drain epitaxial growth in the third source-drain recess and the second source-drain recess to form a third source-drain structure in the second transistor and a second source-drain structure in the lateral diffusion device; removing the third dummy gate structure and the second dummy gate structure, and forming a third gate structure in the second transistor and a second gate structure in the lateral diffusion device; forming a third source-drain metal in the second transistor and a second source-drain metal in the lateral diffusion device on the third source-drain structure and the second source-drain structure; and performing a back-end-of-line process on the third gate structure, the second gate structure, the third source-drain metal, and the second source-drain metal to form a third metal interconnection layer in the second transistor and a second metal interconnection layer in the lateral diffusion device.

[0088] It can be understood that after filling the first recess, a lateral diffusion device can be formed based on the second fin structure in the lateral diffusion region, and a second transistor can be formed based on the second fin structure in the core region, wherein the same device in the second transistor and the lateral diffusion device is formed in the same process, for example, the third dummy gate structure and the second dummy gate structure are formed in the same process, and the third source-drain structure and the second source-drain structure are formed in the same process.

[0089] In an example, the shallow trench isolation structure is etched to a preset height, so that the second fin structure is exposed, and a shallow trench isolation layer is formed. A preset height of oxide is deposited on the surface of the second fin structure to form a second gate oxide layer covering the surface of the second fin structure. Then, a gate recess is opened on the second gate oxide layer by lithography, and a polysilicon is deposited in the gate recess to form a third dummy gate structure in the second transistor and a second dummy gate structure in the lateral diffusion device; a dielectric material is deposited on the sidewall of the third dummy gate structure to form a third spacer in the second transistor, and a dielectric material is deposited on the sidewall of the second dummy gate structure to form a second spacer in the lateral diffusion device. A portion of the second fin structure is etched to form a third source-drain recess and a second source-drain recess; source-drain epitaxial growth is performed in the third source-drain recess to form a third source-drain structure in the second transistor, and source-drain epitaxial growth is performed in the second source-drain recess to form a second source-drain structure in the lateral diffusion device. A dielectric material is deposited on the third source-drain structure, the second source-drain structure and the shallow trench isolation layer to form a third interlayer dielectric layer in the second transistor and a second interlayer dielectric layer in the lateral diffusion device. It should be noted that the height of the third interlayer dielectric layer and the second interlayer dielectric layer is the same as the height of the third dummy gate structure and the second dummy gate structure. Then, the third dummy gate structure and the second dummy gate structure are removed to expose the gate recess, and a metal material is deposited in the gate recess to form a third gate structure in the second transistor and a second gate structure in the lateral diffusion device. An insulating material is deposited on the third interlayer dielectric layer and the second interlayer dielectric layer to form a second contact layer. By lithography, the second contact layer, the third interlayer dielectric layer and the second interlayer dielectric layer are etched to form a third via hole located on the upper surface of the third source-drain structure and a second via hole located on the upper surface of the second source-drain structure. A metal material is deposited in the third via hole and the second via hole to form a third source-drain metal and a second source-drain metal. Finally, a post-process is performed on the second contact layer to form a third metal interconnection layer in the second transistor and a second metal interconnection layer in the lateral diffusion device.

[0090] In some embodiments, the metal material forming the first gate structure, the second gate structure and the third gate structure can include, but is not limited to, tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), and the material of the first gate structure, the second gate structure and the third gate structure can be selected according to actual conditions, and is not limited to the metal materials listed above.

[0091] It should be noted that, for the sake of convenience, the first source / drain structure mentioned in the embodiments of the present application is a simple term, and specifically refers to the first source structure and / or the first drain structure. In addition, the second source / drain structure, the first source / drain metal, the second source / drain metal, etc. are similar to the first source / drain structure, and "source / drain" is a simple term for "source and / or drain".

[0092] In some embodiments, the oxide forming the shallow trench isolation structure can be any one of the following: silicon dioxide (SiO2) or silicon carbon oxide (SiCO), etc.

[0093] Next, taking the first transistor and the second transistor as fin-type field effect transistors as an example, the semiconductor structure provided by the embodiments of the present application is described. Figure 2 is the design layout of the semiconductor structure in the embodiments of the present application. Figure 2 (a) in is the design layout of the lateral diffusion device, and it should be noted that, for the sake of convenience, only the fin structure, the gate structure and the source / drain structure are shown in the design layout; (b) is the design layout of the first transistor; (c) is the design layout of the isolation device; and (d) is the design layout of the second transistor. Figure 3 is the first structure schematic diagram of the semiconductor structure in the embodiments of the present application. Figure 3 (a) in is the sectional view of the semiconductor structure along the A-A' direction of the lateral diffusion region; (b) is the sectional view of the semiconductor structure along the B-B' direction of the lateral diffusion region; (c) is the sectional view of the semiconductor structure along the A1-A1' direction of the core region; and (d) is the sectional view of the semiconductor structure along the B1-B1' direction of the core region.

[0094] Figure 3 The semiconductor structure 10 shown in the figure, the first recess is formed in the first N-type drift region, the etching depth of the first fin structure is the half-depth, and the etching depth of the second fin structure is the full-depth.

[0095] Next, the preparation process of the semiconductor structure 10 shown in the figure is described in combination with the above preparation method. Figure 3 The preparation process of the semiconductor structure 10 shown in the figure is described in combination with the above preparation method. Figure 3 The semiconductor structure 10 shown in the figure can be prepared by Figures 4A-4D The preparation process of the semiconductor structure 10 shown in the figure is described in combination with the above preparation method. Figures 4A-4DFIG. 1 is a schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application.

[0096] In an example, the first preparation process of the semiconductor structure 10 can include the following steps:

[0097] Step 1: Provide a Si substrate 21, perform ion implantation twice on the lateral diffusion region respectively by coating photoresist on the Si substrate 21, to form a high-concentration P-type well region and a low-concentration N-type drift region (see (a) in FIG. 2). Figure 4A

[0098] Step 2: Remove the photoresist and etch the substrate 21 to form a fin structure 22. The fin structure 22 includes a first fin structure 221 and a second fin structure 222 (see (b) in FIG. 2). Figure 4A

[0099] Step 3: Perform a first fin cut on the first fin structure 221 to form a first fin cut groove 231 and a first recess 24 (see (c) in FIG. 2). The depth of the photoetching is a half-depth. Figure 4A

[0100] Step 4: Deposit an oxide on the substrate 21 and the fin structure 22 to form a shallow trench isolation structure 25. The shallow trench isolation structure 25 wraps the fin structure 22, covers the substrate 21, and fills the first recess 24 and the first fin cut groove 231. Then, etch the shallow trench isolation structure 25 to a preset height to expose the first fin structure 221. Deposit an oxide on the surface of the first fin structure 221 to form a first gate oxide layer 261. Form a first dummy gate structure 311, a first spacer 111, a second dummy gate structure 312, and a second spacer 121 on the first gate oxide layer 261 (see (a) in FIG. 3). Figure 4B

[0101] It should be noted that the first gate oxide layer 261 can be prepared from the same material as the shallow trench isolation structure 25.

[0102] Step 5: Etch the first fin structure 221 to form a first source / drain recess and a second source / drain recess, and perform source / drain epitaxial growth in the first source / drain recess and the second source / drain recess to form a first source / drain structure 112 and a second source / drain structure 122 (see (b) in FIG. 4). Figure 4B

[0103] ​​​​​Step 6: Deposit dielectric material on the etched shallow trench isolation structure 25, the first source / drain structure 112, and the second source / drain structure 122 to form the first interlayer dielectric layer 113 and the second interlayer dielectric layer 123. Remove the first dummy gate structure 311 and the second dummy gate structure 312 to expose the gate trench, and deposit insulating material on the surface of the gate trench to form the first gate dielectric layer 114 and the second gate dielectric layer 124; then, deposit metal material in the gate trench to form the first gate structure 115 and the second gate structure 125. Deposit dielectric material on the first interlayer dielectric layer 113 and the second interlayer dielectric layer 123 to form the first contact layer 271. Perform photolithography on the first contact layer 271, the first interlayer dielectric layer 113, and the second interlayer dielectric layer 123 to form the first via and the second via; deposit metal material in the first via and the second via to form the first source / drain metal 116 and the second source / drain metal 126 (see...). Figure 4B (c) In the figure, subsequent processes are performed on the first contact layer 271 to form a first metal interconnect layer and a second metal interconnect layer (not shown).

[0104] It should be noted that the first contact layer 271 can be made of the same material as the spacer wall (such as the first spacer wall 111 and the second spacer wall 121).

[0105] Step 7: After forming the first transistor 11 and the lateral diffusion device 12, an insulating material is deposited on the first transistor 11 and the lateral diffusion device 12 to form a first insulating layer 15. Then, the carrier wafer 16 is bonded to the first insulating layer 15 (see...). Figure 4C (a) in the middle.

[0106] Step 8: Flip the first transistor 11 and the lateral diffusion device 12, and remove the substrate 21 so that the second fin structure 222 faces upward (see...). Figure 4C (b) in the middle.

[0107] Step 9: Perform a second fin cutting process on the second fin structure 222 to form a second fin cutting groove 232 (see...) Figure 4C (c) in the figure. The lithography depth is the full-width depth.

[0108] Step 10: Fill the second fin trench 232 with oxide. Then, remove the oxide from the shallow trench isolation structure 25 and the second fin trench 232 by etching to expose the second fin structure 222 and form a shallow trench isolation layer 251. Deposit oxide on the surface of the exposed second fin structure 222 to form a second gate oxide layer 262. Form a third pseudo-gate structure 313 and a third spacer 131 on the second gate oxide layer 262 in the core region (see...). Figure 4D (a) in the middle.

[0109] Eleventh step: refer to the step of the fifth step above to form the third source-drain structure 132 in the second transistor 13 (see FIG. 8 (c)). Figure 4D

[0110] Twelfth step: refer to the step of the sixth step above to form the third interlayer dielectric layer 133, the third gate dielectric layer 134, the third gate structure 135, the second contact layer 272, the third source-drain metal 136 in the second transistor 13, and the fourth interlayer dielectric layer 143 in the isolation device 14 (see FIG. 8 (c)). And form the third metal interconnection layer in the second transistor 13 and the backside dielectric layer in the isolation device 14 (not shown in the figure). Figure 4D

[0111] Up to here, the semiconductor structure 10 has been prepared according to the first preparation method.

[0112] Figure 5 FIG. 9 is a schematic diagram of a second structure of a semiconductor structure in an embodiment of the present application. Figure 5 FIG. 9 (a) is a sectional view of the semiconductor structure along the A-A' direction of the lateral diffusion region; (b) is a sectional view of the semiconductor structure along the B-B' direction of the lateral diffusion region; (c) is a sectional view of the semiconductor structure along the A1-A1' direction of the core region; (d) is a sectional view of the semiconductor structure along the B1-B1' direction of the core region.

[0113] Figure 5 As shown in FIG. 9, the semiconductor structure 10, the first recess is formed in the first N-type drift region, the etching depth of the first fin structure is the half-amplitude depth, and the etching depth of the second fin structure is the half-amplitude depth.

[0114] The following describes the preparation process of the semiconductor structure 10 shown in FIG. 9 in combination with the preparation method described above. Figure 5 The following describes the preparation process of the semiconductor structure 10 shown in FIG. 9 in combination with the preparation method described above. Figure 5 The semiconductor structure 10 shown in FIG. 9 can be prepared by the flow shown in FIG. 10. Figure 6 The semiconductor structure 10 shown in FIG. 9 can be prepared by the flow shown in FIG. 10. Figure 6 FIG. 11 is a schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application.

[0115] In an example, the second preparation process of the semiconductor structure 10 can include the following steps:

[0116] First step: refer to the first preparation method above to form the first transistor 11 and the lateral diffusion device 12, after developing and removing the substrate of the first transistor 11 and the lateral diffusion device 12, perform second fin cutting processing on the second fin structure 222, and the etching depth is the half-amplitude depth to form the second fin cutting groove 232 (see FIG. 9 (a)). Figure 6

[0117] ​​​Second step: forming the second transistor 13 and the isolation device 14 according to the first preparation method (see Figure 6

[0118] At this point, the semiconductor structure 10 is prepared according to the second preparation method.

[0119] In the embodiment of the present application, when the first fin structure and the second fin structure are subjected to the photolithography processing, the etching depth is selected as the half-depth, which causes poor self-alignment between the front-side device (i.e., the first transistor and the lateral diffusion device) and the back-side device (i.e., the second transistor and the isolation device), and the etching misalignment phenomenon (as shown in Figure 5 It should be noted that, Figure 5 The above-mentioned semiconductor structure prepared by the second preparation method is only one example of the semiconductor structure prepared by the second preparation method, and cannot be used to limit all examples of the semiconductor structure prepared by the second preparation method. In some embodiments, the semiconductor structure prepared by the second preparation method can also not have the misalignment phenomenon between the front-side device and the back-side device.

[0120] Figure 7 FIG. 3 is a third structure schematic diagram of the semiconductor structure in the embodiment of the present application. Figure 7 (a) is a sectional view of the semiconductor structure along the A-A' direction of the lateral diffusion region; (b) is a sectional view of the semiconductor structure along the B-B' direction of the lateral diffusion region; (c) is a sectional view of the semiconductor structure along the A1-A1' direction of the core region; and (d) is a sectional view of the semiconductor structure along the B1-B1' direction of the core region.

[0121] Figure 7 The semiconductor structure 10 shown in FIG. 2, the first recess is formed in the second N-type drift region, the etching depth of the first fin structure is the half-depth, and the etching depth of the second fin structure is the half-depth. Among them, Figure 7 The semiconductor structure 10 shown in FIG. 2, the lateral diffusion device 12 is arranged side by side with the second transistor 13, and the preparation method of the lateral diffusion device 12 can refer to the preparation method of the lateral diffusion device 12 in the first preparation method; the isolation device 14 is arranged side by side with the first transistor 11, and the preparation method of the isolation device 14 can refer to the preparation method of the isolation device 14 in the first preparation method, and the preparation methods of other structures in the semiconductor structure 10 are the same as those in the first preparation method, and the embodiment of the present application will not be repeated here.

[0122] ​In the embodiment of the present application, by forming the first recess in the N-type drift region and filling the oxide in the first recess while performing the first fin cutting process on the first fin-shaped structure or performing the second fin cutting process on the second fin-shaped structure, the formed lateral diffusion device can withstand higher voltage while being compatible with the process of preparing the stacked transistors, thereby optimizing the preparation process of the semiconductor structure.

[0123] Further, since the second fin cutting process is performed on the second fin-shaped structure, different etching depths can be selected according to actual needs, that is, the etching depth of the second fin cutting process is equal to the height of the fin-shaped structure or equal to half of the height of the fin-shaped structure, so that the layout of the internal device of the semiconductor structure is more flexible.

[0124] Further, the semiconductor structure provided by the embodiment of the present application can be detected by detection analysis instruments, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), and the like. Taking the TEM as an example, the semiconductor structure provided by the embodiment of the present application can be detected in the TEM slice mode, for example, the lateral diffusion device is only distributed on the front surface or the back surface of the semiconductor structure, and the oxide in the first recess of the lateral diffusion device forms an A-shaped structure with the gate oxide layer (that is, the first gate oxide layer or the second gate oxide layer).

[0125] Further, the preparation method of the semiconductor structure described in the embodiment of the present application can be applied to the next generation integrated circuit process, and is a process-compatible LDMOS transistor scheme, which has great application potential.

[0126] The embodiment of the present application provides a semiconductor device, including: the semiconductor structure as described in the above embodiments. The specific limitation of the semiconductor structure can be referred to the semiconductor structure as shown in the above Figure 3 、 Figure 5 and Figure 7 , which will not be repeated here.

[0127] The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific limitation of the semiconductor structure can be referred to the semiconductor structure as shown in the above Figure 3 、 Figure 5 and Figure 7 , which will not be repeated here.

[0128] In the description of the application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are contained in at least one embodiment or example of the embodiments of the application. In the present application, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0129] The above is only the preferred embodiment of the present application, and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The semiconductor structure includes a lateral diffusion device and a core device. The core device includes a first transistor and a second transistor stacked along a first direction. The semiconductor structure also includes a lateral diffusion device, which is arranged side by side with the first transistor or side by side with the second transistor. The method includes: A substrate is provided; the substrate includes a lateral diffusion region and a core region; the lateral diffusion region and the core region are disposed adjacent to each other in a second direction; the second direction is perpendicular to the first direction; Ion implantation is performed in the lateral diffusion region to form a P-type trap region and an N-type drift region; The lateral diffusion region and the core region are etched to form a fin-like structure; the fin-like structure includes a first fin-like structure and a second fin-like structure stacked along the first direction; The first fin structure is subjected to a first fin cutting process to form a first fin cutting groove; the first fin cutting groove is perpendicular to the extension direction of the first fin structure; the etching depth of the first fin cutting process is half the height of the fin structure; Fill the first fin groove with oxide; The first transistor is formed based on the first fin structure; The wafer is then poured and the substrate is removed. The second fin structure is subjected to a second fin cutting process to form a second fin cutting groove; the second fin cutting groove is perpendicular to the extension direction of the second fin structure; the etching depth of the second fin cutting process is equal to the height of the fin structure or equal to half the height of the fin structure; The oxide is filled into the second fin groove; The second transistor is formed based on the second fin structure; The method further includes: while performing a first fin-cutting process on the first fin structure, forming a first groove in the N-type drift region corresponding to the first fin structure, and forming the lateral diffusion device based on the first groove; or, while performing a second fin-cutting process on the second fin structure, forming a first groove in the N-type drift region corresponding to the second fin structure, and forming the lateral diffusion device based on the first groove; the first groove is used to fill the oxide.

2. The method according to claim 1, characterized in that, The first fin-cutting process performed on the first fin-like structure to form the first fin-cutting groove includes: The first fin structure is subjected to a first fin cutting process to form a first fin cutting groove in the core region corresponding to the first fin structure and a first groove in the N-type drift region corresponding to the first fin structure. The step of filling the first fin groove with oxide includes: The oxide is deposited on the fin structure and the substrate to form a shallow trench isolation structure; the shallow trench isolation structure encloses the fin structure and fills the first groove and the first fin cut trench.

3. The method according to claim 2, characterized in that, The formation of the first transistor based on the first fin structure includes: Based on the first fin structure, a first pseudo-gate structure in the first transistor and a second pseudo-gate structure in the lateral diffusion device are formed. A portion of the first fin structure is etched to form a first source drain groove and a second source drain groove; Source drain epitaxial growth is performed in the first source drain groove and the second source drain groove to form the first source drain structure in the first transistor and the second source drain structure in the lateral diffusion device; Remove the first pseudo-gate structure and the second pseudo-gate structure to form the first gate structure in the first transistor and the second gate structure in the lateral diffusion device; A first source / drain metal in the first transistor and a second source / drain metal in the lateral diffusion device are formed on the first source / drain structure and the second source / drain structure; Back-end processing is performed on the first gate structure, the second gate structure, the first source / drain metal, and the second source / drain metal to form a first metal interconnect layer in the first transistor and a second metal interconnect layer in the lateral diffusion device.

4. The method according to claim 2, characterized in that, The second transistor is formed based on the second fin structure, including: Based on the second fin structure, a third pseudo-gate structure is formed in the second transistor; A portion of the second fin structure is etched to form a third source drain groove; Source-drain epitaxial growth is performed in the third source-drain groove to form the third source-drain structure in the second transistor; Remove the third pseudo-gate structure and form the third gate structure in the second transistor; The third source / drain metal of the second transistor is formed on the third source / drain structure; Back-end processing is performed on the third gate structure and the third source / drain metal to form the third metal interconnect layer in the second transistor and the back dielectric layer in the isolation device; the lateral diffusion device and the isolation device are stacked along the first direction.

5. The method according to claim 1, characterized in that, The second fin-cutting process performed on the second fin-like structure to form a second fin-cutting groove includes: The second fin structure is subjected to a second fin cutting process to form a second fin cutting groove in the core region corresponding to the second fin structure, and to form the first groove in the N-type drift region corresponding to the second fin structure; The step of filling the second fin groove with the oxide includes: The oxide is filled into the second fin groove and the first groove.

6. The method according to claim 5, characterized in that, The formation of the first transistor based on the first fin structure includes: Based on the first fin structure, a first pseudo-gate structure is formed in the first transistor; A portion of the first fin structure is etched to form a first source / drain groove; Source-drain epitaxial growth is performed in the first source-drain groove to form the first source-drain structure in the first transistor; Remove the first dummy gate structure and form the first gate structure in the first transistor; The first source / drain metal of the first transistor is formed on the first source / drain structure; Back-end processing is performed on the first gate structure and the first source / drain metal to form the first metal interconnect layer in the first transistor and the front dielectric layer in the isolation device; the isolation device and the lateral diffusion device are stacked along the first direction.

7. The method according to claim 5, characterized in that, The second transistor is formed based on the second fin structure, including: Based on the second fin structure, a third pseudo-gate structure is formed in the second transistor and a second pseudo-gate structure is formed in the lateral diffusion device; A portion of the second fin structure is etched to form a third source drain groove and a second source drain groove; Source-drain epitaxial growth is performed in the third source-drain groove and the second source-drain groove to form the third source-drain structure in the second transistor and the second source-drain structure in the lateral diffusion device; Remove the third pseudo-gate structure and the second pseudo-gate structure to form the third gate structure in the second transistor and the second gate structure in the lateral diffusion device; The third source / drain metal in the second transistor and the second source / drain metal in the lateral diffusion device are formed on the third source / drain structure and the second source / drain structure; Back-end processing is performed on the third gate structure, the second gate structure, the third source / drain metal, and the second source / drain metal to form the third metal interconnect layer in the second transistor and the second metal interconnect layer in the lateral diffusion device.

8. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method described in any one of claims 1 to 7, wherein the semiconductor structure comprises: Core components; the core components include a first transistor and a second transistor stacked along the first direction; Lateral diffusion device; the lateral diffusion device is arranged side by side with the first transistor or side by side with the second transistor; An isolation device; the isolation device and the lateral diffusion device are stacked in the first direction; The lateral diffusion device includes a P-type well region and an N-type drift region; a first groove is provided in the N-type drift region of the lateral diffusion device, and the first groove is used to fill oxide.

9. A semiconductor device, characterized in that, include: The semiconductor structure as described in claim 8.

10. An electronic device, characterized in that, include: The circuit board and the semiconductor device as described in claim 9, wherein the semiconductor device is disposed on the circuit board.

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