Package-level DFT (Discrete Fourier Transform) structure

Abstract

The invention relates to a packaging-level DFT structure, and the structure comprises a substrate which is provided with a daisy chain communication network, and the daisy chain communication network is electrically connected with a third bonding pad. A fourth bonding pad and a fifth bonding pad are fixedly arranged on the substrate, and one end of the fifth bonding pad is connected with a ground network; when the daisy chain communication network is tested, the fourth bonding pad and the third bonding pad are connected with a jumper resistor, and the fourth bonding pad extends to the outer side of the substrate and is connected with a test network. When the daisy chain communication network works, the jumper resistor is connected between the fourth bonding pad and the fifth bonding pad. In the research and development stage, a jumper resistor interconnects a signal with a test network and leads the signal to a solder ball, and the signal quality and the working state of a chip are evaluated by using a physical test means for the test network, so that the problem that an internal interconnection structure of the system-in-package cannot be tested is solved; in the mass production stage, in order to prevent the test network from being isolated and suspended in the package, the test network is interconnected to the ground network through the bridging resistor, and EMI-related electromagnetic interference possibly brought by the test network is weakened.

Description

Technical Field

[0001] The present invention relates to the field of packaging and testing of semiconductor integrated circuits, and in particular to a packaging-level testing structure. Background Art

[0002] With the continuous upgrading and modularization of electronic devices, the packaging technology of integrated circuits (ICs) has also experienced significant development, especially in the fields of modern consumer electronics, communication equipment, automotive electronics and industrial control. System-in-Package (SiP) technology has been widely used due to its excellent integration, small size and excellent performance. System-in-Package can integrate multiple integrated circuits and other electronic components in one package, thereby improving the functional density of the product, shortening the signal path, improving the overall performance, and reducing manufacturing costs. However, this highly integrated packaging form also brings new challenges, especially in the testing and verification stages.

[0003] Traditional testing methods rely on testing and verifying the external pins of the package. Testers directly contact the pins or solder balls of the chip through physical means (such as probe testing, boundary scan testing, etc.) to test the quality of the chip signal. Due to the complex structure, dense wiring, and direct connection of signals between chips inside the SiP, the structure is often covered and hidden by the packaging material, making it impossible for the probe to reach. Although the boundary scan method can solve the problem of invisible signals inside some packages, its coverage is limited. For more complex SiP structures, the test effect is not ideal.

[0004] Therefore, the industry has gradually turned to non-physical contact testing methods such as code testing and simulation testing. These methods evaluate the function and performance of the chip by sending test vectors to the chip and observing the chip's response. However, these methods also have certain limitations. First, code testing requires writing complex test programs, and the test cycle is long. The test is often a test of a certain function and cannot reflect the details of the signal quality on the line; second, simulation testing requires building an accurate simulation model, which is time-consuming and resource-consuming; finally, these test methods are often difficult to fully cover all functions and scenarios of SiP, especially for the complex interconnection structure and signal transmission path inside the package, the test effect is even more limited.

[0005] Due to the limitations of the test methods, the testing cost of SiP has also increased. In order to ensure the comprehensiveness and accuracy of the test, testers often need to design multiple test schemes and conduct multiple rounds of test verification. This not only increases the test time and labor costs, but may also lead to a waste of test resources. In addition, due to the complexity and high integration of SiP, once a fault or problem is found during the test process, in-depth troubleshooting and location work is often required, which further increases the test cost and time. Summary of the invention

[0006] The purpose of the implementation of the present invention is to provide a packaging-level test structure, so that during the product testing phase, the internal directly connected network can be tested by physical means; electromagnetic interference is avoided during the mass production phase, thereby meeting the different requirements of the testing phase and the mass production phase.

[0007] A package-level DFT structure proposed in the present invention comprises: a substrate, on which a daisy chain communication network is arranged, and the daisy chain communication network is electrically connected to a third pad; a fourth pad and a fifth pad are fixedly arranged on the substrate, and one end of the fifth pad is connected to a ground network;

[0008] When the daisy chain communication network is tested:

[0009] The fourth pad is connected to the third pad via a jumper resistor, and the fourth pad is extended to the outside of the substrate and connected to a test network extension component;

[0010] The daisy chain communication network works as follows:

[0011] The jumper resistor is connected between the fourth pad and the fifth pad.

[0012] Preferably, the third pad is electrically connected to the first pad, and the connection distance is less than or equal to 0.5 mm.

[0013] Preferably, the daisy chain communication network includes: a driving chip and at least one receiving chip installed on a substrate, the driving chip and the receiving chip are electrically connected to a first pad, the first pad is connected to one end of a second pad through a termination resistor, and the other end of the second pad is connected to a power supply network.

[0014] Preferably, the second pad includes but is not limited to being directly electrically interconnected with the power source, being electrically interconnected with the power source via an AC coupling capacitor, or being electrically interconnected with the ground network.

[0015] Preferably, the driving chip includes but is not limited to MCU, SoC, FPGA or DSP, one or a combination of several having control computing functions.

[0016] Preferably, the receiving chip type includes but is not limited to one or a combination of RAM, ROM or Flash Memory digital storage types.

[0017] Preferably, the fourth pad is connected to the test network extension component via a solder ball.

[0018] Preferably, the fifth pad is connected to the ground network through a metal wire.

[0019] Preferably, the test network extension component comprises: a printed circuit board, on which a test pad is mounted, and the test pad is electrically connected to the fourth pad via an interconnection network.

[0020] Preferably, there is at least one group of test networks, and the number of the test networks is less than the daisy chain communication networks.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] During the research and development stage, jumper resistors interconnect the signal with the test network and lead it out to the solder balls. By using physical testing methods on the test network extension components, the signal quality, chip working status, etc. are evaluated, solving the problem that the internal interconnection structure of the system-level package cannot be tested. In the mass production stage, in order to avoid the test network from being isolated and suspended inside the package, jumper resistors interconnect the test network to the ground network to reduce EMI-related electromagnetic interference that may be caused by the test network. At the same time, the third pad is always interconnected with the first pad. The closer distance between the two pads makes the signal "stub line" shorter to reduce the signal reflection at the end of the interconnection line. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of the packaging test structure of the present invention;

[0024] FIG2( a ) is a schematic diagram of the packaging structure in the test phase of Example 1 of the present invention;

[0025] FIG2( b ) is a schematic diagram of the packaging structure of Example 1 of the present invention at the mass production stage;

[0026] FIG3( a ) is a schematic diagram of receiving performance of a first receiving chip in an embodiment of the present invention;

[0027] FIG3( b ) is a schematic diagram of the receiving performance of the second receiving chip in an embodiment of the present invention;

[0028] FIG3( c ) is a partially enlarged diagram of the performance diagram of two receiving chips in an embodiment of the present invention;

[0029] In the figure, 101 is a substrate; 102 is a driver chip; 103 is a daisy-chain communication network; 104 is a receiving chip; 105 is a first pad; 106 is a second pad; 107 is a termination resistor; 108 is a power supply interconnection network; 109 is a power supply network; 110 is a third pad; 111 is a signal interconnection network; 112 is a fourth pad; 113 is a jumper resistor; 114 is a test interconnection network; 115 is a solder ball; 116 is a fifth pad; 117 is a ground network; 118 is a printed circuit board; 119 is a printed circuit board 118 interconnection network; 120 is a test pad. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] like Figure 1 As shown in FIG. 3(C) , the present invention provides a technical solution: a package-level DFT structure, comprising: a substrate 101 , on which a daisy chain communication network 103 is arranged.

[0032] The daisy chain communication network 103 includes: a driving chip 102 and at least one receiving chip 104 mounted on a substrate 101, wherein the driving chip 102 and the receiving chip 104 are electrically connected to a first pad 105, the first pad 105 is connected to one end of a second pad 106 via a termination resistor 107, and the other end of the second pad 106 is connected to a power supply network 109. The second pad 106 includes but is not limited to being electrically interconnected with the power supply network 109 directly, electrically interconnected with the power supply network 109 via an AC coupling capacitor, or electrically interconnected with a ground network.

[0033] Daisy chain communication network 103: In this embodiment, the daisy chain communication network 103 is specifically one of the address, control, command and other signals of DDR. In the system-level package circuit, its link includes the signal pin bumps of the driver chip 102, the electrical connection holes and metal wires on the substrate 101, the signal pin bumps of the receiving chip 104, the termination resistor 107, the power supply interconnection network 108 and the power supply network 109. The signal quality is optimized through simulation. In this embodiment, the termination form of the resistor pull-up to the power supply is adopted;

[0034] The driver chip 102 is mounted on the substrate 101 and is electrically interconnected with the substrate 101 by means of, but not limited to, flip-chip bonding, wire bonding, etc. In this embodiment, a field programmable gate array chip (FPGA) is used to provide data processing and data calculation functions for the system;

[0035] The driving chip 102 includes but is not limited to MCU, SoC, FPGA or DSP, one or a combination of several having control computing functions.

[0036] The receiving chip 104 is mounted on the substrate 101 and is electrically interconnected with the substrate 101 by means of, but not limited to, flip-chip bonding, wire bonding, etc. In this embodiment, two double data rate synchronous dynamic random access memory (DDR) chips are used to provide data caching and data storage functions for the system;

[0037] The type of the receiving chip 104 includes but is not limited to one or a combination of RAM, ROM or Flash Memory digital storage types.

[0038] Termination resistor 107: soldered between the first pad 105 and the second pad 106 on the substrate 101. This embodiment uses a chip resistor with a package size of 0201 to save internal wiring space of the package.

[0039] The daisy chain communication network 103 is electrically connected with a third pad 110, which is arranged on the substrate 101. To avoid signal integrity issues, the first pad 105 and the third pad 110 are interconnected with a relatively close spacing in any case. In this embodiment, a copper foil with the same width as the pad is used for connection. The third pad 110 is electrically connected to the first pad 105 through a signal interconnection network 111, and the connection distance is less than or equal to 0.5 mm, preferably 0.5 mm; 0.4 mm or 0.2 mm can also be used. The closer distance between the two pads makes the "stub line" of the signal shorter to reduce the reflection of the signal at the end of the interconnection line.

[0040] The substrate 101 is fixedly provided with a fourth pad 112 and a fifth pad 116 . One end of the fifth pad 116 is connected to a ground network 117 . The fifth pad 116 is connected to the ground network 117 through a metal wire.

[0041] The fourth pad 112 is a multiplexed pad. The fifth pad 116 is disposed on the ground network 117 or interconnected to the ground network 117 through metal wires, electrical connection holes, etc.;

[0042] When testing the daisy chain communication network 103:

[0043] A jumper resistor 113 is connected between the fourth pad 112 and the third pad 110 , and the fourth pad 112 extends to the outside of the substrate 101 and is connected to a test network extension component;

[0044] When the daisy chain communication network 103 is working:

[0045] The jumper resistor 113 is connected between the fourth pad 112 and the fifth pad 116 .

[0046] The fourth pad 112 is connected to the test network extension component through a solder ball 115 .

[0047] A test interconnection network 114 is connected between the fourth pad 112 and the solder ball 115 .

[0048] There is at least one group of test networks, and the number of the test networks is less than the daisy-chain communication networks 103 .

[0049] The test network includes: a fourth pad, an electrical interconnection structure and a solder ball assembly, and the test network extension assembly is connected via the solder ball assembly.

[0050] The test network extension component includes: a printed circuit board 118 , on which a test pad 120 is mounted, the test pad 120 is electrically connected to the solder ball 115 through a printed circuit board interconnection network 119 , and the solder ball 115 is electrically connected to the fourth pad 112 through a test interconnection network 114 .

[0051] Printed circuit board 118: Referring to FIG. 2( a ), the test network extension component externally packaged on the substrate 101 is soldered to the printed circuit board 118 via solder balls 115 , and is electrically interconnected with the test pads 120 provided on the printed circuit board 118 , thereby forming a complete test network extension component.

[0052] In the development and testing stage, referring to FIG. 2( a ), a jumper resistor 113 is installed between the third pad 110 and the fourth pad 112 , and the signal of the daisy chain communication network 103 is connected to the test network and externally led to the solder ball 115 .

[0053] In the mass production stage, referring to FIG. 2( b ), a jumper resistor 113 is installed between the fourth pad 112 and the fifth pad 116 to short-circuit the test network to the ground network 117 .

[0054] ① The original topology link structurally only includes the first pad 105, the second pad 106 and the termination resistor 107;

[0055] ② The test network is enabled, a jumper resistor 113 is installed between the third pad 110 and the fourth pad 112, and the signal test endpoint is the solder ball 115;

[0056] ③ The test network is enabled, a jumper resistor 113 is installed between the third pad 110 and the fourth pad 112, and the signal test end point is the test pad 120 on the printed circuit board 118;

[0057] ④ Disable the test network, install a jumper resistor 113 between the fourth and fifth pads 116, and the third pad 110 is a suspended stub line. In the figure, case 1, case 2, case 3, and case 4 correspond to the above cases ①, ②, ③, and ④ respectively.

[0058] Referring to FIG. 3( a ), FIG. 3( b ) and FIG. 3( c ), FIG. 3( c ) is a partial enlarged view of FIG. 3( a ) and FIG. 3( b ).

[0059] Case ③: Due to the long external signal, a certain degree of signal reflection occurs at the receiving chip 104, causing rising edge distortion and voltage callback, but the amplitude still meets the requirements of high and low level thresholds and steady-state level timing, and can meet the needs of the test phase;

[0060] In case ④, the suspended third pad 110 also causes a certain signal reflection at the receiving chip 104, which causes rising edge distortion. Compared with case ①, the eye width only differs by about 8 picoseconds, which meets the performance requirements of the mass production stage.

[0061] The embodiments of the present invention disclose preferred embodiments, but are not limited thereto. A person skilled in the art can easily understand the spirit of the present invention based on the above embodiments and make different extensions and changes. However, as long as they do not deviate from the spirit of the present invention, they are all within the protection scope of the present invention.

Claims

1. A package-level DFT structure, comprising: A substrate, wherein a daisy chain communication network is arranged on the substrate, and the daisy chain communication network is electrically connected to a third pad; wherein the substrate is fixedly provided with a fourth pad and a fifth pad, and one end of the fifth pad is connected to a ground network; When the daisy chain communication network is tested: The fourth pad is connected to the third pad via a jumper resistor, and the fourth pad is extended to the outside of the substrate and connected to a test network extension component; The daisy chain communication network works as follows: The jumper resistor is connected between the fourth pad and the fifth pad.

2. The package-level DFT structure according to claim 1, characterized in that: The third pad is electrically connected to the first pad, and the connection distance is less than or equal to 0.5 mm.

3. The package-level DFT structure according to claim 1, characterized in that: The daisy chain communication network includes: a driving chip and at least one receiving chip installed on a substrate, the driving chip and the receiving chip are electrically connected to a first pad, the first pad is connected to one end of a second pad through a termination resistor, and the other end of the second pad is connected to a power supply network.

4. The package-level DFT structure according to claim 3, characterized in that: The second pad includes but is not limited to being electrically interconnected with a power source directly, being electrically interconnected with a power source via an AC coupling capacitor, or being electrically interconnected with a ground network.

5. The package-level DFT structure according to claim 3, characterized in that: The driving chip includes but is not limited to MCU, SoC, FPGA or DSP, one or a combination of several having control computing functions.

6. The package-level DFT structure according to claim 3, characterized in that: The receiving chip type includes but is not limited to one or a combination of RAM, ROM or Flash Memory digital storage types.

7. The package-level DFT structure according to claim 1, characterized in that: The fourth pad is connected to the test network extension component through a solder ball.

8. The package-level DFT structure according to claim 1, characterized in that: The fifth pad is connected to the ground network through a metal wire.

9. The package-level DFT structure according to claim 1, characterized in that: The test network extension component comprises: a printed circuit board, on which a test pad is mounted, and the test pad is electrically connected to a fourth pad through an interconnection network.

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