Gate Oxide Integrity Test Structure

Abstract

The present invention provides a gate oxide integrity test structure. The gate oxide integrity test structure includes an active area formed in a substrate and a gate oxide layer, a gate electrode and a positioning structure stacked from bottom to top on the substrate; the positioning structure is located in a first metal layer above the gate electrode, the positioning structure includes a plurality of positioning units arranged in an array, a marking pattern in each positioning unit independently numbers each positioning unit, and the positioning structure uses the positioning unit to locate the position of a failure point in the gate oxide layer. In this way, the gate oxide integrity test structure can accurately locate the position of the failure point, improve the efficiency of failure analysis, have a wide range of applications and strong process feasibility.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a gate oxide integrity test structure. Background Art

[0002] In the semiconductor field, Gate Oxide Integrity (GOI) testing is a common test method to verify the quality of the gate oxide layer. It can be used to detect whether there are defects in the gate oxide layer and prevent the gate oxide layer defects from causing a decrease in device reliability. It is usually necessary to form a special gate oxide integrity test structure on the wafer.

[0003] For samples with abnormal gate oxide integrity test, failure analysis is required to find the root cause of gate oxide integrity failure and optimize the process. Due to the large area of ​​the gate oxide integrity test structure, electrical testing is required to locate the failure point, i.e. hot spot analysis; then the hot spot position is de-layered, and after the failure point is found, cross-section cutting is performed to prepare cross-section samples, and then the root cause of the gate oxide integrity failure is obtained through scanning electron microscopy observation and elemental analysis.

[0004] However, if the failure point cannot be accurately located, it is easy to miss the actual failure position when making cross-sectional samples, which affects the analysis efficiency. Summary of the invention

[0005] One of the purposes of the present invention is to provide a gate oxide integrity test structure that can accurately locate the failure point, improve the efficiency of failure analysis, have a wide range of applications and strong process feasibility.

[0006] In order to achieve the above-mentioned purpose, the gate oxide integrity test structure provided by the present invention includes an active area formed in a substrate and a gate oxide layer, a gate electrode and a positioning structure stacked from bottom to top on the substrate; the positioning structure is located in the first metal layer above the gate electrode, and the positioning structure includes a plurality of positioning units arranged in an array, and the marking pattern in each of the positioning units independently numbers each of the positioning units, and the positioning structure uses the positioning unit to locate the failure point position in the gate oxide layer.

[0007] Optionally, each of the positioning units includes multiple first marking graphics, at least one second marking graphic and at least one third marking graphic; for one positioning unit, multiple first marking graphics are arranged in a row, and the second marking graphics and the third marking graphics are arranged on the sides of the multiple first marking graphics, and the number of rows of the positioning unit in the positioning structure is marked by the number of the second marking graphics and the positional relationship between the second marking graphics and the multiple first marking graphics, and the number of columns of the positioning unit in the positioning structure is marked by the number of the third marking graphics and the positional relationship between the third marking graphics and the multiple first marking graphics, and the multiple first marking graphics are also used to mark the position of the failure point in the area where the positioning unit is located.

[0008] Optionally, in one of the positioning units, the second marking pattern is arranged on one side of the plurality of first marking patterns, and the third marking pattern is arranged on the other side of the plurality of first marking patterns.

[0009] Optionally, the shapes of the second marking graphic and the third marking graphic are the same or different.

[0010] Optionally, the first marking graphic is a rectangle, and the second marking graphic and the third marking graphic are both square or circular.

[0011] Optionally, the number of the first mark graphics in all the positioning units is k; for one positioning unit, when the number of the second mark graphics is one and the second mark graphics is located on the side of the i-th first mark graphics, it indicates that the positioning unit is a positioning unit in the i-th row; for one positioning unit, when the number of the second mark graphics is two, one second mark graphics is located on the side of the i-th first mark graphics and the other second mark graphics is located on the side of the j-th first mark graphics, it indicates that the positioning unit is a positioning unit in the i+j-th row; k is a positive integer greater than or equal to 2, and i and j are both positive integers less than or equal to k.

[0012] Optionally, for one of the positioning units, when the number of the third mark graphics is one and the third mark graphics is located on the side of the m-th first mark graphics, it indicates that the positioning unit is a positioning unit in the m-th column; for one of the positioning units, when the number of the third mark graphics is two, one of the third mark graphics is located on the side of the m-th first mark graphics and the other of the third mark graphics is located on the side of the n-th first mark graphics, it indicates that the positioning unit is a positioning unit in the m+n-th column; m and n are both positive integers less than or equal to k.

[0013] Optionally, the active area is in the shape of a whole block or is separated into a plurality of strip-shaped active areas by a plurality of isolation structures; the gate electrode is in the shape of a whole block, or the gate electrode includes a plurality of strip-shaped gates.

[0014] Optionally, the plurality of positioning units of the positioning structure are arranged by dichotomy.

[0015] Optionally, the positioning structure and the gate electrode, as well as the positioning structure and the substrate are isolated by a dielectric layer.

[0016] The gate oxide integrity test structure provided by the present invention includes an active area formed in a substrate and a gate oxide layer, a gate electrode and a positioning structure stacked from bottom to top on the substrate, wherein the positioning structure is located in a first metal layer above the gate electrode, and the positioning structure includes a plurality of positioning units arranged in an array, and a marking pattern in each of the positioning units independently labels each of the positioning units, and the positioning structure uses the positioning unit to locate the position of the failure point in the gate oxide layer. In the present application, the marking pattern in each positioning unit of the positioning structure independently labels each positioning unit, and the positioning structure can accurately locate the position of the failure point of the gate oxide layer, which can improve the efficiency of failure analysis, and the positioning structure is formed in the first metal layer so that the setting position of the positioning unit in the positioning structure is not limited by the active area pattern and the gate electrode pattern, thereby expanding the scope of application of the gate oxide integrity test structure and having strong process feasibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic top view of a gate oxide integrity test structure provided by an embodiment of the present invention.

[0018] Figure 2 A partial cross-sectional schematic diagram of a gate oxide integrity test structure provided by an embodiment of the present invention.

[0019] Explanation of the reference numerals: 10 - active area; 11 - gate oxide layer; 12 - gate electrode; 13 - dielectric layer; 14 - positioning structure; 140 - positioning unit; 141 - first marking pattern; 142 - second marking pattern; 143 - third marking pattern. DETAILED DESCRIPTION

[0020] The gate oxide integrity test structure of the present application is provided with a positioning structure in the first metal layer above the gate electrode, wherein the positioning structure includes a plurality of positioning units arranged in an array, and a marking pattern in each positioning unit independently labels each positioning unit, so that the position of the failure point in the gate oxide layer can be accurately located by using the positioning unit, thereby improving the efficiency of failure analysis, and because the positioning structure is formed in the first metal layer, the positioning unit is not in contact with the active area and the gate electrode, so that the setting position of the positioning unit is not restricted by the active area pattern and the gate electrode pattern, thereby expanding the application scope of the gate oxide integrity test structure, and the positioning structure can be synchronously formed in the manufacturing process of the first metal layer, thereby enhancing the process feasibility of the gate oxide integrity test structure.

[0021] The gate oxide integrity test structure proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0022] It should be understood that in the description of the present application, it should be understood that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or more features. In the description of the present application, "multiple" means two or more, and at least one means one, two, or more than two, unless otherwise clearly and specifically defined.

[0023] Figure 1 A schematic top view of a gate oxide integrity test structure provided by an embodiment of the present invention. Figure 2 A partial cross-sectional schematic diagram of a gate oxide integrity test structure provided by an embodiment of the present invention.

[0024] refer to Figure 1 and Figure 2As shown, the gate oxide integrity test structure includes an active area 10 formed in a substrate and a gate oxide layer 11, a gate electrode 12 and a positioning structure 14 stacked from bottom to top on the substrate; the positioning structure 14 is located in the first metal layer above the gate electrode 12, and the positioning structure 14 includes a plurality of positioning units 140 arranged in an array, and the marking pattern in each of the positioning units 140 independently numbers each of the positioning units 140, and the positioning structure 14 uses the positioning unit 140 to locate the failure point position in the gate oxide layer 11.

[0025] Exemplarily, each positioning unit 140 includes a plurality of first marking patterns 141, at least one second marking pattern 142, and at least one third marking pattern 143. For one positioning unit 140, a plurality of the first marking patterns 141 are arranged in a row, and the second marking pattern 142 and the third marking pattern 143 are arranged on the side of the first marking pattern 141, wherein the number of rows of the positioning unit 140 in the positioning structure 14 is marked by the number of the second marking patterns 142 and the positional relationship between the second marking pattern 142 and the plurality of first marking patterns, and the number of columns of the positioning unit 140 in the positioning structure 14 is marked by the number of the third marking patterns 143 and the positional relationship between the third marking pattern 143 and the plurality of first marking patterns 141, and the plurality of first marking patterns 141 are also used to mark the position of the failure point in the area where the positioning unit is located.

[0026] In this embodiment, Figure 1 As shown, in one of the positioning units 140, the second marking pattern 142 is arranged on one side of the plurality of first marking patterns 141, and the third marking pattern 143 is arranged on the other side of the plurality of first marking patterns 141, so that the second marking pattern 142 and the third marking pattern 143 do not occupy each other's setting space, which facilitates the setting of the second marking pattern 142 and the third marking pattern 143, and even if the second marking pattern 142 and the third marking pattern 143 have the same shape, they can be distinguished. In this embodiment, the shapes of the second marking pattern 142 and the third marking pattern 143 can be the same or different.

[0027] In other embodiments, in one of the positioning units 140, the second marking graphic 142 and the third marking graphic 143 can be set on the same side of the plurality of first marking graphics 141. In this case, in order to distinguish the second marking graphic 142 from the third marking graphic 143, the shapes of the second marking graphic 142 and the third marking graphic 143 need to be different.

[0028] For example, the first marking graphic 141 may be a rectangle, and the second marking graphic 142 and the third marking graphic 143 may be a square or a circle, but the invention is not limited thereto.

[0029] For example, Figure 1 As shown, in the positioning structure 14, Figure 1 The horizontal direction is the row direction, all the first mark graphics 141 in the positioning units 140 of the same row are arranged in the same row, all the second mark graphics 142 in the positioning units 140 of the same row are located on one side of the first mark graphic row, and all the third mark graphics 143 in the positioning units 140 of the same row are located on the other side of the first mark graphic row.

[0030] like Figure 1 As shown, in the positioning structure 14, the number of first marking patterns 141 in all positioning units 140 is equal. In the same positioning unit, the spacing between two adjacent first marking patterns 141 is equal, and in all positioning units, the spacing between two adjacent first marking patterns 141 is equal. Figure 1 The vertical direction is the column direction. In the same column of the positioning units, the multiple first marking patterns 141 of the positioning units are arranged in multiple columns.

[0031] In this embodiment, the plurality of positioning units of the positioning structure can be arranged by a binary method. Specifically, in the row direction and / or column direction, firstly, based on the layout of the gate oxide integrity test structure, a positioning unit at the center position is set on the 1 / 2 axis of the gate oxide integrity test structure layout, and then positioning units are set on the 1 / 4 axis and the 3 / 4 axis of the gate oxide integrity test structure layout, and then positioning units are set on the side of the 1 / 4 axis away from the 1 / 2 axis and on the side of the 3 / 4 axis away from the 1 / 2 axis, wherein the centers of the positioning units are all set on the corresponding axes.

[0032] It should be noted that the aspect ratio and number of the first mark pattern 141 in the positioning unit can be adjusted according to the layout size of the gate oxide integrity test structure (i.e., the length and width of the layout of the gate oxide integrity test structure). In this embodiment, the sizes of the first mark pattern 141, the second mark pattern 142, and the third mark pattern 143 need to meet the design rules of the first metal layer. Specifically, the widths of the first mark pattern 141, the second mark pattern 142, and the third mark pattern 143 and the spacing therebetween need to meet the design rules of the first metal layer.

[0033] refer to Figure 2As shown, in this embodiment, the first metal layer where the positioning structure 14 is located is the first metal layer on the gate electrode 12, and the first metal layer and the gate electrode 12 as well as the first metal layer and the substrate are isolated by the dielectric layer 13. In other words, the positioning structure 14 and the gate electrode 12 as well as the positioning structure 14 and the substrate are isolated by the dielectric layer 13.

[0034] It should be noted that, since the positioning structure 14 is not in direct contact with the substrate and the gate electrode 12, the setting of the positioning structure does not affect the electrical test of the gate oxide integrity test structure, so that the setting position of the positioning unit in the positioning structure is not limited by the active area pattern and the gate electrode pattern. In the prior art, if the positioning structure is not set in the area corresponding to the gate oxide integrity test structure in the first metal layer, it is necessary to lay a Dummy structure in the area to fill it. The present application replaces the Dummy structure with the positioning structure 14, which does not affect the process technology of the first metal layer and enhances the process feasibility of the gate oxide integrity test structure.

[0035] Exemplarily, the active region 10 may be in a block or may be separated into a plurality of strip-shaped active regions by a plurality of isolation structures. The isolation structure may be a shallow trench isolation structure formed in the substrate, but is not limited thereto. The gate electrode 12 may be in a block or may include a plurality of strip-shaped gates.

[0036] Specifically, in one embodiment, the active area 10, the gate oxide layer 11 and the gate electrode 12 are all in a block shape, and the gate oxide layer 11 and the gate electrode 12 sequentially cover the active area 10. In one embodiment, the active area 10 is divided into multiple strip-shaped active areas by multiple isolation structures, the gate oxide layer 11 and the gate electrode 12 are all in a block shape, and the gate oxide layer 11 and the gate electrode 12 cover multiple strip-shaped active areas. In one embodiment, the active area 10 and the gate oxide layer 11 are all in a block shape, and the gate electrode 12 includes multiple strip-shaped gates.

[0037] When the gate oxide integrity test structure is used to perform the gate oxide integrity test, an electrical test is first performed to locate the failure point of the gate oxide layer, and then the failure point is removed to the first metal layer, and then the failure point is located using the positioning structure 14 of the gate oxide integrity test structure. When the positioning structure 14 is used to locate the failure point, the positioning is performed through the marking pattern of the positioning unit 140.

[0038] Specifically, refer to Figure 1 As shown, the number of first marking patterns 141 in all positioning units 140 is k; for one positioning unit 140, the number of second marking patterns 142 is one and the second marking pattern 142 is located on the side of the i-th first marking pattern 141 (i.e. Figure 1When the number of second marking graphics 142 for a positioning unit 140 is two, one second marking graphic 142 is located on the side of the i-th first marking graphic 141 and the other second marking graphic 142 is located on the side of the j-th first marking graphic 141, it indicates that the positioning unit 140 is a positioning unit of the i+j-th row; k is a positive integer greater than or equal to 2, and i and j are both positive integers less than or equal to k.

[0039] Continue to refer Figure 1 As shown, for one positioning unit 140, the number of the third marking pattern 143 is one and the third marking pattern 143 is located on the side of the mth first marking pattern 141 (ie Figure 1 When the number of third marking patterns 143 for a positioning unit 140 is two, one third marking pattern 143 is located on the side of the mth first marking pattern 141 and the other third marking pattern 143 is located on the side of the nth first marking pattern 141, it indicates that the positioning unit is the positioning unit of the m+nth column; m and n are both positive integers less than or equal to k.

[0040] The gate oxide integrity test structure provided by the present invention includes an active area 10 formed in a substrate, and a gate oxide layer 11, a gate electrode 12 and a positioning structure 14 stacked from bottom to top on the substrate. The positioning structure 14 is located in a first metal layer above the gate electrode 12. The positioning structure 14 includes a plurality of positioning units 140 arranged in an array. The marking pattern in each positioning unit 140 independently labels each positioning unit 140. The positioning structure 14 uses the positioning unit 140 to locate the position of the failure point in the gate oxide layer 11. In the present application, the marking pattern in each positioning unit 140 of the positioning structure 14 independently labels each positioning unit 140. The positioning structure 14 can accurately locate the position of the failure point of the gate oxide layer, which can improve the efficiency of failure analysis. The positioning structure 14 is formed in the first metal layer so that the setting position of the positioning unit in the positioning structure 14 is not limited by the active area pattern and the gate electrode pattern, thereby expanding the application scope of the gate oxide integrity test structure and having strong process feasibility.

[0041] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A gate oxide integrity test structure, characterized in that: It includes an active area formed in a substrate and a gate oxide layer, a gate electrode and a positioning structure stacked from bottom to top on the substrate; the positioning structure is located in a first metal layer above the gate electrode, the positioning structure includes a plurality of positioning units arranged in an array, a marking pattern in each of the positioning units independently labels each of the positioning units, and the positioning structure uses the positioning unit to locate the failure point position in the gate oxide layer; each of the positioning units includes a plurality of first marking patterns, at least one second marking pattern and at least one third marking pattern; for one positioning unit, a plurality of the first marking patterns are arranged in a row, the second marking pattern and the third marking pattern are arranged on the sides of the plurality of the first marking patterns, the number of rows of the positioning unit in the positioning structure is marked by the number of the second marking patterns and the positional relationship between the second marking pattern and the plurality of the first marking patterns, and the number of columns of the positioning unit in the positioning structure is marked by the number of the third marking patterns and the positional relationship between the third marking pattern and the plurality of the first marking patterns.

2. The gate oxide integrity test structure according to claim 1, wherein: The plurality of first marking patterns are also used to mark the position of the failure point in the area where the positioning unit is located.

3. The gate oxide integrity test structure according to claim 2, wherein: In one of the positioning units, the second mark pattern is arranged on one side of the plurality of first mark patterns, and the third mark pattern is arranged on the other side of the plurality of first mark patterns.

4. The gate oxide integrity test structure according to claim 3, characterized in that: The second mark pattern and the third mark pattern may have the same or different shapes.

5. The gate oxide integrity test structure according to claim 3, characterized in that: The first marking pattern is a rectangle, and the second marking pattern and the third marking pattern are both square or circular.

6. The gate oxide integrity test structure according to claim 2, wherein: The number of the first mark graphics in all the positioning units is k; for one positioning unit, when the number of the second mark graphics is one and the second mark graphics is located on the side of the i-th first mark graphics, it indicates that the positioning unit is a positioning unit in the i-th row; for one positioning unit, when the number of the second mark graphics is two, one second mark graphics is located on the side of the i-th first mark graphics and the other second mark graphics is located on the side of the j-th first mark graphics, it indicates that the positioning unit is a positioning unit in the i+j-th row; k is a positive integer greater than or equal to 2, and i and j are both positive integers less than or equal to k.

7. The gate oxide integrity test structure according to claim 6, wherein: For one of the positioning units, when the number of the third mark graphics is one and the third mark graphics is located on the side of the m-th first mark graphics, it indicates that the positioning unit is a positioning unit in the m-th column; for one of the positioning units, when the number of the third mark graphics is two, one of the third mark graphics is located on the side of the m-th first mark graphics and the other of the third mark graphics is located on the side of the n-th first mark graphics, it indicates that the positioning unit is a positioning unit in the m+n-th column; m and n are both positive integers less than or equal to k.

8. The gate oxide integrity test structure according to any one of claims 1 to 7, characterized in that: The active area is in the shape of a whole block or is divided into a plurality of strip-shaped active areas by a plurality of isolation structures; the gate electrode is in the shape of a whole block, or the gate electrode includes a plurality of strip-shaped gate electrodes.

9. The gate oxide integrity test structure according to any one of claims 1 to 7, characterized in that: The plurality of positioning units of the positioning structure are arranged by a dichotomy method.

10. The gate oxide integrity test structure according to any one of claims 1 to 7, characterized in that: The positioning structure and the gate electrode as well as the positioning structure and the substrate are isolated by a dielectric layer.

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