SiC super junction device with high gate oxide reliability

Abstract

The invention provides a SiC super junction device with high gate oxide reliability. The SiC super junction device comprises a source electrode, a polysilicon gate, a P-body region, an N + contact region, a gate trench oxide, a P + gate oxide protection region, a P column region, an N column region, an N type substrate and a drain electrode, according to the SiC super junction device with high gate oxide reliability, a charge-balanced P column structure and a charge-highly-unbalanced P + gate oxide protection region structure are respectively formed through epitaxial backfilling and ion implantation after groove etching, so that low gate oxide electric field and low on-resistance can be considered under the condition of not increasing extra version; the problem of how to realize high performance and high gate oxide reliability of the SiC super-junction device at the same time is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices, in particular to a SiC super junction device with high gate oxide reliability. Background Art

[0002] As one of the representatives of the third generation of wide bandgap semiconductor materials, silicon carbide has the advantages of wider bandgap width (3 times), higher critical electric field (10 times), higher carrier saturation drift velocity (2 times), higher thermal conductivity (2.5 times) than silicon materials, and has broad application prospects in the fields of high-power, high-temperature, high-voltage and radiation-resistant power electronics. SiC power devices have become a new generation of highly competitive low-loss power devices due to their lower switching loss, higher frequency characteristics, lower on-resistance and excellent high-temperature characteristics. However, with the development of SiC theory and technology, the performance improvement space of planar and trench SiC devices has been very limited.

[0003] The superjunction (continuous NP column structure) introduces a periodic charge balance mechanism, which can break through the breakdown voltage (BV) and on-resistance (R ON ) has been widely used in Si-based devices. However, since the critical breakdown electric fields of SiC and SiO2 are at the same order of magnitude, the gate oxide electric field in SiC devices is high, and a highly charge-unbalanced NP structure is required to ensure its long-term reliability, which conflicts with the charge balance of the superjunction. Therefore, how to achieve high-performance SiC superjunction devices with good gate oxide reliability is a problem.

[0004] In view of this, the present invention designs a SiC super junction device with high gate oxide reliability, which can simultaneously achieve low gate oxide electric field and low on-resistance, and is suitable for various devices such as MOSFET and IGBT. Summary of the invention

[0005] The purpose of the present invention is to propose a SiC super junction device with high gate oxide reliability, which forms a charge-balanced P column structure and a charge-highly unbalanced P+ gate oxide protection zone structure respectively through epitaxial backfilling and ion implantation after trench etching, thereby taking into account both low gate oxide electric field and low on-resistance without adding additional versions, and solving the problem of how to simultaneously achieve high performance and high gate oxide reliability of SiC super junction devices. The size and doping concentration of the P+ gate oxide protection zone can be optimized and adjusted by changing the energy, angle and dose of ion implantation.

[0006] To achieve the above-mentioned object of the invention, the first SiC super junction device with high gate oxide reliability provided by the present invention is:

[0007] A SiC super junction device with high gate oxide reliability comprises an N-type substrate 9, an N-column region 8 located above the N-type substrate, a P-column region 7 located on both sides of the N-column region 8, a P+ gate oxide protection region 6 located on both sides of the upper half of the P-column region 7, a source electrode 1 located above the P-column region 7 and forming an ohmic contact with the P+ gate oxide protection region 6, a gate trench oxide 5 located between adjacent P+ gate oxide protection regions 6 above the N-column region 8, a polysilicon gate 2 located inside the gate trench oxide 5, a P-body region 3 and an N+ contact region 4 located between the gate trench oxide 5 and the P+ gate oxide protection region 6 above the N-column region 8, the N+ contact region 4 being located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 10 located below the N-type substrate 9 and forming an ohmic contact with the N-type substrate 9.

[0008] As a preferred embodiment, the P column region 7 is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection region 6 is formed by oblique ion implantation into the trench sidewall.

[0009] To achieve the above-mentioned purpose of the invention, the present invention also provides a second SiC super junction device with high gate oxide reliability, comprising an N-type substrate 9, an N-column region 8 located above the N-type substrate, a P-column region 7 located on both sides of the N-column region 8, the P-column region 7 being formed by trench etching and epitaxial backfilling, a P+ gate oxide protection area 6 located above the P-column region 7, the P+ gate oxide protection area 6 and the P-column region 7 being formed by ion implantation under the same mask, a source electrode 1 located above the P+ gate oxide protection area 6 and forming an ohmic contact with the P+ gate oxide protection area 6, a gate trench oxide 5 located between adjacent P+ gate oxide protection areas 6 above the N-column region 8, a polysilicon gate 2 located inside the gate trench oxide 5, a P-body region 3 and an N+ contact region 4 located between the gate trench oxide 5 and the P+ gate oxide protection area 6 above the N-column region 8, the N+ contact region 4 being located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 10 located below the N-type substrate 9 and forming an ohmic contact with the N-type substrate 9.

[0010] As a preferred embodiment, the P column region 7 is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection region 6 is formed by ion implantation after epitaxial backfilling.

[0011] To achieve the above-mentioned object of the invention, the present invention also provides a third SiC super junction device with high gate oxide reliability, comprising an N-type substrate 9, an N-column region 8 located above the N-type substrate, a P-column region 7 located on both sides of the N-column region 8, the P-column region 7 being formed by trench etching and epitaxial backfilling, a source trench structure 11 located above the P-column region 7, a source trench oxide 12 located inside the source trench structure 11, a source electrode 1 above the source trench oxide 12, and P+ gate oxide protection areas 6 located on both sides of the source trench structure 11, the P + gate oxide protection area 6 is formed by trench sidewall ion implantation, a gate trench oxide 5 is located between adjacent P+ gate oxide protection areas 6 above the N column area 8, a polysilicon gate 2 is located inside the gate trench oxide 5, a P-body area 3 and an N+ contact area 4 are located between the gate trench oxide 5 and the P+ gate oxide protection area 6 above the N column area 8, the N+ contact area 4 is located above the P-body area 3 and forms an ohmic contact with the source electrode 1, and a drain electrode 10 is located below the N-type substrate 9 and forms an ohmic contact with the N-type substrate 9.

[0012] As a preferred embodiment, the P column region 7 is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection region 6 is formed by ion implantation into the trench sidewall and bottom.

[0013] To achieve the above-mentioned purpose of the invention, the present invention also provides a fourth SiC super junction device with high gate oxide reliability, comprising an N-type substrate 9, an N-column region 8 located above the N-type substrate, a P-column region 7 located on both sides of the N-column region 8, wherein the P-column region 7 is formed by trench etching and epitaxial backfilling, a source trench structure 11 located above the P-column region 7, a source electrode 1 located above the source trench structure 11, a P+ gate oxide protection region 6 located on both sides below the source trench structure 11, wherein the P+ gate oxide protection region 6 is formed by trench sidewall ion implantation, a Schottky contact region 13 located above the P+ gate oxide protection region 6, a P-body region 3 located above the Schottky contact region 13, an N+ contact region 4 and a P+ contact region 14 located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 10 located below the N-type substrate 9 and forming an ohmic contact with the N-type substrate 9.

[0014] As a preferred embodiment, the P column region 7 is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection region 6 is formed by ion implantation at the bottom of the trench.

[0015] As a preferred embodiment, the N-type substrate 9 is changed to the opposite doping type, that is, P-type doping.

[0016] As a preferred embodiment, each doping type in the device is changed to opposite doping, that is, P-type doping is changed to N-type doping and N-type doping is changed to P-type doping at the same time.

[0017] The beneficial effects of the present invention are as follows: a charge-balanced P column region and a charge-highly unbalanced P+ gate oxide protection region are formed respectively through trench epitaxial backfilling and ion implantation processes, which can take into account both low gate oxide electric field and low on-resistance without adding additional versions, thereby solving the problem of how to simultaneously achieve high performance and high gate oxide reliability of SiC super junction devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of the device structure of Example 1 of the present invention;

[0019] Figure 2 is a schematic diagram of the device structure of embodiment 2 of the present invention;

[0020] Figure 3 is a schematic diagram of the device structure of embodiment 3 of the present invention;

[0021] Figure 4 is a schematic diagram of the device structure of embodiment 4 of the present invention;

[0022] Among them, 1 is the source electrode, 2 is the polysilicon gate, 3 is the P-body region, 4 is the N+ contact region, 5 is the gate trench oxide, 6 is the P+ gate oxide protection region, 7 is the P column region, 8 is the N column region, 9 is the N-type substrate, 10 is the drain electrode, 11 is the source trench structure, 12 is the source trench oxide, 13 is the Schottky contact region, and 14 is the P+ contact region. DETAILED DESCRIPTION

[0023] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0024] Embodiment 1:

[0025] like Figure 1As shown, a SiC super junction device with high gate oxide reliability in this embodiment includes an N-type substrate 9, an N-column region 8 located above the N-type substrate, a P-column region 7 located on both sides of the N-column region 8, a P+ gate oxide protection area 6 located on both sides of the upper half of the P-column region 7, a source electrode 1 located above the P-column region 7 and forming an ohmic contact with the P+ gate oxide protection area 6, a gate trench oxide 5 located between adjacent P+ gate oxide protection areas 6 above the N-column region 8, a polysilicon gate 2 located inside the gate trench oxide 5, a P-body region 3 and an N+ contact region 4 located between the gate trench oxide 5 and the P+ gate oxide protection area 6 above the N-column region 8, the N+ contact region 4 being located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 10 located below the N-type substrate 9 and forming an ohmic contact with the N-type substrate 9.

[0026] Preferably, the P column region 7 is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection region 6 is formed by performing inclined ion implantation on the trench sidewall.

[0027] Preferably, the N-type substrate 9 is changed to the opposite doping type, ie, P-type doping.

[0028] Preferably, each doping type in the device is changed to opposite doping, that is, P-type doping is changed to N-type doping and N-type doping is changed to P-type doping at the same time.

[0029] The beneficial effects of this example are:

[0030] Through trench epitaxial backfill and ion implantation processes, a charge-balanced P column region 7 and a charge-highly unbalanced P+ gate oxide protection region 6 are formed respectively. This can take into account both low gate oxide electric field and low on-resistance without adding additional versions, thus solving the problem of how to simultaneously achieve high performance and high gate oxide reliability of SiC super junction devices.

[0031] Embodiment 2:

[0032] like Figure 2As shown, a SiC super junction device with high gate oxide reliability in this embodiment includes an N-type substrate 9, an N-column region 8 located above the N-type substrate, P-column regions 7 located on both sides of the N-column region 8, the P-column region 7 being formed by trench etching and epitaxial backfilling, a P+ gate oxide protection area 6 located above the P-column region 7, the P+ gate oxide protection area 6 and the P-column region 7 being formed by ion implantation under the same mask, a source electrode 1 located above the P+ gate oxide protection area 6 and forming an ohmic contact with the P+ gate oxide protection area 6, a gate trench oxide 5 located between adjacent P+ gate oxide protection areas 6 above the N-column region 8, a polysilicon gate 2 located inside the gate trench oxide 5, a P-body region 3 and an N+ contact region 4 located between the gate trench oxide 5 and the P+ gate oxide protection area 6 above the N-column region 8, the N+ contact region 4 being located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 10 located below the N-type substrate 9 and forming an ohmic contact with the N-type substrate 9.

[0033] Preferably, the P column region 7 is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection region 6 is formed by ion implantation after epitaxial backfilling.

[0034] Preferably, the N-type substrate 9 is changed to the opposite doping type, ie, P-type doping.

[0035] Preferably, each doping type in the device is changed to opposite doping, that is, P-type doping is changed to N-type doping and N-type doping is changed to P-type doping at the same time.

[0036] The beneficial effects of this example are:

[0037] On the basis of Example 1, a P+ gate oxide protection area 6 is formed by vertical ion implantation after epitaxial backfilling, so that a smaller cell size can be achieved and the device specific on-resistance can be reduced.

[0038] Embodiment 3:

[0039] like Figure 3As shown, a SiC super junction device with high gate oxide reliability in this embodiment includes an N-type substrate 9, an N-column region 8 located above the N-type substrate, a P-column region 7 located on both sides of the N-column region 8, the P-column region 7 is formed by trench etching and epitaxial backfilling, a source trench structure 11 located above the P-column region 7, a source trench oxide 12 located inside the source trench structure 11, a source electrode 1 above the source trench oxide 12, and P+ gate oxide protection areas 6 located on both sides of the source trench structure 11. The protection region 6 is formed by ion implantation of the trench sidewall, comprising a gate trench oxide 5 located between adjacent P+ gate oxide protection regions 6 above the N-column region 8, a polysilicon gate 2 located inside the gate trench oxide 5, a P-body region 3 and an N+ contact region 4 located between the gate trench oxide 5 and the P+ gate oxide protection region 6 above the N-column region 8, the N+ contact region 4 being located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 10 being located below the N-type substrate 9 and forming an ohmic contact with the N-type substrate 9.

[0040] Preferably, the P column region 7 is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection region is formed by ion implantation into the trench sidewall and bottom.

[0041] Preferably, the N-type substrate 9 is changed to the opposite doping type, ie, P-type doping.

[0042] Preferably, each doping type in the device is changed to opposite doping, that is, P-type doping is changed to N-type doping and N-type doping is changed to P-type doping at the same time.

[0043] The beneficial effects of this example are:

[0044] A deeper P+ gate oxide protection area 6 can be formed by trench ion implantation, thereby reducing the electric field of the gate trench oxide 5 and improving the gate oxide reliability of the device.

[0045] Embodiment 4:

[0046] like Figure 4 As shown, a SiC super junction device with high gate oxide reliability in this embodiment includes an N-type substrate 9, an N-column region 8 located above the N-type substrate, a P-column region 7 located on both sides of the N-column region 8, the P-column region 7 being formed by trench etching and epitaxial backfilling, a source trench structure 11 located above the P-column region 7, a source electrode 1 located above the source trench structure 11, a P+ gate oxide protection region 6 located on both sides below the source trench structure 11, the P+ gate oxide protection region 6 being formed by trench sidewall ion implantation, a Schottky contact region 13 located above the P+ gate oxide protection region 6, a P-body region 3 located above the Schottky contact region 13, an N+ contact region 4 and a P+ contact region 14 located above the P-body region 3 and forming an ohmic contact with the source electrode 1, and a drain electrode 10 located below the N-type substrate 9 and forming an ohmic contact with the N-type substrate 9.

[0047] Preferably, the P column region 7 is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection region 6 is formed by ion implantation at the bottom of the trench.

[0048] Preferably, the N-type substrate 9 is changed to the opposite doping type, ie, P-type doping.

[0049] Preferably, each doping type in the device is changed to opposite doping, that is, P-type doping is changed to N-type doping and N-type doping is changed to P-type doping at the same time.

[0050] The beneficial effects of this example are:

[0051] A Schottky contact region 13 is introduced above the P+ gate oxide protection region 6. The formed Schottky diode is turned on when the device is in the freewheeling working state, which can reduce the freewheeling conduction voltage drop of the device and improve its third quadrant capability.

Claims

1. A SiC super junction device with high gate oxide reliability, characterized in that: The invention comprises an N-type substrate (9), an N-column region (8) located above the N-type substrate, a P-column region (7) located on both sides of the N-column region (8), a P+ gate oxide protection region (6) located on both sides of the upper half of the P-column region (7), a source electrode (1) located above the P-column region (7) and forming an ohmic contact with the P+ gate oxide protection region (6), a gate trench oxide (5) located between adjacent P+ gate oxide protection regions (6) above the N-column region (8), a polysilicon gate (2) located inside the gate trench oxide (5), a P-body region (3) and an N+ contact region (4) located between the gate trench oxide (5) and the P+ gate oxide protection region (6) above the N-column region (8), the N+ contact region (4) being located above the P-body region (3) and forming an ohmic contact with the source electrode (1), and a drain electrode (10) located below the N-type substrate (9) and forming an ohmic contact with the N-type substrate (9).

2. A SiC super junction device with high gate oxide reliability according to claim 1, characterized in that: The P column region (7) is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection region (6) is formed by oblique ion implantation into the trench sidewall.

3. A SiC super junction device with high gate oxide reliability, characterized in that: The invention comprises an N-type substrate (9), an N-column region (8) located above the N-type substrate, a P-column region (7) located on both sides of the N-column region (8), wherein the P-column region (7) is formed by trench etching and epitaxial backfilling, a P+ gate oxide protection region (6) located above the P-column region (7), wherein the P+ gate oxide protection region (6) and the P-column region (7) are formed by ion implantation under the same mask, a source electrode (1) located above the P+ gate oxide protection region (6) and forming an ohmic contact with the P+ gate oxide protection region (6), and a source electrode (1) located above the N-column region (8). A gate trench oxide (5) between adjacent P+ gate oxide protection areas (6), a polysilicon gate (2) located inside the gate trench oxide (5), a P-body area (3) and an N+ contact area (4) located between the gate trench oxide (5) and the P+ gate oxide protection area (6) above an N column area (8), the N+ contact area (4) being located above the P-body area (3) and forming an ohmic contact with a source electrode (1), and a drain electrode (10) being located below an N-type substrate (9) and forming an ohmic contact with the N-type substrate (9).

4. A SiC super junction device with high gate oxide reliability according to claim 3, characterized in that: The P column region (7) is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection region (6) is formed by ion implantation after epitaxial backfilling.

5. A SiC super junction device with high gate oxide reliability, characterized in that: The invention comprises an N-type substrate (9), an N-column region (8) located above the N-type substrate, a P-column region (7) located on both sides of the N-column region (8), wherein the P-column region (7) is formed by trench etching and epitaxial backfilling, a source trench structure (11) located above the P-column region (7), a source trench oxide (12) located inside the source trench structure (11), a source electrode (1) above the source trench oxide (12), and P+ gate oxide protection regions (6) located on both sides of the source trench structure (11), wherein the P+ gate oxide protection regions (6) are formed by trench sidewall ion implantation. , a gate trench oxide (5) located between adjacent P+ gate oxide protection areas (6) above an N column area (8), a polysilicon gate (2) located inside the gate trench oxide (5), a P-body area (3) and an N+ contact area (4) located between the gate trench oxide (5) and the P+ gate oxide protection area (6) above the N column area (8), the N+ contact area (4) being located above the P-body area (3) and forming an ohmic contact with a source electrode (1), and a drain electrode (10) being located below an N-type substrate (9) and forming an ohmic contact with the N-type substrate (9).

6. A SiC super junction device with high gate oxide reliability according to claim 5, characterized in that: The P column area (7) is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection area (6) is formed by ion implantation into the trench sidewall and bottom.

7. A SiC super junction device with high gate oxide reliability, characterized in that: The invention comprises an N-type substrate (9), an N-column region (8) located above the N-type substrate, a P-column region (7) located on both sides of the N-column region (8), the P-column region (7) being formed by trench etching and epitaxial backfilling, a source trench structure (11) located above the P-column region (7), a source electrode (1) located above the source trench structure (11), a P+ gate oxide protection region (6) located on both sides below the source trench structure (11), the P+ gate oxide protection region (6) being formed by trench sidewall ion implantation, a Schottky contact region (13) located above the P+ gate oxide protection region (6), a P-body region (3) located above the Schottky contact region (13), an N+ contact region (4) and a P+ contact region (14) located above the P-body region (3) and forming an ohmic contact with the source electrode (1), and a drain electrode (10) located below the N-type substrate (9) and forming an ohmic contact with the N-type substrate (9).

8. The SiC super junction device with high gate oxide reliability according to claim 7, characterized in that: The P column area (7) is formed by trench etching and epitaxial backfilling, and the P+ gate oxide protection area (6) is formed by ion implantation at the bottom of the trench.

9. A SiC super junction device with high gate oxide reliability according to any one of claims 1, 3, 5 and 7, characterized in that: The N-type substrate (9) is changed to the opposite doping type, namely P-type doping.

10. A SiC super junction device with high gate oxide reliability according to any one of claims 1, 3, 5 and 7, characterized in that: Each doping type in the device is changed to opposite doping accordingly, that is, P-type doping is changed to N-type doping and N-type doping is changed to P-type doping at the same time.

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