Composite cross discharge ESD (Electro-Static Discharge) device

Abstract

The invention discloses a composite cross discharge ESD device, which belongs to the technical field of semiconductors, and comprises a substrate, a first electrode, a second electrode, a third electrode and a fourth electrode, the SCR structure is distributed in the substrate in the Y direction, an intersection region is arranged between well regions of the SCR structure, and insulating media are arranged at the positions, adjacent to the well regions and the substrate, of the intersection region; and the at least one discharge unit is arranged in the insulating medium of the crossing region, the discharge unit comprises a first polysilicon gate region, a first N-type channel region, a P-type channel region, a second N-type channel region and a second polysilicon gate region which are sequentially arranged along the X direction, and the P-type channel region penetrates out of the insulating medium at two sides in the Y direction so as to be connected with the well region. By improving the structure of a traditional SCR device, on the basis that the area of the device is not increased, an NPN type composite channel region of a super junction structure is added, and therefore adjustable current distribution and parameter characteristics of the SCR device, ESD protection in a crossed multi-current direction and better unit area integration performance are achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a composite cross-discharge ESD device. Background Technology

[0002] ESD, or electrostatic discharge, is an ancient natural phenomenon. ESD exists in every corner of daily life. However, this seemingly commonplace electrical phenomenon poses a fatal threat to delicate integrated circuits. Electrical surges / transient voltages refer to sudden, random, and abnormally high voltages or currents exceeding normal conditions in a circuit. They are characterized by their short duration and extremely high instantaneous energy. Electrical surges are highly destructive to electronic components and integrated circuits. At best, they induce malfunctions in logic circuits; at worst, they cause secondary breakdowns of transistors, latch-up effects in Complementary Metal Oxide Semiconductors (CMOS), and other severe thermal effects that lead to device or integrated circuit failure. Electrical surges typically have two random sources: the first is instability in the power grid, such as sudden switching on / off, sudden starting of capacitive or inductive loads, hot-plugging of related equipment, and unstable operation of related power supplies. The second is sudden external interference, such as lightning or electrostatic discharge.

[0003] With advancements in integrated circuit manufacturing processes, the minimum linewidth has decreased to the submicron or even nanometer level. While this has led to improved chip performance, it has also significantly reduced the chip's resistance to ESD (Electrostatic Discharge), making electrostatic damage more severe. Most ESD incidents cause non-fatal damage to integrated circuits, reducing their lifespan and reliability, and ultimately leading to system functional degradation. This poses a significant obstacle to achieving large-scale, highly reliable integration.

[0004] ESD devices are important semiconductor protection devices. When turned on, they have extremely low resistance and can absorb transient pulse power up to several kilowatts, clamping the voltage at the port to a relatively safe preset value. This protects the corresponding circuit from damage or even irreversible damage caused by transient voltage pulses or current surges. ESD devices are widely used for overvoltage protection in various fields such as electromechanical systems, power supply equipment, electromagnetic interference suppression, input / output interfaces, communication equipment, and relays. For example... Figure 1 The diagram shows a traditional SCR device structure. Based on this, it is difficult to improve the current discharge capability while maintaining integration. Therefore, this invention proposes a composite cross-discharge ESD protection device with excellent characteristics.

[0005] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a composite cross-discharge ESD protection device to solve the problem of difficulty in improving current discharge capability while maintaining high integration.

[0007] To address the aforementioned technical problems, this invention provides a composite cross-discharge ESD device, comprising:

[0008] Substrate;

[0009] An SCR structure is distributed in the substrate along the Y direction, and a cross region is provided between the well regions of the SCR structure. An insulating medium is provided at the intersection of the cross region, the well regions, and the substrate.

[0010] At least one discharge unit is disposed within the insulating medium of the cross region. The discharge unit includes a first polysilicon gate region, a first N-type channel region, a P-type channel region, a second N-type channel region, and a second polysilicon gate region arranged sequentially along the X direction. The P-type channel region extends through the insulating medium on both sides in the Y direction to connect with the well region.

[0011] Preferably, an insulating layer is provided between the cross region and the substrate, and the insulating layer extends to the bottom of the well region on both sides in the Y direction to separate the well region and the substrate.

[0012] Preferably, the first N-type channel region and the first polysilicon gate region are respectively provided with a first sidewall isolation medium and a second sidewall isolation medium on both sides in the Y direction.

[0013] Preferably, the second N-type channel region and the second polysilicon gate region are respectively provided with a third sidewall isolation medium and a fourth sidewall isolation medium on both sides in the Y direction.

[0014] Preferably, the SCR structure includes an N-type well region and a P-type well region arranged sequentially along the Y direction, and the intersection region is located between the N-type well region and the P-type well region.

[0015] Preferably, the N-type well region has a first N-type region and a first P-type region distributed along the Y direction, with a gap between the first N-type region and the first P-type region, and the first N-type region and the first P-type region are also interconnected by wires, serving as the anode of the ESD device.

[0016] Preferably, the P-type well region has a second N-type region and a second P-type region distributed along the Y direction, with a gap between the second N-type region and the second P-type region, and the second N-type region and the second P-type region are interconnected by wires, serving as the cathode of the ESD device.

[0017] Preferably, the first polysilicon gate region and the second polysilicon gate region are externally biased.

[0018] Preferably, the first polysilicon gate region and the second polysilicon gate region serve as the cathode and anode of the ESD device, respectively, and are connected to external devices for discharging current.

[0019] Preferably, it includes two discharge units, with two adjacent discharge units sharing a polysilicon gate region, and each polysilicon gate region is used for external bias voltage.

[0020] The composite cross-discharge ESD device provided by this invention, without increasing the device area, improves the structure of traditional SCR devices by adding an NPN-type composite channel region of a superjunction structure. This enables adjustable current distribution and parameter characteristics of the SCR device, as well as cross-multi-current-direction ESD protection and better integration performance per unit area. Attached Figure Description

[0021] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0022] Figure 1 This is a schematic diagram of a traditional SCR device structure;

[0023] Figure 2 This is a schematic diagram of the structure of a composite cross-discharge ESD device according to an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of a dual-path protection scheme for a composite cross-discharge ESD device according to an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the application circuit of a composite cross-discharge ESD device according to an embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of the structure of a composite cross-discharge ESD device according to another embodiment of the present invention.

[0027] In the attached image:

[0028] 101. P-type substrate; 102. Insulating layer; 103. First polysilicon gate region; 104. Second polysilicon gate region; 105. N-type well region; 106. P-type well region; 107. First N-type region; 108. First P-type region; 109. Second N-type region; 110. Second P-type region; 111. First N-type channel region; 112. P-type channel region; 113. Second N-type channel region; 114. First sidewall isolation medium; 115. Second sidewall isolation medium; 116. Third sidewall isolation medium; 117. Fourth sidewall isolation medium. Detailed Implementation

[0029] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0030] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0031] The following disclosure provides numerous different embodiments or examples for implementing various functions of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, forming a first feature on a second feature can include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0032] In addition, for ease of description, this document may use spatial relative terms such as "below," "under," "lower part," "above," "upper part," "left side," and "right side" to describe the relationship between one element or feature and another, as shown in the figure. Besides the orientations described in the figure, spatial relative terms also include different orientations of the device during use or operation. The device may also have other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptors used here can also be interpreted accordingly.

[0033] The inventors discovered through research that, for example Figure 1 The diagram shows a traditional SCR device structure. Based on this, it is difficult to improve the current discharge capability while maintaining high integration.

[0034] Based on this, the core idea of ​​this invention is to fully utilize the area between the well regions of traditional SCR devices on the basis of traditional SCR device structure, and combine SOI technology, superjunction structure and trenching process to propose an ESD device that is flexible in design, reliable in performance, adjustable in device performance parameters, and has cross-current direction ESD protection and better unit area integration performance.

[0035] Example 1

[0036] For details, please refer to Figures 2-4 This is a schematic diagram of one embodiment of the present invention, and the description here only takes the setting of a discharge unit as an example. Figure 2 As shown, a composite cross-discharge ESD device includes:

[0037] Substrate;

[0038] An SCR structure is distributed in the substrate along the Y direction, and a cross region is provided between the well regions of the SCR structure. An insulating medium is provided at the intersection of the cross region, the well regions, and the substrate.

[0039] At least one discharge unit is disposed within the insulating medium of the crossover region. The discharge unit includes a first polysilicon gate region 103, a first N-type channel region 111, a P-type channel region 112, a second N-type channel region 113, and a second polysilicon gate region 104 arranged sequentially along the X-direction. The P-type channel region 112 extends through the insulating medium on both sides in the Y-direction to connect with the well region. The X, Y, and Z directions are labeled as follows: Figure 2 As shown, the devices in the well region are distributed in the Y direction, and the regions of the discharge unit are distributed in the X direction accordingly, which greatly improves the integration of the devices.

[0040] By improving the structure of traditional SCR devices, an NPN composite channel region with a superjunction structure is added without increasing the device area. This enables adjustable current distribution and parameter characteristics of SCR devices, as well as ESD protection across multiple current directions and better integration performance per unit area.

[0041] Even better, the substrate is a P-type substrate 101.

[0042] In one embodiment, the first polysilicon gate region 103 and the second polysilicon gate region 104 are located inside the P-type substrate 101, and between the N-type well region 105 and the P-type well region 106. Their left edges are tangent to the right edge of the N-type well region 105, their right edges are tangent to the left edge of the P-type well region 106, their upper edges are tangent to the upper edge of the P-type substrate 101, and their lower edges are tangent to the upper edge of the insulating layer 102. In the X-axis, the first polysilicon gate region 103 is positioned in front of the second polysilicon gate region 104, with a distance between them.

[0043] The first N-type channel region 111, the P-type channel region 112, and the second N-type channel region 113 are located inside the P-type substrate 101, between the first polysilicon gate region 103 and the second polysilicon gate region 104. The relative positions of the first N-type channel region 111, the P-type channel region 112, and the second N-type channel region 113 from front to back are as follows: first N-type channel region 111, P-type channel region 112, and second N-type channel region 113. Their upper edges are tangent to the upper edge of the P-type substrate 101, and their lower edges are tangent to the upper edge of the insulating layer 102.

[0044] Specifically, an insulating layer 102 is disposed between the cross region and the substrate, and the insulating layer 102 extends to the bottom of the well region on both sides in the Y direction, serving to separate the well region and the substrate. Figure 2 As shown, the insulating layer 102 is located inside the P-type substrate 101, with its lower edge higher than the lower edge of the P-type substrate 101 and its upper edge lower than the upper edge of the P-type substrate 101.

[0045] Specifically, the first N-type channel region 111 and the first polysilicon gate region 103 are respectively provided with a first sidewall isolation medium 114 and a second sidewall isolation medium 115 on both sides in the Y direction. The second N-type channel region 113 and the second polysilicon gate region 104 are respectively provided with a third sidewall isolation medium 116 and a fourth sidewall isolation medium 117 on both sides in the Y direction.

[0046] The first sidewall isolation medium 114 and the second sidewall isolation medium 115 are located on both sides of the first N-type channel region 111, separating the first N-type channel region 111 from the N-type well region 105 and the P-type well region 106, respectively. The left and right edges of the first sidewall isolation medium 114 are tangent to the right edge of the N-type well region 105 and the left edge of the first N-type channel region 111, respectively, and the upper and lower edges are tangent to the lower edge of the P-type channel region 112 and the upper edge of the first polysilicon gate region 103, respectively. Conversely, the left and right edges of the second sidewall isolation medium 115 are tangent to the right edge of the first N-type channel region 111 and the left edge of the P-type well region 106, respectively, and the upper and lower edges are tangent to the lower edge of the P-type channel region 112 and the upper edge of the first polysilicon gate region 103, respectively.

[0047] The third sidewall isolation medium 116 and the fourth sidewall isolation medium 117 are located on both sides of the second N-type channel region 113, isolating the second N-type channel region 113 from the N-type well region 105 and the P-type well region 106, respectively. The left and right edges of the third sidewall isolation medium 116 are tangent to the right edge of the N-type well region 105 and the left edge of the second N-type channel region 113, respectively, and the upper and lower edges are tangent to the lower edge of the second polysilicon gate region 104 and the upper edge of the P-type channel region 112, respectively. Conversely, the left and right edges of the fourth sidewall isolation medium 117 are tangent to the right edge of the second N-type channel region 113 and the left edge of the P-type well region 106, respectively, and the upper and lower edges are tangent to the lower edge of the second polysilicon gate region 104 and the upper edge of the P-type channel region 112, respectively. Here, the left and right edges are used to describe regions in, for example... Figure 2 The position shown is in the Y direction, the upper and lower edges are in the Z direction, and the front and back are in the X direction.

[0048] Specifically, the SCR structure includes an N-type well region 105 and a P-type well region 106 arranged sequentially along the Y direction, with the intersection region located between the N-type well region 105 and the P-type well region 106. Within the N-type well region, a first N-type region 107 and a first P-type region 108 are distributed along the Y direction, with a gap between them. The first N-type region 107 and the first P-type region 108 are also interconnected by a wire, serving as the anode of the ESD device. Within the P-type well region 106, a second N-type region 109 and a second P-type region 110 are distributed along the Y direction, with a gap between them. The second N-type region 109 and the second P-type region 110 are also interconnected by a wire, serving as the cathode of the ESD device.

[0049] Understandably, the N-type well region 105 and the P-type well region 106 are located inside the P-type substrate 101, both situated above the insulating layer 102. Their lower edges are tangent to the upper edge of the insulating layer 102, and their upper edges are tangent to the upper edge of the P-type substrate 101. For example, the N-type well region 105 is positioned to the left of the P-type well region 106, and the right edge of the N-type well region 105 is a distance away from the left edge of the P-type well region 106.

[0050] In one embodiment, a first N-type region 107 and a first P-type region 108 are located inside an N-type well region 105, with their upper edges tangent to the upper edge of the N-type well region 105 and their lower edges higher than the lower edge of the N-type well region 105. The first N-type region 107 is positioned to the left of the first P-type region 108, and its right edge is slightly spaced from the left edge of the first P-type region 108. A second N-type region 109 and a second P-type region 110 are located inside a P-type well region 106, with their upper edges tangent to the upper edge of the P-type well region 106 and their lower edges higher than the lower edge of the P-type well region 106. The second N-type region 109 is positioned to the left of the second P-type region 110, and its right edge is slightly spaced from the left edge of the second P-type region 110.

[0051] The first N-type region 107 and the first P-type region 108 are interconnected by wires to form the anode of the ESD device, and the second N-type region 109 and the second P-type region 110 are interconnected by wires to form the cathode of the ESD device. The first polysilicon gate region 103 and the second polysilicon gate region 104 are the gates of the ESD device.

[0052] In one embodiment, the dual-path protection scheme of the composite cross-discharge ESD device is as follows: Figure 3 As shown, the first polysilicon gate region 103 and the second polysilicon gate region 104 are externally biased, and the specific circuit application is as follows. Figure 4 As shown, the anode and cathode of the ESD device are connected to the first protection chip (Protected IC1), and the polysilicon gate region serves as the positive and negative electrodes, respectively, connected to the second protection chip (Protected IC2). Due to the introduction of an NPN channel current path and a sidewall gate in the middle of the device, it possesses ESD protection in two directions: when the device is operating normally, the NPN channel region between the N-type well region 105 and the P-type well region 106, resembling a superjunction structure, forms two PN junctions. The magnitude and distribution of the current through the channel region can be controlled by applying different bias voltages to the gate, thus achieving regulation and control of the SCR device. At this time, the device provides ESD protection in the lateral direction using the SCR structure through the anode and cathode.

[0053] In one embodiment, the first polysilicon gate region 103 and the second polysilicon gate region 104 serve as the cathode and anode of the ESD device, respectively, connected to an external device for current discharge. It is understood that the device can also provide cross-direction ESD protection. In this case, the two gates of the device serve as the anode and cathode. When an ESD event occurs on one of the gates, current is discharged through the NPN structure between the two gates, achieving cross-direction ESD protection.

[0054]

Example 2

[0055] For details, please refer to Figure 5 This is a schematic diagram of another multi-cell structure of the composite cross-discharge ESD device of the present invention. The composite cross-discharge ESD device includes two discharge units, with two adjacent discharge units sharing a polysilicon gate region. Each polysilicon gate region is used to connect an external bias voltage. Figure 2 The discharge unit in the illustrated composite cross-discharge ESD device is the basic unit, integrating multiple devices together. A new discharge unit is connected in the X-direction to the second polysilicon gate region 104 of the first composite cross-discharge ESD device discharge unit, and this process is repeated to obtain a multi-cell structure of composite cross-discharge ESD devices with any number of basic units. Clearly, any number of discharge units can be integrated as basic units according to the actual application scenario and application requirements.

[0056] Understandably, when the aforementioned ESD devices with two or more discharge units are applied for ESD protection in the Y-direction, the current distribution is adjusted by applying different voltages to different gates and thus controlling the depletion layer width. When the same voltage is applied to different gates, a uniform current distribution in the channel region can be achieved. When the device is applied for ESD protection in the cross direction, this direction can be considered as multiple NPN transistors stacked in series, increasing the device voltage and achieving ESD protection under high-voltage applications.

[0057] The composite cross-discharge ESD device structure proposed in this invention combines SOI technology, superjunction structure, and trenching process. It introduces an NPN superjunction channel, polysilicon side gate, and sidewall isolation dielectric between the N-type and P-type well regions of a traditional SCR device, achieving adjustable current distribution and parameter characteristics. Simultaneously, it achieves ESD protection in the cross direction without increasing the device's footprint, essentially integrating two low-voltage ESD protection devices together without increasing the area between them.

[0058] When performing Y-axis ESD protection, if an ESD event occurs at the anode, the device uses a lateral SCR structure to discharge current, achieving ESD protection. During device operation, two PN junctions are formed in the NPN superjunction channel region. When different bias voltages are applied to different gate sides, the depletion layer widths of the two PN junctions change, thus altering the current path width of the device channel and regulating the channel current. Applying the same bias voltage to different gate sides allows for a uniform current distribution within the device channel region.

[0059] When the first polysilicon gate region 103 of the device is used as Gate 1 as the anode and the second polysilicon gate region 104 is used as Gate 2 as the cathode, ESD protection in the cross direction can be achieved. When an ESD event occurs at Gate 1 (anode), the NPN structure in the cross direction will turn on to discharge current, achieving ESD current protection in the cross direction. If multiple composite cross-discharge ESD devices are integrated together to realize an NPN stacked structure in the cross direction, the voltage of the devices in the cross direction can be increased, achieving ESD protection under high-voltage applications.

[0060] The device structure and accompanying drawings presented in this invention are merely a representation and illustration of a composite cross-discharge ESD device structure. Apart from the structure shown in the drawings, any person skilled in the art may modify or change the above structure without departing from the spirit and scope of this invention. For example, the SCR structure described above may be changed to a PNP structure, NPN structure, diode structure, MOS structure, etc., and these structures should obviously be within the protection scope of this invention.

[0061] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A compound cross-discharge ESD device, characterized in that, include: Substrate; An SCR structure is distributed in the substrate along the Y direction, and a cross region is provided between the well regions of the SCR structure. An insulating medium is provided at the intersection of the cross region, the well regions, and the substrate. At least one discharge unit is disposed within the insulating medium of the cross region. The discharge unit includes a first polysilicon gate region, a first N-type channel region, a P-type channel region, a second N-type channel region, and a second polysilicon gate region arranged sequentially along the X direction. The P-type channel region extends through the insulating medium on both sides in the Y direction to connect with the well region.

2. The compound cross-discharge ESD device of claim 1, wherein, An insulating layer is provided between the cross region and the substrate, and the insulating layer extends to the bottom of the well region on both sides in the Y direction to separate the well region and the substrate.

3. The composite cross-discharge ESD device according to claim 1, characterized in that, The first N-type channel region and the first polysilicon gate region are respectively provided with a first sidewall isolation medium and a second sidewall isolation medium on both sides in the Y direction.

4. The composite cross-discharge ESD device according to claim 1, characterized in that, The second N-type channel region and the second polysilicon gate region are respectively provided with a third sidewall isolation medium and a fourth sidewall isolation medium on both sides in the Y direction.

5. The composite cross-discharge ESD device according to claim 1, characterized in that, The SCR structure includes an N-type well region and a P-type well region arranged sequentially along the Y direction, and the cross region is located between the N-type well region and the P-type well region.

6. The composite cross-discharge ESD device according to claim 5, characterized in that, The N-type well region has a first N-type region and a first P-type region distributed along the Y direction. The first N-type region and the first P-type region are spaced apart and interconnected by wires, serving as the anode of the ESD device.

7. The composite cross-discharge ESD device according to claim 5, characterized in that, The P-type well region has a second N-type region and a second P-type region distributed along the Y direction, with a gap between the second N-type region and the second P-type region, and the second N-type region and the second P-type region are also interconnected by wires, which are used as the cathode of the ESD device.

8. The composite cross-discharge ESD device according to claim 1, characterized in that, The first polysilicon gate region and the second polysilicon gate region are externally biased.

9. The composite cross-discharge ESD device according to claim 1, characterized in that, The first polysilicon gate region and the second polysilicon gate region serve as the cathode and anode of the ESD device, respectively, and are connected to external devices to discharge current.

10. The composite cross-discharge ESD device according to claim 1, characterized in that, It includes two discharge units, with two adjacent discharge units sharing a polysilicon gate region, and each polysilicon gate region is used for external bias voltage.

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