Series battery pack protection circuits, chips and devices

Abstract

This invention provides a series battery pack protection circuit, chip, and device, including: a voltage and current protection circuit; the circuit includes a switched capacitor circuit, a first-stage amplifier, a second-stage preamplifier, a latch comparator, and switches SW1, SW2, and SW3. The switched capacitor circuit includes a first unit and a second unit; the first unit is used to receive the positive and negative voltages output by the series battery pack, the voltage at the first and second terminals of the sensing resistor of the peripheral circuit, and a reference signal, and is controlled by a first control signal; the second unit is controlled by signals φ1 and φ2; SW1 and SW2 are controlled by signal CP1; the second-stage preamplifier is controlled by signal CP3, and SW3 is controlled by signal CP2; the latch comparator is controlled by signal CP4; the voltage and current protection circuit can operate in voltage protection mode or current protection mode according to the different states of each control signal, and has both current protection and voltage protection functions, which can save circuit area and cost.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to a series battery pack protection circuit, chip, and device. Background Technology

[0002] With the widespread application of new energy electric vehicles, battery capacity, safety, health status, and range are increasingly becoming key concerns. A Battery Management System (BMS) is a device that monitors the status of energy storage batteries. It is primarily used for intelligent management and maintenance of individual battery cells, preventing overcharging and over-discharging, extending battery life, and monitoring battery status. However, voltage protection circuits and current protection circuits in a BMS are typically separated, resulting in wasted circuit space. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, the present invention provides a series battery pack protection circuit, chip, and device, specifically comprising:

[0004] In a first aspect, the present invention provides a series battery pack protection circuit, comprising:

[0005] Voltage and current protection circuit;

[0006] The voltage and current protection circuit includes a switched capacitor circuit, a first-stage amplifier with a closed-loop switch and a double-ended input and double-ended output, a second-stage preamplifier with an input reset switch and a latch comparator, switches SW1, SW2 and SW3, and the switched capacitor circuit includes a first unit and a second unit.

[0007] The input terminals of the first unit are used to receive the positive and negative voltages output by the series battery pack, the voltage SRP on the first terminal and the voltage SRN on the second terminal of the peripheral circuit sensing resistor, as well as the reference signal Vref1, the reference signal Vref2 and the first control signal. The output terminals are all connected to the second unit.

[0008] The first and second output terminals of the second unit are connected to the positive and negative input terminals of the first stage amplifier, respectively. The control signal input terminals of the second unit are used to receive signals φ1 and φ2, respectively.

[0009] The first and second output terminals of the first-stage amplifier are connected to the inverting and non-inverting input terminals of the second-stage preamplifier, respectively.

[0010] The positive input terminal and the first output terminal, the negative input terminal and the second output terminal of the first stage amplifier are respectively connected across the two ends of switch SW1 and switch SW2. Switch SW1 and switch SW2 are controlled by signal CP1. When signal CP1 is high, switch SW1 and switch SW2 are turned on.

[0011] The positive and negative input terminals of the second-stage preamplifier are connected across the two ends of switch SW3. The enable terminal is used to receive signal CP3. The output terminals are connected to the input terminals of the latch comparator. Switch SW3 is controlled by signal CP2. When signal CP2 is high, switch SW3 is turned on.

[0012] The enable pin of the latch comparator is used to receive signal CP4;

[0013] The first unit transmits the positive and negative voltages output by the series battery pack, as well as the reference signal Vref1, to the second unit according to the first control signal, so that the voltage and current protection circuit operates in current protection mode according to the switching states of switches SW1, SW2, and SW3, and signals CP3, CP4, φ1, and φ2. Alternatively, the first unit transmits the voltage SRP on the first terminal and the voltage SRN on the second terminal of the peripheral circuit sensing resistor, as well as the reference signal Vref2, to the second unit according to the first control signal, so that the voltage and current protection circuit operates in voltage protection mode according to the switching states of switches SW1, SW2, and SW3, and signals CP3, CP4, φ1, and φ2.

[0014] In a second aspect, the present invention also provides a chip including any of the series battery pack protection circuits provided in the first aspect.

[0015] Thirdly, the present invention also provides a chip, including any of the chips provided in the second aspect.

[0016] The beneficial effects of this invention are:

[0017] The present invention provides a series battery pack protection circuit, chip, and device, comprising: a voltage and current protection circuit; the voltage and current protection circuit includes a switched capacitor circuit, a first-stage amplifier with a closed-loop switch and a double-ended input and double-ended output, a second-stage preamplifier with an input reset switch and a latch comparator, switches SW1, SW2, and SW3, the switched capacitor circuit including a first unit and a second unit; the input terminals of the first unit are respectively used to receive the positive and negative voltages output by the series battery pack, the voltage SRP on the first terminal and the voltage SRN on the second terminal of the sensing resistor of the peripheral circuit, and a reference signal Vref1. The reference signal Vref2 and the first control signal are both connected to the second unit. The first and second outputs of the second unit are connected to the positive and negative inputs of the first-stage amplifier, respectively. The control signal inputs of the second unit are used to receive signals Φ1 and Φ2, respectively. The first and second outputs of the first-stage amplifier are connected to the negative and positive inputs of the second-stage preamplifier, respectively. The positive input, first output, negative input, and second output of the first-stage amplifier are connected across switches SW1 and SW2, respectively. Switches SW1 and SW2 are controlled by signal CP1. When signal CP1 is high, switches SW1 and SW2 are turned on; the positive and negative input terminals of the second-stage preamplifier are connected across switch SW3, the enable terminal is used to receive signal CP3, and the output terminals are connected to the input terminals of the latch comparator. Switch SW3 is controlled by signal CP2; when signal CP2 is high, switch SW3 is turned on; the enable terminal of the latch comparator is used to receive signal CP4; the first unit transmits the positive and negative voltages output by the series battery pack, as well as the reference signal Vref1, to the second unit according to the first control signal, so that the voltage and current protection circuit can adjust according to switch SW1 and switch SW2. The switching states of SW2 and SW3, as well as signals CP3, CP4, φ1, and φ2, enable the circuit to operate in current protection mode. Alternatively, the voltage SRP at the first terminal and the voltage SRN at the second terminal of the peripheral circuit sensing resistor, along with a reference signal Vref2, are transmitted to the second unit according to the first control signal. This allows the voltage and current protection circuit to operate in voltage protection mode based on the switching states of SW1, SW2, and SW3, as well as signals CP3, CP4, φ1, and φ2, thus providing both current and voltage protection functions, saving circuit area and reducing costs.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 This is a schematic diagram illustrating an application scenario of a series battery pack protection circuit provided by the present invention.

[0020] Figure 2A schematic diagram of a voltage and current protection circuit provided by the present invention;

[0021] Figure 3 This is a schematic diagram of the structure of the second unit of a switched capacitor circuit provided by the present invention;

[0022] Figure 4 A timing diagram of a voltage and current protection circuit provided by the present invention;

[0023] Figure 5 A schematic diagram of a switched capacitor provided by the present invention;

[0024] Figure 6 A schematic diagram of the structure of a first-stage amplifier provided by the present invention;

[0025] Figure 7 A schematic diagram of the structure of a second-stage preamplifier provided by the present invention;

[0026] Figure 8 A schematic diagram of a latch comparator provided by the present invention;

[0027] Figure 9 A schematic diagram of a discharge short-circuit overcurrent protection circuit provided by the present invention;

[0028] Figure 10 This is a schematic diagram of an over-temperature protection circuit provided by the present invention. Detailed Implementation

[0029] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0030] Figure 1 This diagram illustrates an application scenario of a series battery pack protection circuit provided by the present invention, including peripheral circuitry and the series battery pack protection circuit itself. The peripheral circuitry includes a 12-cell series battery pack output, an RC filter network, and a current sensing resistor R. SENSE The circuit includes a high-side charging switch (CHW) and a discharging switch (DSW). An RC filter circuit reduces noise interference in the output voltage input signal of the series battery pack. The current sensing resistor (SRN and SRP) is connected to the series battery pack protection circuit. External current flows through resistor R. SENSE A voltage drop is generated, and the series battery pack protection circuit measures the resistance R. SENSE The voltage drop is used to detect the charging and discharging current status of the circuit. CHG is connected to the gate of CSW to control the switching state of the charging switch; DSG is connected to the gate of DSW to control the switching state of the discharging switch.

[0031] The series battery pack protection circuit may specifically include voltage and current protection circuits, short-circuit and overcurrent protection circuits, over-temperature protection circuits, digital control circuits, and switch drive circuits. The output voltage signal of the series battery pack is selected by a high-voltage multiplexer, and the two output ports output the positive and negative voltages of the selected series battery pack, respectively, which are then transmitted to the voltage and current protection circuit. Current sensing resistor R... SENSE The input voltages at both ends are also fed into the voltage and current protection circuit to achieve overcurrent protection during charging and discharging. These two input terminals are also connected to the short-circuit protection circuit. The over-temperature protection circuit determines whether there is an over-temperature risk by using an internal current proportional to absolute temperature (PTAT). The output signal of the above protection circuit, after passing through the digital control circuit and the high-side switch drive circuit, controls the switching state of the charging and discharging transistors in the peripheral circuit via the DSG and CHG outputs, thereby achieving protection management of the series battery pack output.

[0032] Figure 2 This is a schematic diagram of a series battery pack protection circuit provided by the present invention, as shown below. Figure 2 As shown, the circuit includes:

[0033] Voltage and current protection circuit.

[0034] The voltage and current protection circuit includes a switched capacitor circuit 21, a first-stage amplifier 22 with a closed-loop switch and a dual-input dual-output circuit, a second-stage preamplifier 23 with an input reset switch, a latch comparator 24, and switches SW1, SW2, and SW3.

[0035] The switched capacitor circuit 21 includes a first unit 211 and a second unit 212.

[0036] The input terminals of the first unit 211 are used to receive the positive voltage Vn and negative voltage Vp output by the series battery pack, the voltage SRP on the first terminal and the voltage SRN on the second terminal of the peripheral circuit sensing resistor, as well as the reference signal Vref1, the reference signal Vref2 and the first control signal. The output terminals are all connected to the second unit.

[0037] The first and second output terminals of the second unit 212 are respectively connected to the positive input terminal and the inverted input terminal of the first stage amplifier 22. The control signal input terminals of the second unit 212 are used to receive signals φ1 and φ2 respectively.

[0038] The first and second output terminals of the first-stage amplifier 22 are respectively connected to the inverted input terminal and the positive input terminal of the second-stage preamplifier 23.

[0039] The positive input terminal and first output terminal, negative input terminal and second output terminal of the first stage amplifier 22 are respectively connected across switch SW1 and switch SW2. Switch SW1 and switch SW2 are controlled by signal CP1. When signal CP1 is high, switch SW1 and switch SW2 are turned on.

[0040] The positive and negative input terminals of the second-stage preamplifier 23 are connected across the two ends of switch SW3, the enable terminal is used to receive signal CP3, and the output terminals are connected to the input terminals of latch comparator 24.

[0041] The enable terminal of latch comparator 24 is used to receive signal CP4. Switch SW3 is controlled by signal CP2. When signal CP2 is high, switch SW3 is turned on.

[0042] The first unit 211 transmits the positive and negative voltages output by the series battery pack, as well as the reference signal Vref1, to the second unit 212 according to the first control signal, so that the voltage and current protection circuit operates in the current protection mode according to the switching states of switches SW1, SW2, and SW3, as well as signals CP3, CP4, φ1, and φ2. Alternatively, it transmits the voltage SRP on the first terminal and the voltage SRN on the second terminal of the peripheral circuit sensing resistor, as well as the reference signal Vref2, to the second unit 212 according to the first control signal, so that the voltage and current protection circuit operates in the voltage protection mode according to the switching states of switches SW1, SW2, and SW3, as well as signals CP3, CP4, φ1, and φ2.

[0043] Specifically, when signal CP3 is high, the second-stage preamplifier 23 operates normally; when signal CP4 is high, the latch comparator 24 operates normally.

[0044] This circuit can provide both current and voltage protection, saving circuit area and reducing costs.

[0045] Comparators compare the magnitude of an input voltage with a threshold voltage and are commonly used integrated circuit modules in BMS (Battery Management Systems). Comparators can be divided into continuous-time comparators and discrete-time comparators. Continuous-time comparators can output a result at any time, while discrete-time comparators are clock-driven and can only output a comparison result within a certain time interval of the clock. Switched-capacitor comparators are a type of discrete-time comparator. They are often used in analog-to-digital converters (ADCs), combining the comparator with a switched-capacitor circuit. This allows for automatic zeroing of the DC offset voltage and comparison of differential signals using a single-ended circuit. Current research largely focuses on improving the speed and accuracy of switched-capacitor comparators; however, switched-capacitor comparators suffer from relatively limited structural and comparison modes. Switched-capacitor comparators typically utilize the low offset characteristic of switched-capacitor circuits to directly compare the input voltage with a reference voltage. Alternatively, based on the shared charge characteristic of capacitors, the connection relationship between the capacitor array and the reference voltage can be controlled to change the comparison threshold, achieving a more accurate comparison result. However, this method limits the comparison threshold to the reference voltage, failing to meet the needs of various scenarios.

[0046] Furthermore, the present invention in Figure 2 Based on the circuit shown, a second unit circuit structure is also provided, such as... Figure 3 As shown, the second unit includes:

[0047] Switches K1, K2, K3, K4, K5, K6, K7, and K8; capacitors C1, C2, C3, C4, C5, and C6.

[0048] The first terminals of switches K1, K2, and K3, as well as the first terminals of switches K6, K7, and K8, are all connected to the first unit.

[0049] The first end of capacitor C1 is connected to the second end of switch K1 and the second end of switch K2 respectively. The second end of capacitor C1 is connected to the second end of capacitor C2, the second end of capacitor C6 and the positive input terminal of the first stage amplifier respectively.

[0050] The first terminal of capacitor C2 is connected to switch K3 and switch K4 respectively.

[0051] The first end of capacitor C3 is connected to the second end of switch K5 and the second end of switch K6 respectively. The second end of capacitor C3 is connected to the second end of capacitor C4, the second end of capacitor C5 and the negative input terminal of the first stage amplifier respectively.

[0052] The first terminal of capacitor C4 is connected to switch K7 and switch K8 respectively.

[0053] Switches K1, K3, K5, and K7 are controlled by signal φ1. When signal φ1 is high, switches K1, K3, K5, and K7 are turned on.

[0054] Switches K2, K3, K6, and K8 are controlled by signal φ2. When signal φ2 is high, switches K2, K3, K6, and K8 are turned on.

[0055] The following is combined with Figure 4 The timing diagram shown provides a detailed explanation. Figure 2 The operating timing sequence of the voltage and current protection circuit shown includes:

[0056] Within any given period:

[0057] At time t1, signal φ2 reaches the falling edge; at time t2, signals φ1 and φ2 are at a low level, and signal CP1 reaches the rising edge; at time t3, signal φ1 reaches the rising edge; at time t4, signal CP1 reaches the falling edge; at time t5, signal φ1 reaches the falling edge; at time t6, signal CP2 reaches the rising edge; at time t7, signal φ2 reaches the rising edge; at time t8, signal CP2 reaches the falling edge, and signal CP3 reaches the rising edge at the same time; at time t9, signal CP4 reaches the rising edge; at time t10, signals CP3 and CP4 simultaneously reach the falling edge.

[0058] Optional, in Figure 3 In the circuit shown, the capacitance of capacitor C1 is equal to the capacitance of capacitor C4, the capacitance of capacitor C2 is equal to the capacitance of capacitor C3, and the capacitance of capacitor C5 is equal to the capacitance of capacitor C6.

[0059] When signal φ1 is high and signal φ2 is low, the lower plate of capacitor C1 is connected to the reverse voltage Vn, the lower plate of capacitor C2 is connected to the reference voltage V-ref, the lower plate of capacitor C3 is connected to ground GND, and the lower plate of capacitor C4 is connected to the forward voltage Vp. When signal φ1 is low and signal φ2 is high, capacitor C1 is connected to the forward voltage Vp, the lower plate of capacitor C2 is connected to ground GND, the lower plate of capacitor C3 is connected to the reference voltage V-ref, and the lower plate of capacitor C4 is connected to the reverse voltage Vn.

[0060] Wherein, when the reverse voltage Vn is the negative voltage output by the series battery pack, the forward voltage Vp is the positive voltage output by the series battery pack, and the reference voltage V-ref is the reference signal Vref1; when the reverse voltage Vn is the voltage SRN on the second terminal of the sensing resistor of the peripheral circuit, the forward voltage Vp is the voltage SRP on the first terminal of the sensing resistor of the peripheral circuit, and the reference voltage V-ref is the reference signal Vref2.

[0061] The following is combined Figure 4 right Figure 3 The principle of the circuit shown will be analyzed:

[0062] The switched capacitor circuit transmits the first output signal V through its second unit. o1 The output is fed to the positive input of the first-stage amplifier, and the second output signal V... o2 The output is sent to the inverting input of the first-stage amplifier. The first-stage amplifier has common-mode feedback. Assuming the common-mode feedback voltage is VREF, at time t2, the first-stage amplifier closes its loop, charging the voltage on the upper plate of the capacitor to VREF (i.e., ...). Figure 3 The voltage values ​​of the two output signals Vo1 and Vo2 are both set to VREF. Simultaneously, the closed loop stores the DC input offset voltage through capacitors C5 and C6, reducing the impact of the offset voltage and improving comparison accuracy. At time t6, the two input ports of the second-stage preamplifier are short-circuited for reset, eliminating the influence of residual charge in the circuit. The voltage on the upper plates of each capacitor changes until time t7. At this time, the voltage at the positive input terminal of the first-stage amplifier is:

[0063]

[0064] Where C1, C2 and C5 represent respectively Figure 3 The capacitance values ​​of capacitors C1, C2, and C5, Vp and Vn respectively represent Figure 3 The voltage values ​​of Vp and Vn, where Vref represents... Figure 3 The voltage value of V-ref is shown in the figure, and Vin1 represents the voltage value at the positive input terminal of the first-stage amplifier.

[0065] The voltage at the inverting input of the first-stage amplifier is:

[0066]

[0067] Where C3, C4 and C6 respectively represent Figure 3 The values ​​of capacitors C3, C4, and C6 are given, and Vin2 represents the voltage at the inverting input of the first-stage amplifier.

[0068] For the two equations above to have the same absolute value, the following condition must be met for a comparison to be effective:

[0069] V n <V p ,

[0070] The voltage difference across the input terminals of the first-stage amplifier is:

[0071]

[0072] After a simple transformation, we obtain:

[0073]

[0074] Wherein, coefficient A satisfies:

[0075] Keep coefficient A constant, that is, keep the value of capacitor C1 constant, and keep the sum of the values ​​of capacitor C2 and capacitor C5 constant.

[0076] When the value of capacitor C1 is equal to the value of capacitor C2, that is, when C1 = C2, the comparison threshold is the reference voltage.

[0077] Changing the value of capacitor C2 will change the threshold of the comparator by:

[0078]

[0079] in, ΔC2 This indicates the change in the capacitance value of capacitor C2.

[0080] It is easy to see that, with the reference voltage and capacitor C1 fixed, the threshold step size is determined by... ΔC2 The minimum step size for the threshold is determined to be:

[0081]

[0082] The maximum possible range of the threshold variation is:

[0083]

[0084] At time t8, the second-stage preamplifier starts working; at time t9, the latch comparator starts working; and at time t10, the second-stage preamplifier and the latch comparator are turned off simultaneously, completing the comparison.

[0085] As can be seen from the above analysis, the circuit structure provided by this invention, under the condition of a fixed reference voltage, utilizes a switched capacitor circuit and timing control logic to achieve multi-level selection of the comparator's comparison threshold, and the comparison threshold voltage range is not limited by the reference voltage. The threshold level interval can be achieved by adjusting the capacitance value of a single capacitor in the switched capacitor circuit.

[0086] To further demonstrate the beneficial effects of this invention, a set of comparative quantitative analysis data between this invention and a SAR ADC is provided. Since this invention directly compares the output results and does not have a digital feedback module, it does not involve the concept of bit depth. The letter M represents the number of unit capacitors connected to the input voltage. Referring to Table 1, with a fixed reference voltage Vref, compared to a traditional SAR ADC, the threshold step size of this invention is not affected by the total capacitance size and can be adjusted by the size of individual capacitors. Furthermore, the threshold variation range adjusted by capacitor size is larger than that of a traditional SAR ADC, offering greater operability.

[0087] Table 1 Comparison of Circuit Parameters

[0088]

[0089] The switched capacitor circuit provided by this invention can achieve both voltage protection and current protection. In practical applications, the voltage difference between the positive and negative terminals of the battery varies from approximately 0 to 5V, while the voltage difference between the positive and negative terminals of the current sensing resistor in the external circuit varies from 0 to 0.2V. Furthermore, the magnitude of the fluctuations in these two voltages differs within the circuit. Therefore, the selection of the reference voltage and capacitor value will differ when comparing and measuring these two voltages.

[0090] For ease of understanding, the present invention is in Figure 3 A concrete example is also provided, see below. Figure 5 The switched capacitor circuit includes:

[0091] Switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, and S20, and capacitors C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, and C24.

[0092] The fixed terminal of switch S1 is connected to the first terminal of capacitor C7. The first movable terminal is used to receive the negative voltage output by the series battery pack, the second movable terminal is used to receive the positive voltage output by the series battery pack, and the third movable terminal is grounded.

[0093] The fixed terminal of switch S2 is connected to the first terminal of capacitor C8. The first movable terminal is used to receive the voltage on the second terminal of the sensing resistor of the external circuit. The second movable terminal is used to receive the voltage on the first terminal of the sensing resistor of the external circuit. The third movable terminal is grounded.

[0094] The fixed terminals of switches S3, S4, S5, S6, S7, S8 and S9 are respectively connected to the first terminals of capacitors C9, C10, C11, C12, C13, C14 and C15. The first movable terminals of all switches are connected to the fixed terminal of switch S10, and the second movable terminals of all switches are grounded.

[0095] The first active terminal of switch S10 is used to receive reference signal Vref2, and the second active terminal is used to receive reference signal Vref1.

[0096] The fixed terminal of switch S11 is connected to the second terminal of capacitor C16. The first movable terminal is used to receive the negative voltage output by the series battery pack, the second movable terminal is used to receive the positive voltage output by the series battery pack, and the third movable terminal is grounded.

[0097] The fixed terminal of switch S12 is connected to the second terminal of capacitor C17. The first movable terminal is used to receive the voltage on the second terminal of the sensing resistor of the external circuit. The second movable terminal is used to receive the voltage on the first terminal of the sensing resistor of the external circuit. The third movable terminal is grounded.

[0098] The fixed terminals of switches S13, S14, S15, S16, S17, S18 and S19 are respectively connected to the second terminals of capacitors C18, C19, C20, C21, C22, C23 and C24. The first movable terminals of all switches are connected to the fixed terminal of switch S20, and the second movable terminals of all switches are grounded.

[0099] The first active terminal of switch S20 is used to receive reference signal Vref1, and the second active terminal is used to receive reference signal Vref2.

[0100] The capacitance values ​​of capacitors C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, and C24 are 24C, 60C, C, 2C, 4C, 8C, 16C, 32C, and 64C, respectively, where C represents the capacitance value per unit. (Comparison) Figure 3 The circuit shown and Figure 5 In the circuit shown, capacitor C7 is equivalent to Figure 3 Capacitors C1, C9, C10, C11, C12, C13, and C14 are equivalent to Figure 3 The capacitors C6 and C15 are equivalent to Figure 3 In the diagram, C2 and capacitor C16 are equivalent to... Figure 3Capacitors C4, C17, C18, C19, C20, C21, and C22 correspond to... Figure 3 Capacitors C5 and C23 are equivalent to Figure 3 C3 in the middle.

[0101] When measuring and comparing battery voltages, the reference voltage is Vref2. The input voltage is connected to capacitors C7 and C16 (24C) with their lower plates connected to the ground. Capacitors C8 and C17 (60C) have their lower plates grounded. At this point, the circuit's threshold voltage is... The threshold can be adjusted by controlling the capacitance value through a switch, with a threshold step size of [value missing]. The threshold variation range is

[0102] When measuring and comparing the battery charge and discharge currents, the input voltage is connected to capacitors C8 and C17 (60C capacitance) with their lower plates connected together. Capacitors C7 and C16 (24C capacitance) have their lower plates grounded. The reference voltage is Vref1. The threshold step size is... The threshold variation range is

[0103] Furthermore, the present invention also provides a schematic diagram of the structure of a first-stage amplifier, as shown below. Figure 6 As shown, the first-stage amplifier includes: a PMOS transistor M P1-6 PMOS transistor M P2-6 PMOS transistor M P3-6 PMOS transistor M P4-6 PMOS transistor M P5-6 PMOS transistor M P6-6 PMOS transistor M P7-6 PMOS transistor M P8-6 and PMOS transistor M P9-6 NMOS transistor M N1-6 NMOS transistor M N2-6 NMOS transistor M N3-6 NMOS transistor M N4-6 NMOS transistor M N7-6 and NMOS transistor M N8-6 .

[0104] PMOS transistor M P8-6 and PMOS transistor M P9-6 For the input pair, PMOS transistor M P3-6 and PMOS transistor M P6-6 Gate connection common-mode reference voltage V REF PMOS transistor M P2-6 and PMOS transistor M P5-6 The gate terminals are connected to the two output terminals respectively. When the common-mode voltage of the dual-ended output is normal, the NMOS transistor M...N1-6 and NMOS transistor M N2-6 The current in the same path is the same. When the common-mode voltage of the dual-terminal output is higher than the common-mode reference voltage, the NMOS transistor M... N1-6 The current in the path decreases, and the NMOS transistor M... N2-6 As the current in the path increases, the voltage at point A rises, and the output common-mode voltage decreases, achieving the effect of negative feedback to stabilize the common-mode voltage. NMOS transistor M N7-6 and NMOS transistor M N8-6 The diodes are connected in reverse to limit the output swing, thereby meeting the input swing requirements of the subsequent preamplifier.

[0105] Furthermore, the present invention also provides a schematic diagram of the structure of a second-stage preamplifier, as shown below. Figure 7 As shown, the second-stage preamplifier includes: a PMOS transistor M P1-7 PMOS transistor M P2-7 PMOS transistor M P3-7 PMOS transistor M P4-7 PMOS transistor M P5-7 PMOS transistor M P6-7 PMOS transistor M P7-7 and PMOS transistor M P8-7 NMOS transistor M N1-7 NMOS transistor M N2-7 NMOS transistor M N3-7 NMOS transistor M N4-7 NMOS transistor M N5-7 NMOS transistor M N6-7 NMOS transistor M PN7-7 and NMOS transistor M N8-7 .

[0106] Among them, PMOS transistor M P1-7 PMOS transistor M P2-7 PMOS transistor M P3-7 PMOS transistor M P4-7 PMOS transistor M P5-7 PMOS transistor M P6-7 PMOS transistor M P7-7 and PMOS transistor M P8-7 NMOS transistor M N1-7 NMOS transistor M N2-7 NMOS transistor M N3-7 NMOS transistor M N4-7 NMOS transistor M N5-7 NMOS transistor M N6-7 NMOS transistor M N7-7 and NMOS transistor M N8-7As a switching transistor, its gate terminal is connected to the enable terminal. When the enable terminal signal is low, the comparator works normally, and the input is amplified by two stages before being output.

[0107] Furthermore, the present invention also provides a schematic diagram of a latch comparator, as shown below. Figure 8 As shown, the latch comparator includes: a PMOS transistor M P1-8 PMOS transistor M P2-8 PMOS transistor M P3-8 PMOS transistor M P4-8 PMOS transistor M P5-8 PMOS transistor M P6-8 and PMOS transistor M P7-8 NMOS transistor M N1-8 NMOS transistor M N2-8 NMOS transistor M N3-8 NMOS transistor M N4-8 and NMOS transistor M N5-8 .

[0108] Among them, PMOS transistor M P1-8 PMOS transistor M P2-8 PMOS transistor M P7-8 NMOS transistor M N3-8 NMOS transistor M N4-8 and NMOS transistor M N5-8 As a switch controlled by the enable signal, the comparator works normally when the enable signal is high. The comparator achieves positive feedback through cross-coupling, which improves the speed of the comparator. The output terminals are connected to the latch input.

[0109] The voltage and current protection circuit provided by this invention, when the reference voltage is fixed, utilizes a switched capacitor circuit and timing control logic to achieve multi-level selection of the comparator's comparison threshold, and the comparison threshold voltage range is not limited by the reference voltage. The threshold level interval can be achieved by adjusting the capacitance value of a single capacitor in the switched capacitor circuit.

[0110] Furthermore, the series battery pack protection circuit also includes:

[0111] Discharge short circuit overcurrent protection circuit.

[0112] like Figure 9 As shown, the discharge short-circuit overcurrent protection circuit includes current source I1 and current source I2, resistor R, and PMOS transistor M. p1-9 and PMOS transistor M p2-9 , and comparator U1.

[0113] The first terminals of both current source I1 and current source I2 are used to receive power supply VDD.

[0114] The second terminal of current source I2 is connected to the first terminal of resistor R.

[0115] PMOS transistor M p1-9 The gate is connected to the second terminal of the sensing resistor in the external circuit, the source is connected to the second terminal of the current source I1 and the positive input terminal of the comparator U1 respectively, and the drain is grounded.

[0116] PMOS transistor M p2-9 The gate is connected to the first terminal of the sensing resistor in the peripheral circuit, the source is connected to the second terminal of the resistor R and the negative input terminal of the comparator U1 respectively, and the drain is grounded.

[0117] Optional, PMOS transistor M p1-9 and PMOS transistor M p2-9 They are the same size.

[0118] Specifically, for the overcurrent protection circuit under battery discharge short-circuit conditions, the input voltage SRN > SRP, where the bias current I1 = I2, and the PMOS transistor M... p1-9 and PMOS transistor M p2-9 The transistors are of the same size, ensuring that the source-terminal voltage difference between the two transistors is the same as the input voltage difference when the current flows through them is the same. Different threshold comparisons can be achieved by adjusting the value of resistor R or the magnitude of the bias current, where the threshold value V... TH =I·R, which compares the input voltage. When the input SRN < SRP + V TH When the output is low, the circuit is discharging normally. When the input SRN > SRP + V TH The output is high level, which, after being processed by digital circuitry, triggers overcurrent protection in the discharge state.

[0119] The short-circuit overcurrent protection circuit provided by this invention achieves adjustable threshold voltage comparison by controlling the magnitude of the bias current and the resistance value.

[0120] Furthermore, the series battery pack protection circuit also includes:

[0121] Over-temperature protection circuit.

[0122] like Figure 10 As shown, the over-temperature protection circuit includes resistors R1 and R2, and an NMOS transistor M. N1 Comparator U2, and inverters N1 and N2.

[0123] The first terminal of resistor R2 is used to receive the PATA current in the series battery pack protection circuit, and the second terminal is connected to the first terminal of resistor R1 and the NMOS transistor M. N1 The drain connection.

[0124] The second terminal of resistor R1 and NMOS transistor M N1 The source electrode is grounded.

[0125] The positive input of comparator U2 is connected to the first terminal of resistor R2, and the negative input is used to receive the reference voltage V. REF The output terminal is connected to the input terminal of inverter N1.

[0126] The output of inverter N1 is connected to the input of inverter N2 and NMOS transistor M, respectively. N1 The gate connection.

[0127] Figure I PTAT = k·T, where k is the positive temperature correlation coefficient and T is the temperature. PTAT It is directly proportional to temperature. Under normal temperature conditions, the NMOS transistor M... N1 When the switch is turned on, the input voltage at the positive terminal of comparator U2 is I. PTAT ·R2, at this time I PTAT ·R2<V REF The output voltage is low. When the temperature exceeds a certain value, I... PTAT ·R2>V REF The output voltage jumps to a high level, indicating that the circuit is in an over-temperature state, triggering the over-temperature protection. At the same time, the NMOS transistor M... N1 When the gate terminal goes low, comparator U2 is reset, and NMOS transistor M... N1 When turned off, the input voltage at the positive terminal of comparator U2 becomes I. PTAT ·(R1+R2). Only when the temperature decreases, I PTAT ·(R1+R2)<V REF When the temperature reaches a certain level, the output will switch back to a low level, and the over-temperature protection will be released.

[0128] The over-temperature protection circuit of this invention changes the input voltage by altering the resistance value of the input resistor. The comparator then compares the voltage magnitudes to determine the over-temperature state. This ensures that after the over-temperature protection is triggered, the output of the over-temperature protection circuit will not change due to temperature fluctuations, thus enhancing the stability of the over-temperature protection, ensuring the effectiveness of over-temperature protection release, and meeting the needs of practical applications.

[0129] The present invention also provides a chip including a series battery pack protection circuit as provided in any of the above embodiments.

[0130] The present invention also provides an electronic device, including the chip provided in the above embodiments.

[0131] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0132] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A series battery pack protection circuit, characterized in that, include: Voltage and current protection circuit; The voltage and current protection circuit includes a switched capacitor circuit, a first-stage amplifier with a closed-loop switch and a double-ended input and double-ended output, a second-stage preamplifier with an input reset switch and a latch comparator, switches SW1, SW2 and SW3, and the switched capacitor circuit includes a first unit and a second unit. The input terminals of the first unit are respectively used to receive the positive and negative voltages output by the series battery pack, the voltage SRP on the first terminal and the voltage SRN on the second terminal of the peripheral circuit sensing resistor, as well as the reference signal Vref1, the reference signal Vref2 and the first control signal, and the output terminals are all connected to the second unit. The first output terminal and the second output terminal of the second unit are respectively connected to the positive input terminal and the inverted input terminal of the first stage amplifier, and the control signal input terminal of the second unit is used to receive signal Φ1 and signal Φ2 respectively; The first output terminal and the second output terminal of the first stage amplifier are respectively connected to the inverting input terminal and the non-inverting input terminal of the second stage preamplifier; The positive input terminal and the first output terminal, the negative input terminal and the second output terminal of the first stage amplifier are respectively connected across the two ends of the switch SW1 and the switch SW2. The switch SW1 and the switch SW2 are controlled by the signal CP1. When the signal CP1 is high, the switch SW1 and the switch SW2 are turned on. The positive and negative input terminals of the second-stage preamplifier are connected across the two ends of the switch SW3. The enable terminal is used to receive the signal CP3, and the output terminals are respectively connected to the input terminals of the latch comparator. The switch SW3 is controlled by the signal CP2. When the signal CP2 is high, the switch SW3 is turned on. The enable terminal of the latch comparator is used to receive signal CP4; The first unit transmits the positive and negative voltages output by the series battery pack, as well as the reference signal Vref1, to the second unit according to the first control signal, so that the voltage and current protection circuit operates in current protection mode according to the switching states of the switches SW1, SW2, and SW3, as well as the signals CP3, CP4, φ1, and φ2. Alternatively, the first unit transmits the voltage SRP on the first terminal and the voltage SRN on the second terminal of the peripheral circuit sensing resistor, as well as the reference signal Vref2, to the second unit according to the first control signal, so that the voltage and current protection circuit operates in voltage protection mode according to the switching states of the switches SW1, SW2, and SW3, as well as the signals CP3, CP4, φ1, and φ2.

2. The circuit according to claim 1, characterized in that, The second unit includes: Switches K1, K2, K3, K4, K5, K6, K7 and K8; capacitors C1, C2, C3, C4, C5 and C6. The first ends of switch K1, switch K2, and switch K3, as well as the first ends of switch K6, switch K7, and switch K8, are all connected to the first unit; The first end of capacitor C1 is connected to the second end of switch K1 and the second end of switch K2 respectively. The second end of capacitor C1 is connected to the second end of capacitor C2, the second end of capacitor C6 and the positive input terminal of the first stage amplifier respectively. The first terminal of capacitor C2 is connected to switch K3 and switch K4 respectively; The first terminal of capacitor C3 is connected to the second terminal of switch K5 and the second terminal of switch K6 respectively. The second terminal of capacitor C3 is connected to the second terminal of capacitor C4, the second terminal of capacitor C5 and the negative input terminal of the first stage amplifier respectively. The first terminal of the capacitor C4 is connected to the switch K7 and the switch K8 respectively; The switches K1, K3, K5, and K7 are controlled by the signal φ1. When the signal φ1 is high, the switches K1, K3, K5, and K7 are turned on. The switches K2, K3, K6, and K8 are controlled by the signal φ2. When the signal φ2 is high, the switches K2, K3, K6, and K8 are turned on.

3. The circuit according to claim 2, characterized in that, The capacitance of capacitor C1 is equal to the capacitance of capacitor C4, the capacitance of capacitor C2 is equal to the capacitance of capacitor C3, and the capacitance of capacitor C5 is equal to the capacitance of capacitor C6.

4. The circuit according to claim 2 or 3, characterized in that, Also includes: Discharge short-circuit overcurrent protection circuit; The discharge short-circuit overcurrent protection circuit includes current source I1 and current source I2, resistor R, and PMOS transistor M. p1-8 and PMOS transistor M p2-8 and comparator U1; The first terminals of both current source I1 and current source I2 are used to receive power supply VDD; The second end of the current source I2 is connected to the first end of the resistor R; The PMOS transistor M p1-8 The gate is connected to the second terminal of the sensing resistor in the peripheral circuit, the source is connected to the second terminal of the current source I1 and the positive input terminal of the comparator U1 respectively, and the drain is grounded. The PMOS transistor M p2-8 The gate is connected to the first terminal of the sensing resistor in the peripheral circuit, the source is connected to the second terminal of the resistor R and the negative input terminal of the comparator U1, and the drain is grounded.

5. The circuit according to claim 4, characterized in that, The PMOS transistor M p1-8 and PMOS transistor M p2-8 They are the same size.

6. The circuit according to claim 2 or 3, characterized in that, Also includes: Over-temperature protection circuit; The over-temperature protection circuit includes resistors R1 and R2, and an NMOS transistor M. N1 Comparator U2, and inverters N1 and N2; The first terminal of resistor R2 is used to receive the PATA current in the series battery pack protection circuit, and the second terminal is connected to the first terminal of resistor R1 and the NMOS transistor M. N1 Drain connection; The second terminal of resistor R1 and the NMOS transistor M N1 The source is grounded; The positive input terminal of the comparator U2 is connected to the first terminal of the resistor R2, and the negative input terminal is used to receive the reference voltage V. REF The output terminal is connected to the input terminal of the inverter N1; The output terminal of inverter N1 is connected to the input terminal of inverter N2 and the NMOS transistor M, respectively. N1 The gate connection.

7. The circuit according to claim 1, characterized in that, The voltage and current protection circuit includes: Switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, and S20, and capacitors C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, and C24; The fixed terminal of the switch S1 is connected to the first terminal of the capacitor C7, the first movable terminal is used to receive the negative voltage output by the series battery pack, the second movable terminal is used to receive the positive voltage output by the series battery pack, and the third movable terminal is grounded. The fixed terminal of the switch S2 is connected to the first terminal of the capacitor C8, the first movable terminal is used to receive the voltage on the second terminal of the sensing resistor of the external circuit, the second movable terminal is used to receive the voltage on the first terminal of the sensing resistor of the external circuit, and the third movable terminal is grounded. The fixed terminals of switches S3, S4, S5, S6, S7, S8, and S9 are respectively connected to the first terminals of capacitors C9, C10, C11, C12, C13, C14, and C15. The first movable terminals of all switches S10 are connected to the fixed terminal of switch S10, and the second movable terminals of all switches S10 are grounded. The first active terminal of the switch S10 is used to receive the reference signal Vref2, and the second active terminal is used to receive the reference signal Vref1. The fixed terminal of the switch S11 is connected to the second terminal of the capacitor C16, the first movable terminal is used to receive the negative voltage output by the series battery pack, the second movable terminal is used to receive the positive voltage output by the series battery pack, and the third movable terminal is grounded. The fixed end of the switch S12 is connected to the second end of the capacitor C17, the first movable end is used to receive the voltage on the second end of the sensing resistor of the external circuit, the second movable end is used to receive the voltage on the first end of the sensing resistor of the external circuit, and the third movable end is grounded. The fixed terminals of switches S13, S14, S15, S16, S17, S18, and S19 are respectively connected to the second terminals of capacitors C18, C19, C20, C21, C22, C23, and C24. The first movable terminals of all switches S13, S14, S15, S16, S17, S18, and S19 are connected to the fixed terminal of switch S20, and the second movable terminals of all switches S20 are grounded. The first active terminal of the switch S20 is used to receive the reference signal Vref1, and the second active terminal is used to receive the reference signal Vref2.

8. The circuit according to claim 2 or 3, characterized in that, The operating timing sequence of the switched capacitor circuit includes: Within any given period: At time t1, the signal φ2 reaches the falling edge; At time t2, signals φ1 and φ2 are at a low level, and signal CP1 reaches its rising edge; At time t3, the signal φ1 reaches its rising edge; At time t4, the signal CP1 reaches its falling edge; At time t5, the signal φ1 reaches the rising edge; At time t6, signal CP2 reaches the rising edge; At time t7, the signal φ2 reaches its rising edge; At time t8, signal CP2 reaches its falling edge, and signal CP3 reaches its rising edge. At time t9, the signal CP4 reaches its rising edge; At time t10, signals CP3 and CP4 arrive at the falling edge simultaneously.

9. A chip, characterized in that, Includes the series battery pack protection circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the chip as described in claim 9.

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