Analog-to-digital conversion circuit and electronic equipment

Abstract

The present invention provides an analog-to-digital conversion circuit and electronic equipment, which relates to the field of integrated circuits. The coarse quantization unit and the fine quantization unit simultaneously sample the input differential signal and store it on the capacitor array of the fine quantization unit. The coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage quantity and obtains 2 M The ‑1-bit thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit, and is transcoded to obtain an M-bit binary code. The fine quantization unit, in conjunction with the redundant bit capacitor and the resistor string unit, calibrates and fine-quantizes the residual voltage to obtain an N+2-bit binary code. The digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain an M+N-bit binary code and output it. The present invention successfully solves the problem of mismatch between the coarse and fine quantization of the entire ADC due to limited coarse quantization accuracy. This enables the analog-to-digital conversion circuit proposed in the present invention to achieve the accuracy of a traditional high-precision SAR ADC. The overall power consumption is saved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an analog-to-digital conversion circuit and electronic equipment. Background Art

[0002] Analog-to-digital converters (ADCs) are a crucial bridge between the physical and virtual worlds. The development of IoT systems often requires ADCs with medium-to-high precision and high energy efficiency. Successive approximation register ADCs (SAR ADCs) are currently the most widely used ADCs.

[0003] Currently, there are several improvements to the traditional SAR ADC architecture, such as those with separate coarse and fine quantization. However, these SAR ADCs suffer from a mismatch between the coarse and fine quantization accuracies, resulting in excessively large residual voltages during fine quantization, preventing proper quantization. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide an analog-to-digital conversion circuit and an electronic device that solve the above problems or partially solve the above problems.

[0005] A first aspect of an embodiment of the present invention provides an analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising: a coarse quantization unit, a fine quantization unit, a resistor string unit, and a digital error correction unit;

[0006] The coarse quantization unit and the fine quantization unit simultaneously sample the input differential signal and end sampling at the falling edge of a sampling clock, and store a voltage corresponding to the input differential signal on a capacitor array of the fine quantization unit, wherein the capacitor array of the fine quantization unit includes a thermometer code capacitor, a binary capacitor, and a redundant bit capacitor;

[0007] After the sampling is completed, the coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage quantity to obtain 2 M -1-bit thermometer code, and after the coarse quantization is completed, the quantized thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit, and at the same time, the quantized thermometer code is transcoded to obtain an M-bit binary code and transmitted to the digital error correction unit;

[0008] The fine quantization unit performs a subtraction operation using the capacitor array based on the thermometer code capacitor control logic and the voltage to obtain a residual voltage, and calibrates and fine-quantizes the residual voltage in combination with the redundant bit capacitor and the resistor string unit to obtain an N+2-bit binary code, which is then transmitted to the digital error correction unit;

[0009] The digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain and output an M+N-bit binary code, where the M+N-bit binary code is a digital value corresponding to the voltage.

[0010] Optionally, the coarse quantization unit includes: a comparator array, a thermometer code register, and a thermometer code to binary code decoder;

[0011] Each comparator in the comparator array has: a pair of positive and negative input terminals of the comparator connected to the two ends of a unit resistor in the resistor string unit respectively, and another pair of positive and negative input terminals receiving the input differential signal;

[0012] The output terminals of all comparators are connected to the thermometer code register;

[0013] The thermometer code register is connected to the thermometer code to binary code decoder;

[0014] Among them, one end of the resistor string unit receives the reference voltage and the other end is grounded, so the resistor string unit generates 2 M -1 reference voltage, respectively V R1 ,V R2 ,…,V R2 M -1 , the 2 M -1 reference voltage is provided to 2 M - 1 comparator as the reference voltage for each comparator;

[0015] During the coarse quantization, each comparator generates a code value of 0 or 1 according to the size of its own reference voltage and the input differential voltage. All comparators generate a total of 2 M -1-bit thermometer code and transmitted to the thermometer code register for storage;

[0016] The thermometer code register will be the 2 M -1 bit thermometer code is transmitted to the thermometer code capacitor control logic and the thermometer code to binary code decoder;

[0017] The thermometer code to binary code decoder is used to convert the 2 M -1 bit thermometer code is transcoded to obtain M bit binary code and transmitted to the digital error correction unit;

[0018] The number of unit resistors in the resistor string unit is: 2 M .

[0019] Optionally, the fine quantization unit includes: the capacitor array, the switch array, the fine quantization comparator and the logic unit; the thermometer code capacitor, the binary capacitor and the redundant bit capacitor all include: sub-capacitors;

[0020] The thermometer code capacitor, the sub-capacitor of the redundant bit capacitor, and each sub-capacitor in the binary capacitor except the target sub-capacitor are connected to three control switches at the bottom, respectively connected to the input differential signal, the reference voltage, and the ground; the top plates are connected to the bias voltage and the two input terminals of the fine quantization comparator; and the output terminal of the fine quantization comparator is connected to the logic unit;

[0021] The lower plate of the target sub-capacitor is connected to three control switches, which are respectively connected to the switch array, the reference voltage and the ground, and the upper plates are connected to the bias voltage and two input terminals of the fine quantization comparator. The switch array is connected to the resistor string unit;

[0022] The thermometer code capacitor is controlled by the thermometer code capacitor control logic, and the lower plate of the thermometer code capacitor is controlled to be grounded or connected to the reference voltage according to the thermometer code, so as to perform the subtraction operation and subtract the coarse quantized voltage to obtain the residual voltage.

[0023] The binary capacitor performs a first successive approximation operation from high to low using the fine quantization comparator and the logic unit, and after the lower plate of the target unit capacitor is determined to be connected to the reference voltage or ground, the switch array in combination with the resistor string unit continues to perform a second successive approximation operation, thereby completing fine quantization;

[0024] During the binary capacitor fine quantization process, if an ultra-fine quantization range occurs, the redundant bit capacitor is used to correct and calibrate the erroneous thermometer code to obtain the N+2-bit binary code, and transmit it to the digital error correction unit;

[0025] The size of each sub-capacitor in the thermometer code capacitor is 2 M C, the redundant capacitor includes: two sub-capacitors, both of which are 2 M-1 C, the binary capacitor neutron capacitance size from 2 M-1 C to 1C, decreasing successively by multiples of 2, wherein the smallest 1C sub-capacitor is the target sub-capacitor.

[0026] Optionally, the redundant capacitor further comprises: two redundant sub-capacitors each having a size of 1C;

[0027] The sizes are all 2 M-1The lower plates of the two redundant sub-capacitors of size C and the two redundant sub-capacitors of size 1C are connected to two control switches, respectively connected to the reference voltage and ground, and the upper plates are connected to the bias voltage.

[0028] Optionally, the switch array comprises: a plurality of switches;

[0029] Each of the switches is controlled by the logic unit, and according to different closing and opening conditions of the switch, the lower plate of the target sub-capacitor receives different voltages generated on the resistor string unit.

[0030] Optionally, in the sampling phase, the sampling signal is valid at a high level, the comparator array in the coarse quantization unit is reset and the output is cleared, and the thermometer code value output by the comparator array is: TH<2 M -1: 1>=00...0000. At the same time, the upper plate of the capacitor array is connected to the bias voltage, and the lower plate is connected to the input differential signal. At this time, the charge on the capacitor array is expressed as:

[0031] Q DACP =(V cM -V in )·2 2M C

[0032] Q DACN =(V CM -V ip )·2 2M C

[0033] In the above formula, Q DACP represents the charge on the capacitor array connected to the positive input of the fine quantization comparator, Q DACN represents the charge on the capacitor array connected to the negative input terminal of the fine quantization comparator;

[0034] The sampling phase ends, the sampling signal is inactive at a low level, and each comparator in the comparator array of the coarse quantization unit outputs a code value of 0 or 1 according to the magnitude of the input differential voltage and the reference voltage, and latches the code value and transmits it to the thermometer code capacitor control logic;

[0035] When the sampling signal is at a low level and is invalid, the switch of the upper plate of the capacitor array connected to the bias voltage is disconnected, the lower plates of all sub-capacitors of the capacitor array connected to the positive input terminal of the fine quantization comparator, excluding the thermometer code capacitor and the target sub-capacitor, are switched from being connected to the input differential signal to being connected to the reference voltage, and the lower plates of all sub-capacitors of the capacitor array connected to the negative input terminal of the fine quantization comparator, excluding the thermometer code capacitor and the target sub-capacitor, are switched from being connected to the input differential signal to being grounded. At this time, the charges at both ends of the capacitor array connected to the positive input terminal and the negative input terminal of the fine quantization comparator are respectively:

[0036] Q DACP =V DACP 2 2M C+V REF ·(2 M -K)·2 M C

[0037] Q DACN =V DACP 2 2M C+V REF ·K·2 M C

[0038] In the above formula, V DACP and V DACN Respectively represent the voltage values ​​of the positive and negative input terminals of the fine quantization comparator, K represents that in the coarse quantization output, there are K 1 code values ​​output, and 2 0 code values ​​output. M -1-K, then according to the principle of charge conservation, the voltages at the positive and negative input terminals of the fine-grained comparator can be obtained as:

[0039]

[0040] Then the following formula is obtained for the fine quantization comparator:

[0041]

[0042] According to the above formula, the thermometer code value is subtracted from the capacitor array to obtain the residual voltage, where is a coarsely quantized voltage value, and the voltage value corresponding to the differential input signal ranges from a negative reference voltage to a positive reference voltage;

[0043] After the subtraction operation is completed to obtain the residual voltage, the remaining voltage on the capacitor array is the residual voltage, and the quantization stage is entered. In the quantization stage, first, the binary capacitor is 2 M -1C sub-capacitance begins to change, V DACP Sub-capacitor 2 MThe lower plate of -1C is switched from the reference voltage to ground, and V DACN Sub-capacitor 2 M When the lower plate of -1C switches from ground to the reference voltage, a voltage change occurs on the upper plate of the sub-capacitor, which is expressed as follows:

[0044]

[0045] If the voltage V DACP >V DACN , then the fine quantization comparator outputs a code value of 1, V DACP Sub-capacitor 2 M -1C's lower plate is kept grounded, V DACN Sub-capacitor 2 M The lower plate of -1C is kept connected to the reference voltage. At this time, the total voltage change of the upper and lower plates of the capacitor array is:

[0046] If the voltage V DACP <V DACN , then the fine quantization comparator outputs a code value of 0, V DACP Sub-capacitor 2 M -1C's lower plate is switched back to the reference voltage, V DACN Sub-capacitor 2 M -1C's lower plate is switched back to ground, and the voltages on the upper and lower plates of the capacitor array remain unchanged;

[0047] Size is 2 M After the -1C sub-capacitance change is completed, the next value is 2 M -2C sub-capacitor begins to change, the fine quantization comparator outputs a code value of 0 or 1 according to the above theory, and determines the sub-capacitor 2 M The lower plate of -2C is connected to the reference voltage or grounded, and the above process is repeated until the last sub-capacitor of 1C is reached, completing the first successive approximation operation.

[0048] Optionally, after completing the first successive approximation operation, the switch array in combination with the resistor string unit continues to perform a second successive approximation operation on the target sub-capacitor. When the second successive approximation operation is an L-bit successive approximation operation, first, the switches in the switch array are closed or turned on, so that the voltage received by the lower plate of the first target sub-capacitor connected to the positive input terminal of the fine quantization comparator is switched from the reference voltage to 1 / 2 of the reference voltage, and the voltage received by the lower plate of the second target sub-capacitor connected to the negative input terminal of the fine quantization comparator is switched from ground to 1 / 2 of the reference voltage.

[0049] If V DACP >V DACN , the voltage received by the lower plate of the first target sub-capacitor and the voltage received by the lower plate of the second target sub-capacitor are both maintained at 1 / 2 of the reference voltage, otherwise the received voltage is restored to the reference voltage and grounded, and then an L-1-bit successive approximation operation is performed until the second successive approximation operation is completed.

[0050] Optionally, the size of each sub-capacitor in the thermometer code capacitor is 2 M C. When the coarse quantization thermometer code is judged to be wrong, the fine quantization unit exceeds the range, and the error voltage caused on the capacitor array after being transmitted to the fine quantization unit is Then the voltage remaining on the plates of the capacitor array is: residual voltage + error voltage;

[0051] The sub-capacitor size of the redundant capacitor is 2 M-1 C, the highest bit capacitance in the binary capacitor is 2 M -1 C, setting the sum of the sub-capacitor weights of the redundant capacitor and the highest sub-capacitor weight to be equivalent to the weight of a single sub-capacitor in the thermometer code capacitor, so that when the thermometer code is erroneous, the code values ​​corresponding to the sub-capacitors of the redundant capacitor and the highest capacitor are both 1 or 0, and the weights of the superposition of the two compensate for the error voltage, and the residual voltage is further quantized by the binary capacitor;

[0052] When the coarsely quantized thermometer code is determined to be correct, the fine quantization unit will not have an over-range situation, the sub-capacitor of the redundant capacitor and the highest-order sub-capacitor do not participate in quantization at the same time, and the code values ​​corresponding to the two are not 1 or 0 at the same time, and there is no error voltage.

[0053] Optionally, the analog-to-digital conversion circuit further includes: an asynchronous clock unit;

[0054] The asynchronous clock unit is configured to generate a quantized clock signal;

[0055] The quantization clock signal is configured to control the switching from the end of the sampling phase to the first successive approximation operation and the second successive approximation operation, and to control the resetting and comparison of the fine quantization comparator;

[0056] The fine quantization comparator is reset during the low-level period of the quantization clock signal, generates the binary code at the rising edge of the fine quantization comparator, and latches the binary code when the quantization clock signal is at a high level. The binary code is transmitted to the digital error correction unit and also to the logic unit to control the switches of the capacitor array, thereby completing the first successive approximation operation and the second successive approximation operation.

[0057] A second aspect of an embodiment of the present invention provides an electronic device, comprising: an analog-to-digital conversion circuit as described in any one of the first aspects.

[0058] In the analog-to-digital conversion circuit provided by the present invention, the coarse quantization unit and the fine quantization unit simultaneously sample the input differential signal, and both end sampling at the falling edge of the sampling clock, and store the voltage corresponding to the input differential signal on the capacitor array of the fine quantization unit. After the sampling is completed, the coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage to obtain 2 M -1-bit thermometer code, and after the coarse quantization is completed, the quantized thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit, and at the same time, the quantized thermometer code is transcoded to obtain an M-bit binary code and transmitted to the digital error correction unit.

[0059] The fine quantization unit is based on the thermometer code capacitor control logic and voltage quantity, and uses the capacitor array to complete the subtraction operation to obtain the residual voltage quantity. The residual voltage quantity is calibrated and quantized together with the redundant bit capacitor and the resistor string unit to obtain an N+2-bit binary code, and transmitted to the digital error correction unit. Finally, the digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain an M+N-bit binary code and output it. The M+N-bit binary code is the digital value corresponding to the voltage quantity.

[0060] The analog-to-digital conversion circuit proposed in the present invention performs coarse and fine quantization sampling simultaneously at the same speed as a traditional SAR ADC. Since coarse quantization can be completed in a very short time after sampling, more time is left for fine quantization when the time is fixed. The cycle of a single comparison is relatively longer, the noise is lower, and the power consumption is also lower.

[0061] The structure incorporates redundant bit calibration logic, combined with redundant bit capacitance, to correct fine quantization over-range issues caused by errors in coarse quantization code value judgment. This successfully resolves the mismatch between coarse and fine quantization in the ADC due to limited coarse quantization accuracy. This also addresses the problem of excessive residual voltage during fine quantization, preventing proper quantization. This enables the proposed analog-to-digital conversion circuit to achieve the same accuracy as traditional high-precision SAR ADCs.

[0062] Furthermore, by time-sharing multiplexing the resistor string units, coarse quantization is achieved while providing a low-bit quantization voltage for fine quantization, saving overall power consumption. Fine quantization using resistor string units for low-bit quantization also reduces the total capacitance of the capacitor array in traditional SAR ADCs to a certain extent and compensates for the high power consumption of the resistor string units caused by meeting speed requirements during coarse quantization. Therefore, the analog-to-digital conversion circuit proposed in this invention has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0064] Figure 1 is an architecture diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention;

[0065] Figure 2 is a structural diagram of a coarse quantization unit in an embodiment of the present invention;

[0066] Figure 3 is a structural diagram of a fine quantization unit in an embodiment of the present invention;

[0067] Figure 4 This is a working timing diagram of a preferred analog-to-digital conversion circuit in an embodiment of the present invention;

[0068] Figure 5 This is a preferred analog-to-digital conversion circuit structure diagram in an embodiment of the present invention;

[0069] Figure 6 is a schematic diagram of a quantization error in a fine quantization unit caused by low quantization accuracy of a coarse quantization unit in an embodiment of the present invention;

[0070] Figure 7 3 is a schematic diagram of a voltage search interval for correcting coarse quantization errors after introducing redundant capacitors in an embodiment of the present invention. DETAILED DESCRIPTION

[0071] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0072] The inventors have found that there are currently many structures that have been improved based on the traditional SAR ADC structure, such as: a two-stage pipeline ADC, a structure based on an operational amplifier and an inter-stage amplifier, various coarse and fine quantization combined structures, and the like.

[0073] The coarse quantization unit in a two-stage pipeline ADC can speed up conversion, but it consumes a significant amount of power. Furthermore, this structure requires an interstage amplifier based on an operational amplifier, which limits bandwidth and also creates a tradeoff between energy efficiency and accuracy. This interstage amplifier structure based on an operational amplifier also limits bandwidth and also creates a tradeoff between energy efficiency and accuracy.

[0074] Furthermore, while some new interstage amplifiers improve the overall energy efficiency of two-stage pipeline ADCs, they often suffer from PVT sensitivity, which means that the performance of the interstage amplifier is affected and degraded by variations in process, voltage, and temperature.

[0075] In response to the above problems, the inventors, after in-depth research, creatively proposed an analog-to-digital conversion circuit and electronic device of the present invention. The technical solution proposed by the present invention is explained and illustrated in detail below.

[0076] The analog-to-digital conversion circuit of the present invention includes: a coarse quantization unit, a fine quantization unit, a resistor string unit, and a digital error correction unit. Figure 1 The architecture diagram of the analog-to-digital conversion circuit shown in FIG. 1 includes a coarse quantization unit, a fine quantization unit, a resistor string unit, and a digital error correction unit.

[0077] During operation, the coarse quantization unit and the fine quantization unit sample the input differential signal simultaneously, and both end sampling at the falling edge of the sampling clock. At this time, the voltage corresponding to the input differential signal is stored on the capacitor array of the fine quantization unit. The capacitor array of the fine quantization unit includes: thermometer code capacitors, binary capacitors and redundant bit capacitors.

[0078] After the sampling is completed, the coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage, and obtains 2 M-1 The quantized thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit after the coarse quantization is completed. At the same time, the quantized thermometer code is transcoded to obtain an M-bit binary code and transmitted to the digital error correction unit.

[0079] After the coarse quantization is completed, the fine quantization unit uses the capacitor array to complete the subtraction operation based on the thermometer code capacitor control logic and voltage to obtain the residual voltage. It then combines the redundant bit capacitors and the resistor string unit to calibrate and quantize the residual voltage to obtain an N+2-bit binary code, which is then transmitted to the digital error correction unit.

[0080] Finally, the digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain and output an M+N-bit binary code. The output M+N-bit binary code is the digital value corresponding to the input differential signal voltage.

[0081] The main working contents of the analog-to-digital conversion unit of the present invention can be divided into three stages:

[0082] In the sampling phase: the coarse quantization unit and the fine quantization unit sample the input differential signal at the same time. At the falling edge of the sampling clock, both units end sampling at the same time. At this time, the input differential signal is stored on the capacitor array.

[0083] The quantization phase then begins: the coarse quantization unit first performs coarse quantization on the input differential signal, using an M-bit quantization bit width. After the coarse quantization unit completes quantization, the generated thermometer code is passed to the thermometer code capacitor control logic of the fine quantization unit (i.e., the logic that controls the thermometer code capacitor switches). The fine quantization unit then performs a subtraction operation using the capacitor array, subtracting the coarse quantization voltage from the remaining fine quantization residual voltage.

[0084] After the thermometer code is transmitted, the fine quantization unit begins the successive approximation quantization of the residual voltage, which is also known as the first successive approximation quantization operation. The fine quantization performed by the fine quantization unit consists of two parts, completing a total of N-bit quantization. First, the capacitor array performs the (NL)-bit quantization, and the resistor string unit (i.e., the multiplexed resistor string unit) completes the final L-bit quantization. Due to the presence of redundant capacitors, the residual voltage can be calibrated, resulting in an N+2-bit binary code. Finally, the digital error correction unit processes the residual voltage to obtain an M+N-bit binary code.

[0085] For the coarse quantization unit, a better coarse quantization unit structure includes: a comparator array, a thermometer code register, and a thermometer code to binary code decoder. For the comparator array, each comparator has:

[0086] A pair of positive and negative input terminals of the comparator are connected to the two ends of a unit resistor in the resistor string unit respectively, and the other pair of positive and negative input terminals receive the input differential signal; that is, the comparator has a total of 4 input terminals, two pairs of positive and negative input terminals. In order to better understand the preferred coarse quantization unit structure, refer to Figure 2 As shown, Figure 2 To better understand the structure of the coarse quantization unit, the resistor string unit and three comparators CMP are shown as examples. This does not mean that the comparator array contains only three comparators. The outputs of all comparators are connected to the thermometer code register, which is connected to the thermometer code-to-binary code decoder.

[0087] Among them, one end of the resistor string unit receives the reference voltage V REF , the other end is grounded GND, then the resistor string unit generates a total of 2 M -1 reference voltage, respectively VR1 ,V R2 ,…,V R2 M -1 , these 2 M -1 reference voltage is provided to 2 M -1 comparator as the reference voltage for each comparator. For the resistor string unit, the number of unit resistors is: 2 M .

[0088] During coarse quantization, each comparator generates a voltage proportional to its own reference voltage and input differential voltage V IN 、V IP The size of the code generates a value of 0 or 1, and all comparators generate a total of 2 M -1-bit thermometer code and transferred to the thermometer code register for storage. Figure 2 Medium CLK S Represents the sampled signal.

[0089] Thermometer Code Register will be 2 M -1 digit thermometer code ( Figure 2 Middle 2 M -1-bit) is transmitted to the thermometer code capacitor control logic ( Figure 2 Thermometer code to binary code decoder 2 M -1 bit thermometer code is converted into M bit binary code ( Figure 2 M-bit) and transmitted to the digital error correction unit ( Figure 2 not shown).

[0090] The thermometer code transmitted to the thermometer code capacitor control logic is used to control the lower plate of the thermometer code capacitor in the fine quantization unit to GND or reference voltage V REF , thereby realizing the voltage subtraction operation and obtaining the residual voltage.

[0091] For the fine quantization unit, a preferred structure of the fine quantization unit includes: a capacitor array, a switch array, a fine quantization comparator and a logic unit; the thermometer code capacitor, the binary capacitor and the redundant bit capacitor all include: sub-capacitors.

[0092] To better understand the structure of the fine quantization unit, refer to Figure 3 , which shows a structural diagram of a fine quantization unit in an embodiment of the present invention. Figure 3 Medium V IN 、V IP represents the input differential voltage, which is stored on the capacitor array at the end of the sampling phase, Figure 3 In the capacitor array, the sub-capacitors in the rightmost dotted box form a thermometer code capacitor. The size of each sub-capacitor in the thermometer code capacitor is 2M C. Figure 3 The M-bit Flah-Stag is used to represent the thermometer code capacitor. The capacitor is controlled by the thermometer code so that the lower plate of the sub-capacitor is connected to GND or the reference voltage V REF , thereby realizing the voltage subtraction operation and obtaining the residual voltage.

[0093] The two sizes of the dotted box (middle dotted box) adjacent to the thermometer code capacitor are both 2 M-1 The sub-capacitors of C form redundant capacitors. Figure 3 The figure also preferably shows two redundant sub-capacitors (dashed boxes on the left) of size 1C, which also constitute redundant capacitors of size 2 M-1 The lower plates of the two redundant sub-capacitors of C and the two redundant sub-capacitors of 1C are connected to two control switches and are respectively connected to the reference voltage V REF and ground GND, the upper plate is connected to the bias voltage V CM . Figure 3 Redundant capacitors, represented by "Redundant Bits," can be used for calibration when the quantization exceeds the range. Two redundant sub-capacitors, each 1C in size, can be placed or not based on accuracy requirements. When accuracy requirements are high, these two redundant sub-capacitors can be placed; when accuracy requirements are relatively low, these two redundant sub-capacitors can be omitted, thus reducing area overhead.

[0094] The sub-capacitors except the three dotted boxes constitute the binary capacitor, the thermometer code capacitor, the sub-capacitor of the redundant bit capacitor, and the sub-capacitor of the binary capacitor except the target sub-capacitor ( Figure 3 Except for the 1C capacitor on the left, the lower plate of each sub-capacitor is connected to three control switches, which are respectively connected to the input differential signal V IN 、V IP , reference voltage V REF and ground GND, the upper plate is connected to the bias voltage V CM , fine quantization comparator ( Figure 3 The output of the fine quantization comparator CMP is connected to the logic unit SAR Logic. The size of the sub-capacitor in the binary capacitor ranges from 2 M-1 From C to 1C, the value decreases in multiples of 2.

[0095] Target subcapacitance ( Figure 3 The lower plate of the leftmost 1C capacitor is connected to three control switches, which are connected to the switch array RDAC, the reference voltage V REF and ground GND, the upper plate is connected to the bias voltage V CM , the two input ends of the fine quantization comparator CMP, the switch array RDAC and the resistor string unit Res Ladder are connected.

[0096] Among them, the thermometer code capacitor is controlled by the thermometer code capacitor control logic, and the lower plate of the thermometer code capacitor is grounded GND or connected to the reference voltage V according to the thermometer code. REF , to perform a subtraction operation, subtract the coarse quantized voltage amount to obtain the residual voltage amount.

[0097] The binary capacitor uses the fine quantization comparator CMP and the logic unit SAR Logic to perform the first successive approximation operation from high to low, and determines the reference voltage V at the lower plate of the target unit capacitor. REF Or after grounding GND, the switch array RDAC and the resistor string unit Res Ladder continue to perform the second successive approximation operation to complete the fine quantization. The switch array includes: multiple switches;

[0098] Each of the switches is controlled by the logic unit, and according to different closing and opening conditions of the switch, the lower plate of the target sub-capacitor receives different voltages generated on the resistor string unit.

[0099] In the process of binary capacitor quantization, if the ultra-fine quantization range occurs, the redundant bit capacitor is used to correct the erroneous thermometer code to obtain N+2-bit binary code and transmit it to the digital error correction unit ( Figure 3 not shown).

[0100] also, Figure 3 In order to better understand the entire analog-to-digital conversion circuit and the implementation of high-speed quantization, Figure 3 In addition to the structure of the fine quantization unit, the asynchronous clock unit ASY_CLK_GNE is also shown. The asynchronous clock unit ASY_CLK_GNE is used to generate a high-speed quantization signal CKC to achieve high-speed quantization, which is different from the sampling information CLK provided by the external clock. S .

[0101] The asynchronous clock unit ASY_CLK_GNE is configured to generate a quantization clock signal CKC; the quantization clock signal CKC is configured to control the switching from the end of the sampling phase to the first successive approximation operation and the second successive approximation operation, and control the resetting and comparison of the fine quantization comparator CMP.

[0102] The fine quantization comparator CMP is reset during the low-level period of the quantization clock signal. A binary code is generated at the rising edge of the fine quantization comparator CMP and latched when the signal is high. The binary code is transmitted to the digital error correction unit and also to the logic unit SAR Logic to control the switching of the capacitor array, completing the first successive approximation operation and the second successive approximation operation. Figure 3RDY represents a start enable signal, which is an enable signal sent by the logic unit SAR Logic to the asynchronous clock unit ASY_CLK_GNE, causing the asynchronous clock unit ASY_CLK_GNE to generate a high-speed quantized clock signal CKC.

[0103] The specific working principle of the coarse and fine quantization of the entire analog-to-digital conversion circuit can be combined Figure 4 The timing diagram shown, Figure 5 The preferred analog-to-digital conversion circuit structure diagram shown is as follows:

[0104] First, in the sampling stage, the sampling signal CLK S High level is valid, the comparator array in the coarse quantization unit is reset and the output is cleared. The thermometer code value output by the comparator array is: TH<2 M -1:1>=00…0000, at the same time, the upper plate of the capacitor array in the fine quantization unit is connected to the bias voltage V CM , the lower plate is connected to the input differential signal V IN 、V IP , the charge on the capacitor array is expressed as:

[0105] Q DACP =(V CM -V in )·2 2M C

[0106] Q DACN =(V CM -V ip )·2 2M C

[0107] In the above formula, Q DACP Represents the charge on the capacitor array connected to the positive input of the fine quantization comparator CMP, Q DACN Represents the charge on the capacitor array connected to the negative input terminal of the fine quantization comparator CMP.

[0108] The sampling phase ends and the sampling signal CLK S Low level is invalid. At this time, each comparator in the comparator array of the coarse quantization unit is based on the input differential voltage V IN 、V IP and reference voltage V REF The code value 0 or 1 is output respectively, and the code value is latched and transmitted to the thermometer code capacitor control logic.

[0109] The sampling signal CLK S When the low level is invalid, the upper plate of the capacitor array is connected to the bias voltage V CMThe switch is disconnected, and the capacitor array at the positive input of the quantization comparator CMP is connected to the lower plate of all sub-capacitors except the thermometer code capacitor and the target sub-capacitor, and the input differential signal V IN 、V IP Switch to the reference voltage V REF , connect the capacitor array of the negative input terminal of the quantization comparator CMP to the lower plate of all sub-capacitors except the thermometer code capacitor and the target sub-capacitor, and connect the input differential signal V IN 、V IP Switch to ground GND. At this time, the charges at both ends of the capacitor array connected to the positive input and negative input of the quantization comparator CMP are:

[0110] Q DACP =V DACP 2 2M C+V REF ·(2 M —K)·2 M C

[0111] Q DACN =V DACP 2 2M C+V REF ·K·2 M C

[0112] In the above formula, V DACP and V DACN They represent the voltage values ​​of the positive and negative input terminals of the fine quantization comparator CMP respectively. K means that in the coarse quantization output, there are K 1 code values ​​output and 2 0 code values ​​output. M -1-K, then according to the principle of charge conservation, the voltages at the positive and negative input terminals of the fine-grained comparator CMP are:

[0113]

[0114] Then for the fine quantization comparator CMP, the following formula is obtained:

[0115]

[0116] According to the above formula, the thermometer code value completes the subtraction operation on the capacitor array to obtain the residual voltage, where is the coarse quantized voltage value, the differential input signal V IN 、V IP The corresponding voltage range is within the negative reference voltage -V REF To the positive reference voltage +V REF between.

[0117] After completing the subtraction operation to obtain the residual voltage, the remaining voltage on the capacitor array is the residual voltage, and the quantization stage begins. In the quantization stage, first, the binary capacitor is 2 M-1 The sub-capacitance of C begins to change, V DACP Sub-capacitor 2 M-1 The lower plate of C is connected to the reference voltage V REF Switch to ground GND, and V DACN Sub-capacitor 2 M-1 The lower plate of C is switched from ground GND to the reference voltage V REF , then a voltage change is generated on the upper plate of the sub-capacitor, and its expression is as follows:

[0118]

[0119] If the voltage V DACP >V DACN , then the fine quantization comparator CMP outputs code value 1, V DACP Sub-capacitor 2 M-1 The lower plate of C is kept grounded GND, V DACN Sub-capacitor 2 M-1 The lower plate of C is kept connected to the reference voltage V REF , at this time, the total change of the upper and lower plate voltages of the capacitor array is: If the voltage V DACP <V DACN , then the fine quantization comparator CMP outputs code value 0, V DACP Sub-capacitor 2 M-1 The lower plate of C is switched back to the reference voltage V REF , V DACN Sub-capacitor 2 M-1 The lower plate of C is switched back to ground GND, and the voltages on the upper and lower plates of the capacitor array remain unchanged.

[0120] Size is 2 M-1 After the sub-capacitance of C changes, the value is 2 M-2 The sub-capacitance of C begins to change, and the fine-grained comparator is 2 M-1 The same principle as the sub-capacitor of C theoretically outputs code value 0 or 1, and determines the sub-capacitor 2 M-2 The lower plate of C is connected to the reference voltage V REF Or ground GND, followed by a value of 2 M-2 The above process is repeated for the sub-capacitors of 1C until the last sub-capacitor of 1C (another sub-capacitor of 1C except the target sub-capacitor of 1C), completing the first successive approximation operation.

[0121] After the first successive approximation operation is completed, the second successive approximation operation is continued on the target sub-capacitor 1C by the switch array RDAC combined with the resistor string unit Res Ladder. When the second successive approximation operation is an L-bit successive approximation operation, the switch of the RDAC in the switch array is first closed or turned on, so that the first target sub-capacitor ( Figure 3 、 Figure 5 The lower plate of the 1C sub-capacitor on the left receives a voltage from the reference voltage V REF Switch to 1 / 2 of the reference voltage V REF , that is, cut to 1 / 2V REF , a second target sub-capacitor connected to the negative input terminal of the fine quantization comparator CMP ( Figure 3 、 Figure 5 The voltage received by the lower plate of the 1C sub-capacitor on the leftmost side of the figure switches from ground GND to 1 / 2 of the reference voltage V REF , that is, cut to 1 / 2V REF .

[0122] If V DACP >V DACN , the voltage received by the lower plate of the first target sub-capacitor and the voltage received by the lower plate of the second target sub-capacitor are both kept at 1 / 2 of the reference voltage, otherwise the received voltage is restored to the reference voltage V REF and ground GND, and then perform the L-1 bit successive approximation operation until the second successive approximation operation is completed.

[0123] It should be noted that Figure 5 Medium CLK D Represents the readout signal, which is used to output the N+M-Bit binary code. FLASH control indicates that the switch of the thermometer code capacitor is controlled by the thermometer code. SAR control indicates that it is controlled by the N+2-Bit code value of the logic unit. VR n and VR p represents the voltage value connected between the lower plates of the two target sub-capacitors (determined by the switch array RDAC and the resistor string unit Res Ladder). Multiple dashed boxes and a comparator CMP, shown as an example in a dashed box, represent the comparator array in the coarse quantization unit. Encoder represents the thermometer code-to-binary code decoder, which generates an M-bit binary code and sends it to the digital error correction unit DEC. The digital error correction unit DEC performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain an N+M-bit binary code, which it outputs to the register array.

[0124] The above working process explains the working process of the analog-to-digital conversion circuit, but does not explain the serious precision mismatch problem in the process of passing the code value obtained by the coarse quantization unit to the fine quantization unit. Since the quantization precision of the coarse quantization unit is low, while the quantization precision of the fine quantization unit is high, when the input voltage is at the quantization boundary of the coarse quantization unit, it is very likely that the coarse quantization interval judgment will be wrong due to the misjudgment of the coarse quantization unit. This will cause the code value obtained by the coarse quantization unit to be passed to the fine quantization unit, and the residual voltage of the fine quantization will be too large to complete the quantization normally. Figure 6 The diagram shown is a schematic diagram of quantization errors in fine quantization units caused by low quantization accuracy of the coarse quantization unit.

[0125] Figure 6 The dashed box on the left shows a schematic diagram when the coarse quantization interval judgment is correct, and the dashed box on the right shows a schematic diagram when the coarse quantization interval judgment is incorrect. It can be seen that when the coarse quantization interval judgment is incorrect, the fine quantization residual voltage will exceed the range.

[0126] Since the size of each sub-capacitor in the thermometer code capacitor is 2 M C. When the coarse quantization thermometer code makes an error, the fine quantization unit will exceed the range. The error voltage caused on the capacitor array after being transmitted to the fine quantization unit is The remaining voltage on the plates of the capacitor array is the residual voltage + the error voltage. However, in a traditional SAR ADC structure, the voltage generated by the accumulation of low-order weights in the capacitor array does not exceed Verror. Therefore, the traditional SAR ADC structure cannot quantify the magnitude of the residual voltage.

[0127] The sub-capacitor size of the redundant capacitor designed by the present invention is 2 M-1 C, the highest bit capacitance in binary capacitance is 2 M-1 C, set the sum of the sub-capacitor weights of the redundant capacitor and the highest-order sub-capacitor weight to be equivalent to the weight of a single sub-capacitor in the thermometer code capacitor. Then, when the thermometer code is wrong, the code values ​​corresponding to the sub-capacitors of the redundant capacitor and the highest-order capacitor are both 1 or 0 at the same time. The superposition of the weights compensates for the error voltage, and the residual voltage is further quantized by the binary capacitor.

[0128] When the coarse quantization thermometer code is correctly determined, the fine quantization unit will not exceed the range. The sub-capacitors of the redundant capacitor and the highest-order sub-capacitor will not participate in quantization at the same time, and the code values ​​corresponding to them will not be 1 or 0 at the same time, resulting in no error voltage. For example, the sub-capacitor size of the redundant capacitor is 16C, and the highest-order capacitor size in the binary capacitor is 16C. The design of two 16C sub-capacitors takes into account the directionality of voltage and implements weighted addition in different directions. The sum of the sub-capacitors and the highest-order binary capacitor 16C is +32C or -32C, equivalent to the thermometer capacitor 32C. When the thermometer code is incorrect, the code values ​​corresponding to the sub-capacitors 16C of the redundant capacitor and the highest-order binary capacitor 16C are both 1 or 0 at the same time, and the weighted sum of the two compensates for the error voltage. When the coarse quantization thermometer code is correctly determined, the fine quantization unit will not exceed the range. The sub-capacitors of the redundant capacitor and the highest-order binary capacitor 16C will not participate in quantization at the same time, and the code values ​​corresponding to them will not be 1 or 0 at the same time, resulting in no error voltage.

[0129] The voltage search interval diagram for correcting coarse quantization errors after introducing redundant capacitors is shown in the figure below. Figure 7 shown. Figure 7 The left side shows the case where the coarse quantization interval judgment is correct when there is redundant capacitance, where B N Indicates the highest bit capacitance of binary, B N-1 It represents the redundant capacitance. When the fine quantization unit does not exceed the range, the redundant capacitance and the highest bit capacitance of the binary are not involved at the same time, so B N and B N-1 It cannot be 1 or 0 at the same time. Figure 7 The right side of the middle figure shows the error in the interval judgment of coarse quantization with redundant capacitors. When the error occurs, the search voltage interval of the fine quantization unit exceeds the range. N and B N-1 It is 1 or 0 at the same time, thereby correcting the error voltage caused by the thermometer code capacitance and ensuring the correctness of subsequent quantization.

[0130] Based on the above analog-to-digital conversion circuit, an embodiment of the present invention further provides an electronic device, which includes: the above analog-to-digital conversion circuit.

[0131] Through the above embodiment, the analog-to-digital conversion circuit provided by the present invention, the coarse quantization unit and the fine quantization unit simultaneously sample the input differential signal, and both end sampling at the falling edge of the sampling clock, and store the voltage corresponding to the input differential signal on the capacitor array of the fine quantization unit. After the sampling is completed, the coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage, and obtains 2 M-1-bit thermometer code, and after the coarse quantization is completed, the quantized thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit, and at the same time, the quantized thermometer code is transcoded to obtain an M-bit binary code and transmitted to the digital error correction unit.

[0132] The fine quantization unit is based on the thermometer code capacitor control logic and voltage quantity, and uses the capacitor array to complete the subtraction operation to obtain the residual voltage quantity. The residual voltage quantity is calibrated and quantized together with the redundant bit capacitor and the resistor string unit to obtain an N+2-bit binary code, and transmitted to the digital error correction unit. Finally, the digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain an M+N-bit binary code and output it. The M+N-bit binary code is the digital value corresponding to the voltage quantity.

[0133] The analog-to-digital conversion circuit proposed in the present invention performs coarse and fine quantization sampling simultaneously at the same speed as a traditional SAR ADC. Since coarse quantization can be completed in a very short time after sampling, more time is left for fine quantization when the time is fixed. The cycle of a single comparison is relatively longer, the noise is lower, and the power consumption is also lower.

[0134] The structure incorporates redundant bit calibration logic, combined with redundant bit capacitance, to correct fine quantization over-range issues caused by errors in coarse quantization code value judgment. This successfully resolves the mismatch between coarse and fine quantization in the ADC due to limited coarse quantization accuracy. This also addresses the problem of excessive residual voltage during fine quantization, preventing proper quantization. This enables the proposed analog-to-digital conversion circuit to achieve the same accuracy as traditional high-precision SAR ADCs.

[0135] Furthermore, by time-sharing multiplexing the resistor string units, coarse quantization is achieved while providing a low-bit quantization voltage for fine quantization, saving overall power consumption. Fine quantization using resistor string units for low-bit quantization also reduces the total capacitance of the capacitor array in traditional SAR ADCs to a certain extent and compensates for the high power consumption of the resistor string units caused by meeting speed requirements during coarse quantization. Therefore, the analog-to-digital conversion circuit proposed in this invention has high practicality.

[0136] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0137] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. An analog-to-digital conversion circuit, characterized in that: The analog-to-digital conversion circuit includes: a coarse quantization unit, a fine quantization unit, a resistor string unit, and a digital error correction unit; The coarse quantization unit and the fine quantization unit simultaneously sample the input differential signal and end sampling at the falling edge of a sampling clock, and store a voltage corresponding to the input differential signal on a capacitor array of the fine quantization unit, wherein the capacitor array of the fine quantization unit includes a thermometer code capacitor, a binary capacitor, and a redundant bit capacitor; After the sampling is completed, the coarse quantization unit first uses the resistor string unit to coarsely quantize the voltage quantity to obtain 2 M -1-bit thermometer code, and after the coarse quantization is completed, the quantized thermometer code is transmitted to the thermometer code capacitor control logic of the fine quantization unit, and at the same time, the quantized thermometer code is transcoded to obtain an M-bit binary code and transmitted to the digital error correction unit; The fine quantization unit performs a subtraction operation using the capacitor array based on the thermometer code capacitor control logic and the voltage to obtain a residual voltage, and calibrates and fine-quantizes the residual voltage in combination with the redundant bit capacitor and the resistor string unit to obtain an N+2-bit binary code, which is then transmitted to the digital error correction unit; The digital error correction unit performs digital error correction on the M-bit binary code and the N+2-bit binary code to obtain and output an M+N-bit binary code, where the M+N-bit binary code is a digital value corresponding to the voltage.

2. The analog-to-digital conversion circuit according to claim 1, wherein: The coarse quantization unit includes: a comparator array, a thermometer code register and a thermometer code to binary code decoder; Each comparator in the comparator array has: a pair of positive and negative input terminals of the comparator connected to the two ends of a unit resistor in the resistor string unit respectively, and another pair of positive and negative input terminals receiving the input differential signal; The output terminals of all comparators are connected to the thermometer code register; The thermometer code register is connected to the thermometer code to binary code decoder; Among them, one end of the resistor string unit receives the reference voltage and the other end is grounded, so the resistor string unit generates 2 M -1 reference voltage, respectively V R1 ,V R2 ,…,V R2 M -1 , the 2 M -1 reference voltage is provided to 2 M - 1 comparator as the reference voltage for each comparator; During the coarse quantization period, each comparator generates a code value of 0 or 1 according to the size of its own reference voltage and input differential voltage. All comparators generate a total of 2 M -1-bit thermometer code and transmitted to the thermometer code register for storage; The thermometer code register will be the 2 M -1 bit thermometer code is transmitted to the thermometer code capacitor control logic and the thermometer code to binary code decoder; The thermometer code to binary code decoder is used to convert the 2 M -1 bit thermometer code is transcoded to obtain M bit binary code and transmitted to the digital error correction unit; The number of unit resistors in the resistor string unit is: 2 M .

3. The analog-to-digital conversion circuit according to claim 1, wherein: The fine quantization unit includes: the capacitor array, the switch array, the fine quantization comparator and the logic unit; the thermometer code capacitor, the binary capacitor and the redundant bit capacitor all include: sub-capacitors; The thermometer code capacitor, the sub-capacitor of the redundant bit capacitor, and each sub-capacitor in the binary capacitor except the target sub-capacitor are connected to three control switches at the bottom, respectively connected to the input differential signal, the reference voltage, and the ground; the top plates are connected to the bias voltage and the two input terminals of the fine quantization comparator; and the output terminal of the fine quantization comparator is connected to the logic unit; The lower plate of the target sub-capacitor is connected to three control switches, which are respectively connected to the switch array, the reference voltage and the ground, and the upper plates are connected to the bias voltage and two input terminals of the fine quantization comparator. The switch array is connected to the resistor string unit; The thermometer code capacitor is controlled by the thermometer code capacitor control logic, and the lower plate of the thermometer code capacitor is controlled to be grounded or connected to the reference voltage according to the thermometer code, so as to perform the subtraction operation and subtract the coarse quantized voltage to obtain the residual voltage. The binary capacitor performs a first successive approximation operation from high to low using the fine quantization comparator and the logic unit, and after the lower plate of the target unit capacitor is determined to be connected to the reference voltage or ground, the switch array in combination with the resistor string unit continues to perform a second successive approximation operation, thereby completing fine quantization; During the binary capacitor fine quantization process, if an ultra-fine quantization range occurs, the redundant bit capacitor is used to correct and calibrate the erroneous thermometer code to obtain the N+2-bit binary code, and transmit it to the digital error correction unit; The size of each sub-capacitor in the thermometer code capacitor is 2 M C, the redundant bit capacitor includes: two sub-capacitors, both of which are 2 M-1 C, the binary capacitor neutron capacitance size from 2 M-1 C to 1C, decreasing successively by multiples of 2, wherein the smallest 1C sub-capacitor is the target sub-capacitor.

4. The analog-to-digital conversion circuit according to claim 3, wherein: The redundant bit capacitor further comprises: two redundant sub-capacitors each having a size of 1C; The sizes are all 2 M-1 The lower plates of the two redundant sub-capacitors of size C and the two redundant sub-capacitors of size 1C are connected to two control switches, respectively connected to the reference voltage and ground, and the upper plates are connected to the bias voltage.

5. The analog-to-digital conversion circuit according to claim 3, wherein: The switch array includes: a plurality of switches; Each of the switches is controlled by the logic unit, and according to different closing and opening conditions of the switch, the lower plate of the target sub-capacitor receives different voltages generated on the resistor string unit.

6. The analog-to-digital conversion circuit according to claim 3, wherein: In the sampling phase, the sampling signal is valid at a high level, the comparator array in the coarse quantization unit is reset and the output is cleared to zero, and the thermometer code value output by the comparator array is: TH<2 M -1:1>=00…0000. At the same time, the upper plate of the capacitor array is connected to the bias voltage, and the lower plate is connected to the input differential signal. At this time, the charge on the capacitor array is expressed as: In the above formula, Q DACP represents the charge on the capacitor array connected to the positive input of the fine quantization comparator, Q DACN represents the charge on the capacitor array connected to the negative input terminal of the fine quantization comparator; The sampling phase ends, the sampling signal is inactive at a low level, and each comparator in the comparator array of the coarse quantization unit outputs a code value of 0 or 1 according to the magnitude of the input differential voltage and the reference voltage, and latches the code value and transmits it to the thermometer code capacitor control logic; When the sampling signal is at a low level and is invalid, the switch of the upper plate of the capacitor array connected to the bias voltage is disconnected, the lower plates of all sub-capacitors of the capacitor array connected to the positive input terminal of the fine quantization comparator, excluding the thermometer code capacitor and the target sub-capacitor, are switched from being connected to the input differential signal to being connected to the reference voltage, and the lower plates of all sub-capacitors of the capacitor array connected to the negative input terminal of the fine quantization comparator, excluding the thermometer code capacitor and the target sub-capacitor, are switched from being connected to the input differential signal to being grounded. At this time, the charges at both ends of the capacitor array connected to the positive input terminal and the negative input terminal of the fine quantization comparator are respectively: In the above formula, V DACP and V DACN Respectively represent the voltage values ​​of the positive and negative input terminals of the fine quantization comparator, K represents that in the coarse quantization output, there are K 1 code values ​​output, and 2 0 code values ​​output. M -1-K, then according to the principle of charge conservation, the voltages at the positive and negative input terminals of the fine-grained comparator can be obtained as: Then the following formula is obtained for the fine quantization comparator: According to the above formula, the thermometer code value is subtracted from the capacitor array to obtain the residual voltage, where is a coarsely quantized voltage value, and the voltage value corresponding to the input differential signal ranges from a negative reference voltage to a positive reference voltage; After the subtraction operation is completed to obtain the residual voltage, the remaining voltage on the capacitor array is the residual voltage, and the quantization stage is entered. In the quantization stage, first, the binary capacitor is 2 M -1C sub-capacitance begins to change, V DACP Sub-capacitor 2 M The lower plate of -1C is switched from the reference voltage to ground, and V DACN Sub-capacitor 2 M When the lower plate of -1C switches from ground to the reference voltage, a voltage change occurs on the upper plate of the sub-capacitor, which is expressed as follows: If the voltage V DACP >V DACN , then the fine quantization comparator outputs a code value of 1, V DACP Sub-capacitor 2 M -1C's lower plate is kept grounded, V DACN Sub-capacitor 2 M The lower plate of -1C is kept connected to the reference voltage. At this time, the total voltage change of the upper and lower plates of the capacitor array is: ; If the voltage V DACP <V DACN , then the fine quantization comparator outputs a code value of 0, V DACP Sub-capacitor 2 M -1C's lower plate is switched back to the reference voltage, V DACN Sub-capacitor 2 M -1C's lower plate is switched back to ground, and the voltages on the upper and lower plates of the capacitor array remain unchanged; Size is 2 M After the -1C sub-capacitance change is completed, the next value is 2 M -2C sub-capacitor begins to change, the fine quantization comparator outputs a code value of 0 or 1, and determines the sub-capacitor 2 M The lower plate of -2C is connected to the reference voltage or grounded, and the above process is repeated until the last sub-capacitor of 1C is reached, completing the first successive approximation operation.

7. The analog-to-digital conversion circuit according to claim 6, wherein: After completing the first successive approximation operation, the switch array in combination with the resistor string unit continues to perform a second successive approximation operation on the target sub-capacitor. When the second successive approximation operation is an L-bit successive approximation operation, first, the switches in the switch array are closed or turned on, so that the voltage received by the lower plate of the first target sub-capacitor connected to the positive input terminal of the fine quantization comparator is switched from the reference voltage to 1 / 2 of the reference voltage, and the voltage received by the lower plate of the second target sub-capacitor connected to the negative input terminal of the fine quantization comparator is switched from ground to 1 / 2 of the reference voltage. If V DACP >V DACN , the voltage received by the lower plate of the first target sub-capacitor and the voltage received by the lower plate of the second target sub-capacitor are both maintained at 1 / 2 of the reference voltage, otherwise the received voltage is restored to the reference voltage and grounded, and then an L-1-bit successive approximation operation is performed until the second successive approximation operation is completed.

8. The analog-to-digital conversion circuit according to claim 6, wherein: The size of each sub-capacitor in the thermometer code capacitor is 2 M C. When the coarse quantization thermometer code is judged to be wrong, the fine quantization unit exceeds the range, and the error voltage caused on the capacitor array after being transmitted to the fine quantization unit is , then the remaining voltage on the plates of the capacitor array is: residual voltage + error voltage; The sub-capacitor size of the redundant capacitor is 2 M-1 C, the highest bit capacitance in the binary capacitor is 2 M- 1 C, setting the sum of the sub-capacitor weights of the redundant capacitor and the highest sub-capacitor weight to be equivalent to the weight of a single sub-capacitor in the thermometer code capacitor, so that when the thermometer code is erroneous, the code values ​​corresponding to the sub-capacitors of the redundant capacitor and the highest capacitor are both 1 or 0, and the weights of the superposition of the two compensate for the error voltage, and the residual voltage is further quantized by the binary capacitor; When the coarsely quantized thermometer code is correctly determined, the fine quantization unit does not exceed the range, the sub-capacitor of the redundant bit capacitor and the highest bit sub-capacitor do not participate in quantization at the same time, the code values ​​corresponding to the two are not 1 or 0 at the same time, and there is no error voltage.

9. The analog-to-digital conversion circuit according to claim 7, wherein: The analog-to-digital conversion circuit further includes: an asynchronous clock unit; The asynchronous clock unit is configured to generate a quantized clock signal; The quantization clock signal is configured to control the switching from the end of the sampling phase to the first successive approximation operation and the second successive approximation operation, and to control the resetting and comparison of the fine quantization comparator; The fine quantization comparator is reset during the low-level period of the quantization clock signal, generates the binary code at the rising edge of the fine quantization comparator, and latches the binary code when the quantization clock signal is at a high level. The binary code is transmitted to the digital error correction unit and also to the logic unit to control the switches of the capacitor array, thereby completing the first successive approximation operation and the second successive approximation operation.

10. An electronic device, characterized in that: The electronic device comprises: the analog-to-digital conversion circuit according to any one of claims 1-9.

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