Semiconductor device and method for manufacturing the same

Abstract

The invention relates to a semiconductor device and a method for manufacturing the same. A semiconductor device includes: a substrate including a core region and a peripheral region; a first conductive pattern including a stacked structure of a gate dielectric layer and a gate electrode over the substrate in the core region, and including a high-k layer interposed at an interface between the gate dielectric layer and the gate electrode; and a second conductive pattern including a stacked structure of a gate dielectric layer and a gate electrode over the substrate in the peripheral region, and including a high-k layer covering an interface between the gate dielectric layer and the gate electrode and both sidewalls of the gate electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0074749, filed on June 12, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a gate structure optimized for a peripheral region and a core region, and a method for manufacturing the semiconductor device. Background Art

[0004] As semiconductor devices are integrated, there are advantages to increasing production efficiency and reducing associated costs, which shrinks the constituent elements and increases the complexity of processing and manufacturing. In particular, as the size of transistors decreases, the thickness of the gate oxide should be reduced to maintain performance while having a reduced gate length. To reduce gate leakage, high-k gate dielectric layers are being used, which allow for greater physical thickness of the dielectric layer while maintaining the same effective capacitance provided by a typical gate oxide for nodes of larger technology sizes.

[0005] Furthermore, a method of replacing a polysilicon gate electrode with a metal gate electrode is being applied to improve the performance of a device. Summary of the invention

[0006] Embodiments of the present invention are directed to a semiconductor device including a metal gate electrode optimized for a core region and a peripheral region.

[0007] According to one embodiment of the present invention, a semiconductor device includes: a substrate including a core region and a peripheral region; a first conductive pattern including a stacked structure of a gate dielectric layer and a gate electrode above the substrate in the core region, and including a high-k layer inserted at an interface between the gate dielectric layer and the gate electrode; and a second conductive pattern including a stacked structure of a gate dielectric layer and a gate electrode above the substrate in the peripheral region, and including a high-k layer covering the interface between the gate dielectric layer and the gate electrode and two side walls of the gate electrode.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a substrate, which includes a core region and a peripheral region, each region including an NMOS region and a PMOS region; a first gate structure, which is formed above the substrate of the NMOS region of the core region and the peripheral region, and includes a stacked structure of a gate dielectric layer, a high-k layer and a gate electrode; and a second gate structure, which is formed above the substrate of the PMOS region of the core region and the peripheral region, and includes a stacked structure of a gate dielectric layer, a dipole layer, a high-k layer and a gate electrode.

[0009] According to another embodiment of the present invention, a semiconductor device includes: a substrate, which includes a cell region, a core region and a peripheral region, wherein each of the core region and the peripheral region includes an NMOS region and a PMOS region; a bit line structure, which is formed above the substrate of the cell region; a first gate structure, which is formed above the substrate of the NMOS region of the core region and the peripheral region and includes a stacked structure of a gate dielectric layer, a high-k layer and a gate electrode; and a second gate structure, which is formed above the substrate of the PMOS region of the core region and the peripheral region and includes a stacked structure of a gate dielectric layer, a dipole layer, a high-k layer and a gate electrode.

[0010] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: providing a substrate including a cell region, a core region and a peripheral region; forming a bit line structure, in which a bit line contact, a bit line and a bit line hard mask are stacked above the substrate in the cell region; forming a first RMG structure, in which a gate dielectric layer, a strip-shaped high-k layer and a metal gate electrode are stacked above the substrate in the core region; and forming a second RMG structure, in which a gate dielectric layer, a U-shaped high-k layer and a metal gate electrode are stacked above the substrate in the peripheral region, and the bottom surface and two side walls of the metal gate electrode are covered by the U-shaped high-k layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1A to 1C is a cross-sectional view illustrating a gate structure of a core region according to an embodiment of the present invention.

[0012] FIG. 2A to FIG. 2C is a cross-sectional view illustrating a gate structure of a peripheral region according to another embodiment of the present invention.

[0013] Figure 3 is a cross-sectional view illustrating a gate structure of each region according to still another embodiment of the present invention.

[0014] Figure 4 is a cross-sectional view illustrating a semiconductor device according to a further embodiment of the present invention.

[0015] FIG. 5A to FIG. 5N is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to still another embodiment of the present invention. DETAILED DESCRIPTION

[0016] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be complete and will convey the scope of the present invention to those skilled in the art. Throughout the present disclosure, throughout the various figures and embodiments of the present invention, similar reference numerals refer to similar parts.

[0017] The drawings are not necessarily to scale, and in some instances, the proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, this refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate. In the present disclosure, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0018] Semiconductor memory devices, particularly dynamic random access memory (DRAM) devices, typically include three regions. The first region may be a cell array in which memory cells are arranged in a matrix form, and the second region may be a peripheral region, which is a non-repetitive circuit that stores and transmits data and drives the cell array. Hereinafter, the peripheral circuit region will be referred to as the peripheral region. The third region may be a core region, which is a repetitive circuit including a sense amplifier, a decoder, etc.

[0019] Each of the peripheral region and the core region may include an NMOS region and a PMOS region. A high voltage NMOS transistor and a low voltage NMOS transistor may be formed in the NMOS region of the peripheral region, and a high voltage PMOS transistor and a low voltage PMOS transistor may be formed in the PMOS region of the peripheral region. A high voltage NMOS transistor and a low voltage NMOS transistor may be formed in the NMOS region of the core region, and a high voltage PMOS transistor and a low voltage PMOS transistor may be formed in the PMOS region of the core region. The high voltage transistor may have a line width greater than the line width of the low voltage transistor.

[0020] The gate structure described in this embodiment of the present invention may be a replacement metal gate (RMG) structure. The RMG structure refers to a structure obtained by forming a dummy gate pattern and gate spacers on both sidewalls of the dummy gate pattern and replacing the dummy gate pattern with a metal gate.

[0021] In the gate structure described in this embodiment of the present invention, the order of forming the high-k layer and the dipole layer may be different depending on the region where each gate structure is formed. For the convenience of describing this embodiment of the present invention, the high-k layer and the dipole layer will be referred to as HK first, HK last, dipole first, and dipole last, according to the order of formation. For example, an RMG structure in which a high-k layer is formed during a dummy gate formation process and is retained and not removed during an RMG structure formation process may be referred to as a HK first gate structure. Moreover, an RMG structure in which a high-k layer is not formed during a dummy gate formation process but is formed during an RMG structure formation process may be referred to as a HK last gate structure.

[0022] Figures 1A to 1C is a cross-sectional view illustrating a gate structure of a core region according to an embodiment of the present invention. Figures 1A to 1C is a cross-sectional view illustrating a stacked structure of a gate structure, and for ease of description, an interlayer dielectric layer and a gate spacer may be omitted.

[0023] refer to Figures 1A to 1C The gate structure of the core region may be an RMG structure. The gate structure of the core region may generally include a gate dielectric layer GDL, a high-k layer HKL, and a gate electrode GE, and may include or omit a dipole layer DPL as required.

[0024] The gate structure in the core region may be a HK-first RMG structure including a high-k layer formed during the dummy gate patterning process. In other words, the high-k layer may be inserted only at the interface between the gate dielectric layer and the gate electrode and have a stripe shape to maximize the control of the work function in the local region.

[0025] The dummy gate pattern formation process may be formed during Figures 1A to 1C Each gate dielectric layer GDL shown in FIG. Figures 1A to 1C Each gate electrode GE illustrated in can be formed during the RMG structure formation process. Figures 1A to 1C The gate dielectric layer GDL, the high-k layer HKL, and the gate electrode GE illustrated in FIG. 5 may include the same material.

[0026] Figures 1A to 1C The gate dielectric layer GDL illustrated in FIG. 4 may include, for example, silicon oxide.

[0027] The high-k layer HKL may include a high-k material having a dielectric constant greater than that of silicon oxide. For example, the high-k layer HKL may include one or more of the following: boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, and combinations thereof.

[0028] The gate electrode GE may include at least one or more of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide and conductive metal oxynitride. The gate electrode GE may include at least one or more of the following: for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN) , tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and combinations thereof, but the concept and scope of the present invention are not limited thereto. The conductive metal oxides and conductive metal oxynitrides may be oxidized forms of the above materials, but the concept and scope of the present invention are not limited thereto.

[0029] Figure 1A A HK first gate structure not including a dipole layer is shown. The HK first gate structure may include: a stacked structure of a gate dielectric layer GDL and a high-k layer HKL formed during a dummy gate formation process, and a gate electrode GE formed during an RMG structure formation process. The gate dielectric layer GDL and the high-k layer HKL may be sequentially stacked at an interface between a substrate Sub and a gate electrode GE. Since the gate dielectric layer GDL and the high-k layer HKL are formed by patterning, the two layers may be in a strip shape.

[0030] Figure 1B A dipole first HK first gate structure is shown. Figure 1B The gate structure may include: a) a stacked structure of a gate dielectric layer GDL, a dipole layer DPL, and a high-k layer HKL formed during a dummy gate formation process, and b) a gate electrode GE formed during an RMG structure formation process. The gate dielectric layer GDL, the dipole layer DPL, and the high-k layer HKL may be sequentially stacked at an interface between a substrate Sub and the gate electrode GE. The gate dielectric layer GDL, the dipole layer DPL, and the high-k layer HKL may have a stripe shape.

[0031] Figure 1C A dipole-last HK-first gate structure is shown. Figure 1CThe gate structure may include: a) a stacked structure of a gate dielectric layer GDL and a high-k layer HKL formed during a dummy gate formation process, and b) a dipole layer DPL and a gate electrode GE formed during an RMG structure formation process. The gate dielectric layer GDL and the high-k layer HKL may be sequentially stacked at an interface between a substrate Sub and the dipole layer DPL. The gate dielectric layer GDL and the high-k layer HKL may have a strip shape. The dipole layer DPL may include a U-shaped pad. The dipole layer DPL may cover the bottom surface and the side surface of the gate electrode GE. The top surface of the dipole layer DPL may be at the same level as the top surface of the gate electrode GE.

[0032] FIG. 2A to FIG. 2C is a cross-sectional view illustrating a gate structure of a peripheral region according to another embodiment of the present invention. FIG. 2A to FIG. 2C is a cross-sectional view illustrating a stacked structure of a gate structure, and for ease of description, an interlayer dielectric layer and a gate spacer may be omitted.

[0033] refer to FIG. 2A to FIG. 2C The gate structure in the peripheral region may be an RMG structure. The gate structure in the peripheral region may generally include a gate dielectric layer GDL, a high-k layer HKL, and a gate electrode GE, and may include or omit a dipole layer DPL if necessary.

[0034] The gate structure of the peripheral region may be a HK-last RMG structure obtained by removing the high-k layer formed during the dummy gate pattern formation process and then newly applying a U-shaped high-k layer during the RMG formation process. In other words, when the U-shaped high-k layer covers the bottom surface and sidewalls of the gate electrode, the performance of the device can be maximized.

[0035] The gate structure of the peripheral region can be a HK first RMG structure, which applies a U-shaped pad type high-k layer to cover the bottom surface and sidewalls of the metal gate electrode. In other words, the high-k layer can be set only at the interface between the gate dielectric layer and the gate electrode, and has a strip shape to maximize the control of the work function in the local area.

[0036] FIG. 2A to FIG. 2C Each gate dielectric layer GDL illustrated in FIG. 1 may be formed during a dummy gate pattern forming process. FIG. 2A to FIG. 2C Each gate electrode GE illustrated in can be formed during the RMG structure formation process. FIG. 2A to FIG. 2C Each of the gate dielectric layer GDL, the high-k layer HKL, and the gate electrode GE illustrated in FIG. 4 may include the same material.

[0037] FIG. 2A to FIG. 2C The gate dielectric layer GDL illustrated in FIG. 4 may include, for example, silicon oxide.

[0038] The high-k layer HKL may include a high-k material having a dielectric constant greater than that of silicon oxide. For example, the high-k layer HKL may include at least one or more of the following: boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, and combinations thereof.

[0039] The gate electrode GE may include at least one or more of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide and conductive metal oxynitride, and combinations thereof. The gate electrode GE may include at least one or more of the following: for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN) , tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and combinations thereof, but the concept and scope of the present invention are not limited thereto. The conductive metal oxides and conductive metal oxynitrides may be oxidized forms of the above materials, but the concept and scope of the present invention are not limited thereto.

[0040] Figure 2A A high-k last (HK last) gate structure not including a dipole may be shown. The HK last gate structure may include: a) a stacked structure of a gate dielectric layer GDL formed during a dummy gate formation process, and b) a high-k layer HKL and a gate electrode GE formed during an RMG structure formation process. The gate dielectric layer GDL may have a strip shape. The high-k layer HKL may include a U-shaped pad. The high-k layer HKL may cover the bottom surface and the side surface of the gate electrode GE. The top surface of the high-k layer HKL may be at the same level as the top surface of the gate electrode GE.

[0041] Figure 2B A dipole first HK last gate structure may be shown. Figure 2BThe gate structure may include: a) a stacked structure of a gate dielectric layer GDL and a dipole layer DPL formed during a dummy gate formation process, and b) a high-k layer HKL and a gate electrode GE formed during an RMG structure formation process. The gate dielectric layer GDL and the dipole layer DPL may be sequentially stacked at an interface between a substrate Sub and the high-k layer HKL. The gate dielectric layer GDL and the dipole layer DPL may have a strip shape. The high-k layer HKL may include a U-shaped pad. The high-k layer HKL may cover the bottom surface and the side surface of the gate electrode GE. The top surface of the high-k layer HKL may be at the same level as the top surface of the gate electrode GE.

[0042] Figure 2C A dipole last HK last gate structure may be shown. Figure 2C The gate structure may include: a) a stacked structure of a gate dielectric layer GDL formed during a dummy gate formation process, and b) a high-k layer HKL, a dipole layer DPL, and a gate electrode GE formed during an RMG structure formation process. The gate dielectric layer GDL may have a strip shape. The high-k layer HKL and the dipole layer DPL may include a U-shaped pad. The high-k layer HKL may cover an outer wall of the dipole layer DPL. The dipole layer DPL may cover a bottom surface and a side surface of the gate electrode GE. The top surface of the high-k layer HKL and the top surface of the dipole layer DPL may be at the same level as the top surface of the gate electrode GE.

[0043] Described above Figures 1A to 1C shows the gate structure of the core region, and FIG. 2A to FIG. 2C A gate structure of a peripheral region is shown, but the concept and scope of the present invention are not limited thereto. Figures 1A to 1C and FIG. 2A to FIG. 2C The gate structure illustrated in the figure can be selectively applied to the core region or the peripheral region as needed. In other words, the structure can be different according to NMOS or PMOS and the high voltage or low voltage of each region. Although the above embodiments of the present invention are described Figures 1A to 1C and FIG. 2A to FIG. 2C The gate structures are illustrated with the same line width, but the line width of the gate structure is not limited thereto, and the line width can be adjusted according to the type and voltage of each region.

[0044] For example, in which the dipole layer is omitted, which deteriorates the reliability Figure 1A or Figure 2A The gate structure may be applied to a high voltage transistor in an NMOS region.

[0045] According to another embodiment of the present invention, Figure 1C or Figure 2B A dipole first gate structure may be applied to the PMOS region in order to maximize the reduction of the threshold voltage Vt.

[0046] According to another embodiment of the present invention, the gate structure of HK first structure can be applied to the core region with various gate shapes and sizes. According to another embodiment of the present invention, the gate structure as HK last can be applied to the NMOS region of the peripheral region to facilitate Tinv scaling (inversion layer thickness scaling). According to another embodiment of the present invention, the dipole first gate structure can be applied to the PMOS region of the peripheral region to improve performance due to the reduction of the threshold voltage Vt.

[0047] The concept and scope of the present invention are not limited thereto, and an appropriate gate structure may be applied according to the gate length, purpose, and type and voltage of each region.

[0048] Figure 3 is a cross-sectional view illustrating a gate structure of each region according to another embodiment of the present invention.

[0049] refer to Figure 3 According to this embodiment of the present invention, different gate structures can be applied to each type and voltage of the core region CORE and the peripheral region PERI. In particular, the HK first gate structure can be applied to the core region CORE where the work function of the local area needs to be adjusted. Moreover, the HK last gate structure can be applied to the peripheral region PERI where the performance needs to be maximized.

[0050] According to this embodiment of the present invention, an isolation layer DIL defining an active area can be formed, while the substrate Sub is divided into a core area CORE and a peripheral area PERI, each of the core area CORE and the peripheral area PERI is divided into an NMOS area and a PMOS area, and each of the NMOS area and the PMOS area is divided into a high voltage transistor area and a low voltage transistor area.

[0051] First, the core region CORE may be divided into an NMOS region and a PMOS region. Furthermore, the NMOS region of the core region CORE may be divided into a low voltage transistor region and a high voltage transistor region.

[0052] A gate structure having a smaller line width than that of the high voltage transistor region may be applied to the low voltage transistor region of the NMOS region of the core region CORE. The gate structure CNS formed in the low voltage transistor region of the NMOS region of the core region CORE may be Figure 1A The HK gate structure not including the dipole layer shown in the figure is first used to improve the reliability of the device. The gate structure CNT formed in the high voltage transistor region of the NMOS region of the core region CORE may be Figure 1C The dipole-last HK-first gate structure is shown to lower the threshold voltage.

[0053] According to another embodiment of the present invention, Figure 1C The dipole last HK first gate structure shown in FIG. 1 can be applied to a low voltage transistor region of an NMOS region of a core region CORE to reduce a threshold voltage. According to yet another embodiment of the present invention, Figure 1A The HK-first gate structure not including a dipole layer shown in FIG. 4 may be applied to a high voltage transistor region of an NMOS region of a core region CORE to improve reliability of the device.

[0054] The PMOS region of the core region CORE may be divided into a low voltage transistor region and a high voltage transistor region.

[0055] A gate structure having a line width smaller than that of the high voltage transistor region may be applied to the low voltage transistor region of the PMOS region of the core region CORE. Figure 1B The dipole first HK first gate structure shown in FIG. 4 may be applied to the gate structure CPS formed in the low voltage transistor region of the PMOS region of the core region CORE to lower the threshold voltage Vt. Figure 1B The dipole first HK first gate structure shown in the figure can be applied to the gate structure CPT formed in the high voltage transistor region of the PMOS region of the core region CORE to reduce the threshold voltage Vt. In other words, regardless of the gate line width, the same gate structure can be applied to the PMOS region of the core region CORE, but the concept and scope of the present invention are not limited thereto.

[0056] The peripheral region PERI may be divided into an NMOS region and a PMOS region. Also, the NMOS region of the peripheral region PERI may be divided into a low voltage transistor region and a high voltage transistor region.

[0057] A gate structure having a line width smaller than that of the high voltage transistor region may be applied to the low voltage transistor region of the NMOS region of the peripheral region PERI. Figure 2C The dipole last HK last gate structure shown in FIG. 4 may be applied to the gate structure PNS formed in the low voltage transistor region of the NMOS region of the peripheral region PERI to lower the threshold voltage. Figure 2A The HK-last gate structure not including a dipole layer shown in FIG. 4 may be applied to a gate structure PNT formed in a high voltage transistor region of an NMOS region of a peripheral region PERI to improve reliability of a device.

[0058] The PMOS region of the peripheral region PERI may be divided into a low voltage transistor region and a high voltage transistor region.

[0059] A gate structure having a line width smaller than that of the high voltage transistor region may be applied to the low voltage transistor region of the PMOS region of the peripheral region PERI. Figure 2B The dipole first HK last gate structure shown in FIG. 4 may be applied to the gate structure PPS formed in the low voltage transistor region of the PMOS region of the peripheral region PERI to lower the threshold voltage. Figure 2B The dipole first HK last gate structure shown in the figure can be applied to the gate structure PPT formed in the high voltage transistor region of the PMOS region of the peripheral region PERI to reduce the threshold voltage. In other words, regardless of the gate line width, the same gate structure can be applied to the PMOS region of the peripheral region PERI, but the concept and scope of the present invention are not limited thereto.

[0060] As described above, the present embodiment of the present invention may apply a gate structure optimized according to the type, gate line width, and voltage of each region, but the concept and scope of the present invention are not limited thereto. Figures 1A to 1C and FIG. 2A to FIG. 2C The gate structure shown in FIG. 1 can be selectively adopted and applied to each region as needed.

[0061] Figure 4 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

[0062] refer to Figure 4 , the substrate 101 may include a cell region CELL, a core region CORE, and a peripheral region PERI.

[0063] The substrate 101 may be a material suitable for semiconductor processing. The substrate 101 may include a semiconductor substrate. The substrate 101 may be formed of a silicon-containing material. The substrate 101 may include, for example, one or more of the following: silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate 101 may also include another semiconductor material, such as, for example, germanium. The substrate 101 may include a III / V semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0064] The substrate 101 may define an active region 103, while being divided into a cell region CELL, a core region CORE, and a peripheral region PERI by an isolation layer 102. The isolation layer 102 may be a shallow trench isolation region (STI) formed by a trench etching process. The isolation layer 102 may be formed by filling a shallow trench (e.g., an isolation trench 102T) with a dielectric material. The isolation layer 102 may include silicon oxide, silicon nitride, or a combination thereof.

[0065] The cell region CELL may include a buried gate structure BG and a bit line structure BL.

[0066] The buried gate structure BG may be formed in the substrate 101. The buried gate structure BG may be buried in the gate trench 105 using the hard mask layer 104 formed over the substrate 101 as an etch barrier. The bottom surface of the gate trench 105 may be disposed at a higher level than the bottom surface of the isolation layer 102.

[0067] The buried gate structure BG may include a buried gate dielectric layer 106 covering the bottom surface and inner sidewalls of the gate trench 105 , and a buried gate electrode 107 and a capping layer 108 sequentially stacked to fill the gate trench 105 above the buried gate dielectric layer 106 .

[0068] The buried gate dielectric layer 106 may include one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof.

[0069] The buried gate electrode 107 may have a single-layer structure or a multi-layer structure. The buried gate electrode 107 may include a semiconductor material or a metal-based material. The buried gate electrode 107 may include a metal material or a metal nitride. For example, the buried gate electrode 107 may include titanium nitride (TiN). According to another embodiment of the present invention, the buried gate electrode 107 may include one or more selected from the group consisting of titanium nitride (TiN), molybdenum (Mo), tantalum nitride (TaN), lanthanum (La), hafnium (Hf), tantalum (Ta), aluminum (Al), aluminum oxide (Al2O3), titanium silicon nitride (TiSiN) and tantalum silicon nitride (TaSiN) and combinations thereof, but the concept and scope of the present invention are not limited thereto.

[0070] The capping layer 108 may fill the upper portion of the gate trench 105 above the buried gate electrode 107. The capping layer 108 may extend over the hard mask layer 104 of the cell region CELL. The capping layer 108 may include a dielectric material. For example, the capping layer 108 may include one or more of the following: silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0071] The first source / drain region 109 and the second source / drain region 110 may be formed in the active region 103 of the cell region CELL. The first source / drain region 109 and the second source / drain region 110 may be regions doped with conductive dopants. For example, the conductive dopant may include one or more of phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The first source / drain region 109 and the second source / drain region 110 may be doped with dopants of the same conductivity type. The first source / drain region 109 and the second source / drain region 110 may be disposed in the active region 103 on both sides of the gate trench 105. The bottom surface of the first source / drain region 109 and the bottom surface of the second source / drain region 110 may be disposed at a predetermined depth from the top surface of the active region 103. The bottom surface of the first source / drain region 109 and the bottom surface of the second source / drain region 110 may be at a higher level than the bottom surface of the gate trench 105.

[0072] The bit line structure BL may be coupled to the first source / drain region 109. The second source / drain region 110 may be coupled to the memory device through a storage node contact.

[0073] The bit line structure BL may include a stacked structure of a bit line contact 120, a bit line 121, and a bit line hard mask 122. The bottom surface of the bit line contact 120 may be disposed at a lower level than the top surface of the substrate 101. The bit line contact 120 may be formed of polysilicon or a metal material. The bit line 122 may include a metal material. The bit line hard mask 123 may include a dielectric material.

[0074] like Figure 3 As shown, each of the core region CORE and the peripheral region PERI can be divided into an NMOS region and a PMOS region. The NMOS region of the core region CORE can be divided into a low voltage transistor region and a high voltage transistor region. The PMOS region of the core region CORE can be divided into a low voltage transistor region and a high voltage transistor region. Each of the NMOS region and the PMOS region of the peripheral region PERI can also be divided into a low voltage transistor region and a high voltage transistor region.

[0075] The core region CORE and the peripheral region PERI may include a gate structure optimized according to the type of each region (e.g., NMOS region and PMOS region) or line width (e.g., high voltage and low voltage). The core region CORE and the peripheral region PERI may include an RMG structure. The gate structure of the core region CORE and the peripheral region PERI may independently include a stacked structure of a gate dielectric layer 130, a high-k layer 132, and a gate electrode 133. It may further include a dipole layer 131 when necessary, but the concept and scope of the present invention are not limited thereto. When necessary, Figures 1A to 1C and FIG. 2A to FIG. 2C One or more of the gate structures illustrated in FIG. 1 may be applied to the gate structures of the core region CORE and the peripheral region PERI. Gate spacers 134 may be formed on both sidewalls of each gate structure. Interlayer dielectric layers 135 may be buried between the gate structures.

[0076] FIG. 5A to FIG. 5N is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0077] refer to Figure 5A , the semiconductor device may provide a substrate 11 including a cell region CELL and a core region CORE / peripheral region PERI.

[0078] The cell region CELL may include a word line, a bit line, a capacitor, etc. The cell region CELL may be a memory cell region for storing data and may be driven by selecting a word line and a bit line. The core region CORE / peripheral region PERI may include a core region and a peripheral circuit region.

[0079] Although this embodiment of the present invention illustrates one gate structure formed in the core region / peripheral region for ease of description, the concept and scope of the present invention are not limited thereto and may be applied from the core region to the peripheral region as needed or in each region. Figures 1A to 1C and FIG. 2A to FIG. 2C According to this embodiment of the present invention, Figure 4 Each of the core region or the peripheral region illustrated in FIG. 1 may be formed separately, and a gate structure suitable for each region may be formed. Figure 3As shown, each of the core region and the peripheral region according to this embodiment of the present invention can be divided into an NMOS region and a PMOS region, and divided into a high voltage transistor region and a low voltage transistor region, and a gate structure suitable for each region can be formed. In particular, according to an embodiment of the present invention, the gate structure of the core region / peripheral region can be formed by different processes to have different structures as needed. For example, when forming the gate structure of the core region, the peripheral region can be covered by a mask pattern, and when forming the gate structure of the peripheral region, the core region can be covered by a mask pattern.

[0080] exist Figure 5A In the embodiment, the substrate 11 may include an isolation layer 12 and active regions 13 defined by the isolation layer 12. The active regions 13 may be spaced apart at regular intervals by the isolation layer 12. The isolation layer 12 may separate the cell region CELL and the core region CORE / peripheral region PERI from each other.

[0081] The substrate 11 may be a material suitable for semiconductor processing. The substrate 11 may include a semiconductor substrate. The substrate 11 may be formed of a silicon-containing material. The substrate 11 may include, for example, one or more of the following: silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate 11 may also include another semiconductor material, such as, for example, germanium. The substrate 11 may include a III / V semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The substrate 11 may include a silicon-on-insulator (SOI) substrate.

[0082] The isolation layer 12 may be formed by a shallow trench isolation (STI) process. The STI process may be performed as follows. The substrate 11 may be etched to form an isolation trench. The isolation trench may be filled with a dielectric material, and as a result, the isolation layer 12 may be formed. The isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes may be used to fill the isolation trench with a dielectric material. A planarization process such as chemical mechanical polishing (CMP) may be additionally used.

[0083] Subsequently, a buried gate structure BG may be formed in the substrate 11 of the cell region CELL. The buried gate structure BG may include a gate trench 15, a gate dielectric layer 16 covering the bottom surface and sidewalls of the gate trench 15, a buried gate electrode 17 partially filling the gate trench 15 over the gate dielectric layer 16, and a gate capping layer 18 formed over the buried gate electrode 17.

[0084] The buried gate structure BG may be formed as follows.

[0085] First, a gate trench 15 may be formed in the substrate 11 of the cell region CELL. The gate trench 15 may have a line shape intersecting the active region 13 and the isolation layer 12. The gate trench 15 may be formed by forming a mask pattern over the substrate 11 and performing an etching process using the mask pattern as an etching mask. In order to form the gate trench 15, a hard mask layer 14 may be used as an etching barrier. The hard mask layer 14 may have a shape patterned by a mask pattern. The hard mask layer 14 may cover the contour of the substrate of the core region CORE / peripheral region PERI. The hard mask layer 14 may include silicon oxide. The hard mask layer 14 may include tetraethyl orthosilicate (TEOS). The bottom surface of the gate trench 15 may be set at a higher level than the bottom surface of the isolation layer 12.

[0086] The active region 13 under the gate trench 15 may protrude by recessing a portion of the isolation layer 12 of the cell region CELL. Therefore, a fin region may be formed under the gate trench 15. The fin region may be a portion of the channel region.

[0087] Subsequently, a gate dielectric layer 16 may be formed on the bottom surface and sidewalls of the gate trench 15. Before forming the gate dielectric layer 16, etching damage on the surface of the gate trench 15 may be addressed. For example, after forming a sacrificial oxide by thermal oxidation treatment, the sacrificial oxide may be removed.

[0088] The gate dielectric layer 16 may be formed by a thermal oxidation process. For example, the gate dielectric layer 16 may be formed by oxidizing the bottom surface and sidewalls of the gate trench 15 .

[0089] According to another embodiment of the present invention, the gate dielectric layer 16 may be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate dielectric layer 16 may include one or more of a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-k material may include a hafnium oxide material. The hafnium-containing material may include one or more of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include one or more of lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0090] According to another embodiment of the present invention, the gate dielectric layer 16 may be formed by depositing a pad polysilicon layer and then radically oxidizing the pad polysilicon layer.

[0091] According to yet another embodiment of the present invention, the gate dielectric layer 16 may be formed by forming a pad silicon nitride layer and then radically oxidizing the pad silicon nitride layer.

[0092] Subsequently, a buried gate electrode 17 may be formed over the gate dielectric layer 16. The buried gate electrode 17 may be formed by forming a conductive layer to fill the gate trench 15 and then performing a recess process. The recess process may be performed as an etch back process, or may be performed by sequentially performing a chemical mechanical polishing (CMP) process and an etch back process. The buried gate electrode 17 may have a recessed shape that partially fills the gate trench 15. In other words, the top surface of the buried gate electrode 17 may be disposed at a lower level than the top surface of the active region 13. The buried gate electrode 17 may include a metal, a metal nitride, or a combination thereof. For example, the buried gate electrode 17 may be formed of one or more of titanium nitride (TiN), tungsten (W), or a titanium nitride / tungsten (TiN / W) stack. The titanium nitride / tungsten (TiN / W) stack may have a structure in which titanium nitride is conformally formed and then the gate trench 15 is partially filled with tungsten. As the buried gate electrode 17, only titanium nitride may be used, and this may be referred to as a "TiN only" structured buried gate electrode 17. As the buried gate electrode 17, a dual gate structure of a titanium nitride / tungsten (TiN / W) stack and a polysilicon layer may be used.

[0093] Subsequently, capping layers 18 and 18A may be formed over the outline of the substrate including the buried gate electrode 17. The capping layers 18 and 18A may include a dielectric material. The capping layers 18 and 18A may include silicon nitride. According to another embodiment of the present invention, the capping layers 18 and 18A may include silicon oxide. According to yet another embodiment of the present invention, the capping layers 18 and 18A may have a nitride-oxide-nitride (NON) structure.

[0094] The capping layers 18 and 18A may include: a gate capping layer 18 gap-filling the gate trench 15 above the buried gate electrode 17, and a protective capping layer 18A covering an upper portion of the hard mask layer 14. The buried gate structure BG may be formed by the gate dielectric layer 16, the buried gate electrode 17, and the gate capping layer 18. The buried gate structure BG may be referred to as a "word line WL".

[0095] A top surface of the protective capping layer 18A may be disposed at a higher level than a top surface of the hard mask layer 14. The protective capping layer 18A may cover both the hard mask layer 14 and the buried gate structure BG.

[0096] Subsequently, a bit line contact hole BH may be formed in the cell region CELL. The bit line contact hole BH may be disposed between adjacent buried gate structures BG. A contact mask for etching the protective cap layer 18A and the hard mask layer 14 may be applied to form the bit line contact hole BH. A portion of the substrate 11 may be exposed through the bit line contact hole BH. The bit line contact hole BH may have a diameter controlled to be a constant line width. The bit line contact hole BH may have a shape that exposes a portion of the active region 13. The bit line contact hole BH may have a diameter greater than the width of the minor axis of the active region 13. Therefore, in the etching process for forming the bit line contact hole BH, a portion of the insulating layer 12 and a portion of the active region 13 may be etched. In other words, the isolation layer 12 and the active region 13 below the bit line contact hole BH may be recessed to a certain depth. Therefore, the bottom portion of the bit line contact hole BH may extend into the substrate 11.

[0097] Subsequently, a preliminary bit line contact 21A may be formed to gap-fill the bit line contact hole BH. The preliminary bit line contact 21A may be formed by a series of processes as follows: a plug conductive layer is formed over the bit line contact hole BH and the protective cap layer 18A, and the plug conductive layer is etched to remain only in the bit line contact hole BH. The preliminary bit line contact 21A may include a material having an etching selectivity relative to the protective cap layer 18A. For example, the preliminary bit line contact 21A may include polysilicon. According to another embodiment of the present invention, the preliminary bit line contact 21A may include polysilicon doped with impurities.

[0098] refer to Figure 5B , the protective cap layer 18A of the core region CORE / peripheral region PERI can be etched (see Figure 5A ). Therefore, the protective capping layer 18B may remain only in the cell region CELL. In the core region CORE / peripheral region PERI, the substrate 11 may be exposed.

[0099] Subsequently, a preliminary gate dielectric layer 31A may be formed over the substrate 11 of the core region CORE / peripheral region PERI. The preliminary gate dielectric layer 31A may form a peripheral gate dielectric layer of a peripheral gate structure through a subsequent process. The preliminary gate dielectric layer 31A may include a dielectric material. For example, the preliminary gate dielectric layer 31A may include silicon oxide. The preliminary gate dielectric layer 31A may be formed by a deposition process or an oxidation process. According to this embodiment of the present invention, the preliminary gate dielectric layer 31A may be formed by an oxidation process. Therefore, the preliminary gate dielectric layer 31A may be selectively formed only over the upper portion of the active region 13 of the core region CORE / peripheral region PERI.

[0100] refer to Figure 5C, a first dummy gate conductive layer 32A may be formed over the entire structure of the preliminary gate dielectric layer 31A including the core region CORE / peripheral region PERI. The first dummy gate conductive layer 32A may include the same material as that of the preliminary bit line contact 21A. For example, the first dummy gate conductive layer 32A may include polysilicon.

[0101] refer to Figure 5D The cell opening mask 40 may be formed over the first dummy gate conductive layer 32A of the core region CORE / peripheral region PERI. The cell opening mask 40 may be a mask for opening the cell region CELL and may cover the core region CORE / peripheral region PERI. The cell opening mask 40 may include a photoresist.

[0102] Subsequently, the first dummy gate conductive layer 32A of the cell region CELL may be etched (see Figure 5C ). Therefore, in the cell region CELL, the protection capping layer 18B and the preliminary bit line contact 21A may be exposed, and the first dummy gate conductive layer 32A may remain only in the core region CORE / peripheral region PERI.

[0103] Subsequently, the cell opening mask 40 may be removed.

[0104] refer to Figure 5E , conductive layers 22A and 33A and a hard mask layer 34A may be sequentially formed over the protection capping layer 18B and the preliminary bit line contact 21A of the cell region CELL and the first dummy gate conductive layer 32B of the core region CORE / peripheral region PERI.

[0105] Conductive layers 22A and 33A may include metal-containing materials. Conductive layers 22A and 33A may include one or more of metal, metal nitride, metal silicide or a combination thereof. According to this embodiment of the present invention, conductive layers 22A and 33A may include tungsten (W). According to another embodiment of the present invention, conductive layers 22A and 33A may include a stack of titanium nitride and tungsten (TiN / W). In this article, titanium nitride may be used as a barrier. According to another embodiment of the present invention, conductive layers 22A and 33A may include a stack structure of Ti / WN / WSiN / W. Conductive layers 22A and 33A may be applied to form a bit line of a cell region CELL and a dummy gate of a core region CORE / peripheral region PERI in a subsequent process. Hereinafter, the conductive layer 22A of the cell region CELL will be referred to as a "bit line conductive layer 22A". The conductive layer 33A of the core region CORE / peripheral region PERI will be referred to as a "second dummy gate conductive layer 33A".

[0106] The hard mask layer 34A may include a material having an etching selectivity with respect to the bit line conductive layer 22A and the second dummy gate conductive layer 33A. The hard mask layer 34A may include a dielectric material. For example, the hard mask layer 34A may include silicon nitride.

[0107] refer to Fig. 5F , the hard mask layer 34A of the core region CORE / peripheral region PERI can be removed (see Figure 5E The hard mask layer 34A may be etched (see Figure 5E ), the purpose of which is to expose the second dummy gate conductive layer 33A of the core region CORE / peripheral region PERI. The hard mask layer 34A can be etched by a chemical mechanical polishing process (see Figure 5E ).

[0108] Therefore, the bit line hard mask layer 23B may remain only in the cell region CELL.

[0109] refer to Figure 5G , a first mask pattern 41 may be formed. The first mask pattern 41 may be patterned to cover the entire cell region CELL and simultaneously define a gate region of the core region CORE / peripheral region PERI. The first mask pattern 41 may include a photoresist.

[0110] refer to Figure 5H , a first mask pattern 41 (see Figure 5G ) as an etching barrier to sequentially etch the second dummy gate conductive layer 33A of the core region CORE / peripheral region PERI (see Figure 5G ), the first dummy gate conductive layer 32B (see Figure 5G ) and preliminary gate dielectric layer 31A (see Figure 5G Since the cell region CELL is completely formed by the first mask pattern 41 (see Figure 5G ) is covered, so the cell area CELL may not be etched.

[0111] Therefore, a dummy gate structure in which the peripheral gate dielectric layer 31 , the first dummy gate 32 , and the second dummy gate 33 are stacked may be formed over the substrate 11 in the core region CORE / peripheral region PERI.

[0112] Subsequently, a peripheral gate spacer 34 may be formed on both sidewalls of the dummy gate structure. The peripheral gate spacer 34 may include a dielectric material. For example, the peripheral gate spacer 34 may include silicon nitride, but the concept and scope of the present invention are not limited thereto.

[0113] Subsequently, peripheral junction regions 35 may be formed on both sides of the dummy gate structure in the substrate 11. The peripheral junction regions 35 may be formed by doping impurities onto the substrate 11, which is exposed by patterning of the dummy gate structure. The peripheral junction regions 35 may be referred to as "peripheral source / drain regions 35".

[0114] As described above, by performing the peripheral junction region 35 process requiring high temperature heat treatment before forming the RMG structure, the reliability of the RMG structure to be formed by the subsequent process can be ensured.

[0115] refer to Fig.5I , an interlayer dielectric layer 51 may be formed over the substrate 11 of the core region CORE / peripheral region PERI. The interlayer dielectric layer 51 may fill the gaps between the dummy gate structures. The interlayer dielectric layer 51 may include a dielectric material. For example, the interlayer dielectric layer 51 may include silicon oxide, but the concept and scope of the present invention are not limited thereto.

[0116] refer to Figure 5J , a peripheral opening mask 42 may be formed. The peripheral opening mask 42 may be formed over the bit line hard mask layer 23B of the cell region CELL. The peripheral opening mask 42 may be a mask for opening the core region CORE / peripheral region PERI and may cover the cell region CELL. The peripheral opening mask 42 may include a photoresist.

[0117] Subsequently, the first dummy gate 32 and the second dummy gate 33 may be removed (see Fig.5I ). Therefore, a dummy recess DR may be formed between the facing dummy gate spacers 34 .

[0118] Subsequently, peripheral opening mask 42 may be removed.

[0119] refer to Figure 5K , a preliminary high-k layer 36A may be formed to cover the inner sidewall and bottom surface of the dummy recess DR. For example, the preliminary high-k layer 36A may include hafnium oxide. The hafnium-containing material may include one or more of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to other embodiments of the present invention, the high-k material may include one or more of lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0120] Subsequently, a preliminary gate conductive layer 37A may be formed over the preliminary high-k layer 36A to gap-fill the dummy recess DR. The preliminary gate conductive layer 37A may include a metal material. For example, the preliminary gate conductive layer 37A may include tungsten (W), but the concept and scope of the present invention are not limited thereto.

[0121] refer to Figure 5L, an RMG structure can be formed in which the peripheral gate dielectric layer 31, the peripheral high-k layer 36 and the peripheral gate electrode 37 are stacked. For this purpose, the dummy recess DR (see Figure 5K ) of the remaining area except the preliminary high-k layer 36A (see Figure 5K ) and preliminary gate conductive layer 37A (see Figure 5K For example, the preliminary high-k layer 36A may be etched by a chemical mechanical polishing (CMP) process (see Figure 5K ) and preliminary gate conductive layer 37A (see Figure 5K ), but the concept and scope of the present invention are not limited thereto.

[0122] Subsequently, the thickness of the bit line hard mask layer 23C of the cell region CELL may be increased. To this end, once the preliminary high-k layer 36A and the preliminary gate conductive layer 37A have been etched through (see Figure 5K ), and the bit line hard mask layer 23B (see Figure 5K ) may be additionally deposited over the bit line hard mask layer 23B.

[0123] refer to Figure 5M , a second mask pattern 43 may be formed. The second mask pattern 43 may be patterned to cover both the core region CORE / peripheral region PERI and simultaneously define a bit line region of the cell region CELL. The second mask pattern 43 may include a photoresist.

[0124] refer to Figure 5N , by using the second mask pattern 43 (see Figure 5M ) as an etching barrier, the bit line hard mask layer 23C of the cell region CELL (see Figure 5M ), bit line conductive layer 22A (see Figure 5M ) and preliminary bit line contact 21A (see Figure 5M ) can be sequentially etched. Since the core region CORE / peripheral region PERI is completely formed by the second mask pattern 43 (see Figure 5M ) is covered, so the core area CORE / peripheral area PERI can be preserved without being damaged.

[0125] Therefore, a bit line structure BL in which the bit line contact 21 , the bit line 22 , and the bit line hard mask 23 are stacked may be formed in the cell region CELL.

[0126] Subsequently, impurity regions 19 and 20 may be formed on both sides of the buried gate structure BG in the substrate 11. The impurity regions 19 and 20 may be formed by a doping process such as implantation. The impurity regions 19 and 20 may be referred to as "cell source / drain regions". The impurity region 19 between adjacent buried gate structures BG may be a region to which a bit line contact plug is to be coupled. The impurity region 20 outside the buried gate structure BG may be a region to which a storage node contact plug is to be coupled. According to this embodiment of the present invention, the process of forming the impurity regions 19 and 20 may be performed after forming the bit line structure BL, but the present embodiment is not limited thereto. According to another embodiment of the present invention, the impurity regions 19 and 20 may be formed after forming the buried gate structure BG. According to another embodiment of the present invention, the impurity regions 19 and 20 may be formed after forming the gate trench 15.

[0127] According to one embodiment of the present invention, there is an effect of ensuring improved semiconductor reliability and improving performance by applying a gate structure optimized for a core region and a peripheral region.

[0128] While the present invention has been described with respect to specific embodiments, it will be apparent to one skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device comprising: a substrate comprising a core region and a peripheral region; a first conductive pattern including a first stacked structure including a first gate dielectric layer and a first gate electrode over the substrate in the core region, and the first conductive pattern including a first high-k layer interposed at an interface between the first gate dielectric layer and the first gate electrode; as well as A second conductive pattern includes a second stacked structure, the second stacked structure includes a second gate dielectric layer and a second gate electrode above the substrate in the peripheral region, and the second conductive pattern includes a second high-k layer inserted at an interface between the second gate dielectric layer and the second gate electrode and covering a side wall of the second gate electrode.

2. The semiconductor device according to claim 1, wherein the first conductive pattern further comprises A first dipole layer is interposed at an interface between the first high-k layer and the first gate electrode.

3. The semiconductor device according to claim 1, wherein the first conductive pattern further comprises A dipole layer is adapted to cover an interface between the first high-k layer and the first gate electrode and to cover a sidewall of the first gate electrode.

4. The semiconductor device according to claim 1, wherein the second conductive pattern further comprises A second dipole layer is interposed at an interface between the second high-k layer and the second gate dielectric layer.

5. The semiconductor device according to claim 1, wherein the second conductive pattern further comprises A second dipole layer is interposed between the second high-k layer and the second gate electrode to cover a bottom surface and the sidewall of the second gate electrode.

6. A semiconductor device comprising: A substrate including a core region and a peripheral region, each region including an NMOS region and a PMOS region; a first gate structure formed over the substrate of the NMOS region of the core region and comprising a first stacked structure including a first gate dielectric layer, a first high-k layer, and a first gate electrode; a second gate structure formed over the substrate of the NMOS region of the peripheral region and comprising a second stacked structure including a second gate dielectric layer, a second high-k layer, and a second gate electrode; a third gate structure formed over the substrate of the PMOS region of the core region and comprising a third stacked structure including a third gate dielectric layer, a first dipole layer, a third high-k layer, and a third gate electrode; as well as A fourth gate structure is formed over the substrate of the PMOS region in the peripheral region and includes a fourth stacked structure including a fourth gate dielectric layer, a second dipole layer, a fourth high-k layer, and a fourth gate electrode. 7 . The semiconductor device of claim 6 , wherein in the first gate structure, the first gate dielectric layer and the first high-k layer are in a stripe shape.

8. The semiconductor device according to claim 6, wherein in the second gate structure, The second gate dielectric layer is in a stripe shape, The second high-k layer is U-shaped, and A bottom surface and sidewalls of the second gate electrode are covered by the second high-k layer.

9. The semiconductor device according to claim 6, wherein the first gate structure further comprises: A third dipole layer is between the first high-k layer and the first gate electrode.

10. The semiconductor device according to claim 6, wherein the second gate structure further comprises: A fourth dipole layer is between the second high-k layer and the second gate electrode.

11. The semiconductor device according to claim 9, wherein in the first gate structure, The first gate dielectric layer and the first high-k layer are in a strip shape, The third dipole layer is U-shaped, and A bottom surface and sidewalls of the first gate electrode are covered by the third dipole layer.

12. The semiconductor device according to claim 10, wherein in the second gate structure, The second gate dielectric layer is in a stripe shape, The second high-k layer and the fourth dipole layer are U-shaped, The second high-k layer covers the outer side wall of the fourth dipole layer, and A bottom surface and side walls of the second gate electrode are covered by the fourth dipole layer.

13. The semiconductor device according to claim 6, wherein in the third gate structure, The third gate dielectric layer, the first dipole layer, and the third high-k layer are in a stripe shape.

14. The semiconductor device according to claim 6, wherein in the fourth gate structure, The fourth gate dielectric layer and the second dipole layer are in a stripe shape, The fourth high-k layer is U-shaped, and A bottom surface and side walls of the fourth gate electrode are covered by the fourth high-k layer.

15. The semiconductor device according to claim 6, wherein each of the core region and the peripheral region includes a low voltage transistor region and a high voltage transistor region, and The gate structure of the low voltage transistor region has a line width smaller than a line width of the gate structure of the high voltage transistor region. 16 . The semiconductor device according to claim 6 , wherein the first to fourth gate structures are replacement metal gate (RMG) structures. 17 . The semiconductor device of claim 6 , wherein each of the first to fourth gate structures further comprises a gate spacer on a sidewall thereof.

18. A semiconductor device comprising: a substrate comprising a cell region, a core region, and a peripheral region, wherein each of the core region and the peripheral region comprises an NMOS region and a PMOS region; a bit line structure formed over the substrate of the cell region; a first gate structure formed over the substrate of the NMOS region of the core region and comprising a first stacked structure of a first gate dielectric layer, a first high-k layer, and a first gate electrode; a second gate structure formed over the substrate of the NMOS region of the peripheral region and comprising a second stacked structure of a second gate dielectric layer, a second high-k layer, and a second gate electrode; a third gate structure formed over the substrate of the PMOS region of the core region and comprising a third stacked structure of a third gate dielectric layer, a first dipole layer, a third high-k layer, and a third gate electrode; as well as A fourth gate structure is formed over the substrate of the PMOS region in the peripheral region and includes a fourth stacked structure of a fourth gate dielectric layer, a second dipole layer, a fourth high-k layer, and a fourth gate electrode.

19. The semiconductor device according to claim 18, wherein in the first gate structure, The first gate dielectric layer and the first high-k layer are in a stripe shape.

20. The semiconductor device according to claim 18, wherein in the second gate structure, The second gate dielectric layer is in a stripe shape, The second high-k layer is U-shaped, and A bottom surface and sidewalls of the second gate electrode are covered by the second high-k layer.

21. The semiconductor device of claim 19, wherein the first gate structure further comprises: A third dipole layer is between the first high-k layer and the first gate electrode.

22. The semiconductor device of claim 20, wherein the second gate structure further comprises: A fourth dipole layer is between the second high-k layer and the second gate electrode.

23. The semiconductor device according to claim 21, wherein in the first gate structure, The first gate dielectric layer and the first high-k layer are in a strip shape, The third dipole layer is U-shaped, and A bottom surface and sidewalls of the first gate electrode are covered by the third dipole layer.

24. The semiconductor device according to claim 22, wherein in the second gate structure, The second gate dielectric layer is in a stripe shape, The second high-k layer and the fourth dipole layer are U-shaped, The second high-k layer covers the outer side wall of the fourth dipole layer, and A bottom surface and side walls of the second gate electrode are covered by the fourth dipole layer.

25. The semiconductor device according to claim 18, wherein in the third gate structure, The third gate dielectric layer, the first dipole layer, and the third high-k layer are in a stripe shape.

26. The semiconductor device according to claim 18, wherein in the fourth gate structure, The fourth gate dielectric layer and the second dipole layer are strip-shaped, and The fourth high-k layer is U-shaped, and A bottom surface and side walls of the fourth gate electrode are covered by the fourth high-k layer.

27. The semiconductor device according to claim 18, wherein each of the core region and the peripheral region includes a low voltage transistor region and a high voltage transistor region, and The gate structure of the low voltage transistor region has a line width smaller than a line width of the gate structure of the high voltage transistor region. 28 . The semiconductor device according to claim 18 , wherein the first to fourth gate structures are replacement metal gate (RMG) structures. 29 . The semiconductor device of claim 18 , wherein each of the first to fourth gate structures further comprises a gate spacer on a sidewall thereof.

30. The semiconductor device according to claim 18, further comprising: A buried gate structure is formed in the substrate in the cell region.

31. A method for manufacturing a semiconductor device, comprising: providing a substrate including a cell region, a core region, and a peripheral region; forming a bit line structure in which a bit line contact, a bit line, and a bit line hard mask are stacked over the substrate of the cell region; forming a first RMG structure in which a first gate dielectric layer, a stripe-shaped high-k layer, and a first metal gate electrode are stacked above the substrate in the core region; as well as forming a second RMG structure in which a second gate dielectric layer, a U-shaped high-k layer, and a second metal gate electrode are stacked over the substrate in the peripheral region, The bottom surface and sidewalls of the second metal gate electrode of the second RMG structure are covered by the U-shaped high-k layer.

32. The method of claim 31 , wherein the forming of the first RMG structure comprises: forming a first dummy gate structure in which the first gate dielectric layer, the strip-shaped high-k layer and the first dummy gate electrode are stacked; forming a first gate spacer on two sidewalls of the first dummy gate structure; forming an interlayer dielectric layer suitable for gap filling between adjacent first dummy gate structures; forming a dummy recess by removing the first dummy gate electrode of the first dummy gate structure; as well as The first metal gate electrode is formed to be suitable for gap-filling the dummy recess.

33. The method of claim 31 , wherein the forming of the second RMG structure comprises: forming a second dummy gate structure in which the second gate dielectric layer, the dummy strip-shaped high-k layer, and the dummy gate electrode are stacked; forming a gate spacer on a sidewall of the second dummy gate structure; forming an interlayer dielectric layer suitable for gap filling between adjacent second dummy gate structures; forming a dummy recess by removing the dummy gate electrode and the dummy strip-shaped high-k layer of the second dummy gate structure; forming the U-shaped high-k layer, wherein the U-shaped high-k layer is suitable for covering the bottom surface and the inner sidewall of the dummy recess; as well as The second metal gate electrode is formed over the U-shaped high-k layer to gap-fill the dummy recess.

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