Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate, the substrate having at least two selection gates, adjacent selection gates having an opening between the selection gates, the selection gates being arranged along a first direction, the first direction being parallel to a surface of the substrate; forming a floating gate layer on a surface of the opening and on a top surface of the selection gates; forming a first sacrificial layer on a surface of the floating gate layer in the opening and on the top of the selection gates; and forming a second sacrificial layer on the first sacrificial layer. The first and second sacrificial layers are used as the sacrificial layer for forming the floating gate. Compared with the prior art in which only the first sacrificial layer is used as the sacrificial layer for forming the floating gate, the thickness of the first sacrificial layer is reduced, the second sacrificial layer with good step coverage and gap filling capability is formed on the first sacrificial layer, the possibility of voids is reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Floating-gate flash memory is the most widely used flash memory technology in practice. It is a type of non-volatile memory whose basic unit is a MOS transistor with a floating gate. However, with the rapid shrinking of flash memory cell size, scaling down floating-gate flash memory proportionally faces significant challenges. In floating-gate flash memory, during the process of filling deep trenches with amorphous carbon, voids exist that are not sealed. This results in a thinner photoresist layer on the surface of the voids. During subsequent photo rework, some of the amorphous carbon is removed, leading to wafer scrap.

[0003] However, currently, increasing the thickness of amorphous carbon to seal the voids at the top is used to solve the problem of voids in deep trenches. However, increasing the thickness of amorphous carbon can lead to over-etching of the floating gate, which in turn can cause active area damage (AA damage) and affect the performance of semiconductor devices. Summary of the Invention

[0004] The technical problem solved by this invention is how to improve the performance of semiconductor devices.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate having at least two selection gates adjacent to each other with an opening between them, the selection gates being arranged along a first direction parallel to the substrate surface; forming a floating gate layer on the surface of the opening and the top surface of the selection gates; forming a first sacrificial layer within the opening and on the surface of the floating gate layer at the top of the selection gates; and forming a second sacrificial layer on the first sacrificial layer, wherein the thickness of the first sacrificial layer ranges from 1000 angstroms to 2000 angstroms, and the thickness of the second sacrificial layer ranges from 800 angstroms to 1000 angstroms.

[0006] Optionally, the process for forming the second sacrificial layer is a chemical vapor deposition process, wherein the parameters of the chemical vapor deposition process are: a deposition rate of 4,000 angstroms per minute to 5,000 angstroms per minute and a deposition time of 10 to 15 seconds.

[0007] Optionally, after forming the second sacrificial layer, the method further includes: forming a photoresist layer with a floating gate pattern on the second sacrificial layer; and sequentially etching the photoresist layer, the second sacrificial layer, the first sacrificial layer, and a portion of the floating gate layer using an etching process with an etching selectivity to form a plurality of floating gates, wherein the floating gates span the selectivity gates and are arranged along a second direction, the second direction being perpendicular to the first direction.

[0008] Optionally, before forming the photoresist layer, the method further includes: forming an anti-reflection layer on the second sacrificial layer; and after forming the selection gate, the method further includes: forming a third sacrificial layer on the surface of the selection gate and the surface of the substrate.

[0009] Optionally, the first sacrificial layer is made of amorphous carbon, the second sacrificial layer is made of silicon dioxide, the photoresist layer has a thickness ranging from 2000 angstroms to 3000 angstroms, the third sacrificial layer has a thickness ranging from 300 angstroms to 500 angstroms, and the third sacrificial layer is made of silicon oxide.

[0010] Optionally, the substrate includes adjacent first and second regions, the selection gate spans the first and second regions, and the first and second regions are arranged along a second direction.

[0011] Optionally, the step of sequentially etching the photoresist layer, the second sacrificial layer, the first sacrificial layer, and a portion of the floating gate layer to form a plurality of floating gates using an etching process with an etching selectivity ratio includes: exposing and developing the photoresist until the surface of the anti-reflection layer on the second region is exposed, forming a photoresist layer with a floating gate pattern; using a first sub-etching process to etch away the anti-reflection layer, the second sacrificial layer, the first sacrificial layer, the floating gate layer, a portion of the third sacrificial layer, and the photoresist layer, the anti-reflection layer, and a portion of the second sacrificial layer on the second region, until the surface of the third sacrificial layer on the second region and the surface of the second sacrificial layer on the first region are exposed; using a second sub-etching process to etch away a portion of the third sacrificial layer on the second region and all of the second sacrificial layer on the first region, until the surface of the third sacrificial layer on the second region and the surface of the first sacrificial layer on the first region are exposed; and using a third sub-etching process to etch away the first sacrificial layer on the first region, until the surface of the third sacrificial layer on the second region and the surface of the floating gate layer on the first region are exposed, forming a floating gate.

[0012] Optionally, the first etching process is a plasma dry etching process. The process parameters of the first etching process include: the etching gas is one or more combinations of CF4, CHF3, CH3F, O2, and Ar; the gas flow rate of the etching gas is 100 sccm to 500 sccm; the bias voltage is 100 V to 200 V; the etching pressure is 30 mTorr to 40 mTorr; and the etching time is 30 seconds to 45 seconds. The first etching process has an etching selectivity ratio of 1:0 for the first sacrificial layer on the second region and the second sacrificial layer on the first region.

[0013] Optionally, the second etching process is a wet etching process, wherein the process parameters of the wet etching process are as follows: the etching solution includes one or more combinations of hydrofluoric acid solution, ammonia solution and water; the reaction temperature range is 20 degrees Celsius to 25 degrees Celsius; the reaction time is 3 minutes to 4 minutes; and the second etching process has an etching selectivity ratio of 2:1 to 2.5:1 for the second sacrificial layer on the first region and the third sacrificial layer on the second region.

[0014] Optionally, the third etching process is a plasma resist removal process. The process parameters of the third etching process include: the etching gas is one or more combinations of CF4, CHF3, CH3F, O2, and Ar; the gas flow rate of the etching gas is 100 sccm to 500 sccm; the bias voltage is 100 V to 200 V; the etching pressure is 30 mTorr to 40 mTorr; and the etching time is 30 seconds to 45 seconds. The third etching process has an etching selectivity ratio of 1:0 for the first sacrificial layer on the first region and the third sacrificial layer on the second region.

[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0016] This invention uses a first sacrificial layer and a second sacrificial layer as sacrificial layers for forming a floating gate. Compared with the prior art, which only uses the first sacrificial layer as the sacrificial layer for forming a floating gate, this invention reduces the thickness of the first sacrificial layer and forms a second sacrificial layer with good step coverage and gap filling ability on the first sacrificial layer, thereby reducing the possibility of voids and improving the performance of semiconductor devices.

[0017] Furthermore, since the first sacrificial layer and the second sacrificial layer are etched using an etching process with an etching selectivity, the second sacrificial layer can act as a barrier layer for the first sacrificial layer while the floating gate layer on the opening is etched subsequently, thus avoiding damage to the active region caused by over-etching of the floating gate and ensuring the integrity of the floating gate.

[0018] Furthermore, by increasing the thickness of the photoresist layer, the present invention increases the etching time of the photoresist on the top surface of the select gate, so that while the first sacrificial layer on the opening is being etched, the second sacrificial layer on the top surface of the select gate is not completely removed. Thus, the second sacrificial layer acts as a barrier layer to ensure the integrity of the subsequently formed floating gate.

[0019] Furthermore, by forming a third sacrificial layer on the surface of the select gate and the surface of the substrate, the present invention enables the third sacrificial layer to act as a barrier layer to protect the substrate from etching during the subsequent formation of the floating gate and the removal of the first and second sacrificial layers on the select gate, thereby avoiding damage to the active region and improving the performance of the device. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the formation process of a semiconductor structure;

[0021] Figures 2 to 22 This is a schematic diagram of the memory structure formation process in an embodiment of the present invention. Detailed Implementation

[0022] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0023] The current process for forming floating gate flash memory is as follows: Figure 1 As shown, the method includes: providing a substrate 100 having at least two selection gates 101, with an opening between adjacent selection gates 101, the selection gates 101 being arranged along a first direction X, the first direction X being parallel to the surface of the substrate 100; forming a floating gate layer 102 on the surface of the opening and the top surface of the selection gates 101; forming a first sacrificial layer 103 in the opening and on the top surface of the selection gates 101; and forming a first anti-reflection layer 104 on the first sacrificial layer 103.

[0024] In the above scheme, during the process of filling the opening with amorphous carbon (i.e., the first sacrificial layer), there is a void 105 that is not sealed, resulting in a thin photoresist layer formed on the surface of the void 105. In the subsequent photo rework process, some of the amorphous carbon will be removed, and the first anti-reflection layer 104 will not be removed during this process, resulting in the wafer being scrapped.

[0025] Currently, the problem of voids in the opening is solved by increasing the thickness of amorphous carbon to seal the voids at the top. However, increasing the thickness of amorphous carbon leads to an increase in the amount of oxygen required during the subsequent removal of amorphous carbon. Furthermore, oxygen will form an oxide layer on the surface of the floating gate layer. During the subsequent removal of the oxide layer, the amount of gas CF4 is increased, which reduces the floating gate layer at the bottom of the opening. This can lead to over-etching of the floating gate, resulting in the risk of active area damage (AA damage) and affecting the performance of the semiconductor device.

[0026] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. By filling the opening on the floating gate with a first sacrificial layer and a second sacrificial layer having a flow ratio, the first and second sacrificial layers can better fill the opening. Furthermore, by using the first and second sacrificial layers as sacrificial layers, the thickness of the first sacrificial layer is reduced, voids are avoided, and the performance of the semiconductor device is improved.

[0027] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0028] Please refer to Figure 2 , Figure 3 as well as Figure 4 , Figure 2 It is a top view. Figure 3 yes Figure 2 Cross-sectional view along line AA1. Figure 4 yes Figure 3 A cross-sectional view along line BB1 ​​shows a substrate 200, which includes adjacent first region I and second region II; a selection gate layer 2021 is formed on the substrate 200; and a selection gate dielectric layer 2022 is formed on the selection gate layer 2021.

[0029] In this embodiment, the second region II includes several separate isolation regions 201.

[0030] In some embodiments, the material of the selection gate layer 2021 includes one or more combinations of monocrystalline silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide, and the material of the selection gate dielectric layer 2022 is silicon dioxide.

[0031] Please refer to Figure 5 , Figure 6 as well as Figure 7 , Figure 5 It is a top view. Figure 6 yes Figure 5 Cross-sectional view along line AA1. Figure 7 yes Figure 5 A cross-sectional view along line BB1 ​​shows a photoresist layer (not shown) with a selection gate pattern formed on the selection gate dielectric layer 2022, forming a selection gate on the substrate 200. The selection gate is arranged along a first direction X, which is parallel to the surface of the substrate 200.

[0032] In this embodiment, the selection gate 202 includes a selection gate layer 2021 and a selection gate dielectric layer 2022 located on the selection gate layer 2021.

[0033] In some embodiments, the substrate 200 has at least two selection gates 202 adjacent to each other, with an opening 2023 between the adjacent selection gates 202.

[0034] Please refer to Figure 8 , Figure 9 as well as Figure 10 , Figure 8 It is a top view. Figure 9 yes Figure 8 Cross-sectional view along line AA1. Figure 10yes Figure 8 A cross-sectional view along line BB1 ​​shows that a floating gate layer 205 is formed on the surface of the opening 2023 and the top surface of the selection gate.

[0035] The material of the floating gate layer 205 includes one or more combinations of monocrystalline silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide.

[0036] In this embodiment, before forming the floating grid layer 205, the method further includes forming a sidewall 203 on the sidewall of the selection grid 202.

[0037] In some embodiments, the sidewall 203 is an ONO structure, and the sidewall 203 includes a silicon oxide layer 2031 located on the sidewall of the select gate, a silicon nitride layer 2032 located on the sidewall of the silicon oxide layer 2031, and a third sacrificial layer 2033 located on the silicon nitride sidewall, the top surface of the select gate, and the surface of the substrate 200.

[0038] The material of the third sacrificial layer 2033 is silicon oxide, and the thickness of the third sacrificial layer 2033 ranges from 300 angstroms to 500 angstroms.

[0039] In some embodiments, the process for forming the third sacrificial layer 2033 is a high-temperature thermal oxidation process (HTO process), with process parameters of a deposition rate of 1.5 Å to 2.5 Å per minute and a deposition time of 12,000 seconds to 20,000 seconds.

[0040] In the above scheme, by forming a third sacrificial layer 2033 on the surface of the select gate and the surface of the substrate 200, the third sacrificial layer 2033 can act as a barrier layer to protect the substrate 200 from being etched after the floating gate is formed and the first sacrificial layer 206 and the second sacrificial layer 207 on the select gate need to be removed, thereby avoiding damage to the active region and improving the performance of the device.

[0041] Please refer to Figure 11 , Figure 12 as well as Figure 13 , Figure 11 It is a top view. Figure 12 yes Figure 11 Cross-sectional view along line AA1. Figure 13 yes Figure 11 A cross-sectional view along line BB1 ​​shows that a first sacrificial layer 206 is formed within the opening 2023 and on the surface of the floating gate layer 205 at the top of the selection gate, and a second sacrificial layer 207 is formed on the first sacrificial layer 206.

[0042] In some embodiments, the material of the first sacrificial layer 206 is amorphous carbon, and the material of the second sacrificial layer 207 is silicon dioxide or TEOS.

[0043] Of course, this invention is not limited thereto, and other materials with good gap filling and morphological flattening properties are also within the scope of protection of this invention.

[0044] In this embodiment, the process for forming the first sacrificial layer 206 is chemical vapor deposition, with process parameters of deposition temperature at 400°C, deposition rate of 3500 angstroms to 4500 angstroms per minute, and deposition time of 13 to 34 seconds.

[0045] In the above scheme, a first sacrificial layer 206 and a second sacrificial layer 207 with a flow ratio are used as sacrificial layers to form a floating gate, so that the first sacrificial layer 206 and the second sacrificial layer 207 can better fill the opening 2023. Compared with the prior art scheme that only uses the first sacrificial layer 206 as the sacrificial layer to form a floating gate, the thickness of the first sacrificial layer 206 is reduced, and a second sacrificial layer 207 with good filling performance is formed on the first sacrificial layer 206, which reduces the possibility of voids and improves the performance of semiconductor devices.

[0046] Furthermore, since the first sacrificial layer 206 on the first region I has a high selectivity when the floating gate layer 205 on the second region II is etched, that is, the first sacrificial layer 206 on the first region I is basically not etched when the floating gate layer 205 on the second region II is etched, the first sacrificial layer 206 can serve as a hard mask layer for the floating gate layer 205, thereby ensuring that the floating gate layer 205 under the first sacrificial layer 206 on the first region I is not affected by etching, thus ensuring the integrity of the floating gate formed subsequently.

[0047] In this embodiment, the process for forming the second sacrificial layer 207 is chemical vapor deposition, and the parameters of the chemical vapor deposition process are: a deposition rate of 4,000 angstroms per minute to 5,000 angstroms per minute and a deposition time of 10 to 15 seconds.

[0048] In this embodiment, after forming the second sacrificial layer 207, the method further includes: forming an anti-reflection layer 208 on the second sacrificial layer 207; and forming a photoresist layer 209 on the anti-reflection layer 208.

[0049] Please refer to Figure 14 as well as Figure 15 , Figure 14 It is a top view. Figure 15 yes Figure 14 A cross-sectional view along line BB1 ​​shows that the photoresist layer 209 is exposed and developed until the anti-reflective layer 208 in the second region II is exposed, forming a photoresist layer 209 located on the first region I. The photoresist layer 209 has a floating gate pattern.

[0050] In some embodiments of the present invention, an etching process with an etching selectivity ratio will be subsequently used to sequentially etch the photoresist layer 209, the antireflection layer 208, the second sacrificial layer 207, the first sacrificial layer 206, the third sacrificial layer 2033 on the second region II, and the floating gate layer 205 on the second region II to form a plurality of floating gates 2051.

[0051] The thickness of the photoresist layer 209 ranges from 2000 angstroms to 3000 angstroms.

[0052] In the above scheme, by increasing the thickness of the photoresist layer 209, the etching time of the photoresist on the top surface of the select gate is increased, so that while the first sacrificial layer 206 on the opening 2023 is being etched, the second sacrificial layer 207 on the top surface of the select gate is not completely removed. Thus, the second sacrificial layer 207 acts as a barrier layer to ensure the integrity of the subsequently formed floating gate 2051.

[0053] Please refer to Figure 16 as well as Figure 17 , Figure 16 View direction and Figure 12 The view directions are the same. Figure 17 View direction and Figure 15 With the same viewing direction, the first etching process is used to etch away the anti-reflection layer 208, the second sacrificial layer 207, the first sacrificial layer 206, the floating gate layer 205 on the second region II, and the photoresist layer 209, the anti-reflection layer 208, and part of the second sacrificial layer 207 on the first region I, so as to expose the surface of the third sacrificial layer 2033 on the second region II and the surface of the second sacrificial layer 207 on the first region I.

[0054] In this embodiment, the first etching process is a plasma dry etching process. The process parameters of the first etching process include: the etching gas is one or more combinations of CF4, CHF3, CH3F, O2, and Ar; the gas flow rate of the etching gas is 100 sccm to 500 sccm; the bias voltage is 100 V to 200 V; the etching pressure is 30 mTorr to 40 mTorr; and the etching time is 30 seconds to 45 seconds. The first etching process has an etching selectivity ratio of 1:0 for the first sacrificial layer 206 on the second region II and the second sacrificial layer 207 on the first region I.

[0055] Specifically, while etching the anti-reflection layer 208 on the second region II, the photoresist layer 209 on the first region I is etched. Simultaneously with etching the second sacrificial layer 207 on the second region II, the anti-reflection layer 208 on the first region I is etched. However, due to the relatively thick thickness of the filled second sacrificial layer 207, after the anti-reflection layer 208 on the first region I is etched, the second sacrificial layer 207 located on the lower surface of the anti-reflection layer 208 on the first region I will continue to be etched. Consequently, after the second sacrificial layer 207 on the first region I is etched, when etching the first sacrificial layer 206 on the second region II, there is no second sacrificial layer 207 on the first region I to act as a hard mask, resulting in the floating gate layer 205 on the first region I also being etched. Therefore, this invention increases the thickness of the photoresist layer 209 so that when the first sacrificial layer 206 on the second region II is subsequently etched, the second sacrificial layer 207 on the first region I is still retained as a hard mask to ensure the integrity of the floating gate layer 205 on the first region I.

[0056] Please refer to Figure 18 as well as Figure 19 , Figure 18 View direction and Figure 16 The view directions are the same. Figure 19 View direction and Figure 17 With the same viewing direction, a second etching process is used to etch away part of the third sacrificial layer 2033 on the second region II and all of the second sacrificial layer 207 on the first region I, until the surface of the third sacrificial layer 2033 on the second region II and the surface of the first sacrificial layer 206 on the first region I are exposed.

[0057] In this embodiment, the second etching process is a wet etching process. The process parameters of the wet etching process are as follows: the etching solution includes one or more combinations of hydrofluoric acid solution, ammonia solution and water; the reaction temperature range is 20 degrees Celsius to 25 degrees Celsius; the reaction time is 3 minutes to 4 minutes; and the second etching process has an etching selectivity ratio of 2:1 to 2.5:1 for the second sacrificial layer 207 on the first region I and the third sacrificial layer 2033 on the second region II.

[0058] In the above scheme, since the second sacrificial layer 207 on the first region I and the third sacrificial layer 2033 on the second region II have an etching selectivity ratio in the second etching process, that is, the etching rate of the second sacrificial layer 207 on the first region I is greater than the etching rate of the third sacrificial layer 2033 on the second region II, the third sacrificial layer 2033 is always present on the second region II as an etching stop layer while the second sacrificial layer 207 on the first region I is being etched, so as to protect the substrate 200 on the second region II from damage.

[0059] Please refer to Figure 20 , Figure 21 as well as Figure 22 , Figure 22 It is a top view. Figure 20 yes Figure 22 Cross-sectional view along line AA1. Figure 21 yes Figure 22 The cross-sectional view along line BB1 ​​shows that the third etching process is used to etch away the first sacrificial layer 206 on the first region I, until the surface of the third sacrificial layer 2033 on the second region II and the surface of the floating gate layer 205 on the first region I are exposed, forming a floating gate.

[0060] In this embodiment, the third etching process is a plasma dry etching process. The process parameters of the third etching process include: the etching gas is one or more combinations of CF4, CHF3, CH3F, O2, and Ar; the gas flow rate of the etching gas is 100 sccm to 500 sccm; the bias voltage is 100V to 200V; the etching pressure is 30 mTorr to 40 mTorr; and the etching time is 30 seconds to 45 seconds. The third etching process has an etching selectivity ratio of 1:0 for the first sacrificial layer 206 on the first region I and the third sacrificial layer 2033 on the second region II.

[0061] In this embodiment, the floating gate spans the selection gate and is arranged along the second direction Y, which is perpendicular to the first direction X.

[0062] In the above scheme, since the third etching process has an etching selectivity ratio for the first sacrificial layer 206 on the first region I and the third sacrificial layer 2033 on the second region II, that is, the etching rate of the first sacrificial layer 206 on the first region I is greater than the etching rate of the third sacrificial layer 2033 on the second region II, the third sacrificial layer 2033 is always present on the second region II as an etching stop layer while the first sacrificial layer 206 on the first region I is being etched, so as to protect the substrate 200 on the second region II from damage.

[0063] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of the invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, the substrate having at least two select gates, adjacent select gates, and openings between adjacent select gates, the select gates being arranged along a first direction, the first direction being parallel to the surface of the substrate; forming a floating gate layer on the surface of the openings and the top surface of the select gates; forming a first sacrificial layer on the floating gate layer in the openings and on the top surface of the select gates; forming a second sacrificial layer with good filling performance on the first sacrificial layer, the thickness of the first sacrificial layer being 1000 angstrom to 2000 angstrom, the thickness of the second sacrificial layer being 800 angstrom to 1000 angstrom, the material of the first sacrificial layer being amorphous carbon, and the material of the second sacrificial layer being silicon dioxide.

2. The method of forming a semiconductor structure of claim 1, wherein, The process for forming the second sacrificial layer is a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are as follows: the deposition rate is 4000 angstrom per minute to 5000 angstrom per minute, and the deposition time is 10 seconds to 15 seconds.

3. The method of forming a semiconductor structure of claim 1, wherein, After the step of forming the second sacrificial layer, the method further comprises the following steps: forming a photoresist layer with a floating gate pattern on the second sacrificial layer; using an etching process with etching selectivity to sequentially etch the photoresist layer, the second sacrificial layer, the first sacrificial layer, and part of the floating gate layer, thereby forming a plurality of floating gates, the floating gates crossing the select gates, and the floating gates being arranged along a second direction, the second direction being perpendicular to the first direction.

4. The method of forming a semiconductor structure of claim 3, wherein, Before the step of forming the photoresist layer, the method further comprises the following steps: forming an anti-reflection layer on the second sacrificial layer; and after forming the select gates, forming a third sacrificial layer on the surface of the select gates and the surface of the substrate.

5. The method of forming a semiconductor structure of claim 4, wherein, The thickness of the photoresist layer is 2000 angstrom to 3000 angstrom, and the thickness of the third sacrificial layer is 300 angstrom to 500 angstrom, and the material of the third sacrificial layer is silicon oxide.

6. The method of forming a semiconductor structure of claim 4, wherein, The substrate comprises adjacent first and second regions, the select gates cross the first and second regions, and the first and second regions are arranged along the second direction.

7. The method of forming a semiconductor structure of claim 6, wherein, The step of using an etching process with etching selectivity to sequentially etch the photoresist layer, the second sacrificial layer, the first sacrificial layer, and part of the floating gate layer to form a plurality of floating gates comprises the following steps: exposing and developing the photoresist to expose the surface of the anti-reflection layer on the second region, thereby forming a photoresist layer with a floating gate pattern; using a first sub-etching process to etch and remove the anti-reflection layer, the second sacrificial layer, the first sacrificial layer, the floating gate layer, part of the third sacrificial layer on the second region, and the photoresist layer, the anti-reflection layer, part of the second sacrificial layer on the first region, thereby exposing the surface of the third sacrificial layer on the second region and the surface of the second sacrificial layer on the first region; using a second sub-etching process to etch and remove part of the third sacrificial layer on the second region and all of the second sacrificial layer on the first region, thereby exposing the surface of the third sacrificial layer on the second region and the surface of the first sacrificial layer on the first region; The third sub-etching process is used to etch and remove the first sacrificial layer on the first region to expose the surface of the third sacrificial layer on the second region and the surface of the floating gate layer on the first region, thereby forming a floating gate.

8. The method of forming a semiconductor structure of claim 7, wherein, The first sub-etching process is a plasma dry etching process, and the process parameters of the first sub-etching process include: the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2 and Ar, the gas flow of the etching gas is 100-500sccm, the bias voltage is 100-200V, the etching pressure is 30-40mTorr, the etching time is 30-45s, and the first sub-etching process has an etching selectivity ratio of 1:0 for the first sacrificial layer on the second region and the second sacrificial layer on the first region.

9. The method of forming a semiconductor structure of claim 7, wherein, The second sub-etching process is a wet etching process, and the process parameters of the wet etching process include: the etching solution includes one or more of a combination of hydrofluoric acid solution, ammonia solution and water, the reaction temperature is 20-25℃, and the reaction time is 3-4min, and the second sub-etching process has an etching selectivity ratio of 2:1-2.5:1 for the second sacrificial layer on the first region and the third sacrificial layer on the second region.

10. The method of forming a semiconductor structure of claim 7, wherein, The third sub-etching process is a plasma etching process, and the process parameters of the third sub-etching process include: the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2 and Ar, the gas flow of the etching gas is 100-500sccm, the bias voltage is 100-200V, the etching pressure is 30-40mTorr, the etching time is 30-45s, and the third sub-etching process has an etching selectivity ratio of 1:0 for the first sacrificial layer on the first region and the third sacrificial layer on the second region.

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