Substrate comprising microstructure thin film capacitor

Abstract

Microelectronic assemblies including strengthened glass cores and related devices and methods are disclosed herein. In some embodiments, a microelectronic substrate having an in-situ capacitor may include a first conductive layer having a first microstructure at a first surface; the second conductive layer is arranged on the first conductive layer and is provided with a second microstructure on a second surface, and the second microstructure and the first microstructure are vertically interlocked; and a high-k dielectric material between the first microstructure and the second microstructure.

Description

Technical Field

[0001] The present disclosure relates to techniques, methods and apparatus for substrates with microstructured thin film capacitors. Background Art

[0002] Electronic circuits are often referred to as integrated circuits (ICs) when they are manufactured on semiconductor material (e.g., silicon) wafers. Wafers with such ICs are typically cut into many individual dies. The dies may be packaged into an IC package that contains one or more dies and other electronic components such as resistors, capacitors, and inductors. IC packages may be integrated into electronic systems such as consumer electronics systems. Some ICs have specific functionality, such as storage or processing. Some other ICs have multiple functionalities, such as systems on a chip (SOCs), in which all or most of the components of a computer or other electronic system are integrated into a single monolithic die. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For ease of description, similar reference numerals denote similar structural elements. In the figures of the accompanying drawings, the embodiments are illustrated by way of example and not limitation.

[0004] Figure 1 is a schematic cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure.

[0005] Figure 2A is a schematic cross-sectional view of a capacitor in a portion of an example microelectronic assembly according to some embodiments of the present disclosure.

[0006] Figure 2B-2E is a perspective view of a portion of an example capacitor according to some embodiments of the present disclosure.

[0007] Figures 3A-3L are simplified cross-sectional views showing various fabrication steps of an example microelectronic assembly according to some embodiments of the present disclosure.

[0008] Figure 4 is a cross-sectional view of a device package that may include one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0009] Figure 5 is a cross-sectional side view of a device assembly that may include one or more microelectronic assemblies according to any embodiment disclosed herein.

[0010] Figure 6 is a block diagram of an example computing device that may include one or more microelectronic assemblies according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0011] In order to explain the IC packaging described herein, it is important to understand the phenomena that may play a role during assembly and packaging. The following basic information can be considered as the basis for properly explaining the present disclosure. Such information is provided for explanation purposes only, and therefore should not be interpreted in a manner that limits the broad scope of the present disclosure and its potential applications.

[0012] Capacitors are included in IC packages to provide current to the die during transient spikes in power demand and to minimize power supply noise. The power delivery requirements of server processors and other advanced processing platforms include an increasing demand for more capacitance adjacent to the die to prevent voltage drops on the voltage rails. Typically, IC packages include pre-manufactured capacitors that can be surface mounted on the die or circuit board. For example, the IC package may include a die-side capacitor (DSC) mounted on the back side of the die or a land-side capacitor (LSC) mounted on the circuit board. Surface-mounted capacitors may increase the delay of power transmission due to increased power trace distance, occupy limited surface area on the die and / or circuit board, and increase the overall z height (e.g., thickness) of the IC package. A traditional solution for incorporating capacitors is to build a metal-insulator-metal (MIM) capacitor in the top die as part of the voltage regulator circuitry necessary for the power delivery function of the IC package, but many dies cannot incorporate a sufficient number of MIM capacitors to meet the capacitance requirements of the power delivery network. Another traditional solution is to incorporate capacitors into the package substrate, which results in a long electrical path from the capacitor to the die. Relative to traditional approaches, various embodiments in the embodiments disclosed herein can help achieve improved power efficiency with greater design flexibility. Another traditional solution for providing the required decoupling capacitance is to integrate the capacitance layer into the substrate below the tube core. Thin film capacitors (TFCs) manufactured in situ in the substrate tend to use high dielectric constant inorganic materials in the capacitor, but organic dielectric materials can also be used for specific applications. As used herein, in-situ TFC refers to TFCs manufactured in and with the substrate, which is different from non-in-situ TFCs manufactured independently of the substrate. Crystalline inorganic materials have high dielectric constants, but also require high annealing temperatures. Amorphous dielectrics, such as organic polymers, generally do not require annealing, but have relatively low dielectric constants, resulting in lower capacitance values. In addition, the manufacturing process for various such inorganic dielectric materials typically involves high annealing temperatures that are incompatible with electronic circuit systems or materials used therewith, often severely limiting the selection of materials that can be used to manufacture in-situ capacitors. It may be desirable to have capacitors with high aspect ratios and high capacitance applications and more efficient and easier to integrate into the substrate of an IC package.

[0013] Thus, embodiments described herein are microelectronic assemblies and related apparatus and methods, the microelectronic assemblies including a substrate having a microstructure capacitor (MSC) therein. In particular, the substrate may include the MSC, and the MSC may include: a first conductive layer having a first microstructure at a first surface; a second conductive layer on the first conductive layer, the second conductive layer having a second microstructure at a second surface, wherein the first microstructure is vertically interlocked with the second microstructure; and a high-k dielectric layer between the first microstructure and the second microstructure.

[0014] MSCs can be formed in situ on a glass carrier using a photolithography process to greatly increase the capacitor film surface area. By using this in-situ manufacturing process, MSCs can be fabricated directly beneath the die area, which eliminates the need for stacked vias that are typically connected to the LSC. In addition, MSCs can be positioned closer to the die, which can enhance performance. By forming MSCs on a glass carrier, higher annealing temperatures can be achieved without affecting the electronic circuitry or materials in the substrate. In addition, glass carriers typically have a lower average surface roughness than typical organic substrates, which is an important parameter for TFCs, where thinner films can lead to higher capacitance.

[0015] Each of the structures, components, packaging, methods, devices, and systems of the present disclosure may have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and drawings.

[0016] In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly used by those skilled in the art to convey the substance of their work to others skilled in the art.

[0017] The terms "circuit" and "circuitry" mean one or more passive and / or active electrical and / or electronic components that are arranged to cooperate with each other to provide a desired functionality. The terms also refer to analog circuitry, digital circuitry, hard-wired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical hardware electrical and / or electronic components.

[0018] The term "integrated circuit" means an electrical circuit integrated into a single piece of semiconductor or similar material.

[0019] In some embodiments, the IC die disclosed herein may include a substantially single-crystal semiconductor (e.g., silicon or germanium) as a substrate material, on which the integrated circuit is fabricated using conventional semiconductor processing methods. The semiconductor substrate material may include, for example, an N-type or P-type material. For example, the die may include a crystalline substrate material formed using bulk silicon (or other bulk semiconductor material) or a semiconductor on insulator (SOI, such as silicon on insulator) structure. In some other embodiments, the substrate material of one or more of the IC dies may include an alternative material that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials. In other embodiments, the substrate material may include a compound semiconductor, for example, a first sub-lattice having at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice having at least one element from Group V of the periodic table (e.g., P, As, Sb). In other embodiments, the substrate material may include an intrinsic IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In other embodiments, the die may include an amorphous material, such as a polymer; for example, the substrate material may include a silicon dioxide filled epoxy. In other embodiments, the substrate material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Typically, the substrate material may include tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten disulfide, N-type or P-type amorphous silicon or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although some examples of materials for the die are described here, any material or structure that can be used as a foundation (e.g., a substrate material) on which IC circuits and structures as described herein can be built falls within the spirit and scope of the present disclosure.

[0020] Unless otherwise noted, an IC die as described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) certain functionality. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., an IC that implements one or more of a memory device, a memory array, control logic configured to control the memory device and array, etc.). In another such example, the term "computing die" may be used to describe a die that includes one or more ICs that implement logic / computing circuitry (e.g., an IC that implements one or more of input / output (I / O) functions, arithmetic operations, data pipelining operations, etc.).

[0021] In another example, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die." It should be noted that the terms "chip," "chiplet," "die," and "IC die" are used interchangeably herein.

[0022] The term "insulation" means "electrical insulation" and the term "conduction" means "electrical conduction", unless otherwise specified. With respect to optical signals and / or devices, components and elements that operate on or use optical signals, the term "conduction" may also mean "optical conduction".

[0023] The terms "oxide", "carbide", "nitride" and the like refer to compounds containing oxygen, carbon, nitrogen and the like, respectively.

[0024] The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.

[0025] The term "insulating material" refers to a solid material (and / or a liquid material that solidifies after treatment as described herein) that is substantially non-conductive of electricity. By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, porcelain, glass, silicon and alumina or combinations thereof. They may include dielectric materials, high polarizability materials and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials are underfills and molding or molding-like materials used in packaging applications, including, for example, materials used in organic inserts, packaging supports and other such components.

[0026] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, and the like. In various embodiments, elements associated with an IC may include those elements monolithically integrated within the IC, those elements mounted on the IC, or those elements connected to the IC. The ICs described herein may be analog or digital and may be used in a variety of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, and the like, depending on the components associated with the IC. The ICs described herein may be used in a single IC die or as part of a chipset for performing one or more related functions in a computer.

[0027] In various embodiments of the present disclosure, the transistors described herein may be field effect transistors (FETs), such as metal oxide semiconductor (MOS) FETs (MOSFETs). Typically, a FET is a three-terminal device including a source, a drain, and a gate terminal, and uses an electric field to control the current flowing through the device. A FET typically includes a channel material, a source region and a drain region provided in and / or on the channel material, and a gate stack, the gate stack including a gate electrode material provided on a portion of the channel material ("channel portion") between the source region and the drain region, or referred to as a "work function" material, and optionally, a gate dielectric material located between the gate electrode material and the channel material.

[0028] In a general sense, "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components to facilitate the communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components to facilitate the communication of optical signals between them. As used herein, both electrical and optical interconnects are included in the term "interconnect". The nature of the interconnect described herein will be understood with reference to the signal medium associated therewith. Therefore, when used with reference to an electronic device (e.g., an IC that operates using electrical signals), the term "interconnect" describes any element formed of an electrically conductive material that is used to provide an electrical connection to one or more elements associated with the IC or / and between various such elements. In this case, the term "interconnect" can refer to electrical traces (sometimes also referred to as "wires", "conductors", "metal wires" or "trench") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, electrically conductive traces and vias may be referred to as "conductive traces" and "conductive vias", respectively, to emphasize the fact that these elements include electrically conductive materials such as metals. Likewise, when used with reference to a device that also operates on optical signals (e.g., a photonic IC (PIC)), "interconnect" may also describe any element formed from an optically conductive material that is used to provide an optical connection to one or more elements associated with the PIC. In this context, the term "interconnect" may refer to an optical waveguide (e.g., a structure that guides and confines light waves), including optical fibers, optical beam splitters, optical combiners, optical couplers, and optical vias.

[0029] The term "conductive trace" may be used to describe electrically conductive elements separated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics provided within the IC die. Within package substrates and printed circuit boards (PCBs), such insulating materials include organic materials such as Ajinomoto built-up film (ABF), polyimide, or epoxy. Such conductive lines are typically arranged in several levels or layers of a metallization stack.

[0030] The term "conductive via" may be used to describe an electrically conductive element that interconnects two or more conductive lines at different levels of a metallization stack. To this end, the via may be provided substantially perpendicular to the plane of the IC die / chip or to a support structure on which the IC structure is provided, and the via may interconnect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.

[0031] The term "package substrate" may be used to describe any substrate material that facilitates packaging together any collection of semiconductor die and / or other electrical components (e.g., passive electrical components). As used herein, a package substrate may be formed of any material, including but not limited to insulating materials such as resin-impregnated fiberglass (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. In addition, as used herein, a package substrate may refer to a substrate including a buildup layer (e.g., ABF layer).

[0032] The term "metallization stack" may be used to refer to a stack of one or more interconnects used to provide connections to different circuit components of an IC die / chip and / or a package substrate.

[0033] The terms "substantially," "close," "approximately," "near," and "about" generally mean within + / - 20% of a target value (e.g., within + / - 5% or 10% of a target value) based on the context of the particular value described herein or known in the art.

[0034] Terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally mean within + / - 5%-20% of a target value based on the context of the specific value described herein or known in the art.

[0035] The term "connected" means a direct connection (which may be one or more of a mechanical, electrical and / or thermal connection) between the connected things without any intermediate devices, while the term "coupled" means a direct connection between the connected things, or an indirect connection through one or more passive or active intermediate devices.

[0036] This specification uses the phrases "in one embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments.

[0037] Furthermore, the terms "comprising," "including," and "having," etc. used with respect to embodiments of the present disclosure are synonymous.

[0038] The present disclosure may use perspective-based descriptions, such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0039] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers, or may have one or more intervening layers. In contrast, a first layer described as being "on" a second layer refers to the layer that is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0040] As used herein, the term "disposed" refers to positioning, location, placement, and / or arrangement, rather than any particular method of formation.

[0041] When used with reference to a measuring range, the term "between" includes the ends of the measuring range.

[0042] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The notation "A / B / C" as used herein means (A), (B), and / or (C).

[0043] Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, "electrically conductive material" may include one or more electrically conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0044] Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates that different instances of similar objects are being referenced and is not intended to imply that the objects described must be in a given sequence in time, space, ranking, or in any other manner.

[0045] In the following detailed description, reference is made to the accompanying drawings which form a part of this document, and in which embodiments that can be practiced are shown by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered to have a limiting meaning.

[0046] The drawings are not necessarily drawn to scale.

[0047] In the drawings, the same reference numerals refer to the same or similar elements / materials shown, so that, unless otherwise stated, the explanation of an element / material with a given reference numeral provided in the context of one of the drawings may be applied to other drawings in which elements / materials with the same reference numeral may be illustrated.

[0048] In addition, some schematic illustrations of example structures of various devices and components described herein may be shown in the accompanying drawings with precise right angles and straight lines, but it should be understood that when any structure described herein is examined using, for example, images of suitable characterization tools (e.g., scanning electron microscope (SEM) images or transmission electron microscope (TEM) images) or non-contact profilometers, such schematic illustrations may not reflect actual process limitations that may cause features to appear less than "ideal." In such images of real structures, possible processing and / or surface defects may also be visible, such as surface roughness, curvature or profile deviations, pits or scratches, imperfectly straight edges of materials, tapered vias or other openings, unintentional rounding of corners of different material layers or variations in thickness, occasional spiral, edge or combined dislocations within a crystal region (single or multiple), and / or occasional dislocation defects of single atoms or clusters of atoms. Other defects not listed here but common in the field of device manufacturing and / or packaging may exist.

[0049] It should be noted that in the figures, various components (e.g., interconnects) are shown as aligned (e.g., at corresponding interfaces) for ease of illustration only; in fact, some or all of them may be misaligned. In addition, there may be other components in the assembly that are not shown in the figures to prevent confusion, such as bonding pads, landing pads, metallizations, etc. In addition, the figures are intended to show the relative arrangement of components within their assemblies, and generally, such assemblies may include other components that are not described (e.g., various interface layers or various other components related to optical functionality, electrical connections, or thermal relief). For example, in some further embodiments, the assemblies shown in the figures may include more dies and other electrical components. In addition, although some components of the assembly are illustrated in the figures as planar rectangles or formed by rectangular entities, this is only for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, which is dictated by the manufacturing process used to manufacture the various components and is sometimes unavoidable.

[0050] In the drawings, specific numbers and arrangements of structures and components are presented for illustrative purposes, and any desired numbers or arrangements of such structures and components may be presented in various embodiments.

[0051] Furthermore, unless otherwise specified, the structures shown in the figures may take any suitable form or shape depending on material properties, manufacturing processes and operating conditions.

[0052] For convenience, if there are graph collections designated with different letters (e.g. Figures 3A-3L ), such a collection may be referenced herein without a letter (e.g., as "FIG. 3"). Similarly, if there is a collection of reference numerals designated with different numbers (e.g., 118-1, 118-2), such a collection may be referenced herein without a number (e.g., as "118").

[0053] Various operations may be described in sequence as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must rely on the order. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0054] Figure 1 is a schematic cross-sectional view of an example microelectronic assembly 100 according to some embodiments of the present disclosure. The microelectronic assembly 100 may include a substrate 112 having an in-situ MSC 119. In particular, the substrate 112 may have a first surface 171-1 and an opposing second surface 171-2, wherein the MSC 119 is at the second surface 171-2 adjacent to the die 114-1, 114-2. The MSC 119 may include: a first conductive layer 118-1 having a first microstructure 115-1; a second conductive layer 118-2 having a second microstructure 115-2, wherein the second microstructure 115-2 is complementary to the first microstructure 115 and vertically interlocked; and a high-k dielectric material 117 between the first microstructure 115-1 and the second microstructure 115-2. As used herein, "interlocking" refers to parts that cooperate with each other (e.g., parts that complement and coordinate with each other so that the parts can be interconnected or closely engaged). The terms "interlocking", "interdigitated", and "interconnect" may be used interchangeably herein.

[0055] Figure 2A1 is a schematic cross-sectional view of an example MSC included in a microelectronic assembly according to some embodiments of the present disclosure. MSC 119 may include: a first conductive layer 118-1, also referred to as a first plate or a first electrode, having a first microstructure 115-1; and a second conductive layer 118-2 on the first conductive layer 118-1 (e.g., in a different metal layer of the substrate 112), the second conductive layer 118-2 also referred to as a second plate or a second electrode, having a second microstructure 115-2 vertically interconnected with the first microstructure 115-1 of the first conductive layer 118-1. Conductive layer 118 may include any suitable conductive material, such as a metal, such as copper. Microstructure 115 may have a thickness 191 (i.e., z dimension, height, or z height) between 2 microns and 20 microns (e.g., between 2 microns and 7 microns, between 7 microns and 12 microns, or between 12 microns and 18 microns). The microstructures 115 can have a width 193 (i.e., y dimension) between 2 microns and 12 microns (e.g., between 2 microns and 7 microns or between 7 microns and 12 microns), such that the microstructures 115 can be spaced 195 apart between 2 microns and 12 microns. The first and second microstructures 115 can include any suitable shape, as described below with reference to Figure 2B-2E As described, and may be configured to increase the surface area of ​​high-k dielectric layer 117 .

[0056] MSC 119 may also include a high-k dielectric layer 117 between the first conductive layer 118-1 and the second conductive layer 118-2. The high-k dielectric layer 117 may have a thickness between 500 nanometers and 2 micrometers. In some embodiments, the material of the high-k dielectric layer 117 may include a material having a dielectric constant greater than 200, or may include a material that can be deposited using a plasma vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. For example, the high-k dielectric material 117 may include barium, titanium, and oxygen (e.g., in the form of barium titanium oxide (BaTiO3)); strontium, titanium, and oxygen (e.g., in the form of strontium titanate (SrTiO3)); or lead, zirconium, and titanium (e.g., in the form of lead zirconate titanate (PZT)).

[0057] Figure 2B-2E is a perspective view of a portion of an example capacitor according to some embodiments of the present disclosure. For example, microstructure 115 may include a column (e.g., Figure 2B and 2C as shown), walls (e.g., Figure 2D as shown) or micro-protrusions or bumps (e.g., as Figure 2E ), wherein the complementary structure may include a void or a recess. Figure 2B-2EOnly the first microstructure 115-1 of the first conductive layer 118-1 is illustrated, but the second microstructure 115-2 of the second conductive layer 118-2 may be formed to complement and interlock with the first microstructure 115-1. Figure 2B-2E The microstructure 115 is shown as having a specific cross-section (e.g., square, rectangular, or circular), but the microstructure 115 can have any suitable cross-section, including triangular, hexagonal, or oval, etc. The microstructure 115 can be configured to increase the surface area of ​​the high-k dielectric layer 117. Figure 2B and 2C As shown, microstructure 115-1 may include pillars having a specific height (eg, thickness), width, and spacing. Figure 2B As shown, microstructures 115-1 may have a height of 5 microns, a width of 5 microns, and may be spaced 5 microns apart so that in 1 square millimeter (mm 2 ) is 10,000, and the surface area of ​​the high-k dielectric layer 117 (not shown) is 2 mm 2 , and every 1mm 2 In another example (not shown), the microstructures 115-1 may have a height of 10 microns, a width of 5 microns, and may be spaced 5 microns apart so that within 1 mm 2 The number of pillars in the area is 10000, and the surface area of ​​the high-k dielectric layer 117 (not shown) is 3 mm 2 , and every 1mm 2 The capacitance increases by 300%. Figure 2C As shown, microstructures 115-1 may have a height of 10 microns, a width of 10 microns, and may be spaced 10 microns apart so that within 1 mm 2 The number of pillars in the area is 2500, and the surface area of ​​the high-k dielectric layer 117 (not shown) is 2 mm 2 , and every 1mm 2 In yet another example (not shown), microstructures 115-1 may have a height of 15 microns, a width of 10 microns, and may be spaced 10 microns apart so that within 1 mm 2 The number of pillars in the area is 2500, and the surface area of ​​the high-k dielectric layer 117 (not shown) is 2.5 mm 2 , and every 1mm 2 The capacitance increases by 250%.

[0058] return Figure 1, the substrate 112 may include a dielectric material 107 and a conductive material 108 (e.g., a line / trace / pad / contact), wherein the conductive material 108 is arranged in the dielectric material 107 to provide a conductive path through the substrate 112 to route power, ground, and signals through the dielectric material 107 (e.g., including conductive traces and / or conductive vias, as shown). The dielectric material 107 of the substrate 112 may be formed in layers. In some embodiments, the dielectric material 107 may include an organic material, such as an organic build-up film. In some embodiments, the dielectric material 107 may include, for example, a ceramic, an epoxy film with filler particles therein, a glass, an inorganic material, or a combination of an organic material and an inorganic material. In some embodiments, the conductive material 108 may include a metal (e.g., copper). The conductive path 108 in the substrate 112 may be defined by a liner material, such as an adhesive liner and / or a barrier liner as desired. Any method known in the art for manufacturing the substrate 112 may be used, including the method discussed below with reference to FIG. 3.

[0059] Although specific numbers and arrangements of layers of dielectric material 107 / conductive material 108 are shown in various figures of the drawings, these specific numbers and arrangements are merely illustrative, and any desired number and arrangement of dielectric material 107 / conductive material 108 may be used. In addition, although a specific number of layers are shown in substrate 112, these layers may represent only a portion of substrate 112, for example, additional layers may be present.

[0060] The microelectronic assembly 100 may also include a die 114-1 and a die 114-2 electrically coupled to a top surface 171-2 of the substrate 112 via an interconnect 130. As used herein, the terms "die," "microelectronic component," and similar variations may be used interchangeably. In particular, the conductive contacts 122 on the bottom surfaces of the die 114-1, 114-2 may be electrically and mechanically coupled to the conductive contacts 174 at the top surface of the substrate 112 via the interconnect 130. The interconnect 130 may enable electrical coupling between the die 114-1 and the die 114-2 via the conductive pathway 108 in the substrate 112. The interconnect 130 disclosed herein may take any suitable form, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or lands in a land grid array arrangement. In some embodiments, a set of interconnects 130 may include solder (e.g., solder bumps or balls that are subjected to thermal reflow to form the interconnect 130). The interconnect 130 including solder may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / zinc / indium / bismuth or other alloys. In some embodiments, a set of interconnects 130 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. The anisotropic conductive material may include a conductive material dispersed in a non-conductive material. In some embodiments, the anisotropic conductive material may include microscopic conductive particles embedded in an adhesive or a thermosetting adhesive film (e.g., a thermosetting biphenyl epoxy or acrylic-based material). In some embodiments, the conductive particles may include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-coated gold or silver-coated copper, which is in turn coated with a polymer. In another example, the conductive particles may include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other side. However, when the anisotropic conductive material is sufficiently compressed (e.g., by conductive contacts on either side of the anisotropic conductive material), the conductive materials near the compressed area can contact each other to form a conductive path from one side of the film to the other side in the compressed area. In some embodiments, the interconnects 130 disclosed herein may have a pitch between about 18 microns and 75 microns. As used herein, the pitch is measured from center to center (e.g., from the center of a conductive contact to the center of an adjacent conductive contact).

[0061] The tube core 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the tube core 114 may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or low-k or ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymer dielectric, photoimageable dielectric and / or benzocyclobutene-based polymer). In some embodiments, the insulating material of the tube core 114 may include a semiconductor material, such as silicon, germanium or III-V group material (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths in the tube core 114 may include conductive traces and / or conductive vias, and any conductive contacts in the tube core 114 may be connected in any suitable manner (e.g., multiple conductive contacts are connected on the same surface or different surfaces of the tube core 114). Conductive paths in die 114 may be defined by a gasket material, for example, a bonding gasket and / or a barrier gasket as desired. In some embodiments, die 114 is a wafer. In some embodiments, die 114 is a monolithic silicon, a fan-out or fan-in packaged die, or a die stack (e.g., a stacked wafer, a stacked die, or a stacked multilayer die). In various embodiments, die 114 may include a central processing unit (CPU), a memory device (e.g., a high bandwidth memory device), a logic circuit, an input / output circuit system, a transceiver (e.g., a field programmable gate array transceiver), a gate array logic of a power delivery circuit system (e.g., a field programmable gate array logic), a III-V or III-N device (e.g., a III-N or III-N amplifier (e.g., a GaN amplifier)), a peripheral component interconnect express (Peripheral Component Interconnect Express (PCIe)) circuit system, a double data rate (DDR) transmission circuit system, or other electronic components known in the art. In some embodiments, die 114-1 and die 114-2 may include different functionalities. As used herein, the term "functionality" with reference to a die refers to one or more functions (e.g., capabilities, tasks, operations, actions, instruction execution, etc.) that the die in question can perform. For example, die 114-1 can be a CPU, while die 114-2 can be a graphics processing unit (GPU) or memory. In other embodiments, die 114-1 and die 114-2 can include the same or similar functionality. For example, IC die 114-1 and die 114-2 can both include memory. Figure 4 The discussion may include example structures in die 114 disclosed herein.

[0062] Figure 1 The microelectronic assembly 100 may also include an insulating material 133 encapsulating the die 114 (e.g., on and around the die 114 and the interconnect 130). The insulating material 133 may extend from the top surface 171-2 of the substrate 112 to the top surface of the die 114. In some embodiments, the insulating material 133 may be: a molding material, such as an organic polymer with inorganic silicon oxide or aluminum oxide particles; a resin material; or an epoxy material. In some embodiments (not shown), other components such as a heat sink may be coupled to the microelectronic assembly 100 based on specific needs.

[0063] Figure 1 The microelectronic assembly 100 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend around the associated interconnect 130 between the die 114-1, 114-2 and the top surface 171-2 of the substrate 112. The underfill material 127 may be an insulating material, such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that helps solder the die 114-1, 114-2 to the substrate 112 when forming the interconnect 130, and then polymerizes and encapsulates the interconnect 130. The underfill process may include dispensing the underfill material in liquid form, allowing the material to flow and fill the gap around the interconnect 130, and subjecting the assembly to a curing process, such as baking, to solidify the material. In some embodiments, the underfill material 127 may be omitted. Although Figure 1 Two separate underfill 127 portions are shown under die 114-1 and die 114-2, but underfill 127 can be a single underfill under die 114-1 and die 114. Underfill material 127 can be selected to have a coefficient of thermal expansion (CTE) that can alleviate or minimize stresses between die 114 and substrate 112 caused by uneven thermal expansion in microelectronic assembly 100. In some embodiments, the CTE of underfill material 127 can have a value intermediate the CTE of dielectric material 107 of substrate 112 and the CTE of insulating material of die 114.

[0064] Figure 1 The microelectronic assembly 100 may also include a circuit board 131. In particular, the conductive contacts 172 on the bottom surface of the substrate 112 may be electrically coupled to the conductive contacts 146 on the top surface of the circuit board 131 via the interconnect 150. The interconnect 150 disclosed herein may take any suitable form, including any form described above with reference to the interconnect 130. Figure 1As shown, in some embodiments, a group of interconnects 150 may include solder (e.g., solder bumps or balls that are subjected to thermal reflow to form interconnects 150). In some embodiments, the interconnects 150 disclosed herein may have a pitch between approximately 50 microns and 300 microns. In some embodiments, the bottom fill material 127 may extend around the associated interconnects 150 between the first surface 171-1 of the substrate 112 and the circuit board 131. For example, the circuit board 131 may be a motherboard and may have other components attached thereto. The circuit board may include conductive pathways and other conductive contacts for routing power, grounding, and signals through the circuit board, as known in the art. In some embodiments, the interconnect 150 may not be coupled to the circuit board 131, but may be coupled to another IC package, an interposer, or any other suitable component.

[0065] In some embodiments, one or more levels of solder resist 126 (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic resin, solvent) may be provided in the IC packages described herein. The solder resist may be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder resist may not be photoimageable.

[0066] although Figure 1 The microelectronic assembly 100 shows a substrate 112 having a particular number and arrangement of MSCs 119, but the microelectronic assembly 100 can have any suitable number and arrangement of MSCs 119 in the substrate 112, including between 2 and 50 (e.g., between 2 MSCs and 20 MSCs, or between 20 MSCs and 50 MSCs).

[0067] Any suitable technique may be used to manufacture the microelectronic assembly 100 disclosed herein. For example, Figures 3A-3L According to various embodiments, Figure 1 The following are side cross-sectional views of various stages in an exemplary process of a microelectronic assembly 100. Although described in a particular order, the following reference Figures 3A-3L The operations discussed in the drawings (and other drawings in the drawings representing the manufacturing process) are described in detail, but these operations may be performed in any suitable order. In addition, additional operations not shown may be performed without departing from the scope of the present disclosure. In addition, the descriptions herein regarding Figures 3A-3L Various operations in the operations discussed may be performed to fabricate other microelectronic assemblies in the microelectronic assembly 100 disclosed herein. Figures 3A-3L The components are shown to be formed simultaneously on the top and bottom surfaces of the carrier, but the components may be formed on a single surface rather than on two surfaces.

[0068] Figure 3AA glass carrier 103 is illustrated that includes a conductive material 310 on a first surface 170-1 and a second surface 170-2. The conductive material 310 may include a metal, such as copper. The conductive material 310 may be deposited on the glass carrier 103 using any suitable technique, such as plating.

[0069] Figure 3B The assembly is illustrated after applying a first photoresist 311-1 to the conductive material 310 on the first surface 170-1 and the second surface 170-2 of the glass carrier 103 and photolithographically patterning the first photoresist 311-1. The first photoresist 311-1 may be a liquid type or a dry film type.

[0070] Figure 3C The assembly is illustrated after removing exposed portions of the conductive material 310. The conductive material 310 may be removed using any suitable process (eg, etching).

[0071] Figure 3D Explains from Figure 3C The component after removing the first photoresist 311 - 1 .

[0072] Figure 3E The assembly is illustrated after applying and photolithographically patterning a second photoresist 311-2 and depositing a conductive material in the opening of the patterned second photoresist 311-2 to form a microstructure 115. The second photoresist 311-2 can be a liquid type or a dry film type. The conductive material can be deposited using any suitable technique (e.g., electrolytic plating) to form the microstructure 115. In some embodiments, excess conductive material can be etched or polished away from the surface of the microstructure 115 using, for example, a chemical / mechanical planarization (CMP) process.

[0073] Figure 3F Explains from Figure 3E The component after removing the second photoresist 311-2. Figure 3F As shown, Figures 3A-3F MSC 119 is formed by the process described in Figure 1 The second conductive layer 118-2 having the second microstructure 115-2 is formed in the MSC 119 in the embodiment of the present invention.

[0074] Figure 3GThe assembly is illustrated after depositing a high-k dielectric layer 117 on the second conductive layer 118-2. The high-k dielectric layer may be deposited using any suitable technique, such as sputtering, PVD, or CVD. The high-k dielectric layer 117 may be sintered after sputtering to stabilize the crystal structure of the high-k dielectric material 117. The glass carrier 103 may withstand the high annealing temperatures required for exposure to the high-k dielectric material 117. For example, the sintering temperature for barium titanium oxide is approximately 900°C, and the softening temperature (e.g., melting transition temperature) for glass is between 700°C and 1500°C. In addition, higher sintering temperatures may result in higher dielectric constant values, resulting in higher capacitance density and improved frequency stability above 100 megahertz (MHz), which enables packaged voltage regulators with higher switching frequencies.

[0075] Figure 3H The assembly is illustrated after applying and photolithographically patterning a third photoresist 311-3 and depositing a conductive material in the openings of the patterned third photoresist 311-3 to form a first conductive layer 118-1 having a first microstructure 115-1. The third photoresist 311-3 may be a liquid type or a dry film type. Any suitable technique may be used to deposit the conductive material.

[0076] Fig. 3I Explains from Figure 3H The component after removing the third photoresist 311-3. Figure 3H As shown, Figures 3A-3H MSC 119 is formed by the process described in the above, including MSC 119-1 and MSC 119-2. MSC 119-1 may be formed of a single continuous second conductive layer 118-2 having a second microstructure 115-2 and two or more first conductive layers 118-1 having first microstructures 115-1 interlocked with the second microstructures 115-2 of the second conductive layer 118-2. MSC 119-2 may be formed of a single second conductive layer 118-2 having a second microstructure 115-2 and a single first conductive layer 118-1 having first microstructures 115-1 interlocked with the second microstructures 115-2 of the second conductive layer 118-2. Although Fig. 3I The MSC 119 illustrated in the drawings includes a specific number and arrangement of first conductive layers 118-1 interconnected with second conductive layers 118-2 (e.g., one second conductive layer 118-2 and one (e.g., MSC 119-2) or two (e.g., MSC 119-1) first conductive layers 118-1), but the MSC 119 can have any suitable number and arrangement of first and second conductive layers 118-1, 118-2, including three or more first conductive layers 118-1 interconnected with second conductive layers 118-2.

[0077] Figure 3J It explains Fig. 3I The component after forming a portion of the substrate 112 including the dielectric material 107 and the conductive path 108 on the component. The portion of the substrate 112 can be formed using any suitable technology, such as a lamination process, a semi-additive process, or other build-up process. The conductive path 108 can be electrically coupled to the first conductive layer 118-1 and the second conductive layer 118-2 to create terminal connections that form the first electrode and the second electrode of the MSC 119, respectively.

[0078] Figure 3K The assembly is illustrated after the substrate 112 is completed by forming additional layers of dielectric material 107 and conductive material 108 .

[0079] Figure 3L The assembly is illustrated after removing the glass carrier 103, forming a via connection 129 to the MSC 119, forming a conductive contact 174, and performing finishing operations. Any suitable technique may be used to form the via connection 129 and the conductive contact 174, including lamination and photolithography (e.g., of the solder resist 126). If multiple assemblies are manufactured together, the multiple assemblies may be singulated. Example finishing operations include depositing solder resist (if not previously deposited), and depositing solder 132 on the conductive contact 174 and depositing solder 136 on the conductive contact 172.

[0080] Figure 3L The assembly itself can be a microelectronic assembly 100, as shown. Figure 3L The microelectronic assembly 100 is subjected to further manufacturing operations to form other microelectronic assemblies 100. For example, Figure 3L The solder 132 of the microelectronic assembly 100 can be electrically coupled to the dies 114-1, 114-2 to form the interconnect 130, and / or the solder 136 can be electrically coupled to the circuit board 131 to form the interconnect 150, similar to Figure 1 114. The die 114 may be placed using any suitable method, such as automated pick and place. The assembly may be subjected to a solder reflow process during which the solder (e.g., solder 132, 136) of the interconnects 130, 150 melts and joins to mechanically and electrically couple the die 114 to the substrate 112. In some embodiments, insulating material 133 may be deposited to completely cover the die 114, and a floating overburden of insulating material 133 may be removed to expose the top surface of the die 114. Insulating material 133 may be removed using any suitable technique, including etching, mechanical milling, or laser ablation. In some embodiments, the bottom fill material (e.g., Figure 1An underfill material 127 may be deposited around the interconnect 130 and around the interconnect 150 prior to overmolding with the insulating material 133 .

[0081] The packages disclosed herein, for example, any microelectronic assembly 100, or any further embodiments described herein, can be included in any suitable electronic component. Figure 4-6 Various examples of packages, components, and devices are shown that may be used with or include any of the IC packages disclosed herein.

[0082] Figure 4 is a side cross-sectional view of an example IC package 2200, which can include a microelectronic assembly according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 can be a system in package (SiP).

[0083] like Figure 4 As shown, the package support portion 2252 can be formed of an insulator (e.g., ceramic, a deposited film, an epoxy film with filler particles therein, etc.), and can have conductive paths extending through the insulator between the first side 2272 and the second side 2274, or between different locations on the first side 2272, and / or between different locations on the second side 2274. These conductive paths can take the form of any interconnect structure, including lines and / or vias, for example, as described above with reference to Figure 1 discussed.

[0084] The package support portion 2252 may include a conductive contact portion 2263 coupled to a conductive path 2262 passing through the package support portion 2252, thereby allowing the circuit system within the tube core 2256 and / or the insert body 2257 to be electrically coupled to the respective conductive contacts in the conductive contact portion 2264 (or other devices included in the package support portion 2252, not shown).

[0085] The IC package 2200 may include an interposer 2257 coupled to the package support 2252 via conductive contacts 2261 of the interposer 2257 , the FLI 2265 , and conductive contacts 2263 of the package support 2252 . Figure 4 The FLI 2265 illustrated in FIG. 2 is a solder bump, but any suitable FLI 2265 may be used, such as a solder bump, a solder column, or a bond wire.

[0086] IC package 2200 may include one or more dies 2256 coupled to interposer 2257 via conductive contacts 2254 of die 2256, FLI 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled to conductive paths (not shown) through interposer 2257, thereby allowing circuitry within die 2256 to be electrically coupled to individual ones of conductive contacts 2261 (or to other devices included in interposer 2257, not shown). Figure 4 The FLI 2258 shown in is a solder bump, but any suitable FLI 2258 may be used, such as a solder bump, a solder column, or a bonding wire. As used herein, a "conductive contact" may refer to a portion of an electrically conductive material (e.g., a metal) that serves as an interface between different components; a conductive contact may be recessed in a surface of a component, flush with a surface of a component, or extend away from a surface of a component, and may take any suitable form (e.g., a conductive pad or a socket).

[0087] In some embodiments, an underfill material 2266 may be disposed between the package support 2252 and the interposer 2257 around the FLI 2265, and a molding 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package support 2252. In some embodiments, the underfill material 2266 may be the same as the molding 2268. An example material that may be used for the underfill material 2266 and the molding 2268 is suitably epoxy. The SLI 2270 may be coupled to the conductive contact 2264. Figure 4 The SLI 2270 illustrated in the drawings is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable SLI 227 may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The SLI 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference to Figure 6 discussed.

[0088] In embodiments where IC package 2200 includes multiple dies 2256, IC package 2200 may be referred to as a multi-chip package (MCP). Dies 2256 may include circuitry for performing any desired functionality. For example, in addition to one or more dies 2256 including components of die 114 as described herein, one or more dies 225 may be logic dies (e.g., silicon-based dies), one or more dies 2256 may be memory dies (e.g., high bandwidth memory), and so on. In some embodiments, at least some of dies 2256 may not include components of die 114 as described herein.

[0089] although Figure 4 The IC package 2200 described in the figure is a flip chip package, but other packaging architectures may also be used. For example, the IC package 2200 may be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mounted resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package support 2252 or disposed on either side of the insert 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0090] Figure 5 is a cross-sectional side view of an IC device assembly 2300, which may include components having one or more microelectronic assemblies 100 according to any embodiments disclosed herein. The IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and an opposing second side 2342 of the circuit board 2302; typically, the components may be disposed on one or both sides 2340 and 2342. In particular, any suitable component among the components of the IC device assembly 2300 may include any one of the one or more microelectronic assemblies 100 according to any embodiments disclosed herein; for example, any of the IC packages discussed below with reference to the IC device assembly 2300 may be employed with reference to the above. Figure 4 Any of the embodiments of IC package 2200 discussed.

[0091] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by insulator layers and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally in conjunction with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB package support.

[0092] Figure 5It is illustrated that in some embodiments, the IC device assembly 2300 can include a package-on-interposer structure 2336 coupled to the first side 2340 of the circuit board 2302 via a coupling component 2316. In other embodiments, the package-on-interposer structure 2336 can include no glass core. The coupling component 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and can include solder balls (as shown), male and female portions of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0093] The package-on-interposer structure 2336 may include an IC package 2320 coupled to the interposer 2304 via a coupling feature 2318. In some embodiments, the IC package 2320 may include the microelectronic assembly 100 and other components described herein, which are not shown to avoid obscuring the drawings. The coupling feature 2318 may take any suitable form depending on the desired functionality, such as those discussed above with reference to the coupling feature 2316. In some embodiments, the IC package 2320 may be or include the IC package 2200, such as those discussed above with reference to the coupling feature 2316. Figure 4 as described.

[0094] Despite Figure 5 A single IC package 2320 is shown in FIG. 2 , but multiple IC packages can be coupled to the interposer 2304; indeed, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate package support portion for bridging the circuit board 2302 and the IC package 2320. In general, the interposer 2304 can redistribute connections to a wider spacing, or reroute connections to different connections. For example, the interposer 2304 can couple the IC package 2320 to a BGA for coupling to a coupling component 2316 of the circuit board 2302.

[0095] exist Figure 5 In the illustrated embodiment, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0096] The insert 2304 may be formed of an epoxy, a glass fiber reinforced epoxy, a ceramic material, or a polymer material such as polyimide. In some embodiments, the insert 2304 may be formed of an alternative rigid or flexible material, which may include the same materials as those described above for the semiconductor substrate, such as silicon, germanium, and other III-V and IV materials. The insert 2304 may include metal interconnects 2308 and vias 2310, including TSVs 2306. The insert 2304 may also include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the insert 2304. The package-on-interposer structure 2336 may take the form of any package-on-interposer structure known in the art.

[0097] In some embodiments, IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0098] In some embodiments, IC device assembly 2300 may include a package-on-package structure 2334 coupled to second side 2342 of circuit board 2302 via coupling component 2328. Package-on-package structure 2334 may include IC package 2326 and IC package 2332 coupled together via coupling component 2330, such that IC package 2326 is disposed between circuit board 2302 and IC package 2332. Coupling components 2328 and 2330 may take the form of any of the embodiments of coupling component 2316 discussed above, and IC package 2326 and / or 2332 may take the form of any of the embodiments of IC package 2320 discussed above. Package-on-package structure 2334 may be configured according to any of the package-on-package structures known in the art.

[0099] Figure 62400, which may include one or more components having one or more IC packages according to any embodiment disclosed herein. For example, any suitable component of computing device 2400 may include microelectronic assembly 100, which includes MSC 119 according to any embodiment disclosed herein. In another example, any one or more components of computing device 2400 may include any embodiment of IC package 2200 (e.g., as Figure 4 In yet another example, any one or more components of the computing device 2400 may include the IC device assembly 2300 (e.g., Figure 5 shown).

[0100] Figure 6 2400, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single SOC die.

[0101] In addition, in various embodiments, the computing device 2400 may not include Figure 6 2400, but the computing device 2400 may include interface circuitry for coupling to one or more of the components. For example, the computing device 2400 may not include the display device 2406, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include the audio input device 2418 or the audio output device 2408, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which the audio input device 2418 or the audio output device 2408 may be coupled.

[0102] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more digital signal processors (DSPs), ASICs, CPUs, GPUs, cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-MRAM).

[0103] In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips; it should be noted that the terms "chip," "die," and "IC die" are used interchangeably herein). For example, communication chip 2412 may be configured to manage wireless communications for transmitting data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, and the like that can communicate data over a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0104] The communication chip 2412 can implement any of a plurality of wireless standards or protocols, including: Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments); Long Term Evolution (LTE) project and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 2412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication chip 2412 may operate in accordance with other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0105] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, the first communication chip 2412 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, while the second communication chip 2412 can be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 2412 can be dedicated to wireless communications, while the second communication chip 2412 can be dedicated to wired communications.

[0106] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).

[0107] Computing device 2400 may include display device 2406 (or corresponding interface circuitry as discussed above). Display device 2406 may include any visual indicator such as, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0108] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry as discussed above). Audio output device 2408 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earbuds.

[0109] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry as discussed above). The audio input device 2418 may include any device that generates a signal representative of sound, such as, for example, a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0110] Computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry as discussed above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0111] Computing device 2400 may include other output devices 2410 (or corresponding interface circuitry as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0112] Computing device 2400 may include other input devices 2420 (or corresponding interface circuitry as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0113] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0114] The above description of the embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific embodiments and examples of the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure as will be appreciated by those skilled in the relevant art.

[0115] The following paragraphs provide various examples of the embodiments disclosed herein.

[0116] Example 1 is a microelectronic substrate, comprising: a first conductive layer, the first conductive layer having a first microstructure at a first surface; a second conductive layer on the first conductive layer, the second conductive layer having a second microstructure at a second surface, wherein the second microstructure is vertically interlocked with the first microstructure; and a high-k dielectric material between the first microstructure and the second microstructure.

[0117] Example 2 may include the subject matter of Example 1, and may further provide that the first microstructure and the second microstructure include pillars or walls.

[0118] Example 3 may include the subject matter of Example 2, and may further provide that the first microstructure has a thickness between 2 micrometers and 20 micrometers.

[0119] Example 4 may include the subject matter of Example 2, and may further provide that the first microstructure comprises a pillar, and one (1) square millimeter (mm) of the first conductive layer 2 ) surface area includes between 2500 and 10000 columns.

[0120] Example 5 may include the subject matter of any of Examples 1-4, and may further provide that the high-k dielectric material has a thickness between 500 nanometers and 2 micrometers.

[0121] Example 6 may include the subject matter of any of Examples 1-5, and may further provide that the high-k dielectric material includes: barium, titanium, and oxygen; strontium, titanium, and oxygen; or lead, zirconium, and titanium.

[0122] Example 7 may include the subject matter of Example 2, and may further provide that the first microstructures include pillars, the thickness of the first microstructures is between 5 micrometers and 15 micrometers, and the spacing between the first microstructures is between 5 micrometers and 10 micrometers.

[0123] Example 8 is a microelectronic component, which includes: a substrate having a first surface and an opposite second surface; a capacitor in the substrate, adjacent to the second surface, the capacitor including: a first conductive layer, the first conductive layer having a first microstructure at a surface; a second conductive layer on the first conductive layer, the second conductive layer having a second microstructure at a surface, wherein the second microstructure is vertically interlocked with the first microstructure; and a high-k dielectric material between the first microstructure and the second microstructure; and a die, the die being at the second surface of the substrate and electrically coupled to the capacitor.

[0124] Example 9 may include the subject matter of Example 8, and may further provide that the first microstructure and the second microstructure comprise pillars or walls.

[0125] Example 10 may include the subject matter of Example 8 or 9, and may further provide that the thickness of the first microstructure is between 2 micrometers and 20 micrometers.

[0126] Example 11 may include the subject matter of Example 8, and may further provide that the first microstructure comprises a pillar, and one (1) square millimeter (mm) of the first conductive layer 2 ) surface area includes between 2500 and 10000 columns.

[0127] Example 12 may include the subject matter of any of Examples 8-11, and may further provide that the high-k dielectric material has a thickness between 500 nanometers and 2 micrometers.

[0128] Example 13 may include the subject matter of any of Examples 8-12, and may further provide that the high-k dielectric material includes: barium, titanium, and oxygen; strontium, titanium, and oxygen; or lead, zirconium, and titanium.

[0129] Example 14 may include the subject matter of any of Examples 8-13, and may further include a circuit board electrically coupled to the first surface of the substrate.

[0130] Example 15 is a microelectronic component, which includes: a substrate having a first surface and an opposite second surface; a plurality of capacitors in the substrate, adjacent to the second surface, the plurality of capacitors including: a first conductive layer, the first conductive layer having a first microstructure at a surface; a second conductive layer on the first conductive layer, the second conductive layer having a second microstructure at a surface, wherein the second microstructure is vertically interlocked with the first microstructure; and a high-k dielectric material between the first microstructure and the second microstructure; and a first die, the first die being at the second surface of the substrate and electrically coupled to one of the plurality of capacitors; and a second die, the second die being at the second surface of the substrate and electrically coupled to another of the plurality of capacitors.

[0131] Example 16 may include the subject matter of Example 15, and may further provide that the first microstructure and the second microstructure comprise pillars or walls.

[0132] Example 17 may include the subject matter of Example 15 or 16, and may further provide that the thickness of the first microstructure is between 2 micrometers and 20 micrometers.

[0133] Example 18 may include the subject matter of any of Examples 15-17, and may further provide that the high-k dielectric material has a thickness between 500 nanometers and 2 micrometers.

[0134] Example 19 may include the subject matter of any of Examples 15-18, and may further provide that the high-k dielectric material includes: barium, titanium, and oxygen; strontium, titanium, and oxygen; or lead, zirconium, and titanium.

[0135] Example 20 may include the subject matter of any of Examples 15-19, and may further provide that the plurality of capacitors includes between 20 and 50 capacitors.

Claims

1. A microelectronic substrate, comprising: a first conductive layer having a first microstructure at a first surface; a second conductive layer on the first conductive layer, the second conductive layer having a second microstructure at a second surface, wherein the second microstructure is vertically interlocked with the first microstructure; as well as A high-k dielectric material is between the first microstructure and the second microstructure.

2. The microelectronic substrate according to claim 1, wherein: The first microstructure and the second microstructure include pillars or walls.

3. The microelectronic substrate according to claim 2, wherein: The thickness of the first microstructure is between 2 micrometers and 20 micrometers.

4. The microelectronic substrate according to claim 2, wherein: The first microstructure includes pillars, and one (1) square millimeter (mm) of the first conductive layer 2 ) surface area includes between 2500 and 10000 columns.

5. The microelectronic substrate according to claim 2, wherein: The first microstructure includes pillars, the thickness of the first microstructure is between 5 micrometers and 15 micrometers, and the spacing between the first microstructures is between 5 micrometers and 10 micrometers.

6. The microelectronic substrate according to any one of claims 1 to 5, wherein: The high-k dielectric material has a thickness between 500 nanometers and 2 micrometers.

7. The microelectronic substrate according to any one of claims 1 to 5, wherein: The high-k dielectric material includes: barium, titanium and oxygen; strontium, titanium and oxygen; or lead, zirconium and titanium.

8. A microelectronic assembly comprising: a substrate having a first surface and an opposing second surface; A capacitor, the capacitor being in the substrate and adjacent to the second surface, the capacitor comprising: a first conductive layer, the first conductive layer having a first microstructure at a surface; a second conductive layer on the first conductive layer, the second conductive layer having a second microstructure at a surface, wherein the second microstructure is vertically interlocked with the first microstructure; and a high-k dielectric material between the first microstructure and the second microstructure; and A die is at the second surface of the substrate and is electrically coupled to the capacitor.

9. The microelectronic assembly of claim 8, wherein: The first microstructure and the second microstructure include pillars or walls.

10. The microelectronic assembly of claim 8, wherein: The thickness of the first microstructure is between 2 micrometers and 20 micrometers.

11. The microelectronic assembly of claim 8, wherein: The first microstructure includes pillars, and one (1) square millimeter (mm) of the first conductive layer 2 ) surface area includes between 2500 and 10000 columns.

12. A microelectronic assembly according to any one of claims 8 to 11, wherein: The high-k dielectric material has a thickness between 500 nanometers and 2 micrometers.

13. A microelectronic assembly according to any one of claims 8 to 11, wherein: The high-k dielectric material includes: barium, titanium and oxygen; strontium, titanium and oxygen; or lead, zirconium and titanium.

14. The microelectronic assembly according to any one of claims 8 to 11, further comprising: A circuit board is electrically coupled to the first surface of the substrate.

15. A microelectronic assembly comprising: a substrate having a first surface and an opposing second surface; a plurality of capacitors, the plurality of capacitors being in the substrate and adjacent to the second surface, the plurality of capacitors comprising: a first conductive layer, the first conductive layer having a first microstructure at a surface; a second conductive layer on the first conductive layer, the second conductive layer having a second microstructure at a surface, wherein the second microstructure is vertically interlocked with the first microstructure; and a high-k dielectric material between the first microstructure and the second microstructure; and a first die at the second surface of the substrate and electrically coupled to one of the plurality of capacitors; and A second die is at the second surface of the substrate and is electrically coupled to another capacitor of the plurality of capacitors.

16. The microelectronic assembly of claim 15, wherein: The first microstructure and the second microstructure include pillars or walls.

17. The microelectronic assembly of claim 15, wherein: The thickness of the first microstructure is between 2 micrometers and 20 micrometers.

18. A microelectronic assembly according to any one of claims 15 to 17, wherein: The high-k dielectric material has a thickness between 500 nanometers and 2 micrometers.

19. A microelectronic assembly according to any one of claims 15 to 17, wherein: The high-k dielectric material includes: barium, titanium and oxygen; strontium, titanium and oxygen; or lead, zirconium and titanium.

20. A microelectronic assembly according to any one of claims 15 to 17, wherein: The plurality of capacitors includes between 20 and 50 capacitors.

Images