Display device and pixel circuit

Abstract

The invention provides a display device and a pixel circuit. The pixel circuit includes: a first storage sub-circuit (7) connected between a first node (N1) and a second node (N2); the data writing sub-circuit (1) is used for charging a second node (N2); the driving sub-circuit (6) is used for controlling the connection or disconnection of the third node (N3) and the fourth node (N4) under the control of the first node (N1); the compensation sub-circuit (2) is used for controlling the connection or disconnection of the first node (N1) and the fourth node (N4) under the control of a first scanning signal end (Gate1); the light-emitting control sub-circuit (5) is used for controlling a first power supply end (VDD) to be connected or disconnected with a third node (N3) under the control of a first light-emitting control signal end (EM1), and is also used for controlling a fourth node (N4) to be connected or disconnected with a first pole of a sub-pixel (L0) under the control of a second light-emitting control signal end (EM2); therefore, the display effect can be improved.

Description

Display device and pixel circuit Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display device and a pixel circuit. Background Art

[0002] Organic electroluminescent displays (OLEDs) are a new generation of display products, following liquid crystal displays (LCDs). Due to their superior color saturation, fast response time, foldability, and thinness, they are gradually becoming the mainstream and leading display technology. However, OLEDs still require further improvement.

[0003] Summary of the Invention

[0004] The present disclosure aims to provide a display device and a pixel circuit, which can improve the display effect.

[0005] According to one aspect of the present disclosure, there is provided a pixel circuit, comprising:

[0006] A first storage sub-circuit connected between the first node and the second node;

[0007] a data writing sub-circuit, connected to the second node, and configured to charge the second node;

[0008] a driving subcircuit, connected to the first node, the third node, and the fourth node, and configured to control the third node to be connected to or disconnected from the fourth node under the control of the first node;

[0009] a compensation subcircuit connected to the first scan signal terminal, the first node, and the fourth node, and configured to control the connection or disconnection between the first node and the fourth node under the control of the first scan signal terminal;

[0010] The light-emitting control subcircuit is connected to the first power supply terminal, the first light-emitting control signal terminal, the third node, the fourth node, the second light-emitting control signal terminal, and the first electrode of the sub-pixel, and is used to control the connection or disconnection between the first power supply terminal and the third node under the control of the first light-emitting control signal terminal, and is also used to control the connection or disconnection between the fourth node and the first electrode of the sub-pixel under the control of the second light-emitting control signal terminal.

[0011] Furthermore, the pixel circuit further includes:

[0012] The first reset subcircuit is connected to the second scan signal terminal, the first reference voltage terminal and the second node, and is used to control the connection or disconnection between the first reference voltage terminal and the second node under the control of the second scan signal terminal.

[0013] Furthermore, the first reset sub-circuit includes:

[0014] A first reset transistor, wherein a control electrode of the first reset transistor is connected to the second scanning signal terminal, a first electrode of the first reset transistor is connected to the first reference voltage terminal, and a second electrode of the first reset transistor is connected to the second node.

[0015] Furthermore, in one frame, a start time when the first reset sub-circuit controls the first reference voltage terminal to be connected to the second node is before a start time when the compensation sub-circuit controls the first node to be connected to the fourth node.

[0016] Furthermore, the pixel circuit further includes:

[0017] a second reset sub-circuit, connected to the first reset signal terminal, the first initialization signal terminal, and the first node, and configured to control the connection or disconnection between the first initialization signal terminal and the first node under the control of the first reset signal terminal;

[0018] The third reset sub-circuit is connected to the second reset signal terminal, the second reference voltage terminal and the third node, and is used to control the second reference voltage terminal to be connected or disconnected from the third node under the control of the second reset signal terminal.

[0019] Furthermore, the second reset sub-circuit includes:

[0020] a second reset transistor, wherein a control electrode of the second reset transistor is connected to the first reset signal terminal, a first electrode of the second reset transistor is connected to the first initialization signal terminal, and a second electrode of the second reset transistor is connected to the first node;

[0021] The third reset sub-circuit comprises:

[0022] A third reset transistor, wherein a control electrode of the third reset transistor is connected to the second reset signal terminal, a first electrode of the third reset transistor is connected to the second reference voltage terminal, and a second electrode of the third reset transistor is connected to the third node.

[0023] Furthermore, the pixel circuit further includes:

[0024] a fourth reset sub-circuit, connected to the second reset signal terminal, the second initialization signal terminal, and the first electrode of the sub-pixel, and configured to control the second initialization signal terminal to be connected to or disconnected from the first electrode of the sub-pixel under the control of the second reset signal terminal;

[0025] The fourth reset sub-circuit includes:

[0026] A fourth reset transistor, wherein a control electrode of the fourth reset transistor is connected to the second reset signal terminal, a first electrode of the fourth reset transistor is connected to the second initialization signal terminal, and a second electrode of the fourth reset transistor is connected to the first electrode of the sub-pixel.

[0027] Furthermore, the data writing sub-circuit includes:

[0028] A data writing transistor, wherein a control electrode of the data writing transistor is connected to the third scanning signal terminal, a first electrode of the data writing transistor is connected to the data signal terminal, and a second electrode of the data writing transistor is connected to the second node.

[0029] Furthermore, the driving sub-circuit includes:

[0030] a driving transistor, wherein a control electrode of the driving transistor is connected to the first node, a first electrode of the driving transistor is connected to the third node, and a second electrode of the driving transistor is connected to the fourth node;

[0031] The compensation sub-circuit comprises:

[0032] A compensation transistor, wherein a control electrode of the compensation transistor is connected to the first scanning signal terminal, a first electrode of the compensation transistor is connected to the fourth node, and a second electrode of the compensation transistor is connected to the first node.

[0033] Furthermore, the light emitting control subcircuit includes:

[0034] a first light-emitting control transistor, wherein a control electrode of the first light-emitting control transistor is connected to the first light-emitting control signal terminal, a first electrode of the first light-emitting control transistor is connected to the first power supply terminal, and a second electrode of the first light-emitting control transistor is connected to the third node;

[0035] a second light-emitting control transistor, wherein the control electrode of the second light-emitting control transistor is connected to the second light-emitting control signal terminal, the first electrode of the second light-emitting control transistor is connected to the fourth node, and the second electrode of the second light-emitting control transistor is connected to the first electrode of the sub-pixel.

[0036] Furthermore, the data writing transistor, the first reset transistor, the second reset transistor and the compensation transistor are oxide thin film transistors, and the first light emission control transistor, the third reset transistor, the driving transistor, the second light emission control transistor and the fourth reset transistor are low-temperature polysilicon thin film transistors.

[0037] Furthermore, the pixel circuit is used in a display device, the display device includes a plurality of sub-pixels distributed in an array, the plurality of sub-pixels constitute a plurality of sub-pixel rows, the plurality of sub-pixel rows constitute one or more pixel groups, and one pixel group includes a plurality of sub-pixel rows;

[0038] A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same first scanning signal terminal; and / or

[0039] A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same second scanning signal terminal; and / or

[0040] A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same first reset signal terminal; and / or

[0041] A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same second reset signal terminal; and / or

[0042] A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same first light emitting control signal terminal; and / or

[0043] A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same second light emitting control signal terminal.

[0044] Furthermore, in one frame, the driving process of the pixel circuit includes a compensation phase, a data writing phase, and a display phase, wherein the compensation phase is before the data writing phase, and the display phase is after the data writing phase;

[0045] In a frame, for multiple sub-pixel rows in one of the pixel groups, the time interval between the start time of charging the second node by the data writing sub-circuit in the pixel circuit connected to the first sub-pixel row and the end time of the compensation phase is greater than the charging time of the second node by one of the data writing sub-circuit; and / or, in a frame, for multiple sub-pixel rows in one of the pixel groups, the time interval between the end time of charging the second node by the data writing sub-circuit in the pixel circuit connected to the last sub-pixel row and the start time of the display phase is greater than the charging time of the second node by one of the data writing sub-circuit.

[0046] According to one aspect of the present disclosure, a display device is provided, comprising the pixel circuit and a sub-pixel connected to the pixel circuit.

[0047] The display device and pixel circuit disclosed herein, during a driving process, causes the driving subcircuit to control the third node to be connected to the fourth node, causes the compensation subcircuit to control the first node to be connected to the fourth node, and causes the light-emitting control subcircuit to control the first power supply terminal to be connected to the third node. Thus, the first node can be charged through the first power supply terminal to compensate for the threshold voltage of the driving subcircuit, thereby solving the problem of poor display effect caused by different threshold voltages and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] FIG1 is a block diagram of a pixel circuit according to an embodiment of the present disclosure.

[0049] FIG. 2 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0050] FIG3( a ), FIG3 ( b ), and FIG3 ( c ) are operation timing diagrams of the pixel circuit shown in FIG2 .

[0051] FIG4 is a simulation diagram of a pixel circuit according to an embodiment of the present disclosure.

[0052] FIG5 is a schematic diagram of the arrangement of sub-pixels according to an embodiment of the present disclosure.

[0053] Explanation of Reference Numerals: 1, data writing subcircuit; 2, compensation subcircuit; 3, first reset subcircuit; 4, second reset subcircuit; 5, light-emitting control subcircuit; 6, driving subcircuit; 7, first storage subcircuit; 8, third reset subcircuit; 9, fourth reset subcircuit; 10, second storage subcircuit; 11, sub-pixel row; 12, sub-pixel column; EM1, first light-emitting control signal terminal; EM2, second light-emitting control signal terminal; Rst1, first reset signal terminal; Rst2, second reset signal terminal; Gate1, first scan signal terminal; Gate2, second scan signal terminal; Gate3, third scanning signal terminal; Init1, first initialization signal terminal; Init2, second initialization signal terminal; Ref1, first reference voltage terminal; Ref2, second reference voltage terminal; VDD, first power supply terminal; C1, first capacitor; C2, second capacitor; L0, sub-pixel; T1, data writing transistor; T2, compensation transistor; T3, driving transistor; T4, second light-emitting control transistor; T5, first light-emitting control transistor; T6, second reset transistor; T7, first reset transistor; T8, fourth reset transistor; T9, third reset transistor. DETAILED DESCRIPTION

[0054] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0055] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar words used in this disclosure and the claims do not indicate any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are for ease of description only and are not limited to a single position or spatial orientation. Terms such as "include" or "comprising" mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. When describing some embodiments, the terms "connected" and "connected" and their derivatives may be used. For example, the term "connected" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. For another example, the term "connected" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the term "connected" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0056] The transistors used in the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the control electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0057] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0058] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0059] An embodiment of the present disclosure provides a pixel circuit. The pixel circuit is used in a display device. As shown in Figure 5, the display device may include multiple sub-pixels L0 and multiple pixel circuits, and the multiple pixel circuits drive the multiple sub-pixels L0 to emit light in a one-to-one correspondence. The multiple sub-pixels L0 include multiple first sub-pixels, multiple second sub-pixels, and multiple third sub-pixels. The first sub-pixels, the second sub-pixels, and the third sub-pixels have different luminous colors. For example, the first sub-pixel emits red light, the second sub-pixel emits green light, and the third sub-pixel emits blue light. The above-mentioned multiple sub-pixels L0 can be distributed in an array and constitute multiple sub-pixel rows 11 and multiple sub-pixel columns 12. A sub-pixel row 11 includes multiple sub-pixels L0 distributed along the row direction, and a sub-pixel column 12 includes multiple sub-pixels L0 distributed along the column direction. Among them, a first sub-pixel, a second sub-pixel, and a third sub-pixel can constitute a pixel. The above-mentioned multiple sub-pixels L0 can form multiple pixels.

[0060] As shown in FIG1 , the pixel circuit may include a first storage subcircuit 7, a data writing subcircuit 1, a driving subcircuit 6, a compensation subcircuit 2, and a light emitting control subcircuit 5, wherein:

[0061] The first storage sub-circuit 7 is connected between the first node N1 and the second node N2. The data writing sub-circuit 1 is connected to the second node N2 and is used to charge the second node N2. The driving sub-circuit 6 is connected to the first node N1, the third node N3, and the fourth node N4, and is used to control the connection or disconnection between the third node N3 and the fourth node N4 under the control of the first node N1. The compensation sub-circuit 2 is connected to the first scan signal terminal Gate1, the first node N1, and the fourth node N4, and is used to control the connection or disconnection between the first node N1 and the fourth node N4 under the control of the first scan signal terminal Gate1. The light control sub-circuit 5 is connected to the first power supply terminal VDD, the first light control signal terminal EM1, the third node N3, the fourth node N4, the second light control signal terminal EM2, and the first electrode of the sub-pixel L0, and is used to control the connection or disconnection between the first power supply terminal VDD and the third node N3 under the control of the first light control signal terminal EM1, and is also used to control the connection or disconnection between the fourth node N4 and the first electrode of the sub-pixel L0 under the control of the second light control signal terminal EM2.

[0062] In the pixel circuit of the embodiment of the present disclosure, during the driving process, the driving sub-circuit 6 controls the third node N3 to be connected to the fourth node N4, the compensation sub-circuit 2 controls the first node N1 to be connected to the fourth node N4, and the light-emitting control sub-circuit 5 controls the first power supply terminal VDD to be connected to the third node N3, so that the first node N1 can be charged through the first power supply terminal VDD to compensate for the threshold voltage of the driving sub-circuit 6, thereby solving the problem of poor display effect caused by different threshold voltages; at the same time, the threshold voltage compensation disclosed in the present disclosure is not affected by the data signal writing time, and the compensation effect can be improved by increasing the compensation time.

[0063] The following describes in detail the various components of the pixel circuit according to the embodiment of the present disclosure:

[0064] As shown in Figures 1 and 2, the data write sub-circuit 1 is connected to the second node N2 and is used to charge the second node N2. Specifically, the data write sub-circuit 1 can be connected to the data signal terminal DATA, the third scan signal terminal Gate3 and the second node N2, and is used to control the data signal terminal DATA to be connected or disconnected from the second node N2 under the control of the third scan signal terminal Gate3. For example, the data write sub-circuit 1 may include a data write transistor T1. The control electrode of the data write transistor T1 is connected to the third scan signal terminal Gate3, the first electrode of the data write transistor T1 is connected to the data signal terminal DATA, and the second electrode of the data write transistor T1 is connected to the second node N2. The data write transistor T1 can be an oxide thin film transistor, and of course, it can also be a low-temperature polysilicon thin film transistor.

[0065] As shown in Figures 1 and 2, the first storage sub-circuit 7 is connected between a first node N1 and a second node N2. For example, the first storage sub-circuit 7 may include a first capacitor C1, a first electrode of the first capacitor C1 being connected to the first node N1, and a second electrode of the first capacitor C1 being connected to the second node N2.

[0066] As shown in Figures 1 and 2, the driver sub-circuit 6 is connected to a first node N1, a third node N3, and a fourth node N4, and is configured to control the connection or disconnection between the third node N3 and the fourth node N4 under the control of the first node N1. For example, the driver sub-circuit 6 may include a driver transistor T3. The control electrode of the driver transistor T3 is connected to the first node N1, the first electrode of the driver transistor T3 is connected to the third node N3, and the second electrode of the driver transistor T3 is connected to the fourth node N4. The driver transistor T3 may be an oxide thin-film transistor, or alternatively, a low-temperature polysilicon thin-film transistor.

[0067] As shown in Figures 1 and 2, the compensation sub-circuit 2 is connected to the first scan signal terminal Gate1, the first node N1, and the fourth node N4, and is used to control the connection or disconnection of the first node N1 and the fourth node N4 under the control of the first scan signal terminal Gate1. For example, the compensation sub-circuit 2 may include a compensation transistor T2. The control electrode of the compensation transistor T2 is connected to the first scan signal terminal Gate1, the first electrode of the compensation transistor T2 is connected to the fourth node N4, and the second electrode of the compensation transistor T2 is connected to the first node N1. The compensation transistor T2 may be an oxide thin film transistor, or of course, a low-temperature polysilicon thin film transistor. Among them, the multiple pixel circuits connected one-to-one with the multiple sub-pixels L0 located in a sub-pixel row 11 can be connected to the same first scan signal terminal Gate1, that is, the compensation sub-circuit 2 of the multiple pixel circuits connected one-to-one with the multiple sub-pixels L0 located in a sub-pixel row 11 can be connected to the same first scan signal terminal Gate1. The above-mentioned multiple sub-pixel rows 11 constitute one or more pixel groups. A pixel group may include multiple sub-pixel rows 11, for example, two sub-pixel rows 11, three sub-pixel rows 11, four sub-pixel rows 11, etc. The number of sub-pixel rows 11 in different pixel groups is the same. The multiple pixel circuits corresponding to the multiple sub-pixels L0 in a pixel group are connected to the same first scan signal terminal Gate1.

[0068] As shown in Figures 1 and 2, the light control subcircuit 5 is connected to a first power supply terminal VDD, a first light control signal terminal EM1, a third node N3, a fourth node N4, a second light control signal terminal EM2, and a first electrode of a sub-pixel L0. The subcircuit 5 is configured to control the connection or disconnection between the first power supply terminal VDD and the third node N3 under the control of the first light control signal terminal EM1, and to control the connection or disconnection between the fourth node N4 and the first electrode of the sub-pixel L0 under the control of the second light control signal terminal EM2. For example, the light control subcircuit 5 may include a first light control transistor T5 and a second light control transistor T4. The control electrode of the first light control transistor T5 is connected to the first light control signal terminal EM1, the first electrode of the first light control transistor T5 is connected to the first power supply terminal VDD, and the second electrode of the first light control transistor T5 is connected to the third node N3. The first light control transistor T5 may be an oxide thin-film transistor, or alternatively, a low-temperature polysilicon thin-film transistor. The control electrode of the second emission control transistor T4 is connected to the second emission control signal terminal EM2, the first electrode of the second emission control transistor T4 is connected to the fourth node N4, and the second electrode of the second emission control transistor T4 is connected to the first electrode of the sub-pixel L0. The second electrode of the sub-pixel L0 can be connected to the second power supply terminal VSS. The second emission control transistor T4 can be an oxide thin film transistor, or alternatively, a low-temperature polysilicon thin film transistor. Furthermore, the plurality of pixel circuits corresponding to the plurality of sub-pixels L0 in a pixel group are connected to the same first emission control signal terminal EM1. The plurality of pixel circuits corresponding to the plurality of sub-pixels L0 in a pixel group are connected to the same second emission control signal terminal EM2.

[0069] As shown in Figures 1 and 2, the pixel circuit of the present disclosure may further include a first reset subcircuit 3. The first reset subcircuit 3 may be connected to the second scan signal terminal Gate2, the first reference voltage terminal Ref1, and the second node N2, and is configured to control the connection or disconnection between the first reference voltage terminal Ref1 and the second node N2 under the control of the second scan signal terminal Gate2. For example, the first reset subcircuit 3 may include a first reset transistor T7. The control electrode of the first reset transistor T7 is connected to the second scan signal terminal Gate2, the first electrode of the first reset transistor T7 is connected to the first reference voltage terminal Ref1, and the second electrode of the first reset transistor T7 is connected to the second node N2. The first reset transistor T7 may be an oxide thin film transistor, or alternatively, a low-temperature polysilicon thin film transistor. As shown in FIG3(a), within a frame, the time interval during which the first reset sub-circuit 3 controls the connection between the first reference voltage terminal Ref1 and the second node N2 (the time interval during which the second scan signal terminal Gate2 is high in the figure) occurs before the data write sub-circuit 1 charges the second node N2. This arrangement ensures that the potential of the second node N2 is not affected by the data signal written to the second node N2 by the data signal terminal DATA in the previous frame during the data write phase t3 of the current frame. Furthermore, within a frame, the start time during which the first reset sub-circuit 3 controls the connection between the first reference voltage terminal Ref1 and the second node N2 (the time during which the second scan signal terminal Gate2 transitions from low to high in the figure) occurs before the start time during which the compensation sub-circuit 2 controls the connection between the first node N1 and the fourth node N4 (the time during which the first scan signal terminal Gate1 transitions from low to high in the figure). This arrangement ensures that the potential of the second node N2 is not affected by the data signal written to the second node N2 by the data signal terminal DATA in the previous frame during the compensation phase t2 of the current frame. In addition, a plurality of pixel circuits correspondingly connected to a plurality of sub-pixels L0 in a pixel group are connected to the same second scanning signal terminal Gate2.

[0070] As shown in Figures 1 and 2, the pixel circuit of the present disclosure may further include a second reset subcircuit 4. The second reset subcircuit 4 may be connected to the first reset signal terminal Rst1, the first initialization signal terminal Init1, and the first node N1, and is used to control the connection or disconnection of the first initialization signal terminal Init1 with the first node N1 under the control of the first reset signal terminal Rst1. For example, the second reset subcircuit 4 may include a second reset transistor T6. The control electrode of the second reset transistor T6 is connected to the first reset signal terminal Rst1, the first electrode of the second reset transistor T6 is connected to the first initialization signal terminal Init1, and the second electrode of the second reset transistor T6 is connected to the first node N1. The second reset transistor T6 may be an oxide thin film transistor, or of course, a low-temperature polysilicon thin film transistor. In addition, multiple pixel circuits corresponding to multiple sub-pixels L0 in a pixel group are connected to the same first reset signal terminal Rst1.

[0071] As shown in Figures 1 and 2, the pixel circuit of the present disclosure may further include a third reset subcircuit 8. The third reset subcircuit 8 may be connected to the second reset signal terminal Rst2, the second reference voltage terminal Ref2, and the third node N3, and is used to control the connection or disconnection of the second reference voltage terminal Ref2 and the third node N3 under the control of the second reset signal terminal Rst2. For example, the third reset subcircuit 8 may include a third reset transistor T9. The control electrode of the third reset transistor T9 is connected to the second reset signal terminal Rst2, the first electrode of the third reset transistor T9 is connected to the second reference voltage terminal Ref2, and the second electrode of the third reset transistor T9 is connected to the third node N3. The third reset transistor T9 may be an oxide thin film transistor, or of course, a low-temperature polysilicon thin film transistor. In addition, multiple pixel circuits corresponding to multiple sub-pixels L0 in a pixel group are connected to the same second reset signal terminal Rst2.

[0072] As shown in Figures 1 and 2, the pixel circuit of the present disclosure may further include a fourth reset subcircuit 9. The fourth reset subcircuit 9 may be connected to the second reset signal terminal Rst2, the second initialization signal terminal Init2, and the first electrode of the sub-pixel L0, and is used to control the connection or disconnection of the second initialization signal terminal Init2 and the first electrode of the sub-pixel L0 under the control of the second reset signal terminal Rst2. For example, the fourth reset subcircuit 9 may include a fourth reset transistor T8. The control electrode of the fourth reset transistor T8 is connected to the second reset signal terminal Rst2, the first electrode of the fourth reset transistor T8 is connected to the second initialization signal terminal Init2, and the second electrode of the fourth reset transistor T8 is connected to the first electrode of the sub-pixel L0. The third reset transistor T9 may be an oxide thin film transistor, or of course, a low-temperature polysilicon thin film transistor.

[0073] As shown in Figures 1 and 2, the pixel circuit of the present disclosure may further include a second storage sub-circuit 10. The second storage sub-circuit 10 is connected between the first power supply terminal VDD and the second node N2. For example, the second storage sub-circuit 10 may include a second capacitor C2, a first electrode of the second capacitor C2 being connected to the second node N2, and a second electrode of the second capacitor C2 being connected to the first power supply terminal VDD.

[0074] As shown in Figures 1, 2, and 3(a), in a frame, the driving process of the pixel circuit includes a compensation phase t2, a data writing phase t3, and a display phase t4. The compensation phase t2 precedes the data writing phase t3, and the display phase t4 follows the data writing phase t3. During the compensation phase t2, the light-emission control subcircuit 5 controls the first power supply terminal VDD to be connected to the third node N3, and the compensation subcircuit 2 controls the first node N1 to be connected to the fourth node N4. In other words, the first power supply terminal VDD is connected to the third node N3 via the first light-emission control transistor T5, and the first node N1 is connected to the fourth node N4 via the compensation transistor T2. During the data writing phase t3, the data writing subcircuit 1 charges the second node N2. In other words, the data signal terminal DATA is connected to the second node N2 via the data writing transistor T1. During display phase t4, the light-emission control subcircuit 5 controls the first power supply terminal VDD to be connected to the third node N3. The light-emission control subcircuit 5 also controls the fourth node N4 to be connected to the first electrode of the subpixel L0. That is, the first power supply terminal VDD is connected to the third node N3 via the first light-emission control transistor T5, and the fourth node N4 is connected to the first electrode of the subpixel L0 via the second light-emission control transistor T4. In a frame, for multiple subpixel rows 11 in a pixel group, the time interval between the start time of charging the second node N2 by the data-writing subcircuit 1 in the pixel circuit connected to the first subpixel row 11 and the end time of the compensation phase t2 is greater than the charging time of the second node N2 by the data-writing subcircuit 1. In a frame, for multiple subpixel rows 11 in a pixel group, the time interval between the end time of charging the second node N2 by the data-writing subcircuit 1 in the pixel circuit connected to the last subpixel row 11 and the start time of the display phase t4 is greater than the charging time of the second node N2 by the data-writing subcircuit 1.

[0075] In addition, as shown in FIG3( a ), in a frame, the driving process of the pixel circuit may further include an initialization phase t1, which precedes the compensation phase t2. During the initialization phase t1, the first reset sub-circuit 3 controls the first reference voltage terminal Ref1 to be connected to the second node N2, the second reset sub-circuit 4 controls the first initialization signal terminal Init1 to be connected to the first node N1, the third reset sub-circuit 8 controls the second reference voltage terminal Ref2 to be connected to the third node N3, and the fourth reset sub-circuit 9 controls the second initialization signal terminal Init2 to be connected to the first electrode of the sub-pixel L0. In other words, the first reference voltage terminal Ref1 is connected to the second node N2 via the first reset transistor T7, the first initialization signal terminal Init1 is connected to the first node N1 via the second reset transistor T6, the second reference voltage terminal Ref2 is connected to the third node N3 via the third reset transistor T9, and the second initialization signal terminal Init2 is connected to the first electrode of the sub-pixel L0 via the fourth reset transistor T8.

[0076] The multiple sub-pixel rows 11 of the above-mentioned display device may include the nth to mth sub-pixel rows 11, where n is greater than or equal to 1, m is greater than n, and m is less than or equal to the number of sub-pixel rows 11 in the display device. The nth to mth sub-pixel rows 11 may constitute the above-mentioned one pixel group. The nth to mth sub-pixel rows 11 may include the fth sub-pixel row 11 and the (f+1)th sub-pixel row 11, where f is greater than or equal to n, and (f+1) is less than or equal to m. The start time of charging the second node N2 by the data write sub-circuit 1 in the pixel circuit connected to the fth sub-pixel row 11 is before the start time of charging the second node N2 by the data write sub-circuit 1 in the pixel circuit connected to the (f+1)th sub-pixel row 11.

[0077] Taking the example of multiple pixel circuits corresponding to the multiple sub-pixels L0 in the nth to mth sub-pixel rows 11 being connected to the same first scanning signal terminal Gate1, the compensation stage t2 of the multiple pixel circuits corresponding to the multiple sub-pixels L0 in the nth to mth sub-pixel rows 11 is located after the start time of the light emitting control sub-circuit 5 in the pixel circuit connected to the mth sub-pixel row 11 controlling the first power supply terminal VDD to be connected to the third node N3, and is located before the start time of the data writing sub-circuit 1 in the pixel circuit connected to the nth sub-pixel row 11 charging the second node N2.

[0078] For example, in FIG3(c), taking the nth to mth sub-pixel rows 11 as an example of forming a pixel group, the multiple pixel circuits corresponding to the multiple sub-pixels L0 in the nth to mth sub-pixel rows 11 are connected to the same first scan signal terminal Gate1 (nth to mth), the multiple pixel circuits corresponding to the multiple sub-pixels L0 in the nth to mth sub-pixel rows 11 are connected to the same second scan signal terminal Gate2 (nth to mth), the multiple pixel circuits corresponding to the multiple sub-pixels L0 in the nth to mth sub-pixel rows 11 are connected to the same first reset signal terminal Rst1 (nth to mth), and the multiple pixel circuits corresponding to the multiple sub-pixels L0 in the nth to mth sub-pixel rows 11 are connected to the same first reset signal terminal Rst1 (nth to mth). Multiple pixel circuits connected to the same second reset signal terminal Rst2 (nth to mth), corresponding to the multiple sub-pixels L0 in the nth to mth sub-pixel rows 11, are connected to the same first light-emitting control signal terminal EM1 (nth to mth), and multiple pixel circuits connected to the multiple sub-pixels L0 in the nth to mth sub-pixel rows 11 are connected to the same second light-emitting control signal terminal EM2 (nth to mth). This configuration can reduce wiring and save layout area of ​​the gate drive circuit, which is equivalent to multiple sub-pixel rows 11 sharing a single-stage shift register, facilitating the realization of a narrow frame. At the same time, the frequency of the clock signal input to the gate drive circuit can be reduced, reducing the demand for the driver chip. The driver chip is used to provide the clock signal to the gate drive circuit. The pixel circuit connected to the nth sub-pixel row 11 is connected to the third scan signal terminal Gate3(n), the pixel circuit connected to the (n+1)th sub-pixel row 11 is connected to the third scan signal terminal Gate3(n+1), and the pixel circuit connected to the mth sub-pixel row 11 is connected to the third scan signal terminal Gate3(m). The compensation phase t2 of the multiple pixel circuits connected corresponding to the multiple sub-pixels L0 in the nth to mth sub-pixel rows 11 is located after the start time of the light-emitting control sub-circuit 5 in the pixel circuit connected to the mth sub-pixel row 11 controlling the first power supply terminal VDD to be connected to the third node N3, and is located before the start time of the data writing sub-circuit 1 in the pixel circuit connected to the nth sub-pixel row 11 charging the second node N2; the display phase t4 of the multiple pixel circuits connected corresponding to the multiple sub-pixels L0 in the nth to mth sub-pixel rows 11 is located after the cut-off time of the data writing sub-circuit 1 in the pixel circuit connected to the mth sub-pixel row 11 charging the second node N2, that is, the nth to mth sub-pixel rows 11 emit light uniformly.

[0079] In addition, in FIG3(c), the time interval ΔT1 between the start time of charging the second node N2 by the data writing sub-circuit 1 in the pixel circuit connected to the nth sub-pixel row 11 and the end time of the compensation phase t2 is greater than the charging time ΔT of the second node N2 by one data writing sub-circuit 1. The charging time ΔT is the time during which the third scanning signal terminal Gate3 is at an effective level. That is, within ΔT, the third scanning signal terminal Gate3 controls the data writing transistor T1 to turn on. In one frame, the time interval ΔT2 between the end time of charging the second node N2 by the data writing sub-circuit 1 in the pixel circuit connected to the mth sub-pixel row 11 and the start time of the display phase t4 is greater than the charging time ΔT of the second node N2 by one data writing sub-circuit 1. The above-mentioned ΔT1 and ΔT2 can be equal, or of course, can be different. Such an arrangement increases the above-mentioned time intervals ΔT1 and ΔT2, thereby reducing the proportion of the phase difference between any two third scanning signal terminals Gate3 to the total time of the data writing phase t3, making the display more uniform.

[0080] The operation process of the pixel circuit in Figure 2 is described in detail below in conjunction with the operation timing diagram of the pixel circuit shown in Figure 3(a), wherein the above-mentioned data writing transistor T1, the first reset transistor T7, the second reset transistor T6 and the compensation transistor T2 are N-type transistors, and the conduction level is a high level; the above-mentioned first light-emitting control transistor T5, the third reset transistor T9, the driving transistor T3, the second light-emitting control transistor T4 and the fourth reset transistor T8 are P-type transistors, and the conduction level is a low level.

[0081] As shown in Figures 2 and 3(a), during the initialization phase t1, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2, the first reset signal terminal Rst1, and the second scan signal terminal Gate2 are at a high level, the second reset signal terminal Rst2, the first scan signal terminal Gate1, and the third scan signal terminal Gate3 are at a low level, the first reset transistor T7, the second reset transistor T6, the fourth reset transistor T8, and the third reset transistor T9 are turned on; the first reference voltage terminal Ref1 is connected to the second node N2 to reset the second node N2; the first initialization signal terminal Init1 is connected to the first node N1 to reset the first node N1; the second initialization signal terminal Init2 is connected to the first electrode of the subpixel L0 to reset the first electrode of the subpixel L0; and the second reference voltage terminal Ref2 is connected to the third node N3 to reset the third node N3. Since the first node N1 and the second node N2 are both reset to the initial voltage, the first capacitor C1 and the second capacitor C2 are also initialized.

[0082] As shown in Figures 2 and 3(a), in the compensation stage t2, the first light-emitting control signal terminal EM1 and the first reset signal terminal Rst1 jump to a low level, the first scan signal terminal Gate1 and the second reset signal terminal Rst2 jump to a high level, the second light-emitting control signal terminal EM2 and the second scan signal terminal Gate2 remain at a high level, the third scan signal terminal Gate3 remains at a low level, the second reset transistor T6, the fourth reset transistor T8 and the third reset transistor T9 are turned off, and the first reset transistor T7 remains on for stabilizing the voltage of the second node N2 (the voltage is written as Vref1 by the first reference voltage terminal Ref1); the first light-emitting control transistor T5 is turned on, the driving transistor T3 is turned on (in the initialization stage t1, the potential of the first initialization signal terminal Init1 is set to turn on the driving transistor T3), the compensation transistor T2 is turned on, the first power supply terminal VDD is connected to the first node N1, and when the voltage at the first node N1 is written as [VDD+Vth(T3)], the driving transistor T3 is turned off.

[0083] As shown in Figures 2 and 3(a), in the data writing phase t3, the first scanning signal terminal Gate1 and the second scanning signal terminal Gate2 successively jump to a low level, and the third scanning signal terminal Gate3 jumps to a high level. The data writing transistor T1 is turned on, the data signal terminal DATA is connected to the second node N2, and the voltage of the second node N2 is written to Vdata by the data signal terminal DATA. Under the coupling effect of the first capacitor C1, the voltage of the first node N1 changes by (Vdata-Vref1)*a, where a is related to the ratio of the first capacitor C1 to the second capacitor C2. At this time, the voltage of the first node N1 is [VDD+Vth(T3)+(Vdata-Vref1)*a]. It can be seen that the compensation phase t2 of the present disclosure is performed separately from the data writing phase t3. The compensation phase t2 is not affected by the writing time of the data signal terminal DATA. The compensation effect can be improved by increasing the duration of the compensation phase t2.

[0084] As shown in Figures 2 and 3(a), in display phase t4, the third scanning signal terminal Gate3 and the second emission control signal terminal EM2 jump to a low level, turning on the driving transistor T3, the second emission control transistor T4, and the first emission control transistor T5, and causing the sub-pixel L0 to emit light. The emission current formula is: I = 1 / 2*μ*Cox*W / L*(Vgs-Vth)^2 = 1 / 2*μ*Cox*W / L*[(Vdata-Vref1)*a]^2, where μ is the electron mobility, Cox is the gate oxide capacitance, Vgs is the voltage difference between the control electrode and the first electrode of the driving transistor T3, and W / L is the width-to-length ratio of the channel region of the driving transistor T3. It can be seen that the emission formula does not contain the Vth(T3) factor, which means that the pixel circuit can compensate for the threshold voltage of the driving transistor T3 to achieve better display uniformity. Figure 4 is a simulation schematic diagram of the pixel circuit.

[0085] Compared with FIG3( a ), the difference between the pixel circuit in FIG2 and the pixel circuit operating according to the timing diagram shown in FIG3( b ) is that: in the display stage t4 , pulse width modulation (PWM) is used for dimming. Specifically, the light-emitting time of the sub-pixel L0 is controlled by controlling the potential of the first light-emitting control signal terminal EM1, thereby controlling the light-emitting brightness of the sub-pixel L0.

[0086] Compared with Figure 3(a), the difference between the pixel circuit in Figure 2 working according to the timing diagram shown in Figure 3(c) is that: in the data writing phase t3, multiple third scanning signal terminals Gate3 [Gate3(n), Gate3(n+1)…Gate3(m)] jump to a high level in turn, and the second nodes N2 of the pixel circuits connected to different sub-pixel rows 11 are written as Vdata in turn.

[0087] The present disclosure also provides a method for driving a pixel circuit, for driving the pixel circuit of the above-mentioned embodiment. The method for driving the pixel circuit may include: causing the data writing subcircuit 1 to charge the second node N2; causing the driving subcircuit 6 to control the connection or disconnection of the third node N3 and the fourth node N4 under the control of the first node N1; causing the compensation subcircuit 2 to control the connection or disconnection of the first node N1 and the fourth node N4 under the control of the first scanning signal terminal Gate1; causing the light-emitting control subcircuit 5 to control the connection or disconnection of the first power supply terminal VDD and the third node N3 under the control of the first light-emitting control signal terminal EM1, and causing the light-emitting control subcircuit 5 to control the connection or disconnection of the fourth node N4 and the first electrode of the sub-pixel L0 under the control of the second light-emitting control signal terminal EM2. Since the pixel circuit driven by the driving method of the present disclosure is the same as the pixel circuit in the above-mentioned embodiment, it has the same beneficial effects and will not be described in detail here.

[0088] The present disclosure also provides a display device. The display device may include any of the aforementioned pixel circuits and sub-pixels connected to the pixel circuit. The display device may be any product or component with a display function, such as a portable phone, a smartphone, a video phone, a smart tablet, a smartwatch, a tablet personal computer, a vehicle navigation system, a television, a computer monitor, a notebook computer, a head-mounted display, or the like. Since the pixel circuit in the display device of the present disclosure is the same as the pixel circuit in the aforementioned embodiment, it has the same beneficial effects and will not be further described here.

[0089] The above is merely a preferred embodiment of the present disclosure and does not constitute any form of limitation to the present disclosure. Although the present disclosure has been disclosed as a preferred embodiment as above, it is not intended to limit the present disclosure. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A pixel circuit, characterized in that: include: A first storage subcircuit connected between the first node and the second node; a data writing subcircuit, connected to the second node, and used to charge the second node; a driving subcircuit connected to the first node, the third node and the fourth node, and configured to control the third node to be connected to or disconnected from the fourth node under the control of the first node; a compensation subcircuit connected to the first scan signal terminal, the first node and the fourth node, and configured to control the first node to be connected or disconnected with the fourth node under the control of the first scan signal terminal; The light-emitting control subcircuit is connected to the first power supply terminal, the first light-emitting control signal terminal, the third node, the fourth node, the second light-emitting control signal terminal and the first pole of the sub-pixel, and is used to control the first power supply terminal to be connected or disconnected with the third node under the control of the first light-emitting control signal terminal, and is also used to control the fourth node to be connected or disconnected with the first pole of the sub-pixel under the control of the second light-emitting control signal terminal.

2. The pixel circuit according to claim 1, characterized in that: The pixel circuit further includes: The first reset subcircuit is connected to the second scan signal terminal, the first reference voltage terminal and the second node, and is used for controlling the first reference voltage terminal to be connected or disconnected with the second node under the control of the second scan signal terminal.

3. The pixel circuit according to claim 2, characterized in that: The first reset sub-circuit comprises: A first reset transistor, wherein a control electrode of the first reset transistor is connected to the second scanning signal terminal, a first electrode of the first reset transistor is connected to the first reference voltage terminal, and a second electrode of the first reset transistor is connected to the second node.

4. The pixel circuit according to claim 2 or 3, characterized in that: In one frame, a start time when the first reset sub-circuit controls the first reference voltage terminal to be connected to the second node is before a start time when the compensation sub-circuit controls the first node to be connected to the fourth node.

5. The pixel circuit according to claim 2 or 3, characterized in that: The pixel circuit further includes: A second reset subcircuit is connected to the first reset signal terminal, the first initialization signal terminal and the first node, and is used to control the first initialization signal terminal to be connected or disconnected from the first node under the control of the first reset signal terminal; and / or The third reset subcircuit is connected to the second reset signal terminal, the second reference voltage terminal and the third node, and is used to control the second reference voltage terminal to be connected or disconnected with the third node under the control of the second reset signal terminal.

6. The pixel circuit according to claim 5, characterized in that: The second reset sub-circuit comprises: a second reset transistor, wherein a control electrode of the second reset transistor is connected to the first reset signal terminal, a first electrode of the second reset transistor is connected to the first initialization signal terminal, and a second electrode of the second reset transistor is connected to the first node; The third reset sub-circuit comprises: A third reset transistor, wherein a control electrode of the third reset transistor is connected to the second reset signal terminal, a first electrode of the third reset transistor is connected to the second reference voltage terminal, and a second electrode of the third reset transistor is connected to the third node.

7. The pixel circuit according to claim 1 or 6, characterized in that: The pixel circuit further includes: a fourth reset subcircuit connected to the second reset signal terminal, the second initialization signal terminal and the first electrode of the subpixel, and configured to control the second initialization signal terminal to be connected or disconnected from the first electrode of the subpixel under the control of the second reset signal terminal; The fourth reset sub-circuit comprises: A fourth reset transistor, wherein a control electrode of the fourth reset transistor is connected to the second reset signal terminal, a first electrode of the fourth reset transistor is connected to the second initialization signal terminal, and a second electrode of the fourth reset transistor is connected to the first electrode of the sub-pixel.

8. The pixel circuit according to claim 7, characterized in that: The data writing sub-circuit comprises: A data writing transistor, wherein a control electrode of the data writing transistor is connected to the third scanning signal terminal, a first electrode of the data writing transistor is connected to the data signal terminal, and a second electrode of the data writing transistor is connected to the second node.

9. The pixel circuit according to claim 8, characterized in that: The driving subcircuit comprises: a driving transistor, wherein a control electrode of the driving transistor is connected to the first node, a first electrode of the driving transistor is connected to the third node, and a second electrode of the driving transistor is connected to the fourth node; The compensation subcircuit comprises: A compensation transistor, wherein a control electrode of the compensation transistor is connected to the first scanning signal terminal, a first electrode of the compensation transistor is connected to the fourth node, and a second electrode of the compensation transistor is connected to the first node.

10. The pixel circuit according to claim 9, characterized in that: The light emitting control subcircuit comprises: a first light emission control transistor, wherein a control electrode of the first light emission control transistor is connected to the first light emission control signal terminal, a first electrode of the first light emission control transistor is connected to the first power supply terminal, and a second electrode of the first light emission control transistor is connected to the third node; A second light emitting control transistor, wherein the control electrode of the second light emitting control transistor is connected to the second light emitting control signal terminal, the first electrode of the second light emitting control transistor is connected to the fourth node, and the second electrode of the second light emitting control transistor is connected to the first electrode of the sub-pixel.

11. The pixel circuit according to claim 10, characterized in that: The data writing transistor, the first reset transistor, the second reset transistor and the compensation transistor are oxide thin film transistors, and the first light emission control transistor, the third reset transistor, the driving transistor, the second light emission control transistor and the fourth reset transistor are low temperature polysilicon thin film transistors.

12. The pixel circuit according to claim 5, characterized in that: The pixel circuit is used for a display device, wherein the display device comprises a plurality of sub-pixels distributed in an array, wherein the plurality of sub-pixels constitute a plurality of sub-pixel rows, wherein the plurality of sub-pixel rows constitute one or more pixel groups, and the pixel group comprises a plurality of sub-pixel rows; A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same first scanning signal terminal; and / or A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same second scanning signal terminal; and / or A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same first reset signal terminal; and / or A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same second reset signal terminal; and / or A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same first light emitting control signal terminal; and / or A plurality of pixel circuits corresponding to a plurality of sub-pixels in one pixel group are connected to the same second light emitting control signal terminal.

13. The pixel circuit according to claim 12, characterized in that: In one frame, the driving process of the pixel circuit includes a compensation phase, a data writing phase and a display phase, wherein the compensation phase is before the data writing phase and the display phase is after the data writing phase; In one frame, for a plurality of sub-pixel rows in one pixel group, a time interval between a start time when a data writing sub-circuit in the pixel circuit connected to a first sub-pixel row charges the second node and a cut-off time of the compensation phase is greater than a charging time length of one data writing sub-circuit for the second node; And / or, in one frame, for a plurality of sub-pixel rows in one of the pixel groups, the time interval between the cutoff time for charging the second node by a data writing sub-circuit in the pixel circuit connected to the last sub-pixel row and the start time of the display phase is greater than the charging time of the second node by one of the data writing sub-circuits.

14. A display device, characterized in that: The invention comprises the pixel circuit according to any one of claims 1 to 13 and a sub-pixel connected to the pixel circuit.

Images