Method and system for testing xmii interface of Ethernet PHY chip

Abstract

The invention discloses a method and system for testing an xmii interface of an Ethernet PHY chip, and the method comprises the following steps: configuring the test item content of a to-be-tested chip, the item content comprising an environment temperature, a test voltage, a chip mode, a chip number and a chip type; a chip to be tested is placed in the test socket, and the temperature control table is pressed down; raising the temperature of the temperature control table to the configured environment temperature; controlling the chip to be tested to the configured test voltage; controlling the chip to be tested to a configured chip mode; controlling the oscilloscope, testing the waveform in the specified chip mode, and obtaining waveform data; and generating a test report according to the test item content of the to-be-tested chip and the waveform data of the oscilloscope. According to the invention, the test efficiency is improved, the human input cost is reduced, and the test range is expanded.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a method and system for testing an Ethernet PHY chip xmii interface. Background Art

[0002] When the chip needs to test the Ethernet PHY chip xmii interface, especially before mass production, it is necessary to first conduct a small batch test on some performance of the chip xmii interface in order to find potential problems, ensure the chip stability before mass production, and ensure the quality of the chip.

[0003] Currently, the chip xmii interface test is done manually, which is inefficient, takes up a lot of manpower, and the test cannot cover all aspects, resulting in failure to meet demand. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a method and system for testing the xmii interface of an Ethernet PHY chip, which improves test efficiency, reduces manpower input costs, and expands the scope of testing.

[0005] The present invention is achieved through the following technical solutions:

[0006] A method for testing an Ethernet PHY chip xmii interface comprises the following steps:

[0007] Configure the test item content of the chip to be tested, the item content includes ambient temperature, test voltage, chip mode, chip number and chip type;

[0008] Place the chip to be tested in the test socket and press down the temperature control table;

[0009] Raise the temperature of the temperature control table to the configured ambient temperature;

[0010] Control the chip under test to the configured test voltage;

[0011] Control the chip under test to the configured chip mode;

[0012] Control the oscilloscope, test the waveform under the specified chip mode, and obtain the waveform data;

[0013] Generate a test report based on the test item content of the chip to be tested and the waveform data of the oscilloscope.

[0014] Further, the method for testing the Ethernet PHY chip xmii interface also includes the following steps:

[0015] Build the test environment, connect the xmii interface of the chip to be tested to the oscilloscope, and connect the test PC, oscilloscope and temperature control station to the same network segment.

[0016] Furthermore, the step of raising the temperature of the temperature control table to the configured ambient temperature specifically includes:

[0017] The temperature control module receives the configuration requirements of the ambient temperature and controls the temperature control station to rise to the specified ambient temperature.

[0018] Furthermore, the step of controlling the chip under test to a configured test voltage specifically includes:

[0019] The PHY chip configuration module receives the configuration requirement of the test voltage, and enables the test socket to reach the specified test voltage through register configuration or by controlling the external power supply.

[0020] Furthermore, the step of controlling the chip to be tested to the configured chip mode specifically includes:

[0021] The PHY chip configuration module receives the configuration requirement of the chip mode, and configures the corresponding chip mode through the register so that the test socket meets the specified chip mode.

[0022] Furthermore, the step of controlling the oscilloscope to test the waveform under the specified chip mode and obtain waveform data specifically includes:

[0023] The oscilloscope control module controls the oscilloscope to perform corresponding waveform configuration according to the configuration requirements of the chip mode, and automatically saves the image and records the obtained test waveform data after completing the waveform measurement.

[0024] Further, the step of generating a test report according to the test item content of the chip to be tested and the waveform data of the oscilloscope specifically includes:

[0025] The report generation module receives the test item content of the chip to be tested and the waveform data of the oscilloscope, and generates a test report according to the test item content of the chip to be tested and the waveform data of the oscilloscope.

[0026] Furthermore, the chip modes include mii, rmii1, rmii2 and rgmii.

[0027] A system for testing an Ethernet PHY chip xmii interface, comprising a test PC, a temperature control station, a test socket for mounting a chip to be tested, and an oscilloscope connected to the test socket, wherein the test PC comprises:

[0028] User operation interface, used to configure the test items of the chip to be tested;

[0029] The execution unit is connected to the user operation interface, the temperature control table, the test socket and the oscilloscope at the same time and is used to execute the test item content configured by the user operation interface.

[0030] Furthermore, the execution unit includes:

[0031] A temperature control module connected to the temperature control station is used to control the temperature control station to rise to a specified ambient temperature;

[0032] A PHY chip configuration module is connected to the test socket and is used to configure the test socket to reach a specified test voltage through register configuration or by controlling an external power supply / configure a corresponding chip mode through registers so that the test socket meets the specified chip mode;

[0033] An oscilloscope control module, connected to the oscilloscope, is used to control the oscilloscope to perform corresponding waveform configuration, automatically save the image after completing the waveform measurement, and record the obtained test waveform data;

[0034] The report generation module is used to generate a test report based on the test item content of the chip to be tested and the waveform data of the oscilloscope.

[0035] Compared with the prior art, the advantages of the present invention are:

[0036] The present invention designs an automated software for the Ethernet PHY chip XMII interface. During the test process, there is no need to manually debug an oscilloscope, configure a chip, or record a test result. Only an environment needs to be built and a test script needs to be run. The test of the chip XMII interface is completed through the control of the software. The software is used to automatically control the chip function, the oscilloscope measurement, and the temperature control console to complete the relevant tests on the PHY chip XMII interface and automatically generate a test report, thereby reducing the manpower input cost, improving the test efficiency, expanding the test scope, and reducing the possibility of manual operation errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A block diagram of a system for testing an Ethernet PHY chip xmii interface;

[0038] Figure 2 A flowchart of a method for testing an Ethernet PHY chip xmii interface;

[0039] Figure 3 A class diagram of a system for testing the xmii interface of an Ethernet PHY chip.

[0040] 1. Test PC; 10. User operation interface; 11. Execution unit; 110. Temperature control module; 111. PHY chip configuration module; 112. Oscilloscope control module; 113. Report generation module; 2. Temperature control station; 3. Test socket; 4. Oscilloscope. DETAILED DESCRIPTION

[0041] The following is a further non-restrictive detailed description of the technical solution of the invention in conjunction with the preferred embodiments and the accompanying drawings. In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings. In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and cannot be understood as limitations on the present invention.

[0042] like Figure 1 As shown, a system for testing the xmii interface of an Ethernet PHY chip includes a test PC 1, a temperature control station 2, a test socket 3 for installing a chip to be tested, and an oscilloscope 4 connected to the test socket 3. The temperature control station 2, the test socket 3 and the oscilloscope 4 are all connected to the test PC 1.

[0043] The test PC 1 includes a user operation interface 10 and an execution unit 11, wherein the user operation interface 10 is used to configure the test item content of the chip to be tested, and the execution unit 11 is connected to the user operation interface 10, the temperature control table 2, the test socket 3 and the oscilloscope 4 at the same time to execute the test item content configured by the user operation interface 10.

[0044] The execution unit 11 includes a temperature control module 110, a PHY chip configuration module 111, an oscilloscope control module 112 and a report generation module 113. The temperature control module 110 is connected to the temperature control station 2 to control the temperature control station 2 to rise to a specified ambient temperature. The PHY chip configuration module 111 is connected to the test socket 3 to configure the test socket to reach a specified test voltage through register configuration or by controlling an external power supply / configure the corresponding chip mode through registers so that the test socket 3 meets the specified chip mode. The oscilloscope control module 112 is connected to the oscilloscope 4 to control the oscilloscope 4 to perform corresponding waveform weighting, and automatically save the image and record the obtained test waveform data after completing the waveform measurement; the report generation module 113 is used to generate a test report according to the test item content of the chip to be tested and the waveform data of the oscilloscope.

[0045] like Figure 2As shown, a method for testing an Ethernet PHY chip xmii interface according to an embodiment of the present invention comprises the following steps:

[0046] S1: Build a test environment, connect the xmii interface of the chip to be tested to the oscilloscope 4, and connect the test PC 1, oscilloscope 4 and temperature control station 2 to the same network segment.

[0047] S2: Configure the test items of the chip to be tested, including ambient temperature, test voltage, chip mode, chip number and chip type.

[0048] The ambient temperature includes high temperature, normal temperature and low temperature. In this embodiment, the high temperature is 150°, the normal temperature is 25° and the low temperature is -50°. Other temperature values ​​may be added according to chip testing requirements.

[0049] In this embodiment, the test voltages include 3.3V and 2.7V, and other voltage values ​​may also be added according to chip test requirements.

[0050] In this embodiment, there are 4 chip modes including mii, rmii1, rmii2 and rgmii.

[0051] The chip number is Arabic numerals 1-10 for easy reporting and registration.

[0052] Chip types include FF, SS, FS and SF.

[0053] S3: Place the chip to be tested in the test socket 3 and press down the temperature control platform 2.

[0054] S4: Raise the temperature of the temperature control station 2 to the configured ambient temperature.

[0055] Specifically, the temperature control module 110 receives the configuration requirement of the ambient temperature and controls the temperature control station 2 to rise to the specified ambient temperature.

[0056] S5: Control the chip under test to the configured test voltage.

[0057] Specifically, the PHY chip configuration module 111 receives the configuration requirement of the test voltage, and enables the test socket 3 to reach the specified test voltage through register configuration or by controlling the external power supply.

[0058] S6: Control the chip under test to the configured chip mode.

[0059] Specifically, the PHY chip configuration module 111 receives the configuration requirement of the chip mode, and configures the corresponding chip mode through the register so that the test socket 3 meets the specified chip mode.

[0060] S7: Control the oscilloscope 4 to test the waveform under the specified chip mode and obtain waveform data.

[0061] Specifically, the oscilloscope control module 112 controls the oscilloscope 4 to perform corresponding waveform configuration according to the configuration requirements of the chip mode, and automatically saves the image and records the obtained test waveform data after completing the waveform measurement.

[0062] S8: Generate a test report according to the test item content of the chip to be tested and the waveform data of the oscilloscope 4.

[0063] Specifically, the report generation module 113 receives the test item content of the chip under test and the waveform data of the oscilloscope 4, and generates a test report according to the test item content of the chip under test and the waveform data of the oscilloscope 4. The test report is in the form of Excel and can be printed out by a printer.

[0064] During the test, the ambient temperature, chip mode, chip number and chip type are configured on the user operation interface 10; then the temperature of the temperature control platform 2 is raised to the configured ambient temperature, and then the chip to be tested is placed in the test socket 3 and the temperature control platform 2 is pressed down. After waiting for 10 seconds, the test voltage is configured through the PHY chip configuration module 111, and the oscilloscope control module 112 controls the oscilloscope 4 to perform corresponding waveform configuration. The oscilloscope displays the test results. The report generation module 113 receives the test item content of the chip to be tested and the waveform data of the oscilloscope 4 to generate a final test report, thereby completing the test of a chip.

[0065] like Figure 3 As shown, Si is the entry file of this test script. Si inherits three classes: measuresi, siTkinter and report. The three classes are: measuresi class: controls the oscilloscope by relying on the keysightMSOx4154 class. The keysightMSOx4154 class is the control API program of the specific oscilloscope. The measuresi class specifies the configurations that need to be tested. For example, the function mesure_mii_rxdv_setup_and_hold() is used to control the setup and hold of rxdv in the mii mode; siTkinter class: used to generate a gui interface; report class: generates a test report.

[0066] At the same time, si also relies on the MAX_TC_MDSocket class, power_supply_2231a class, AWG_AFG1062 class, and power_supply_E3631A class, which are respectively the temperature control console to control the ambient temperature of the chip, the 2231a power supply, the AFG1062 signal generator, and the E3631A power supply.

[0067] The present invention designs an automated software for the Ethernet PHY chip XMII interface. During the test process, there is no need to manually debug an oscilloscope, configure a chip, or record a test result. Only an environment needs to be built and a test script needs to be run. The test of the chip XMII interface is completed through the control of the software. The software is used to automatically control the chip function, the oscilloscope measurement, and the temperature control console to complete the relevant tests on the PHY chip XMII interface and automatically generate a test report, thereby reducing the manpower input cost, improving the test efficiency, expanding the test scope, and reducing the possibility of manual operation errors.

[0068] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for testing an Ethernet PHY chip xmii interface, characterized in that: The following steps are involved: Configure the test item content of the chip to be tested, the item content includes ambient temperature, test voltage, chip mode, chip number and chip type; Place the chip to be tested in the test socket (3) and press down the temperature control platform (2); Raise the temperature of the temperature control table (2) to the configured ambient temperature; Control the chip under test to the configured test voltage; Control the chip under test to the configured chip mode; Controlling the oscilloscope (4) to test the waveform under the specified chip mode and obtain waveform data; A test report is generated according to the test item content of the chip to be tested and the waveform data of the oscilloscope (4).

2. The method for testing the Ethernet PHY chip xmii interface according to claim 1, characterized in that: The method for testing the Ethernet PHY chip xmii interface also includes the following steps: A test environment is set up, the xmii interface of the chip to be tested is connected to an oscilloscope (4), and the test PC (1), the oscilloscope (4) and the temperature control station (2) are all connected to a network in the same network segment.

3. The method for testing the Ethernet PHY chip xmii interface according to claim 1, characterized in that: The step of raising the temperature of the temperature control platform (2) to the configured ambient temperature specifically comprises: The temperature control module (110) receives the configuration requirement of the ambient temperature and controls the temperature control platform (2) to rise to the specified ambient temperature.

4. The method for testing the Ethernet PHY chip xmii interface according to claim 1, characterized in that: The step of controlling the chip under test to a configured test voltage specifically includes: The PHY chip configuration module (111) receives a configuration request for a test voltage, and enables the test socket (3) to reach a specified test voltage through register configuration or by controlling an external power supply.

5. The method for testing the Ethernet PHY chip xmii interface according to claim 1, characterized in that: The step of controlling the chip to be tested to the configured chip mode specifically includes: The PHY chip configuration module (111) receives the configuration requirement of the chip mode, and configures the corresponding chip mode through the register so that the test socket (3) meets the specified chip mode.

6. The method for testing the Ethernet PHY chip xmii interface according to claim 1, characterized in that: The step of controlling the oscilloscope (4) to test the waveform under the specified chip mode and obtain waveform data specifically includes: The oscilloscope control module (112) controls the oscilloscope (4) to perform corresponding waveform configuration according to the configuration requirements of the chip mode, and automatically saves the image and records the obtained test waveform data after completing the waveform measurement.

7. The method for testing the Ethernet PHY chip xmii interface according to claim 1, characterized in that: The step of generating a test report according to the test item content of the chip to be tested and the waveform data of the oscilloscope (4) specifically includes: The report generation module (113) receives the test item content of the chip to be tested and the waveform data of the oscilloscope (4), and generates a test report according to the test item content of the chip to be tested and the waveform data of the oscilloscope (4).

8. The method for testing the Ethernet PHY chip xmii interface according to claim 1, characterized in that: The chip modes include mii, rmii1, rmii2 and rgmii.

9. A system for testing an Ethernet PHY chip xmii interface, characterized in that: The invention comprises a test PC (1), a temperature control platform (2), a test socket (3) for mounting a chip to be tested, and an oscilloscope (4) connected to the test socket (3), wherein the test PC (1) comprises: A user operation interface (10) is used to configure the test items of the chip to be tested; The execution unit (11) is connected to the user operation interface (10), the temperature control table (2), the test socket (3) and the oscilloscope (4) for executing the test item content configured by the user operation interface (10).

10. The system for testing the Ethernet PHY chip xmii interface according to claim 9, characterized in that: The execution unit (11) comprises: A temperature control module (110) connected to the temperature control platform (2) and used to control the temperature control platform (2) to rise to a specified ambient temperature; A PHY chip configuration module (111) is connected to the test socket (3) and is used to configure the test socket to reach a specified test voltage through register configuration or by controlling an external power supply / configure a corresponding chip mode through register configuration so that the test socket (3) meets the specified chip mode; An oscilloscope control module (112) is connected to the oscilloscope (4) and is used to control the oscilloscope (4) to perform corresponding waveform configuration, automatically save the image after completing the waveform measurement, and record the obtained test waveform data; The report generation module (113) is used to generate a test report according to the test item content of the chip to be tested and the waveform data of the oscilloscope.

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