Exposure apparatus, exposure method, and semiconductor device manufacturing method

Abstract

Provided are an exposure apparatus, an exposure method, and a method of manufacturing a semiconductor device that improve the yield of a semiconductor device. The exposure apparatus includes a stage that holds a substrate and a control device. The control device performs function approximation on measurement results of three or more alignment marks arranged on a substrate in an orthogonal coordinate system during exposure processing to calculate a calculation value of a magnification component, and sets a first lower limit value and / or a first upper limit value for an alignment correction value of the magnification component. When the calculated value is equal to or greater than a first lower limit value and / or equal to or less than a first upper limit value, the alignment correction value of the magnification component is set as a first correction value, and when the first lower limit value is set and the calculated value is less than the first lower limit value, the alignment correction value of the magnification component is set as a second correction value that is greater than the calculated value and smaller than the first correction value. When the first upper limit value is set and the calculated value exceeds the first upper limit value, the alignment correction value of the magnification component is set to a third correction value that is larger than the first correction value and smaller than the calculated value.

Description

Technical Field

[0001] Embodiments relate to an exposure apparatus, an exposure method, and a method for manufacturing a semiconductor device. Background Art

[0002] A three-dimensional lamination technique for laminating semiconductor circuit boards in three dimensions is known.

[0003] Prior art literature:

[0004] Patent Literature:

[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-158200 Summary of the invention

[0006] Problems to be solved by the invention:

[0007] Improve the yield of semiconductor devices.

[0008] Means used to solve the problem:

[0009] The exposure device of the embodiment includes a workbench and a control device. The workbench is configured to be able to hold a substrate. The control device performs exposure processing on the substrate. During the exposure processing, the control device performs function approximation on the measurement results of more than three alignment marks arranged on the substrate in an orthogonal coordinate system to calculate the calculated value of the magnification component, sets a first lower limit value and / or a first upper limit value for the alignment correction value of the magnification component, and sets the alignment correction value of the magnification component to the first correction value when the calculated value is above the first lower limit value and / or below the first upper limit value. When the first lower limit value is set and the calculated value is less than the first lower limit value, the alignment correction value of the magnification component is set to a second correction value that is larger than the calculated value and smaller than the first correction value. When the first upper limit value is set and the calculated value exceeds the first upper limit value, the alignment correction value of the magnification component is set to a third correction value that is larger than the first correction value and smaller than the calculated value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a schematic diagram showing an outline of a method for manufacturing a semiconductor device.

[0011] Figure 2 This is a schematic diagram showing an example of the arrangement of alignment marks used in a manufacturing process of a semiconductor device.

[0012] Figure 3 This is a table showing an example of the correction performance of the exposure apparatus and the bonding apparatus with respect to the overlapped components on the wafer surface that may remain in the bonding overlay.

[0013] Figure 4 This is a block diagram showing an example of the configuration of the exposure apparatus according to the first embodiment.

[0014] Figure 5 This is a flowchart showing an example of an exposure method of the exposure apparatus according to the first embodiment.

[0015] Figure 6 This is a schematic diagram showing an example of a superimposition result related to the exposure process of the exposure apparatus related to the first embodiment.

[0016] Figure 7 This is a table showing an example of alignment correction values ​​of wafer magnification components involved in the exposure process of the exposure apparatus involved in the first embodiment.

[0017] Figure 8 This is a scattergram showing an example of distribution of wafer magnification components after the exposure process by the exposure apparatus according to the first embodiment.

[0018] Fig. 9 This is a flowchart showing an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0019] Fig.10 This is a box plot showing an example of changes in distribution of wafer factor components in the method for manufacturing a semiconductor device according to the second embodiment.

[0020] Fig.11 This is a flowchart showing an example of an exposure method of the exposure apparatus according to the third embodiment.

[0021] Fig.12 It is a schematic diagram showing an example of a superimposition result related to the exposure process of the exposure apparatus involved in the third embodiment.

[0022] Fig.13 This is a flowchart showing an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0023] Fig.14 This is a box plot showing an example of changes in distribution of wafer rate components in the method for manufacturing a semiconductor device according to the third embodiment.

[0024] Fig.15 This is a block diagram showing an example of the overall configuration of a memory device according to the fourth embodiment.

[0025] Fig.16 This is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a memory device according to a fourth embodiment.

[0026] Fig.17 It is a perspective view showing an example of the structure of the memory device involved in the fourth embodiment.

[0027] Fig.18 It is a plan view showing an example of a plan layout of a memory cell array included in the memory device according to the fourth embodiment.

[0028] Fig.19 It is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array included in the memory device according to the fourth embodiment.

[0029] Fig. 20 FIG. 1 is a diagram showing an example of a cross-sectional structure of a memory column included in the memory device according to the fourth embodiment. Fig.19 Cross-sectional view of line XX-XX.

[0030] Fig.21 This is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to the fourth embodiment. DETAILED DESCRIPTION

[0031] The following describes various embodiments with reference to the accompanying drawings. Each embodiment illustrates a device or method for specifically realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions or ratios of the drawings are not limited to being the same as in reality. The diagrams of the structures are appropriately omitted. For components with roughly the same function and structure, the same mark is attached. The numbers attached to the reference marks are used to distinguish between similar elements that are referenced by the same reference marks.

[0032] In the following description, two types of horizontal directions that intersect each other are referred to as "X direction" and "Y direction", respectively. In the following description, a plane parallel to the X direction and the Y direction, respectively, is referred to as an "XY plane". In the following description, a direction perpendicular to a horizontally mounted substrate, etc. is referred to as a "Z direction". In this specification, "above" means perpendicularly above relative to a horizontally mounted layer, etc. constituent element. In this specification, "below" means perpendicularly below relative to a horizontally mounted layer, etc. constituent element. In this specification, "looking down" means, for example, visually recognizing a horizontally mounted layer, etc. constituent element from above. "Visual recognition" includes the situation of observing an object using a microscope, a camera, etc.

[0033] The semiconductor device in this specification is formed by joining two semiconductor circuit boards each having a semiconductor circuit formed thereon, and separating the joined semiconductor circuit boards according to each chip. The semiconductor circuit board will be referred to as a "wafer" hereinafter. The process of joining two wafers will be referred to as a "joining process". The device that performs the joining process will be referred to as a "joining device". The wafers arranged on the upper side and the lower side during the joining process will be referred to as an "upper wafer UW" and a "lower wafer LW", respectively. The group of the joined upper wafer UW and lower wafer LW will be referred to as a "joined wafer BW". The "front side of the wafer" corresponds to the side on which the semiconductor circuit is formed by a pre-process. The "back side of the wafer" corresponds to the side opposite to the front side of the wafer.

[0034] <0> Method for manufacturing semiconductor device

[0035] Figure 1 1 is a schematic diagram showing an overview of a method for manufacturing a semiconductor device. Figure 1 , describing a general process flow in a method for manufacturing a semiconductor device.

[0036] First, the wafers are allocated into lots ("batching"). A lot can include multiple wafers. For example, a lot is classified into a lot including an upper wafer UW and a lot including a lower wafer LW. Each upper wafer UW is associated with one lower wafer LW. Then, a pre-process is performed for the lot including the upper wafer UW and the lot including the lower wafer LW. The pre-process includes a combination of "exposure processing", "exposure OL (overlay) measurement" and "etching processing".

[0037] The exposure process is a process of transferring the pattern of a mask (reticle) to the resist material on the wafer in units of exposure blocks (shot). "Exposure blocks" correspond to the divided areas of exposure in the exposure process. The configuration of the exposure block of the upper wafer UW is set to be the same as the configuration of the exposure block of the lower wafer LW. In the exposure process, the exposure of one exposure block is repeatedly performed in a staggered position. In other words, the exposure device exposes the wafer in a step-and-repeat manner. Thereafter, a portion of the resist material is removed by a development process, and the desired pattern is transferred to the resist material. In the exposure process, the configuration or shape of each exposure block is corrected based on the measurement results of the alignment mark, various correction values, etc. Thus, the overlapping position of the pattern of the substrate and the pattern formed by the exposure process is adjusted (aligned).

[0038] Exposure OL measurement is a process for measuring the amount of overlap between the pattern of the substrate and the pattern of the resist material formed by the exposure process. The measurement results obtained by exposure OL measurement are used, for example, to determine rework of the exposure process or to calculate alignment correction values ​​to be applied to subsequent batches.

[0039] The etching process is a process of processing components on the wafer using the resist material formed by the exposure process as a mask. Through the etching process, the components on the wafer are processed into a shape based on the pattern of the resist material. The circuit pattern of each layer can be formed by a combination of such an exposure process and an etching process.

[0040] In addition, although the description is omitted in this specification, the pre-process may also include a heating process, a cleaning process, a film forming process, etc. In addition, by implementing the pre-process of each of the upper wafer UW and the lower wafer LW, the desired semiconductor circuit is formed on the front side of each of the upper wafer UW and the lower wafer LW ("pre-process completion"). Thereafter, the bonding process is performed using the group of the upper wafer UW and the lower wafer LW that are associated.

[0041] During the bonding process, the bonding device makes the front of the upper wafer UW face the front of the lower wafer LW and holds them. Then, based on the measurement results of the alignment marks, the bonding device adjusts (aligns) the overlapping position of the pattern formed by the front of the upper wafer UW and the pattern formed by the front of the lower wafer LW. Then, the bonding device makes the front of the upper wafer UW contact the front of the lower wafer LW. As a result, the front of the upper wafer UW and the front of the lower wafer LW are bonded to form a bonded wafer BW. Thereafter, bonding OL (overlay) measurement is performed on the bonded wafer BW.

[0042] The bonding OL measurement is a process for measuring the deviation of the overlap between the pattern formed by the bonding surface of the upper wafer UW and the pattern formed by the bonding surface of the lower wafer LW. The "bonding layer" corresponds to the layer that is in contact with the boundary portion of the upper wafer UW and the lower wafer LW. The upper wafer UW and the lower wafer LW each have a bonding layer. The measurement results obtained by the bonding OL measurement can be used to calculate the alignment correction value to be applied to the exposure processing of the subsequent batch.

[0043] Thereafter, a wiring process is performed on the bonded wafer BW to form wiring or pads for external connection with the circuit provided on the bonded wafer BW. Then, the bonded wafer BW is separated into individual chips by dicing, thereby forming a plurality of semiconductor devices from one bonded wafer BW.

[0044] In addition, in this specification, "alignment" corresponds to the shape of the wafer in the exposure device benchmark. The deviation amount of overlap corresponds to the positional deviation between the pattern of the overlap source and the pattern of the overlap object. That is, the component that cannot be corrected by the exposure processing based on the measurement result of the alignment is called the overlap deviation. Hereinafter, the correction value used in the alignment of the overlap position is referred to as the "alignment correction value". The coefficients of each term when a polynomial is used in the correction of the alignment are referred to as the "alignment correction coefficient". The alignment correction value can be calculated based on the alignment correction coefficients of each term and the exposure position.

[0045] The deviation of overlap that may occur in each of the exposure process and the bonding process can be expressed by a combination of various components. For example, the measurement result of overlap (alignment) is decomposed according to each K value through polynomial regression. The overlap component represented by the K value includes a bias (offset) component, a magnification component, and an orthogonality component. The following is a list of mathematical formulas corresponding to each component. In addition, in the following mathematical formulas, "x" and "y" correspond to the coordinates in the X direction (X coordinate) and the coordinates in the Y direction (Y coordinate), respectively. "dx" and "dy" correspond to the deviation of overlap in the X direction and the Y direction, respectively. "K1" to "K6" correspond to alignment correction coefficients (polynomial regression coefficients), respectively.

[0046] Bias (offset) component in the X direction: dx = K1

[0047] Bias (offset) component in the Y direction: dy = K2

[0048] The magnification component in the X direction: dx = K3 * x

[0049] The magnification component in the Y direction: dy = K4 * y

[0050] Orthogonality component in the X direction: dx = K5 * y

[0051] Orthogonality component in the Y direction: dy = K6 * x

[0052] In this example, the overlap deviation Ex in the X direction is calculated by "Ex=K1+K3*x+K5*y". The overlap deviation Ey in the Y direction is calculated by "Ey=K2+K4*y+K6*x". In addition, when the overlap component is expressed by polynomial regression, not only K1~K6 but also the coefficients allocated to higher-order overlap components can be used as polynomial regression coefficients. In addition, the above-mentioned overlap deviation can be calculated in the exposure block unit and each within the wafer surface. Hereinafter, the overlap component of the magnification component generated within the wafer surface is referred to as the "wafer magnification component". The wafer magnification component corresponds to the size of the wafer. The overlap component randomly generated within the wafer surface is referred to as the "random component".

[0053] Figure 2 1 is a schematic diagram showing an example of arrangement of alignment marks AM used in a manufacturing process of a semiconductor device. Figure 2 (A) exemplifies the arrangement of a plurality of alignment marks AM on the wafer WF measured during the exposure process. Figure 2 (B) exemplifies the arrangement of a plurality of alignment marks AM on the wafer WF measured during the bonding process.

[0054] like Figure 2 As shown in (A), during the exposure process, the exposure device measures the alignment marks AM at multiple points arranged on the wafer WF (i.e., the upper wafer UW or the lower wafer LW). The number of alignment marks AM measured is preferably 3 or more. The exposure device can calculate the alignment correction values ​​of the offset component, magnification component, orthogonality component, etc. in the X direction and the Y direction by performing function approximation on the measurement results of the alignment marks AM at multiple points in the orthogonal coordinate system. In addition, based on the measurement results of the alignment marks AM at multiple points, the exposure device can correct the overlap of the exposure block unit and the overlap within the wafer surface.

[0055] like Figure 2 As shown in (B), during the bonding process, the bonding device measures, for example, the alignment marks AM_C, AM_L, and AM_R respectively arranged on the upper wafer UW and the lower wafer LW. The alignment mark AM_C is arranged near the center of the wafer. The alignment marks AM_L and AM_R are respectively arranged on one side and the other side of the periphery of the wafer WF. The bonding device can calculate the alignment correction values ​​of the offset component and the rotation component based on the measurement results of the alignment marks AM_C, AM_L, and AM_R of the upper wafer UW and the lower wafer LW. In addition, the bonding device can also correct the common wafer magnification components in the X direction and the Y direction by deforming the worktable holding the wafer.

[0056] Figure 3 This is a table showing an example of the correction performance of the exposure device and the bonding device for the overlapped components in the wafer surface that may remain during the bonding OL. Figure 3As shown, both the exposure device and the bonding device can correct the offset component. Both the exposure device and the bonding device can correct the wafer magnification component common to the X direction and the Y direction (XY common magnification component). In the exposure device, it is possible to correct the wafer magnification component that is different in the X direction and the Y direction (XY difference magnification component). On the other hand, it is difficult to correct the XY difference magnification component in the bonding device. Both the exposure device and the bonding device can correct the rotation component (i.e., the orthogonality component common to the X direction and the Y direction). In the exposure device, the orthogonality component can be corrected. On the other hand, it is difficult to correct the orthogonality component in the bonding device. In the exposure device, the random component can be corrected in units of exposure blocks. On the other hand, it is difficult to correct the random component in the bonding device.

[0057] For example, during the bonding process, the bonding device increases the wafer rate component of the lower wafer LW by deforming the worktable holding the lower wafer LW, and can adjust the overlapping wafer rate component (XY common rate component) of the upper wafer UW and the lower wafer LW. However, the tendency of the overlapping random components changes according to the deformation amount of the lower worktable. Therefore, depending on the correction amount of the wafer rate component involving the lower worktable, the random component of the bonding OL may be deteriorated. On the other hand, it is also considered to make the respective wafer rate components of the upper wafer UW and the lower wafer LW consistent in the exposure process when forming the pattern of the bonding surface, thereby improving the bonding OL. However, in the case of making the wafer rate components at the bonding surface consistent, in the wafer on the other side of the bonding surface exposure process performed according to the wafer rate component of the wafer on the one side serving as the reference, it is possible to cause the overlap of the pattern of the bonding surface and the pattern of its base to deteriorate.

[0058] <1> First Embodiment

[0059] The first embodiment relates to an exposure apparatus and an exposure method that can improve the overlap of wafer magnification components in a bonding process and improve the overlap of a bonding layer and its base. The first embodiment will be described in detail below.

[0060] <1-1> Configuration of Exposure Device 1

[0061] The exposure device 1 involved in the first embodiment is configured to be able to transfer the wafer WF between the coating and developing device. The "coating and developing device" is a device that performs pre-processing and post-processing of the exposure process. The pre-processing of the exposure process includes the process of coating the resist material (photosensitive material) on the wafer. The post-processing of the exposure process includes the process of developing the exposed pattern on the wafer. As the device used in the pre-processing and post-processing of the exposure process, a plurality of semiconductor manufacturing devices can also be used.

[0062] Figure 41 is a block diagram showing an example of the structure of the exposure device 1 according to the first embodiment. Figure 4 As shown, the exposure device 1 includes, for example, a control device 11 , a storage device 12 , a transport device 13 , a communication device 14 , and an exposure unit 15 .

[0063] The control device 11 is a computer or the like that controls the overall operation of the exposure device 1. The control device 11 controls the storage device 12, the conveying device 13, the communication device 14, and the exposure unit 15, respectively. Although not shown in the figure, the control device 11 has a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), etc. The CPU is a processor that executes various programs related to the control of the device. The ROM is a non-volatile storage medium that stores the control program of the device. The RAM is a volatile storage medium used as a working area of ​​the CPU.

[0064] The storage device 12 is a storage medium for storing data, programs, etc. The storage device 12 stores, for example, an exposure recipe 21 and correction value information 22. In addition, the storage device 12 may be externally connected to the exposure device 1.

[0065] The exposure recipe 21 is a table recording the settings of the exposure process. The exposure recipe 21 includes information such as the shape and layout of the exposure block, the exposure amount (Dose), the focus setting, the alignment setting, etc. for each exposure process. The alignment setting includes the selection of the normal mode and the upper and lower limit correction mode. In the alignment of the normal mode, based on the measurement results of multiple alignment marks AM, adjustments are made so that the overlap between the pattern of the substrate and the pattern of the exposure process is close to zero within the possible range. In the alignment of the upper and lower limit correction mode, based on the measurement results of multiple alignment marks AM, adjustments are made taking into account the upper limit value U_Limit and / or the lower limit value L_Limit so that the wafer magnification component in the wafer of the exposure process object is close to the target value W_Mag_TG within the possible range.

[0066] The correction value information 22 includes information on the target value W_Mag_TG, the upper limit value U_Limit, and the lower limit value L_Limit in the process to which the upper and lower limit correction modes are applied. The target value W_Mag_TG corresponds to the numerical value of the wafer rate component of the wafer on the side of the group of the upper wafer UW and the lower wafer LW to which the association is established, and on which the pre-process has been completed. For example, the wafer rate component of the upper wafer UW after the pre-process is completed is used as the target value W_Mag_TG. In this case, in the exposure processing associated with the bonding surface of the lower wafer LW, the upper limit value U_Limit and / or the lower limit value L_Limit are taken into consideration, and adjustments are made so that the alignment correction value of the wafer rate component during alignment is close to the wafer rate component of the upper wafer UW.

[0067] The upper limit value U_Limit and the lower limit value L_Limit represent the range of alignment measurement values ​​that allow the wafer rate component to be adjusted to the target value W_Mag_TG. The upper limit value U_Limit and the lower limit value L_Limit are based on the management specifications of the overlap deviation of the wafer rate component allowed between the pattern of the substrate and the pattern of the exposure process. The management specification can also be replaced by "management value". The upper limit value U_Limit corresponds to the value obtained by adding the upper limit value of the management specification (upper limit management value) to the target value W_Mag_TG. The lower limit value L_Limit corresponds to the value obtained by adding the lower limit value of the management specification (lower limit management value) to the target value W_Mag_TG. In addition, the upper limit value of the management specification is a positive value, and the lower limit value of the management specification is a negative value. For example, when the management specification is ±2ppm and the target value W_Mag_TG is 0.5ppm, the upper limit value U_Limit is set to 2.5ppm, and the lower limit value L_Limit is set to -1.5ppm. In addition, ppm stands for parts per million. For example, when the result of alignment measurement of a 300mm diameter wafer by an exposure device is 1ppm, it means that the diameter of the wafer is 300.0003mm based on the exposure device. Similarly, when the result of alignment measurement of a 300mm diameter wafer by an exposure device is -1ppm, it means that the diameter of the wafer is 299.9997mm based on the exposure device.

[0068] The transport device 13 is a device including a transport arm capable of transporting wafers WF or a transfer member for temporarily placing a plurality of wafers. For example, the transport device 13 transports the wafers WF received from the external coating and developing device to the exposure unit 15. In addition, the transport device 13 transports the wafers WF received from the exposure unit 15 to the external coating and developing device after the exposure process.

[0069] The communication device 14 is a communication interface that can be connected to a network (not shown). The exposure device 1 may be operated based on an operation performed by a terminal on the network. The exposure recipe 21 and the correction value information 22 may be stored in a server on the network.

[0070] The exposure unit 15 is a collection of structures used in the exposure process. The exposure unit 15 includes, for example, a wafer stage 31, a mask stage 32, a light source 33, a projection optical system 34 and a camera 35. The wafer stage 31 has a function of holding the wafer WF. The mask stage 32 has a function of holding the mask RT (mask). The respective worktable positions of the wafer stage 31 and the mask stage 32 can be controlled by the control device 11. The light source 33 irradiates the generated light to the mask RT. The projection optical system 34 collects the light after passing through the mask RT onto the surface of the wafer WF. The camera 35 is a photographic mechanism used in measuring the alignment mark AM. In addition, the wafer WF can also be irradiated with the light reflected on the mask RT. In this case, the projection optical system has a plurality of reflectors.

[0071] <1-2>Exposure method

[0072] Figure 5 1 is a flowchart showing an example of an exposure method of the exposure device 1 according to the first embodiment. Figure 5 As an exposure method of the exposure apparatus 1 according to the first embodiment, a case where an exposure process in which the upper and lower limit correction modes are effective is performed will be described.

[0073] When the exposure device 1 is notified from the coating and developing device that the pre-processing of the wafer WF is completed, the exposure device 1 starts the exposure processing (start).

[0074] First, the exposure device 1 is loaded with a wafer WF ( S101 ). The loaded wafer WF is held by the wafer stage 31 .

[0075] Next, the exposure device 1 confirms the exposure recipe 21 (S102). Specifically, the control device 11 determines the processing conditions applicable to the loaded wafer WF based on the exposure recipe 21. The processing conditions include, for example, the shape and layout of the exposure block, the exposure amount (Dose), the focus setting, and the alignment setting. In this example, the alignment of the readout upper and lower limit correction mode is an effective processing condition.

[0076] Next, the exposure apparatus 1 checks the correction value information 22 ( S103 ). Specifically, the control device 11 obtains detailed settings of alignment in the upper and lower limit correction mode, that is, the target value W_Mag_TG, the upper limit value U_Limit, and the lower limit value L_Limit in the exposure process.

[0077] Next, the exposure device 1 measures the alignment mark AM (S104). Specifically, the wafer stage 31 moves appropriately, and the camera 35 photographs a plurality of alignment marks AM arranged at predetermined positions on the wafer WF. For example, at least three alignment marks AM are photographed. Based on the exposure recipe 21, the position of the alignment mark AM to be photographed in the process of S104 is determined.

[0078] Next, the exposure device 1 calculates the wafer magnification component W_Mag_B of the substrate (S105). Specifically, the control device 11 performs function approximation on the measurement results of the plurality of alignment marks AM in the orthogonal coordinate system to calculate the wafer magnification component W_Mag_B of the substrate. The value of the wafer magnification component W_Mag_B may vary for each wafer WF according to process variation.

[0079] Next, the exposure apparatus 1 checks the value of the wafer magnification component W_Mag_B ( S106 ).

[0080] When the value of the wafer magnification component W_Mag_B is smaller than the lower limit value L_Limit (S106: smaller than L_Limit), the exposure apparatus 1 sets the alignment correction value of the wafer magnification component to "target value W_Mag_TG+wafer magnification component W_Mag_B-lower limit value L_Limit" (S107), and proceeds to the process of S110.

[0081] When the value of the wafer magnification component W_Mag_B is within the range of greater than the lower limit value L_Limit and less than the upper limit value U_Limit (S106: within the range of greater than L_Limit and less than U_Limit), the exposure device 1 sets the alignment correction value of the wafer magnification component to the "target value W_Mag_TG" (S108), and proceeds to the processing of S110.

[0082] When the value of wafer magnification component W_Mag_B exceeds upper limit value U_Limit (S106: exceeds U_Limit), exposure apparatus 1 sets the alignment correction value of the wafer magnification component to "target value W_Mag_TG+wafer magnification component W_Mag_B-upper limit value U_Limit" (S109), and proceeds to the process of S110.

[0083] In the process of S110, the exposure device 1 executes the exposure sequence (S110). Specifically, the control device 11 controls the wafer stage 31 based on the alignment correction value of the wafer magnification component determined in any one of the processes of S107, S108 and S109, and uses the light source 33 to appropriately irradiate the wafer WF with light after passing through the mask RT.

[0084] When the process of S110 is completed, the exposure device 1 unloads the wafer WF ( S111 ). When the exposure device 1 unloads the wafer WF, the exposure process ends (end).

[0085] Figure 6 1 is a schematic diagram showing an example of a superimposition result related to the exposure process of the exposure device 1 involved in the first embodiment. Figure 6 For example, the exposure block shape of the substrate corresponding to the wafer magnification component of the lower wafer LW (five conditions of 2ppm, 1ppm, 0ppm, -1ppm and -2ppm) and the exposure block shape of the exposure process under three conditions of "with correction", "without correction" and "upper and lower limit correction" are shown. In addition, in this example, the upper limit value U_Limit is set to 1ppm, the lower limit value L_Limit is set to -1ppm, and the target value W_Mag_TG is set to 0ppm.

[0086] "With correction" corresponds to the result of the exposure processing when the alignment of the normal mode is applied. When the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the alignment correction value of the wafer rate component in the exposure processing is set to 2ppm, 1ppm, 0ppm, -1ppm and -2ppm respectively based on the alignment measurement value of the substrate wafer. As a result, when the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the overlap (exposure OL) deviation of the exposure pattern relative to each substrate becomes 0ppm. Therefore, in the exposure processing with correction, when the wafer rate component of the substrate is any of 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the overlap (exposure OL) deviation of the substrate pattern and the wafer rate component of the exposure pattern can be within the management specification ( Figure 6 OK).

[0087] "No correction" corresponds to the result of the exposure processing when the correction of the wafer rate component based on the alignment measurement value is not applied. That is, in any case where the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the alignment correction value of the wafer rate component in the exposure processing is set to 0ppm based on a pre-set alignment correction value. For example, the pre-set alignment correction value is set based on the numerical value of the wafer rate component of the upper wafer UW. That is, in this example, the numerical value of the wafer rate component of the upper wafer UW is 0ppm. In this case, the overlap (exposure OL) deviation of the exposure pattern relative to the substrate when the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm becomes -2ppm, -1ppm, 0ppm, 1ppm and 2ppm respectively. Therefore, when the wafer rate component of the substrate is 1ppm, 0ppm and -1ppm, the exposure process without correction can make the overlap deviation of the wafer rate component of the substrate pattern and the exposure pattern converge within the management specification ( Figure 6 On the other hand, when the wafer rate component of the substrate is 2ppm and -2ppm, the exposure process without correction cannot make the overlap deviation of the wafer rate component of the substrate pattern and the exposure pattern converge within the management specification ( Figure 6 of "NG").

[0088] "Upper and lower limit correction" corresponds to the result of exposure processing when the alignment of the upper and lower limit correction mode is applied. When the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the alignment correction value of the wafer rate component in the exposure process is set to 1ppm, 1ppm, 0ppm, -1ppm and -1ppm, respectively. Specifically, when the wafer rate component of the substrate is within the range of above -1ppm and below 1ppm, based on the target value W_Mag_TG, the alignment correction value of the wafer rate component during the exposure process is set to 0ppm. On the other hand, when the wafer rate component of the substrate is 2ppm, based on the upper limit value U_Limit, the alignment correction value of the wafer rate component during the exposure process is set to 0ppm (target value W_Mag_TG) + 2ppm (wafer rate component W_Mag_B) - 1ppm (upper limit value U_Limit) = 1ppm. Similarly, when the wafer rate component of the substrate is -2ppm, based on the lower limit value L_Limit, the alignment correction value of the wafer rate component during the exposure processing is set to 0ppm(target value W_Mag_TG)+(-2ppm)(wafer rate component W_Mag_B)-(-1ppm)(lower limit value L_Limit)=-1ppm. As a result, the overlap (exposure OL) deviations of the exposure patterns corresponding to the cases where the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm are respectively -1ppm, -1ppm, 0ppm, 1ppm and 1ppm. Therefore, the exposure processing under upper and lower limit correction can make the overlap deviation of the wafer rate component of the substrate pattern and the exposure pattern converge within the management specifications in any of the cases where the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm. Figure 6 OK).

[0089] Figure 7 This is a table showing an example of alignment correction values ​​of wafer magnification components involved in the exposure process of the exposure apparatus 1 according to the first embodiment. Figure 7 An example of the results of exposure processing for 10 wafers WF in which the alignment with the upper and lower limit correction modes is applied is shown, and the alignment measurement values ​​(wafer magnification component W_Mag_B of the substrate) corresponding to these results, the alignment correction values ​​of the applied wafer magnification components, and the predicted values ​​of the overlap deviation are shown. In this example, the target value W_Mag_TG is set to 0.5ppm, the upper limit value U_Limit is set to 2.5ppm which is 2ppm larger than the target value W_Mag_TG, and the lower limit value L_Limit is set to -1.5ppm which is 2ppm smaller than the target value W_Mag_TG.

[0090] like Figure 7 As shown, the alignment measurement values ​​of 10 wafers (No. 1 to No. 10) are 2.3ppm, -1.1ppm, 1.2ppm, 3.2ppm, 1.6ppm, 0.5ppm, -1.4ppm, -2.3ppm, -0.3ppm, and 1.5ppm respectively. In this example, the No. 4 wafer exceeds the upper limit value U_Limit (upper limit unqualified), and the No. 8 wafer is below the lower limit value L_Limit (lower limit unqualified).

[0091] In this case, based on the processing of S109, the alignment correction value of the wafer rate component applicable to wafer No. 4 is set to 0.5ppm (target value W_Mag_TG) + 3.2ppm (wafer rate component W_Mag_B) - 2.5ppm (upper limit value U_Limit) = 1.2ppm. Based on the processing of S107, the alignment correction value of the wafer rate component applicable to wafer No. 8 is set to 0.5ppm (target value W_Mag_TG) + (-2.3ppm) (wafer rate component W_Mag_B) - (-1.5ppm) (lower limit value L_Limit) = -0.3ppm. Based on the processing of S108, the alignment correction value of the wafer rate component applicable to other wafers except No. 4 and No. 7 is set to 0.5ppm.

[0092] The predicted values ​​of the overlap deviation of wafers No. 1 to No. 10 obtained by applying the correction of the wafer magnification component described above are -1.8ppm, 1.6ppm, -0.7ppm, -2.0ppm, -1.1ppm, 0ppm, 1.9ppm, 2.0ppm, 0.8ppm, and -1.0ppm, respectively. In this way, the predicted values ​​of the overlap deviation of each wafer No. 1 to No. 10 converge within the management specification. That is, by adjusting the overlap deviation relative to the substrate to within the management specification, the wafer magnification component of each wafer No. 1 to No. 10 is adjusted to a value as close to the target value W_Mag_TG as possible.

[0093] Figure 8 This is a scattergram showing an example of distribution of wafer magnification components after the exposure process of the exposure apparatus 1 according to the first embodiment. Figure 8 Indicates for Figure 7 The distribution of wafer magnification components when the normal mode alignment is applied to the 10 wafers WF shown in the figure, and the distribution of wafer magnification components when the upper and lower limit correction mode alignment is applied. Figure 8As shown, the 3σ of the wafer magnification component when the normal mode alignment is applied is 5.3ppm. On the other hand, the 3σ of the wafer magnification component when the upper and lower limit correction mode is applied is 1.1ppm. As shown in FIG. 1 , the non-uniformity of the wafer magnification component when the upper and lower limit correction mode is applied is smaller than the non-uniformity of the wafer magnification component when the normal mode alignment is applied.

[0094] <1-3> Effects of the First Embodiment

[0095] The exposure device 1 involved in the first embodiment performs alignment based on the wafer rate component W_Mag_B of the substrate, the target value W_Mag_TG, the upper limit value U_Limit and the lower limit value L_Limit in the exposure processing of the bonding layer. Specifically, when the wafer rate component W_Mag_B is within the range of more than the lower limit value L_Limit and less than the upper limit value U_Limit, the wafer rate component of the bonding layer is corrected to the target value W_Mag_TG. Furthermore, when the wafer rate component W_Mag_B is outside the range of more than the upper limit value U_Limit and less than the lower limit value L_Limit, the wafer rate component of the bonding layer is corrected to be close to the target value W_Mag_TG within the management specifications of the overlap between the pattern of the substrate and the pattern of the exposure processing.

[0096] Thus, the exposure device 1 involved in the first embodiment can correct the overlap between the bonding layer and its substrate within a range with a small impact on the yield, and suppress the deviation of the wafer rate component in the bonding layer. The correction amount of the wafer rate component in the bonding process is adjusted to be approximately constant, which can suppress the deterioration of the random component based on the deviation of the wafer rate component. Therefore, the exposure device 1 involved in the first embodiment can improve the overlap between the bonding layer and its substrate and the overlap of the upper wafer UW and the lower wafer LW in the bonding process, and can improve the yield of the semiconductor device.

[0097] In addition, the alignment in the exposure process is usually set so that the overlap deviation between the pattern of the substrate and the pattern of the exposure process is as close to zero as possible, that is, it is set corresponding to the calculated value of the magnification component. In addition, when the target value W_Mag_TG of the wafer magnification component is set, it is assumed that the alignment correction value of the wafer magnification component is set to the target value W_Mag_TG. In contrast, the alignment correction value of the magnification component in the exposure method of the first embodiment can be different from any value of the target value W_Mag_TG and the calculated value (wafer magnification component W_Mag_B).

[0098] The alignment correction value of the magnification component in the first embodiment is set to the first correction value (target value W_Mag_TG) when the calculated value of the wafer magnification component (wafer magnification component W_Mag_B) is within the range of the lower limit value L_Limit and the upper limit value U_Limit, and is set to the second correction value larger than the wafer magnification component W_Mag_B and smaller than the target value W_Mag_TG when the wafer magnification component W_Mag_B is less than the lower limit value L_Limit, and is set to the third correction value larger than the target value W_Mag_TG and smaller than the wafer magnification component W_Mag_B when the wafer magnification component W_Mag_B exceeds the upper limit value U_Limit. The second correction value is more preferably a value obtained by adding the calculated value to the first correction value and then subtracting the lower limit value L_Limit. The third correction value is more preferably a value obtained by adding the calculated value to the first correction value and then subtracting the upper limit value U_Limit.

[0099] <2> Second Embodiment

[0100] The second embodiment relates to a method for manufacturing a semiconductor device in which the exposure method described in the first embodiment is applied to a plurality of layers near the bonding layer and the deviation of the wafer magnification component from the target value is suppressed in stages. The details of the second embodiment are described below mainly focusing on the differences from the first embodiment.

[0101] <2-1> Method for manufacturing semiconductor device

[0102] Fig. 9 FIG. 1 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the second embodiment. Fig. 9 As a method for manufacturing a semiconductor device according to the second embodiment, a case where exposure processing using the upper and lower limit correction modes is performed in three exposure steps for a predetermined wafer WF will be described.

[0103] First, in an exposure process associated with the first layer, an exposure process utilizing an upper and lower limit correction mode is performed (S201). Next, in an exposure process associated with the second layer, an exposure process utilizing an upper and lower limit correction mode is performed (S202). Next, in an exposure process associated with the third layer (bonding layer), an exposure process utilizing an upper and lower limit correction mode is performed (S203). Then, using the wafer WF after each of the processes S201 to S203 is performed, a bonding process (S204) is performed. In addition, when calculating the alignment correction value in each of S201 to S203, since the combined wafer WF is the same, the same target value W_Mag_TG of the wafer magnification component is used. On the other hand, the upper limit value U_Limit and the lower limit value L_Limit of the wafer magnification component can be set individually for each exposure process.

[0104] Fig.10 This is a box plot showing an example of changes in distribution of wafer factor components in the method for manufacturing a semiconductor device according to the second embodiment. Fig.10 Indicates that in a given batch, the following operations are performed in each of the first to third layers: Fig. 9 As described above, the variation in the wafer magnification component in the exposure process in which the alignment in the upper and lower limit correction mode is applied is shown. In this example, the target value W_Mag_TG is 0 ppm.

[0105] like Fig.10 As shown, the range of the wafer rate component in the base of the first layer is 6.0 ppm (measurement (1)).

[0106] In the first layer, the allowable value (management specification) of the deviation of the wafer magnification component is ±1.0ppm. Using the upper limit value U_Limit and the lower limit value L_Limit set based on this value, the exposure process of the first layer is performed (exposure (1)). As a result, the range of the wafer magnification component in the first layer is improved by 2ppm to 4.0ppm (measurement (2)).

[0107] In the second layer, the allowable value (management specification) of the deviation of the wafer magnification component is ±0.4ppm. Using the upper limit value U_Limit and the lower limit value L_Limit set based on this value, the exposure process of the second layer is performed (exposure (2)). As a result, the range of the wafer magnification component in the second layer is improved by 0.8ppm to 3.2ppm (measurement (3)).

[0108] In the third layer, the allowable value (management specification) of the deviation of the wafer magnification component is ±0.5ppm. Using the upper limit value U_Limit and the lower limit value L_Limit set based on this value, the exposure process of the third layer is performed (exposure (3)). As a result, the range of the wafer magnification component in the third layer is improved by 1.0ppm to 2.2ppm (measurement (3)).

[0109] <2-2> Effects of the Second Embodiment

[0110] As described above, the alignment of the upper and lower limit correction modes described in the first embodiment can be used for layers other than the bonding layer and can also be used in multiple processes. In addition, the manufacturing method of the semiconductor device involved in the second embodiment performs the alignment using the upper and lower limit correction modes in multiple processes, thereby gradually making the wafer rate component reach the vicinity of the target value.

[0111] As a result, the method for manufacturing a semiconductor device according to the second embodiment can reduce the correction amount of the overlap between the bonding layer and its substrate, and can improve the overlap between the bonding layer and its substrate compared to the case where only the alignment of the upper and lower limit correction mode is applied to the bonding layer. In addition, the method for manufacturing a semiconductor device according to the second embodiment can suppress the deterioration of the random component in the bonding process, similarly to the first embodiment. Therefore, the method for manufacturing a semiconductor device according to the second embodiment can improve the yield of the semiconductor device.

[0112] <3> Third Embodiment

[0113] In the third embodiment, the exposure device 1 is configured to be able to independently set the upper limit value U_Limit and the lower limit value L_Limit of the wafer magnification component in the X direction and the Y direction. In addition, the upper limit value U_Limit and the lower limit value L_Limit of the X direction and the Y direction are set according to the respective overlap margins in the X direction and the Y direction, and the range of the wafer magnification component relative to the target value is suppressed in stages. The details of the third embodiment are described below mainly with respect to the points different from the first and second embodiments.

[0114] <3-1>Exposure method

[0115] Fig.11 1 is a flowchart showing an example of an exposure method of the exposure apparatus according to the third embodiment. Fig.11 As an exposure method of the exposure apparatus 1 according to the third embodiment, a case of performing exposure processing of an exposure step in which the upper and lower limit correction modes are effective will be described.

[0116] When the exposure device 1 is notified from the coating and developing device that the pre-processing of the wafer WF is completed, the exposure device 1 starts the exposure processing (start).

[0117] First, the exposure device 1 performs the processes of S101 to S104 in the same manner as in the first embodiment. That is, the exposure device 1 loads the wafer WF (S101). Then, the exposure device 1 confirms the exposure recipe 21 (S102) and the correction value information 22 (S103). Then, the exposure device 1 measures the alignment mark AM (S104).

[0118] Next, the exposure device 1 calculates the wafer magnification components W_Mag_BX and W_Mag_BY of the substrate (S301). Specifically, the control device 11 performs function approximation on the measurement results of the plurality of alignment marks AM in the orthogonal coordinate system, thereby calculating the wafer magnification component (W_MagBX) in the X direction of the substrate and the wafer magnification component (W_MagBY) in the Y direction of the substrate.

[0119] Next, the exposure device 1 sets the alignment correction value of the wafer magnification component in the X direction based on the wafer magnification component W_Mag_BX, the target value W_Mag_TG, the lower limit value L_Limit_X and the upper limit value U_Limit_X (S302). Specifically, when calculating the alignment correction value of the wafer magnification component in the X direction, the exposure device 1 performs the same Figure 5 The same processing as S106 to S109 is performed. The upper limit value U_Limit_X is a value obtained based on the upper limit management value of the wafer magnification component in the X direction in the exposure process. The lower limit value L_Limit_X is a value obtained based on the lower limit management value of the wafer magnification component in the X direction in the exposure process. For example, when the value of W_MagBX is less than the lower limit value L_Limit_X, the exposure device 1 sets the alignment correction value of the wafer magnification component in the X direction to "target value W_Mag_TG+wafer magnification component W_Mag_BX-lower limit value L_Limit_X". When the value of W_MagBX is within the range of more than the lower limit value L_Limit_X and less than the upper limit value U_Limit_X, the exposure device 1 sets the alignment correction value of the wafer magnification component in the X direction to "target value W_Mag_TG". When the value of W_MagBX exceeds the upper limit value U_Limit_X, the exposure apparatus 1 sets the alignment correction value of the wafer magnification component in the X direction to “target value W_Mag_TG+wafer magnification component W_Mag_BX−upper limit value U_Limit_X”.

[0120] Next, the exposure device 1 sets the alignment correction value of the wafer magnification component in the Y direction based on the wafer magnification component W_Mag_BY, the target value W_Mag_TG, the lower limit value L_Limit_Y, and the upper limit value U_Limit_Y (S303). Specifically, when calculating the alignment correction value of the wafer magnification component in the Y direction, the exposure device 1 performs the same Figure 5 The same processing as S106 to S109 is performed. The upper limit value U_Limit_Y is a value obtained based on the upper limit management value of the wafer magnification component in the Y direction in the exposure process. The lower limit value L_Limit_Y is a value obtained based on the lower limit management value of the wafer magnification component in the Y direction in the exposure process. The upper limit value U_Limit_Y may be the same as or different from the upper limit value U_Limit_X. The lower limit value L_Limit_Y may be the same as or different from the lower limit value L_Limit_X. For example, when the value of W_MagBY is less than the lower limit value L_Limit_Y, the exposure device 1 sets the alignment correction value of the wafer magnification component in the Y direction to "target value W_Mag_TG+wafer magnification component W_Mag_BY-lower limit value L_Limit_Y". When the value of W_MagBY is within the range of the lower limit value L_Limit_Y or more and the upper limit value U_Limit_Y or less, the exposure device 1 sets the alignment correction value of the wafer magnification component in the Y direction to the "target value W_Mag_TG". When the value of W_MagBY exceeds the upper limit value U_Limit_Y, the exposure device 1 sets the alignment correction value of the wafer magnification component in the Y direction to "target value W_Mag_TG+wafer magnification component W_Mag_BY-upper limit value U_Limit_Y".

[0121] Next, the exposure device 1 executes the exposure sequence (S110) similarly to the first embodiment. Specifically, the control device 11 controls the wafer stage 31 based on the alignment correction value of the wafer magnification component determined in the processes of S302 and S303, and uses the light source 33 to appropriately irradiate the wafer WF with light that has passed through the mask RT.

[0122] When the process of S110 is completed, the exposure device 1 unloads the wafer WF ( S111 ). When the exposure device 1 unloads the wafer WF, the exposure process ends (end).

[0123] In addition, in the processing of S302 and S303, as the value of the wafer magnification component of the base, the common component of the wafer magnification component in the X direction and the Y direction (wafer magnification component W_Mag_B) can also be used. The upper and lower limit correction mode can also be applied when calculating the alignment correction value of the wafer magnification component in one of the X direction and the Y direction, and the normal mode can be applied when calculating the alignment correction value of the wafer magnification component in the other direction. In this case, the processing of one of S302 and S303 is omitted. In addition, in the upper and lower limit correction mode, the alignment when the upper and lower limit values ​​of the management specifications are respectively approximately zero is the same as the normal mode. That is, in the upper and lower limit correction mode, the exposure device 1 sets the upper and lower limit values ​​of the management specifications of one of the X direction and the Y direction to approximately zero, and appropriately sets the upper and lower limit values ​​of the management specifications of the other of the X direction and the Y direction, so that it is possible to perform an alignment in which the upper and lower limit correction mode is essentially applied only to one direction.

[0124] Fig.12 Schematic diagram showing an example of the superposition result involved in the exposure process of the exposure device involved in the third embodiment. Fig.12 , the exposure block shapes of the substrate corresponding to the wafer magnification components (five conditions: 2ppm, 1ppm, 0ppm, -1ppm, and -2ppm), and the exposure block shapes of the exposure processing under three conditions: "X normal / Y upper and lower limit correction", "X upper and lower limit correction / Y normal", and "X / Y upper and lower limit correction". In addition, in this example, the upper limit values ​​U_Limit_X and U_Limit_Y are set to 1ppm, the lower limit values ​​L_Limit_X and L_Limit_Y are set to -1ppm, and the target value W_Mag_TG is set to 0ppm. Hereinafter, the alignment correction value of the wafer magnification component in the X direction / Y direction in the exposure process is referred to as "correction value X / Y". In addition, the overlap deviation in the X direction / Y direction of the exposure pattern is referred to as "OL deviation X / Y".

[0125] "X normal / Y upper and lower limit correction" corresponds to the result of exposure processing when the alignment of the normal mode is applied in the X direction and the alignment of the upper and lower limit correction mode is applied in the Y direction. When the wafer magnification component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the correction value X / Y is set to 2 / 1ppm, 1 / 0ppm, 0 / 0ppm, -1 / 0ppm and -2 / -1ppm respectively.

[0126] Specifically, the alignment correction value of the wafer rate component in the X direction is set to the same value as the wafer rate component in the X direction of the substrate based on the application of the normal mode alignment. On the other hand, the alignment correction value of the wafer rate component in the Y direction is set to 0ppm based on the target value W_Mag_TG when the wafer rate component in the Y direction of the substrate is within the range of -1ppm or more and 1ppm or less. The alignment correction value of the wafer rate component in the Y direction is set to 0ppm (target value W_Mag_TG) + 2ppm (wafer rate component W_Mag_B) - 1ppm (upper limit value U_Limit_Y) = 1ppm based on the case where the wafer rate component in the Y direction of the substrate is 2ppm. When the wafer rate component of the substrate is -2ppm, the alignment correction value of the wafer rate component in the Y direction is set to 0ppm (target value W_Mag_TG) + (-2ppm) (wafer rate component W_Mag_B) - (-1ppm) (lower limit L_Limit_Y) = -1ppm based on the case where it is less than the lower limit L_Limit_Y. As a result, the OL deviation X / Y corresponding to the cases where the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, respectively, becomes 0 / -1ppm, 0 / -1ppm, 0 / 0ppm, 0 / 1ppm and 0 / 1ppm, respectively. Therefore, in any case where the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the exposure processing under the X normal / Y upper and lower limit correction can make the overlap deviation of the wafer rate component of the substrate pattern and the exposure pattern converge within the management specification.

[0127] "X upper and lower limit correction / Y normal" corresponds to the result of exposure processing when the alignment of the upper and lower limit correction mode is applied in the X direction and the alignment of the normal mode is applied in the Y direction. When the wafer magnification component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the correction value X / Y is set to 1 / 2ppm, 0 / 1ppm, 0 / 0ppm, 0 / -1ppm and -1 / -2ppm respectively.

[0128] Specifically, the alignment correction value of the wafer rate component in the Y direction is set to the same value as the wafer rate component in the Y direction of the substrate based on the application of the normal mode alignment. On the other hand, the alignment correction value of the wafer rate component in the X direction is set to 0ppm based on the target value W_Mag_TG when the wafer rate component in the X direction of the substrate is within the range of -1ppm or more and 1ppm or less. The alignment correction value of the wafer rate component in the X direction is set to 0ppm (target value W_Mag_TG) + 2ppm (wafer rate component W_Mag_B) - 1ppm (upper limit value U_Limit_X) = 1ppm based on the upper limit value U_Limit_X when the wafer rate component in the X direction of the substrate is 2ppm. When the wafer rate component of the substrate is -2ppm, the alignment correction value of the wafer rate component in the X direction is set to 0ppm (target value W_Mag_TG) + (-2ppm) (wafer rate component W_Mag_B) - (-1ppm) (lower limit value L_Limit_X) = -1ppm based on the lower limit value L_Limit_X. As a result, the OL deviation X / Y corresponding to the cases where the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, respectively, becomes -1 / 0ppm, -1 / 0ppm, 0 / 0ppm, 1 / 0ppm and 1 / 0ppm, respectively. Therefore, in any case where the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the exposure processing of the X upper and lower limit correction / Y normal case can make the overlap deviation of the wafer rate component of the substrate pattern and the exposure pattern converge within the management specification.

[0129] "X / Y upper and lower limit correction" corresponds to the result of exposure processing when the alignment of the upper and lower limit correction mode is applied in the X direction and the Y direction respectively. When the wafer magnification component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the correction value X / Y is set to 1 / 1ppm, 0 / 0ppm, 0 / 0ppm, 0 / 0ppm and -1 / -1ppm respectively. That is, the alignment correction value of the wafer magnification component used in the X / Y upper and lower limit correction is equivalent to the alignment correction value formed by combining the alignment correction value of the wafer magnification component in the Y direction in the case of X normal / Y upper and lower limit correction and the alignment correction value of the wafer magnification component in the X direction in the case of X upper and lower limit correction / Y normal. As a result, the OL deviation X / Y corresponding to the cases where the wafer magnification component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, respectively, becomes -1 / -1ppm, -1 / -1ppm, 0 / 0ppm, 1 / 1ppm and 1 / 1ppm. Therefore, when the wafer rate component of the substrate is 2ppm, 1ppm, 0ppm, -1ppm and -2ppm, the exposure processing under X / Y upper and lower limit correction can make the overlap deviation of the wafer rate component of the substrate pattern and the exposure pattern converge within the management specifications.

[0130] <3-2> Method for manufacturing semiconductor device

[0131] Fig.13 FIG. 1 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the third embodiment. Fig.13 As a method for manufacturing a semiconductor device according to a third embodiment, a case is described in which exposure processing capable of distinguishing between a normal mode and an upper and lower limit correction mode in two directions is performed in three exposure steps for a predetermined wafer WF.

[0132] First, in an exposure process associated with the first layer, an exposure process is performed in which the wafer magnification component of the first direction (e.g., X direction) is set by the normal mode and the wafer magnification component of the second direction (e.g., Y direction) is set by the upper and lower limit correction mode (S311). Next, in an exposure process associated with the second layer, an exposure process is performed in which the wafer magnification component of the second direction (e.g., Y direction) is set by the normal mode and the wafer magnification component of the first direction (e.g., X direction) is set by the upper and lower limit correction mode (S312). Next, in an exposure process associated with the third layer (bonding layer), an exposure process is performed in which the wafer magnification components of the first direction and the second direction are set by the upper and lower limit correction mode (S313). Then, a bonding process (S314) is performed using the wafer WF after each of the processes S311 to S313 has been executed. In addition, when calculating the alignment correction value in each of S311 to S313, since the combined wafers WF are the same, the same target value W_Mag_TG of the wafer magnification component is used. On the other hand, the upper limit value U_Limit and the lower limit value L_Limit of the wafer magnification component in each of the first direction and the second direction may be set individually for each exposure process.

[0133] Fig.14 This is a box plot showing an example of changes in distribution of wafer rate components in the method for manufacturing a semiconductor device according to the third embodiment. Fig.14 Indicates that in a specified batch, the following operations are performed in each of the first to third layers: Fig.13 Changes in deviations of the wafer magnification component in the X direction (W_Mag_X) and the wafer magnification component in the Y direction (W_Mag_Y) in the case of exposure processing in which the alignment in the upper and lower limit correction mode is applied as described in . In this example, the target value W_Mag_TG is 0 ppm.

[0134] like Fig.14 As shown, in the first layer of the base, the range of the wafer rate component in the X direction is 6.0 ppm, and the range of the wafer rate component in the Y direction is 6.0 ppm (measurement (1)). That is, the range of the wafer rate component X / Y is 6.0 / 6.0 ppm.

[0135] In the first layer, the allowable value (management specification) of the deviation of the wafer magnification component in the X direction is ±1.5ppm, and high-precision overlap is required in the Y direction. Therefore, in the exposure process of the first layer, based on the management specification, an alignment is performed in which the upper and lower limit correction mode is applied in the X direction and the normal mode is applied in the Y direction (exposure (1)). As a result, in the exposure process of the first layer, only the range of the wafer magnification component in the X direction is improved by 3.0ppm. As a result, the wafer magnification component range X / Y after processing of the first layer becomes 3.0 / 6.0ppm (measurement (2)).

[0136] In the second layer, the allowable value (management specification) of the deviation of the wafer magnification component in the Y direction is ±1.5ppm, and high-precision overlap is required in the X direction. Therefore, in the exposure processing of the second layer, based on the management specification, an alignment is performed in which the upper and lower limit correction mode is applied in the Y direction and the normal mode is applied in the X direction (exposure (2)). As a result, in the exposure processing of the second layer, only the range of the wafer magnification component in the Y direction is improved by 3.0ppm. As a result, the range X / Y of the wafer magnification component after processing of the second layer becomes 3.0 / 3.0ppm (measurement (3)).

[0137] In the third layer, the allowable value (management specification) of the deviation of the wafer magnification component in the X direction and the Y direction is ±0.5ppm. Therefore, in the exposure process of the third layer, based on the management specification, the upper and lower limit correction mode is applied in the X direction and the Y direction respectively (exposure (3)). As a result, in the exposure process of the third layer, the range of the wafer magnification component in the X direction and the Y direction is improved by 1.0ppm. As a result, the range of the wafer magnification component X / Y after the process of the third layer becomes 2.0 / 2.0ppm (measurement (4)).

[0138] In addition, in this example, the case where the normal mode alignment is applied in the direction requiring high-precision overlap is described, but the present invention is not limited thereto. The upper and lower limit correction mode alignment may also be applied in the direction requiring high-precision overlap. In this case, the management specification in the direction requiring high-precision overlap is set to zero or a smaller value within a possible range.

[0139] <3-3> Effects of the third embodiment

[0140] As described above, in the alignment of the upper and lower limit correction modes described in the first embodiment, upper and lower limit values ​​may be set individually for the X direction and the Y direction. In addition, the method for manufacturing a semiconductor device according to the third embodiment applies the alignment of the upper and lower limit correction modes to the directions having margins in the management specifications based on the management specifications for overlap in the X direction and the management specifications for overlap in the Y direction. In addition, the method for manufacturing a semiconductor device according to the third embodiment makes the wafer rate component reach the vicinity of the target value in stages, similarly to the second embodiment.

[0141] As a result, the method for manufacturing a semiconductor device according to the third embodiment can reduce the correction amount of the overlap between the bonding layer and its substrate, as in the second embodiment, and can improve the overlap between the bonding layer and its substrate compared to the case where only the alignment of the upper and lower limit correction modes is applied to the bonding layer. In addition, the method for manufacturing a semiconductor device according to the third embodiment can suppress the deterioration of the random component in the bonding process, as in the first embodiment. Therefore, the method for manufacturing a semiconductor device according to the third embodiment can improve the yield of the semiconductor device.

[0142] <4> Fourth Embodiment

[0143] The fourth embodiment relates to a specific example of a semiconductor device manufactured by the exposure method described in the above embodiment. Hereinafter, a memory device having a junction structure will be described as a specific example of a semiconductor device.

[0144] <4-1> Overall Configuration of Memory Device 100

[0145] Fig.15 1 is a block diagram showing an example of the overall configuration of the memory device 100 according to the fourth embodiment. Fig.15 As shown, the memory device 100 includes, for example, a memory interface (memory I / F) 101 , a sequencer 102 , a memory cell array 103 , a driver module 104 , a row decoder module 105 , and a sense amplifier module 106 .

[0146] The memory I / F 101 is a hardware interface connected to an external memory controller via a channel CH. The memory I / F 101 communicates in accordance with the interface standard between the memory device 100 and the memory controller. The memory I / F 101 supports, for example, the NAND interface standard.

[0147] The sequencer 102 is a control circuit that controls the overall operation of the memory device 100. Based on commands received via the memory I / F 101, the sequencer 102 controls the driver module 104, the row decoder module 105, the sense amplifier module 106, etc., and performs read operations, write operations, erase operations, etc.

[0148] The memory cell array 103 is a storage circuit including a collection of a plurality of memory cells. The memory cell array 103 includes a plurality of blocks BLK0 to BLKn (n is an integer greater than or equal to 1). The block BLK is used as a data deletion unit, for example. A plurality of bit lines and a plurality of word lines are provided in the memory cell array 103. Each memory cell is associated with, for example, one bit line BL and one word line WL. Each memory cell is identified based on an address for identifying the word line WL and an address for identifying the bit line BL.

[0149] The driver module 104 is a driver circuit that generates voltages used in read operations, write operations, erase operations, etc. The driver module 104 is connected to the row decoder module 105 via a plurality of signal lines. The driver module 104 can change the voltage applied to each of the plurality of signal lines based on the page address received via the memory I / F 101.

[0150] The row decoder module 105 is a decoder that decodes the row address received via the memory I / F 101. The row decoder module 105 selects one block BLK based on the decoding result. Then, the row decoder module 105 transfers the voltages applied to the plurality of signal lines to the plurality of wirings (such as word lines WL) provided in the selected block BLK.

[0151] The sense amplifier module 106 is a sensing circuit that senses data read from the selected block BLK based on the voltage of the bit line BL in the read operation. The sense amplifier module 106 sends the read data to the memory controller via the memory I / F 101. In addition, the sense amplifier module 106 can apply a voltage corresponding to the data written to the memory cell to each bit line BL in the write operation.

[0152] <4-2> Circuit Structure of Memory Cell Array 103

[0153] Fig.16 1 is a circuit diagram showing an example of a circuit configuration of a memory cell array 103 included in a memory device 100 according to the fourth embodiment. Fig.16 1 shows one block BLK among the plurality of blocks BLK included in the memory cell array 103. Fig.16 As shown, the block BLK includes, for example, four string units SU0 ˜ SU3 .

[0154] Each string unit SU includes multiple NAND strings NS. The NAND strings NS are associated with bit lines BL0 to BLm (m is an integer greater than 1). Different column addresses are assigned to the bit lines BL0 to BLm. Each bit line BL is shared by the NAND strings NS assigned the same column address between multiple blocks BLK. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors STD and STS.

[0155] Each memory cell transistor MT includes a control gate and a charge accumulation layer, and stores data non-volatilely. The memory cell transistors MT0 to MT7 of each NAND string NS are connected in series. The control gates of the memory cell transistors MT0 to MT7 are connected to the word lines WL0 to WL7, respectively. Word lines WL0 to WL7 are set for each block BLK. A collection of multiple memory cell transistors MT connected to a common word line WL in the same string unit SU is, for example, referred to as a "cell unit CU". When each memory cell transistor MT stores 1 bit of data, the cell unit CU stores "1 page of data". The cell unit CU can have a storage capacity of more than 2 pages of data corresponding to the number of bits of data stored in the memory cell transistor MT.

[0156] The selection transistors STD and STS are each used to select the string unit SU. The drain of the selection transistor STD is connected to the associated bit line BL. The source of the selection transistor STD is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The gate of the selection transistor STD included in the string units SU0 to SU3 is connected to the selection gate lines SGD0 to SGD3, respectively. The drain of the selection transistor STS is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the selection transistor STS is connected to the source line SL. The gate of the selection transistor STS is connected to the selection gate line SGS. The source line SL is shared by, for example, a plurality of blocks BLK.

[0157] <4-3> Configuration of Memory Device 100

[0158] An example of the structure of the memory device 100 according to the fourth embodiment is described below. In the fourth embodiment, the X direction corresponds to, for example, the extending direction of the word line WL. The Y direction corresponds to, for example, the extending direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the front surface of the semiconductor substrate (wafer) used when forming the memory device 100.

[0159] Fig.17 1 is a perspective view showing an example of the structure of the memory device 100 according to the fourth embodiment. Fig.17As shown, the memory device 100 includes a memory chip MC and a CMOS chip CC. The memory chip MC includes, for example, a memory region MR, lead regions HR1 and HR2, and a pad region PR1. The CMOS chip CC includes, for example, a sense amplifier region SR, a peripheral circuit region PERI, transfer regions XR1 and XR2, and a pad region PR2.

[0160] The memory region MR includes a memory cell array 103. The lead-out regions HR1 and HR2 include wirings and the like used for connecting the stacked wirings provided in the memory chip MC and the row decoder module 105 provided in the CMOS chip CC. The pad region PR1 includes pads and the like used for connecting the memory device 100 to the memory controller. The lead-out regions HR1 and HR2 sandwich the memory region MR in the X direction. The pad region PR1 is adjacent to the memory region MR and the lead-out regions HR1 and HR2 in the Y direction.

[0161] The sense amplifier region SR includes a sense amplifier module 106. The peripheral circuit region PERI includes a sequencer 102, a driver module 104, etc. The transfer regions XR1 and XR2 include a row decoder module 105. The pad region PR2 includes a memory I / F 101. The sense amplifier region SR and the peripheral circuit region PERI are arranged adjacent to each other in the Y direction and overlap with the memory region MR in the Z direction. The transfer regions XR1 and XR2 sandwich the group of the sense amplifier region SR and the peripheral circuit region PERI in the X direction and overlap with the lead-out regions HR1 and HR2, respectively. The pad region PR2 overlaps with the pad region PR1 of the memory chip MC in the Z direction.

[0162] The memory chip MC has a plurality of bonding pads BP at the bottom of each of the memory region MR, the lead-out regions HR1 and HR2, and the pad region PR1. The bonding pads BP of the memory region MR are connected to the associated bit lines BL. The bonding pads BP of the lead-out region HR are connected to the associated wiring (e.g., word lines WL) among the stacked wirings provided in the memory region MR. The bonding pads BP of the pad region PR1 are connected to pads (not shown) provided on the upper surface of the memory chip MC. The pads provided on the upper surface of the memory chip MC are used, for example, for connection between the memory device 100 and the memory controller.

[0163] The CMOS chip CC has a plurality of bonding pads BP on the upper portions of the sense amplifier region SR, the peripheral circuit region PERI, the transfer regions XR1 and XR2, and the pad region PR2. The bonding pads BP of the sense amplifier region SR overlap with the bonding pads BP of the memory region MR in the Z direction. The bonding pads BP of the transfer regions XR1 and XR2 overlap with the bonding pads BP of the lead-out regions HR1 and HR2 in the Z direction, respectively. The bonding pads BP of the pad region PR1 overlap with the bonding pads BP of the pad region PR2 in the Z direction.

[0164] The memory device 100 has a structure in which the lower surface of the memory chip MC (the front surface of the semiconductor substrate on which the memory chip MC is formed) and the upper surface of the CMOS chip CC (the front surface of the semiconductor substrate on which the CMOS chip CC is formed) are joined. Two bonding pads BP opposing each other between the memory chip MC and the CMOS chip CC among the plurality of bonding pads BP provided in the memory device 100 are electrically connected by being joined. Thus, the circuit in the memory chip MC and the circuit in the CMOS chip CC are electrically connected via the bonding pads BP. The group of two bonding pads BP opposing each other between the memory chip MC and the CMOS chip CC may have a boundary or may be integrated.

[0165] <4-3-1> Structure of the memory cell array 103

[0166] The structure of the memory cell array 103 will be described below.

[0167] (Planar Layout of Memory Cell Array 103)

[0168] Fig.18 It is a plan view showing an example of the plan layout of the memory cell array 103 included in the memory device 100 according to the fourth embodiment. Fig.18 1 shows an area including one block BLK in the memory area MR. Fig.18 As shown, the memory device 100 includes, for example, a plurality of slits SLT, a plurality of slits SHE, a plurality of memory pillars MP, a plurality of bit lines BL, and a plurality of contacts CV. In the memory region MR, the planar layout described below is repeatedly arranged in the Y direction.

[0169] Each slit SLT has, for example, a structure in which an insulating member is embedded. Each slit SLT insulates adjacent wiring (e.g., word lines WL0 to WL7 and selection gate lines SGD and SGS) across the slit SLT. Each slit SLT has a portion extending along the X direction, and crosses the memory region MR and the lead-out regions HR1 and HR2 along the X direction. A plurality of slits SLT are arranged in the Y direction. The region divided by the slit SLT corresponds to the block BLK.

[0170] Each slit SHE has, for example, a structure in which an insulating component is embedded. Each slit SHE insulates adjacent wiring (at least the selection gate line SGD) across the slit SLT. Each slit SHE has a portion extending along the X direction, crossing the memory region MR. A plurality of slits SHE are arranged in the Y direction. In this example, three slits SHE are arranged between adjacent slits SLT. The plurality of regions divided by the slits SLT and SHE correspond to the string units SU0 to SU3, respectively.

[0171] Each memory column MP functions as, for example, one NAND string NS. A plurality of memory columns MP are arranged in a staggered pattern of, for example, 19 columns in the region between two adjacent slits SLT. In addition, counting from the top of the paper, the memory column MP in the 5th column, the memory column MP in the 10th column, and the memory column MP in the 15th column overlap with one slit SHE, respectively.

[0172] Each bit line BL has a portion extending in the Y direction and crosses the region where the plurality of blocks BLK are arranged in the Y direction. The plurality of bit lines BL are arranged in the X direction. Each bit line BL is configured to overlap at least one memory column MP for each string unit SU. In this example, two bit lines BL overlap each memory column MP.

[0173] Each contact CV is provided between one bit line BL among a plurality of bit lines BL overlapping the memory pillar MP and the memory pillar MP. The contact CV electrically connects the memory pillar MP and the bit line BL. In addition, the contact CV between the memory pillar MP and the bit line BL overlapping the slit SHE is omitted.

[0174] (Cross-sectional Structure of Memory Cell Array 103)

[0175] Fig.19 It is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 103 included in the memory device 100 according to the fourth embodiment. Fig.19 2 shows a cross section including the memory pillar MP and the slit SLT in the memory region MR and along the Y direction. Fig.19 As shown, the memory device 100 includes, for example, insulator layers 110 ˜ 118 , conductor layers 120 ˜ 126 , and contacts V1 and V2 .

[0176] The insulator layer 110 is provided, for example, at the bottom layer of the memory chip MC. A wiring used for connecting the conductor layer 120 or the pad PD may also be provided in the layer formed with the insulator layer 110. A conductor layer 120 is provided on the insulator layer 110. An insulator layer 111 is provided on the conductor layer 120. On the insulator layer 111, conductor layers 121 and 112 are alternately provided. On the conductor layer 121 of the uppermost layer, an insulator layer 113 is provided. On the insulator layer 113, conductor layers 122 and 114 are alternately provided. On the conductor layer 122 of the uppermost layer, an insulator layer 115 is provided. On the insulator layer 115, conductor layers 123 and 116 are alternately provided. On the conductor layer 123 of the uppermost layer, an insulator layer 117 is provided. On the insulator layer 117, a conductor layer 124 is provided. An insulator layer 118 is provided on the conductor layer 124. The layer formed with the insulator layer 118 includes contacts V1 and V2, and conductor layers 125 and 126. The contact V1 is provided on the conductor layer 124. The conductor layer 125 is provided on the contact V1. The contact V2 is provided on the conductor layer 125. The conductor layer 126 is provided on the contact V2.

[0177] The conductor layers 120, 121, 122 and 123 each have a plate-shaped portion extending along the XY plane, for example. The conductor layer 124 has a linear portion extending in the Y direction, for example. The conductor layers 120, 121 and 123 are used as the source line SL, the selection gate line SGS and the selection gate line SGD, respectively. The plurality of conductor layers 123 are used as word lines WL0 to WL7 in order from the bottom. The conductor layer 124 is used as the bit line BL. The conductor layers 124 and 125 are connected via the contact V1. The conductor layer 125 and the conductor layer 126 are connected via the contact V2. The conductor layer 126 is in contact with the interface (joining surface) of the memory chip MC and is used as a bonding pad BP. The conductor layer 126 contains, for example, copper.

[0178] The slit SLT has a plate-shaped portion extending along the XZ plane, dividing the insulator layers 111 to 116 and the conductor layers 121 to 123. Each memory column MP is extended along the Z direction, penetrating the insulator layers 111 to 116 and the conductor layers 121 to 123. Each memory column MP includes, for example, a core component 130, a semiconductor layer 131, and a stacked film 132. The core component 130 is an insulator extending along the Z direction. The semiconductor layer 131 covers the core component 130. The lower part of the semiconductor layer 131 is in contact with the conductor layer 120. The stacked film 132 covers the side of the semiconductor layer 131. A contact CV is provided on the semiconductor layer 131. The semiconductor layer 131 is electrically connected to the conductor layer 124 via the contact CV.

[0179] In addition, in the illustrated area, a contact CV corresponding to one memory column MP among the two memory columns MP is indicated. On the memory column MP that is not connected to the contact CV in the area not illustrated, a contact CV is connected. The portion where the memory column MP intersects with the plurality of conductive layers 121 functions as a selection transistor STS. The portion where the memory column MP intersects with the conductive layer 122 functions as a memory single transistor MT. The portion where the memory column MP intersects with the plurality of conductive layers 123 functions as a selection transistor STD. Hereinafter, the wiring layers including the conductive layers 124, 125, and 126 will be referred to as "M0," "M1," and "M2," respectively.

[0180] (Cross-sectional structure of memory pillar MP)

[0181] Fig. 20 An example of a cross-sectional structure of a memory pillar MP provided in the memory device 10 according to the fourth embodiment is shown along Fig.19 Cross-sectional view of line XX-XX. Fig. 20 1 shows a cross section including the memory pillar MP and the conductive layer 122 and parallel to the X direction and the Y direction. Fig. 20 As shown, the stacked film 132 includes, for example, a trench insulating film 133 , an insulating film 134 , and a barrier insulating film 135 .

[0182] The core component 130 is, for example, disposed at the center of the memory column MP. The semiconductor layer 131 surrounds the side of the core component 130. The trench insulating film 133 surrounds the side of the semiconductor layer 131. The insulating film 134 surrounds the side of the trench insulating film 133. The blocking insulating film 135 surrounds the side of the insulating film 134. The conductive layer 122 surrounds the side of the blocking insulating film 135. The semiconductor layer 131 is used as a channel (current path) of the memory single transistors MT0 to MT7 and the selection transistors STD and STS. The trench insulating film 133 and the blocking insulating film 135 each contain, for example, silicon dioxide (SiO2). The insulating film 134 is used as a charge accumulation layer of the memory single transistor MT, for example, containing silicon nitride (SiN). Thus, each memory column MP functions as a NAND string NS.

[0183] <4-3-2> Cross-sectional structure of memory device 100

[0184] Fig.21 It is a cross-sectional view showing an example of the cross-sectional structure of the memory device 100 according to the fourth embodiment. Fig.21 FIG. 4 shows a cross section including the memory region MR and the sense amplifier region SR, that is, a cross section including the memory chip MC and the CMOS chip CC. Fig.21As shown, the memory device 100 includes, for example, a semiconductor substrate 140 , conductive layers GC and 141 ˜ 144 , and contacts CS and C0 ˜ C3 in a sense amplifier region SR.

[0185] The semiconductor substrate 140 is a substrate used when forming the CMOS chip CC. The semiconductor substrate 140 includes a plurality of well regions (not shown). For example, a transistor TR is formed in each of the plurality of well regions. The plurality of well regions are separated by, for example, STI (Shallow Trench Isolation). A conductive layer GC is provided on the semiconductor substrate 140 via a gate insulating film. The conductive layer GC in the sense amplifier region SR is used as a gate electrode of the transistor TR included in the sense amplifier module 106. A contact C0 is provided on the conductive layer GC. Two contacts CS are provided on the semiconductor substrate 140 corresponding to the source and drain of the transistor TR.

[0186] A conductor layer 141 is provided on the contact CS and on the contact C0, respectively. A contact C1 is provided on the conductor layer 141. A conductor layer 142 is provided on the contact C1. The conductor layers 141 and 142 are electrically connected via the contact C1. A contact C2 is provided on the conductor layer 142. A conductor layer 143 is provided on the contact C2. The conductor layers 142 and 143 are electrically connected via the contact C2. A contact C3 is provided on the conductor layer 143. A conductor layer 144 is provided on the contact C3. The conductor layers 143 and 144 are electrically connected via the contact C3. Hereinafter, the wiring layers provided with the conductor layers 141 to 144 are referred to as "D0", "D1", "D2" and "D3", respectively.

[0187] The conductor layer 144 is in contact with the interface (joining surface) of the CMOS chip CC and is used as a bonding pad BP. The conductor layer 144 in the sense amplifier region SR is bonded to the conductor layer 126 in the memory region MR arranged opposite to each other (i.e., the bonding pad BP of the memory chip MC). In addition, each conductor layer 144 in the sense amplifier region SR is electrically connected to one bit line BL. The conductor layer 144 includes, for example, copper. In the memory device 100, the memory chip MC and the CMOS chip CC are joined so that the wiring layer D3 of the CMOS chip CC is adjacent to the wiring layer M2 of the memory chip MC.

[0188] In this example, the semiconductor substrate used when forming the memory chip MC is removed along with the process of forming the pad after the bonding process. In addition, the semiconductor substrate used when forming the memory chip MC may also be retained. In addition, the number of wiring layers of the memory chip MC and the CMOS chip CC can be appropriately changed according to the configuration of the memory device 100.

[0189] <4-4> Effects of the Fourth Embodiment

[0190] In manufacturing the memory device 100 according to the fourth embodiment described above, the exposure method described in the first embodiment or the semiconductor device manufacturing method described in the second and third embodiments can be applied. The following describes a case where the semiconductor device manufacturing method according to the third embodiment is applied to the memory device 100 according to the fourth embodiment.

[0191] For example, in the wiring layer M0, the bit line BL having a portion extending in the Y direction is the main pattern, and the difficulty of overlapping in the X direction is high, but the management specification of overlapping in the Y direction has a margin. In the wiring layer M1, the conductive layer 125 having a portion extending in the X direction is provided, and the difficulty of overlapping in the Y direction is high, but the management specification of overlapping in the X direction has a margin. In the wiring layer M0, since the processing of the pattern is relatively rough, the management specification of overlapping in both the X direction and the Y direction has a margin.

[0192] In this case, in the alignment of the exposure process associated with the wiring layer M0, the upper and lower limit correction mode is preferably applied in the Y direction, and the normal mode is applied in the X direction. Similarly, in the alignment of the exposure process associated with the wiring layer M1, the upper and lower limit correction mode is preferably applied in the X direction, and the normal mode is applied in the Y direction. In the alignment of the exposure process associated with the wiring layer M2, the upper and lower limit correction mode is preferably applied in both the X direction and the Y direction.

[0193] As described above, the alignment of the upper and lower limit correction mode is applied to one or both of the X direction and the Y direction according to the pattern set in each layer. In other wiring layers, the alignment of the upper and lower limit correction mode can also be appropriately applied based on the management specification of the overlap in the X direction and the Y direction. As a result, by applying the manufacturing method of the semiconductor device involved in the third embodiment, the yield of the memory device 100 involved in the fourth embodiment can be improved.

[0194] In addition, the object to which the exposure method described in the first embodiment or the semiconductor device manufacturing method described in the second and third embodiments is applied is not limited to the memory device 100. The object to which the exposure method described in the first embodiment or the semiconductor device manufacturing method described in the second and third embodiments is applied can be any semiconductor device having a junction structure.

[0195] <5> Modifications, etc.

[0196] In the above-mentioned embodiment, the flowchart used in describing the exposure method or the method for manufacturing a semiconductor device is only an example. Each action described using the flowchart may be processed in a different order within a possible range, other processing may be added, or some processing may be omitted. Fig. 9 In the example of performing the exposure processing using the upper and lower limit correction mode in three layers, the present invention is not limited to this. In the second embodiment, the exposure processing using the upper and lower limit correction mode can be performed in two or more layers. Fig.13 In the third embodiment, the exposure process applying the upper and lower limit correction mode in the X direction and / or the Y direction may be performed in two or more layers.

[0197] In the above embodiment, the case where the alignment correction is performed in the upper and lower limit correction mode with both the upper limit value U_Limit and the lower limit value L_Limit of the wafer magnification component set, but the present invention is not limited to this. In the upper and lower limit correction mode, either only the upper limit value U_Limit of the wafer magnification component or only the lower limit value L_Limit of the wafer magnification component can be set. For example, in the case where only the lower limit value L_Limit is set in the upper and lower limit correction mode, Figure 5 In the process of S106, if the value of the wafer magnification component W_Mag_B of the base is greater than L_Limit, the process of S108 is executed. In addition, if only the upper limit value U_Limit is set in the upper and lower limit correction mode, Figure 5 In the process of S106, when the value of the wafer magnification component W_Mag_B of the base is less than U_Limit, the process of S108 is executed. Alignment correction that sets only the upper limit U_Limit or the lower limit L_Limit of the wafer magnification component can be applied independently to the X direction and the Y direction as in the third embodiment.

[0198] As the control device 11, an MPU (Micro Processing Unit), an ASIC (Application Specific Integrated Circuit) or an FPGA (Field-Programmable Gate Array) etc. may be used instead of the CPU. In addition, each of the processes described in the above embodiment may also be implemented by dedicated hardware. In the processes described in the above embodiment, the processes executed by software and the processes executed by hardware may be mixed or only one of them may be implemented.

[0199] The circuit structure, plane layout, and cross-sectional structure of the memory device 100 described in the fourth embodiment can be appropriately changed according to the design of the memory device 100. For example, in the fourth embodiment, a case where a memory chip MC is provided on a CMOS chip CC is illustrated, but a CMOS chip CC may be provided on the memory chip MC. In the fourth embodiment, a case where a memory chip MC is allocated to the lower wafer LW and a CMOS chip CC is allocated to the upper wafer UW is illustrated, but a memory chip MC may be allocated to the upper wafer UW and a CMOS chip CC may be allocated to the lower wafer LW.

[0200] In this specification, "connection" means electrical connection, and does not exclude the case of connection via other elements. "Electrical connection" can be used as long as it can operate in the same way as the electrically connected structure, and can also be separated by an insulator. "Region" can also be regarded as a structure included by the semiconductor substrate. For example, in the case where it is specified that the semiconductor substrate 140 includes a memory region MR, the memory region MR is associated with the region above the semiconductor substrate 140. The bonding pad BP can also be referred to as "bonding metal". The camera 35 of the exposure device 1 can also have a structure that separates the optical system (microscope) from the light receiving sensor. The measuring mechanism equivalent to the camera 35 can also be externally connected to the exposure device 1. In this specification, "overlap deviation" can also be replaced by "position deviation". "Visual recognition" includes observing the object from the desired direction via a microscope or camera.

[0201] Several embodiments of the present invention are described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. An exposure device, wherein: have: a worktable configured to hold a substrate; and a control device for performing exposure processing on the substrate, The control device, during the exposure process, The measurement results of the three or more alignment marks arranged on the substrate are approximated by functions in an orthogonal coordinate system to calculate a calculated value of the magnification component. For the alignment correction value of the magnification component, a first lower limit value and / or a first upper limit value is set, When the calculated value is equal to or greater than a first lower limit value and / or equal to or less than a first upper limit value, the alignment correction value of the magnification component is set to a first correction value, When the first lower limit value is set and the calculated value is smaller than the first lower limit value, the alignment correction value of the magnification component is set to a second correction value that is larger than the calculated value and smaller than the first correction value, When the first upper limit value is set and the calculated value exceeds the first upper limit value, the alignment correction value of the magnification component is set to a third correction value that is larger than the first correction value and smaller than the calculated value.

2. The exposure device according to claim 1, wherein: The second correction value is a value obtained by adding the calculated value to the first correction value and then subtracting the first lower limit value. The third correction value is a value obtained by adding the calculated value to the first correction value and further subtracting the first upper limit value.

3. The exposure device according to claim 1, wherein: The first lower limit value is a value obtained by adding the first correction value to a lower limit management value of the overlay deviation of the magnification component in the target step of the exposure processing. The first upper limit value is a value obtained by adding the first correction value to an upper limit management value of the overlay deviation of the magnification component in the target step of the exposure processing.

4. The exposure device according to claim 1, wherein: The orthogonal coordinate system includes a first direction and a second direction orthogonal to the first direction. The first correction value, the second correction value, and the third correction value are alignment correction values ​​of the magnification component in the first direction, respectively. The control device, during the exposure process, A second lower limit value and / or a second upper limit value are further set for the alignment correction value of the magnification component. When the calculated value is equal to or greater than the second lower limit value and / or equal to or less than the second upper limit value, the alignment correction value of the magnification component in the second direction is set to a fourth correction value, When the second lower limit value is set and the calculated value is smaller than the second lower limit value, the alignment correction value of the magnification component in the second direction is set to a fifth correction value that is larger than the calculated value and smaller than the fourth correction value, When the second upper limit value is set and the calculated value exceeds the second upper limit value, the alignment correction value of the magnification component in the second direction is set to a sixth correction value that is larger than the fourth correction value and smaller than the calculated value, The second lower limit value is different from the first lower limit value, The second upper limit value is different from the first upper limit value.

5. The exposure device according to claim 1, wherein: The orthogonal coordinate system includes a first direction and a second direction orthogonal to the first direction. The first correction value, the second correction value, and the third correction value are alignment correction values ​​of the magnification component in the first direction, respectively. The control device sets the alignment correction value of the magnification component in the second direction to a value substantially the same as the calculated value in the exposure process.

6. An exposure method, wherein: The steps include: The measurement results of three or more alignment marks arranged on the substrate are approximated by functions in an orthogonal coordinate system to calculate a calculated value of the magnification component; Setting a first lower limit value and / or a first upper limit value for the alignment correction value of the magnification component; When the calculated value is equal to or greater than a first lower limit value and / or equal to or less than a first upper limit value, setting the alignment correction value of the magnification component to a first correction value; When the first lower limit value is set and the calculated value is smaller than the first lower limit value, the alignment correction value of the magnification component is set to a second correction value that is larger than the calculated value and smaller than the first correction value; as well as When the first upper limit value is set and the calculated value exceeds the first upper limit value, the alignment correction value of the magnification component is set to a third correction value that is larger than the first correction value and smaller than the calculated value.

7. The exposure method according to claim 6, wherein: The second correction value is a value obtained by adding the calculated value to the first correction value and then subtracting the first lower limit value. The third correction value is a value obtained by adding the calculated value to the first correction value and further subtracting the first upper limit value.

8. The exposure method according to claim 6, wherein: The first lower limit value is a value obtained by adding the first correction value to a lower limit management value of the overlay deviation of the magnification component in the target step of the exposure process. The first upper limit value is a value obtained by adding the first correction value to an upper limit management value of the overlay deviation of the magnification component in the target step of exposure processing.

9. The exposure method according to claim 6, wherein: The orthogonal coordinate system includes a first direction and a second direction orthogonal to the first direction. The first correction value, the second correction value, and the third correction value are alignment correction values ​​of the magnification component in the first direction, respectively. The exposure method further comprises the following steps: Further setting a second lower limit value and / or a second upper limit value for the alignment correction value of the magnification component; When the calculated value is greater than or equal to the second lower limit value and / or less than or equal to the second upper limit value, the alignment correction value of the magnification component in the second direction is set to a fourth correction value; When the second lower limit value is set and the calculated value is smaller than the second lower limit value, the alignment correction value of the magnification component in the second direction is set to a fifth correction value that is larger than the calculated value and smaller than the fourth correction value; as well as When the second upper limit value is set and the calculated value exceeds the second upper limit value, the alignment correction value of the magnification component in the second direction is set to a sixth correction value that is larger than the fourth correction value and smaller than the calculated value, The second lower limit value is different from the first lower limit value, The second upper limit value is different from the first upper limit value.

10. The exposure method according to claim 6, wherein: The orthogonal coordinate system includes a first direction and a second direction orthogonal to the first direction. The first correction value, the second correction value, and the third correction value are alignment correction values ​​of the magnification component in the first direction, respectively. The exposure method further comprises the following steps: The alignment correction value of the magnification component in the second direction is set to a value substantially the same as the calculated value.

11. A method for manufacturing a semiconductor device, wherein: The first exposure process includes the following steps: The measurement results of three or more alignment marks arranged on the substrate are approximated by functions in an orthogonal coordinate system to calculate a first calculated value of the magnification component. Setting a first lower limit value and / or a first upper limit value for the alignment correction value of the magnification component; When the first calculated value is equal to or greater than a first lower limit value and / or equal to or less than a first upper limit value, setting the alignment correction value of the magnification component to a first correction value; When the first lower limit value is set and the first calculated value is smaller than the first lower limit value, the alignment correction value of the magnification component is set to a second correction value that is larger than the first calculated value and smaller than the first correction value; as well as When the first upper limit value is set and the first calculated value exceeds the first upper limit value, the alignment correction value of the magnification component is set to a third correction value that is larger than the first correction value and smaller than the first calculated value.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The second correction value is a value obtained by adding the first calculated value to the first correction value and then subtracting the first lower limit value. The third correction value is a value obtained by adding the first calculated value to the first correction value and further subtracting the first upper limit value.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: The first lower limit value is a value obtained by adding the first correction value to a lower limit management value of the overlay deviation of the magnification component in the first exposure step. The first upper limit value is a value obtained by adding the first correction value to an upper limit management value of the overlay deviation of the magnification component in the first exposure step.

14. The method for manufacturing a semiconductor device according to claim 11, wherein: The orthogonal coordinate system includes a first direction and a second direction orthogonal to the first direction. The first correction value, the second correction value, and the third correction value are alignment correction values ​​of the magnification component in the first direction, respectively. The first exposure process also includes the following steps: Further setting a second lower limit value and / or a second upper limit value for the alignment correction value of the magnification component; When the first calculated value is equal to or greater than a second lower limit value and / or equal to or less than a second upper limit value, setting the alignment correction value of the magnification component in the second direction to a fourth correction value; When the second lower limit value is set and the first calculated value is smaller than the second lower limit value, the alignment correction value of the magnification component in the second direction is set to a fifth correction value that is larger than the first calculated value and smaller than the fourth correction value; as well as When the second upper limit value is set and the first calculated value exceeds the second upper limit value, the alignment correction value of the magnification component in the second direction is set to a sixth correction value that is larger than the fourth correction value and smaller than the first calculated value, The second lower limit value is different from the first lower limit value, The second upper limit value is different from the first upper limit value.

15. The method for manufacturing a semiconductor device according to claim 11, wherein: The orthogonal coordinate system includes a first direction and a second direction orthogonal to the first direction. The first correction value, the second correction value, and the third correction value are alignment correction values ​​of the magnification component in the first direction, respectively. The first exposure process also includes the following steps: The alignment correction value of the magnification component in the second direction is set to a value substantially the same as the first calculated value.

16. The method for manufacturing a semiconductor device according to claim 11, wherein: The second exposure process after the first exposure process on the substrate includes the following steps: performing function approximation on measurement results of three or more alignment marks arranged on the substrate in an orthogonal coordinate system to calculate a second calculated value of the magnification component; For the alignment correction value of the magnification component, a third lower limit value and / or a third upper limit value is set; When the second calculated value is equal to or greater than a third lower limit value and / or equal to or less than a third upper limit value, setting the alignment correction value of the magnification component to a seventh correction value; When the third lower limit value is set and the second calculated value is smaller than the third lower limit value, the alignment correction value of the magnification component is set to an eighth correction value that is larger than the second calculated value and smaller than the seventh correction value; as well as When the third upper limit value is set and the second calculated value exceeds the third upper limit value, the alignment correction value of the magnification component is set to a ninth correction value that is larger than the seventh correction value and smaller than the second calculated value.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The orthogonal coordinate system includes a first direction and a second direction orthogonal to the first direction. The first correction value, the second correction value, and the third correction value are alignment correction values ​​of the magnification component in the first direction, respectively. The seventh correction value, the eighth correction value, and the ninth correction value are alignment correction values ​​of the magnification component in the second direction, respectively.

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