Regulator and circuit arrangement

Abstract

Regulators and circuit arrangements are provided. A regulator that regulates an input voltage and outputs an output voltage includes: a voltage divider circuit that outputs, as a feedback voltage, a voltage obtained by dividing the output voltage; an operational amplifier that compares the feedback voltage with a reference voltage; a driving transistor provided between a node of the input voltage and a node of the output voltage, the driving transistor being controlled based on an output of the operational amplifier; a logic circuit that outputs an adjustment signal of the output voltage; and an output voltage adjustment circuit that adjusts the output voltage on the basis of the adjustment signal. The voltage division circuit includes a plurality of resistors and a plurality of switches, each of the plurality of switches is provided in parallel with each of the plurality of resistors, and the output voltage adjustment circuit outputs a control signal corresponding to the adjustment signal to the plurality of switches and supplies an output voltage to the output voltage adjustment circuit as a power supply voltage.

Description

Technical Field

[0001] The invention relates to a regulator and a circuit arrangement. Background Art

[0002] Patent document 1 describes a control device for controlling power supply when discharging power from a battery is supplied to a power supply target. Figure 6 et al. disclose a regulator that regulates an input voltage and outputs an output voltage.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2017-143704

[0004] It is known that in such a regulator, the output voltage may become unstable, for example, at the time of initial setting of the regulator, at the start of operation, or during operation. Summary of the invention

[0005] One embodiment of the present disclosure relates to a regulator that adjusts an input voltage and outputs an output voltage. The regulator includes: a voltage divider circuit that outputs a voltage obtained by dividing the output voltage as a feedback voltage; an operational amplifier that compares the feedback voltage with a reference voltage; a driving transistor that is arranged between a node of the input voltage and a node of the output voltage and is controlled based on the output of the operational amplifier; a logic circuit that outputs an adjustment signal for the output voltage; and an output voltage adjustment circuit that adjusts the output voltage based on the adjustment signal. The voltage divider circuit includes: a plurality of resistors; and a plurality of switches, each of the plurality of switches being arranged in parallel with each of the plurality of resistors. The output voltage adjustment circuit outputs a control signal corresponding to the adjustment signal to the plurality of switches, and provides the output voltage as a power supply voltage to the output voltage adjustment circuit.

[0006] In addition, other embodiments of the present disclosure relate to a circuit device, which includes: the regulator described above; a charging circuit that charges a charging object based on the input voltage; and a charging control circuit that controls the charging circuit to provide the output voltage as a power supply voltage for the charging control circuit or a power supply voltage for a detection circuit of the charging control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a configuration example of the regulator according to this embodiment.

[0008] Figure 2 This is a detailed configuration example of the regulator according to this embodiment.

[0009] Figure 3 It is a signal waveform diagram illustrating the operation of the regulator.

[0010] Figure 4 It is an explanatory diagram of the problem of the comparative example.

[0011] Figure 5 3 is a signal waveform diagram of each node in the comparative example.

[0012] Figure 6 3 is a signal waveform diagram of each node in this embodiment.

[0013] Figure 7 This is a detailed configuration example of a voltage divider circuit.

[0014] Figure 8 This is a diagram for explaining a method of setting the output voltage to a given set voltage.

[0015] Fig. 9 This is a configuration example of a circuit device according to this embodiment.

[0016] Description of symbols

[0017] 2: Circuit device; 10, 12: Regulator; 20: Voltage divider circuit; 21: First resistor group; 22: Second resistor group; 30: Output voltage adjustment circuit; 40: Logic circuit; 42: Initial value register; 48: Non-volatile memory; 50: Rectifier circuit; 60: Charging circuit; 62: Charging control circuit; 70: Detection circuit; 72: A / D conversion circuit; 80: Power supply circuit; 100: Power transmission device; 110: Battery; 120: Power supply object; AS, AS1~AS7: Adjustment signal; BF1~BF4: Drive circuit; CS, CS1~CS7, XCS1~XCS4: Control signal No.; IV11~IV24: inverter; LS1~LS4: level shifter; NT1~NT4: transistor; OP: operational amplifier; R0~R5, RA1~RA7, RB1~RB7, RC3, RC4: resistor; SA1~SA7, SB1~SB7, SW1~SW4, SWC4: switch; TF1~TF4: transmission gate; TR: driving transistor; VBT: battery voltage; VD5: input voltage; VDD: output voltage; VFB: feedback voltage; VRF: reference voltage; XEN: enable signal; XPOR: power-on reset signal; DASW: data switching signal. DETAILED DESCRIPTION

[0018] The preferred embodiment of the present invention will be described in detail below. The embodiment described below does not unduly limit the content of the present invention described in the claims, and not all structures described in the embodiment are necessarily essential as the solution means of the present invention.

[0019] 1. Regulator

[0020] Figure 1 The following is a structural example of the regulator 10 of the present embodiment. The regulator 10 is a circuit that adjusts the input voltage VD5 and outputs the output voltage VDD. For example, the regulator 10 generates and outputs the regulated voltage VDD, which is the output voltage VDD after the input voltage VD5 is stepped down, based on the reference voltage VRF. In this way, for example, a reference voltage VRF generated by a reference voltage generating circuit (not shown) such as a bandgap reference circuit can be used to generate a constant voltage output voltage VDD after the input voltage VD5 is adjusted. The input voltage VD5 is, for example, the first power supply voltage, and the output voltage VDD is, for example, the second power supply voltage. As an example, the input voltage VD5 is about 5.0V to 3.5V, and the output voltage VDD is, for example, about 1.8V. The regulator 10 includes a voltage divider circuit 20, an operational amplifier OP, a driving transistor TR, an output voltage adjustment circuit 30, and a logic circuit 40. In addition, the regulator 10 is not limited to Figure 1 , described later Figure 2 , Figure 7 The structures of the present invention may be modified in various ways, such as omitting some of the structural elements, adding other structural elements, replacing some of the structural elements with other structural elements, etc.

[0021] The voltage divider circuit 20 outputs a voltage obtained by dividing the output voltage VDD as the feedback voltage VFB. For example, the voltage divider circuit 20 as a voltage division circuit outputs a voltage obtained by dividing the output voltage VDD by a resistor as the feedback voltage VFB. The feedback voltage VFB is a voltage divided by the voltage divider circuit 20 from the output voltage VDD.

[0022] The operational amplifier OP compares the feedback voltage VFB from the voltage divider circuit 20 with the reference voltage VRF. For example, the operational amplifier OP has a first input terminal and a second input terminal. The first input terminal is, for example, an inverting input terminal, and the second input terminal is, for example, a non-inverting input terminal. Moreover, the reference voltage VRF is input to the first input terminal of the operational amplifier OP, and the feedback voltage VFB is input to the second input terminal. Then, the operational amplifier OP outputs a signal based on the difference between the feedback voltage VFB and the reference voltage VRF. The operational amplifier OP is, for example, a differential amplifier circuit having a differential portion to which the reference voltage VRF and the feedback voltage VFB are differentially input and an output portion to which the output of the differential portion is input, and operates, for example, using the input voltage VD5 as a power supply voltage.

[0023] The driving transistor TR is provided between a node NV5 of an input voltage VD5 and a node NVD of an output voltage VDD. The driving transistor TR is controlled based on the output of the operational amplifier OP. For example, the output signal of the operational amplifier OP is input to the gate of the driving transistor TR to control the driving transistor TR. Figure 1In the embodiment, the driving transistor TR is a P-type MOS transistor. For example, the source of the driving transistor TR is connected to the node NV5 of VD5, the gate is connected to the output of the operational amplifier OP, and the drain is connected to the node NVD of VDD. In addition, the driving transistor TR is not limited thereto, and may also be an N-type MOS transistor or a bipolar transistor. For example, when an N-type transistor is used as the driving transistor TR, a reference voltage VRF is input to the non-inverting input terminal of the operational amplifier OP, and a feedback voltage VFB is input to the inverting input terminal.

[0024] The logic circuit 40 outputs adjustment signals AS1 to AS4 of the output voltage VDD. The adjustment signals AS1 to AS4 are signals for adjusting the voltage value of the output voltage VDD and may also be referred to as adjustment codes of the output voltage VDD. Figure 1 In the embodiment, the logic circuit 40 outputs four adjustment signals AS1 to AS4 corresponding to four bits, but the present embodiment is not limited thereto, and for example, five or more adjustment signals may be used. The logic circuit 40 is a control circuit, and as an example, can be implemented by a circuit of an ASIC (Application Specific Integrated Circuit) based on automatic configuration and wiring such as a gate array.

[0025] The output voltage adjustment circuit 30 adjusts the output voltage VDD according to the adjustment signals AS1 to AS4. For example, the output voltage adjustment circuit 30 adjusts the output voltage VDD by controlling the voltage dividing circuit 20 based on the adjustment signals AS1 to AS4.

[0026] Specifically, if Figure 1 As shown in FIG. 1 , the voltage divider circuit 20 includes a plurality of resistors R0 to R5 and a plurality of switches SW1 to SW4. Each switch of the switches SW1 to SW4 is connected in parallel with each resistor of the plurality of resistors R1 to R4. Figure 1 In the voltage divider circuit 20, resistors R0 and R5 without switches connected in parallel are also provided. Resistors R0 to R5 are connected in series between the node NVD of VDD and the node NS of VSS to form a ladder resistor circuit. The node of VSS is a node of a specified voltage, for example, a node of a voltage of 0V corresponding to GND, but is not limited thereto. For example, resistor R1 and switch SW1 are connected in parallel between node N1 and node N2 of the voltage divider circuit 20, and resistor R2 and switch SW2 are connected in parallel between node N2 and node NF. In addition, resistor R3 and switch SW3 are connected in parallel between node NF and node N3 of the voltage divider circuit 20, and resistor R4 and switch SW4 are connected in parallel between node N3 and node N4. In addition, resistor R0 without switches connected in parallel is provided between node NVD and node N1, and resistor R5 without switches connected in parallel is provided between node N4 and node NS. In addition, in Figure 1In order to simplify the description, an example is shown in which the number of resistors is 6 and the number of switches is 4, but the number of resistors and the number of switches in the voltage divider circuit 20 are not limited to 4. Figure 1 The number of is arbitrary.

[0027] Moreover, the output voltage adjustment circuit 30 outputs control signals CS1 to CS4 corresponding to the adjustment signals AS1 to AS4 to a plurality of switches SW1 to SW4. The control signals CS1 to CS4 are signals for turning the switches SW1 to SW4 on or off. For example, when the control signals of CS1 to CS4 are at an effective level, the switches to which the control signals are input are turned on, and when the control signals are at an ineffective level, the switches to which the control signals are input are turned off. The effective level is, for example, a high level, and the ineffective level is, for example, a low level. For example, it is assumed that a resistor R and a switch SW are arranged in parallel between a node NA and a node NB. In this case, when the switch SW is turned on, the node NA and the node NB are short-circuited, and the resistor R is bypassed. On the other hand, when the switch SW is turned off, the resistance value between the node NA and the node NB is set by the resistor R. In addition, the on-resistance of the transistor that actually constitutes the switch SW also contributes to the resistance value between the node NA and the node NB.

[0028] For example, the voltage divider circuit 20 outputs the feedback voltage VFB from the node NF which is the feedback voltage node. For example, the resistance value of the voltage divider circuit 20 between the node NF and the node NS is r1, and the resistance value of the voltage divider circuit 20 between the node NVD and the node NF is r2. The resistance value r1 is the resistance value of the series connection of the resistors R3, R4, and R5, and the resistance value r2 is the resistance value of the series connection of the resistors R0, R1, and R2. In this case, the output voltage VDD of the regulator 10 is expressed as shown in the following formula (1).

[0029] VDD={(r1+r2) / r1}×VRF…(1)

[0030] According to the control signals CS1 to CS4 from the output voltage adjustment circuit 30, the switches SW1 to SW4 are turned on or off, and the resistance values ​​r1 and r2 in the above formula (1) are set to adjust the voltage value of the output voltage VDD. Thus, even when the reference voltage VRF and the resistance value of the resistor vary due to, for example, semiconductor process variations, the regulator 10 can output the output voltage VDD with high voltage accuracy.

[0031] Furthermore, in this embodiment, if Figure 1As shown, the output voltage VDD is provided as the power supply voltage to the output voltage adjustment circuit 30. For example, the output voltage adjustment circuit 30 uses the output voltage VDD as the power supply voltage and outputs the control signals CS1 to CS4 to the switches SW1 to SW4. For example, the high-level voltage of the control signals CS1 to CS4 becomes the voltage level of the output voltage VDD as the power supply voltage.

[0032] For example, in order to appropriately control the on / off of the switches SW1 to SW4 of the voltage dividing circuit 20 , it is preferable that the output voltage adjustment circuit 30 is supplied with an input voltage VD5 higher than VDD as a power supply voltage and outputs the control signals CS1 to CS4 .

[0033] However, when the voltage level of the control signals CS1 to CS4 for adjusting the output voltage VDD changes, the feedback voltage VFB of the voltage divider circuit 20 fluctuates due to the change in the voltage level. And the voltage fluctuation is transmitted to the input voltage VD5 via the driving transistor TR, etc., and a voltage fluctuation occurs in the input voltage VD5. For example, a situation occurs where both the input voltage VD5 and the output voltage VDD fluctuate. In this case, when the output voltage adjustment circuit 30 generates the control signals CS1 to CS4 using the input voltage VD5 as the power supply voltage instead of the output voltage VDD, the voltage fluctuation of the input voltage VD5 is transmitted to the control signals CS1 to CS4, and a situation occurs where the feedback voltage VFB fluctuates again. As a result, a situation occurs where the voltage fluctuations of the input voltage VD5 and the output voltage VDD do not converge. For example, the input voltage VD5 and the output voltage VDD fluctuate with different phases, and a situation occurs where both the voltages of VD5 and VDD do not converge, and a problem occurs where the output of the regulator 10 is unstable.

[0034] In this regard, in the present embodiment, the output voltage adjustment circuit 30 outputs the control signals CS1 to CS4 using the output voltage VDD instead of the input voltage VD5 as the power supply voltage. Therefore, even if the feedback voltage VFB fluctuates and the input voltage VD5 fluctuates due to changes in the control signals CS1 to CS4, the fluctuation of the input voltage VD5 can be suppressed from being transmitted to the output voltage adjustment circuit 30 as the fluctuation of the power supply voltage. Therefore, it is possible to effectively prevent the output of the regulator 10 from being unstable due to the situation that neither the input voltage VD5 nor the output voltage VDD converges.

[0035] Figure 2 A detailed configuration example of the regulator 10 according to this embodiment is shown. Figure 2In the voltage divider circuit 20, each of the multiple switches SW1 to SW4 is composed of an N-type transistor and a P-type transistor connected in parallel. For example, the switches SW1 to SW4 are realized by transmission gates TF1 to TF4 in which an N-type transistor and a P-type transistor are connected in parallel. Moreover, the output voltage adjustment circuit 30 includes: inverters IV11 to IV14, which output control signals XCS1 to XCS4; and inverters IV21 to IV24, which are input with the outputs of the inverters IV11 to IV14 and output control signals CS1 to CS4. Adjustment signals AS1 to AS4, for example, from the logic circuit 40 are input to the inverters IV11 to IV14. Inverter IV11 to IV14 is the first inverter, and the control signal XCS1 to XCS4 is the first control signal. In Figure 2 In the embodiment, the P-type transistors of switches SW1 to SW4 (TF1 to TF4) are controlled by XCS1 to XCS4 as the first control signals. However, N-type transistors may also be controlled by the first control signal. In addition, inverters IV21 to IV24 are second inverters, and control signals CS1 to CS4 are second control signals. Figure 2 In the embodiment, the N-type transistors of the switches SW1 to SW4 (TF1 to TF4) are controlled by CS1 to CS4 as the second control signals. However, the P-type transistors may also be controlled by the second control signal. Here, the output voltage VDD is provided to the inverters IV11 to IV14 and the inverters IV21 to IV24 as the power supply voltage. Thus, the output voltage adjustment circuit 30 includes: a first inverter, which outputs a first control signal for controlling one of the N-type transistors and the P-type transistors of the switches SW1 to SW4; and a second inverter, which receives the output of the first inverter and outputs a second control signal for controlling the other of the N-type transistors and the P-type transistors of the switches SW1 to SW4.

[0036] In this way, Figure 2 In the embodiment, each switch of switches SW1 to SW4 is composed of an N-type transistor and a P-type transistor connected in parallel, and the output voltage adjustment circuit 30 outputs control signals XCS1 to XCS4, CS1 to CS4 that turn these N-type transistors and P-type transistors on and off (conducting and cutting off). According to such a structure, the on-resistance of switches SW1 to SW4 when they are turned on can be reduced, and switches SW1 to SW4 can be properly turned on by the control signal from the output voltage adjustment circuit 30. For example, in the present embodiment, an output voltage VDD lower than the input voltage VD5 is used as the power supply voltage of the output voltage adjustment circuit 30. Therefore, in the case where switches SW1 to SW4 are composed of only N-type transistors, for example, the on-resistance of the switch near the node NVD of the output voltage VDD may become very high, or it may not be properly turned on. In this regard, in Figure 2In the embodiment, switches SW1 to SW4 are composed of N-type transistors and P-type transistors connected in parallel. Therefore, for example, when the N-type transistors are not properly turned on, switches SW1 to SW4 can be properly turned on by turning on the P-type transistors.

[0037] In addition, Figure 2 In the embodiment, the logic circuit 40 includes an initial value register 42. The initial value register 42 is a register for storing the initial value of the adjustment value of the output voltage VDD, and can be realized by a storage circuit such as a flip-flop circuit, for example. Moreover, the logic circuit 40 outputs adjustment signals AS1 to AS4 according to the initial value of the adjustment value of the output voltage VDD from the initial value register 42 after power-on reset. For example, after the power-on reset is released, the logic circuit 40 generates adjustment signals AS1 to AS4 according to the initial value of the adjustment value of the output voltage VDD stored in the initial value register 42, and outputs them to the output voltage adjustment circuit 30. The output voltage adjustment circuit 30 outputs control signals XCS1 to XCS4 and CS1 to CS4, which are buffered adjustment signals AS1 to AS4 based on the initial value of the adjustment value of the output voltage VDD, to the voltage divider circuit 20, and controls the on / off of switches SW1 to SW4. In this way, the on / off of the switches SW1 to SW4 is controlled by the control signal based on the initial value of the adjustment value, thereby setting the resistance ratio in the voltage divider circuit 20 to the resistance ratio corresponding to the initial value, and setting the output voltage VDD to the voltage corresponding to the initial value of the adjustment value. In this way, after the power-on reset, the on / off of the switches SW1 to SW4 can be appropriately controlled, and the output voltage VDD can be set to the voltage corresponding to the initial value of the adjustment value.

[0038] In addition, Figure 2 In the embodiment, the logic circuit 40 outputs adjustment signals AS1 to AS4 according to the adjustment value of the output voltage VDD read from the nonvolatile memory 48. That is, the nonvolatile memory 48 is provided in the following Fig. 9The circuit device 2 having the regulator 10 described in the above embodiment stores the adjustment value of the output voltage VDD. The nonvolatile memory 48 is, for example, an EEPROM such as a FAMOS (Floatinggate Avalanche injection MOS) memory or a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) memory, but is not limited thereto and may also be an OTP (One Time Programmable) memory or a fuse-type ROM. For example, during the manufacture or inspection of the semiconductor of the circuit device 2, the adjustment value of the output voltage VDD is determined by monitoring the output voltage VDD using a measuring device such as a tester. That is, the adjustment value for setting the output voltage VDD to a voltage of a desired specification is determined, and the determined adjustment value is written into the nonvolatile memory 48 of the circuit device 2. Furthermore, when the circuit device 2 is operating, the logic circuit 40 reads the adjustment value from the nonvolatile memory 48 and generates adjustment signals AS1 to AS4 based on the read adjustment value. The output voltage adjustment circuit 30 outputs control signals XCS1 to XCS4 and CS1 to CS4, which are buffered adjustment signals AS1 to AS4 based on the adjustment value of the output voltage VDD, to the voltage divider circuit 20 to control the on / off of the switches SW1 to SW4. In this way, by controlling the on / off of the switches SW1 to SW4 with control signals based on the adjustment value stored in the nonvolatile memory 48, the resistance ratio in the voltage divider circuit 20 is set to a resistance ratio corresponding to the adjustment value, and the output voltage VDD is set to a voltage corresponding to the adjustment value. In this way, the on / off of the switches SW1 to SW4 can be appropriately controlled according to the adjustment value stored in the nonvolatile memory 48, and the output voltage VDD can be set to a voltage corresponding to the adjustment value.

[0039] In addition, Figure 2 In the embodiment, the output voltage VDD is provided as a power supply voltage to both the output voltage adjustment circuit 30 and the logic circuit 40. That is, the output voltage VDD is provided as a power supply voltage to the output voltage adjustment circuit 30, and the output voltage VDD is also provided to the logic circuit 40. In this way, the logic circuit 40 can be operated according to the output voltage VDD generated by the regulator 10, and the adjustment signals AS1 to AS4 can be generated, and the adjustment signals AS1 to AS4 are input to the output voltage adjustment circuit 30 that operates with the same output voltage VDD as the power supply voltage. In addition, the voltage divider circuit 20 is controlled by the control signals CS1 to CS4 and the control signals XCS1 to XCS4, so that the output voltage VDD can be adjusted.

[0040] Figure 31 is a signal waveform diagram for explaining the operation of the regulator 10 of the present embodiment. When the input voltage VD5 of the regulator 10 rises and the output voltage VDD of the regulator 10 rises, a power-on reset is performed according to the power-on reset signal XPOR from the power-on reset circuit. For example, the negative logic enable signal XEN is a signal for starting the regulator 10 and becomes a low level as an effective level. And, when the negative logic power-on reset signal XPOR becomes a high level, the reset state of the logic circuit 40 is released, as shown in FIG. Figure 3 As shown in A2 of FIG. 1 , the initial value of the adjustment value of the output voltage VDD is read from the initial value register 42, and the adjustment signals AS1 to AS4 corresponding to the initial value are output from the logic circuit 40 to the output voltage adjustment circuit 30. Then, the output voltage adjustment circuit 30 outputs a control signal corresponding to the initial value to the voltage divider circuit 20, thereby setting the resistance value (resistance ratio) of the voltage divider circuit 20, and outputting the output voltage VDD corresponding to the initial value from the regulator 10. The output voltage VDD corresponding to the initial value is a voltage of about 1.8V as a typical value.

[0041] After that, when the data switching signal DASW becomes a high level as an effective level after a given period, the adjustment value of the output voltage VDD stored in the nonvolatile memory 48 is read out. Then, the adjustment signals AS1 to AS4 corresponding to the adjustment value are output from the logic circuit 40 to the output voltage adjustment circuit 30. The adjustment value is a value set by monitoring the output voltage VDD when manufacturing the circuit device 2 having the regulator 10, etc. Then, the output voltage adjustment circuit 30 outputs a control signal corresponding to the adjustment value to the voltage divider circuit 20, thereby setting the resistance value of the voltage divider circuit 20, and outputting the output voltage VDD corresponding to the adjustment value from the regulator 10. As a result, the output voltage VDD in which the influence of the manufacturing variation of the semiconductor is reduced is output from the regulator 10, and the output voltage VDD with high voltage accuracy can be output.

[0042] As described above, in this embodiment, in the regulator 10 that outputs a constant voltage, in order to improve the unstable behavior of the regulator output when the output voltage VDD changes dynamically due to the loading of data from the initial value register 42 and the non-volatile memory 48, its own output voltage VDD is provided for the power supply of the output voltage adjustment circuit 30.

[0043] For example, Figure 4 The structure of the regulator 10 of the comparative example of the present embodiment is shown. The regulator 10 is supplied with an input voltage VD5 of 3.5V to 5.0V from a high withstand voltage HV (high voltage) regulator (not shown) as a power supply, and outputs a constant voltage output voltage VDD of, for example, 1.8V. The output voltage VDD is used as a logic circuit 40 and a control circuit described later. Fig. 9The detection circuit 70 and the charging control circuit 62 are used as the power supply of the detection circuit 70 and the charging control circuit 62. In addition, in order to improve the voltage accuracy of the output voltage VDD, the regulator 10 has an output voltage adjustment circuit 30. Moreover, the output voltage adjustment circuit 30 is composed of a drive circuit BF1 to BF4 that outputs control signals CS1 to CS4 of switches SW1 to SW4 that adjust the feedback resistance ratio of the voltage divider circuit 20. The drive circuit BF1 to BF4 uses the input voltage VD5 of the regulator from HV as a power supply, and the switches SW1 to SW4 are composed of only N-type MOS transistors NT1 to NT4. In addition, level shifters LS1 to LS4 are provided in the output voltage adjustment circuit 30, and the level shifters LS1 to LS4 are used to shift the voltage level of the adjustment signals AS1 to AS4 from the logic circuit 40 that uses 1.8V VDD as a power supply. In addition, data for adjusting VDD to 1.8V is stored in the non-volatile memory 48. When the voltage of VD5 becomes higher than the specified voltage level, the power-on reset is released and the logic circuit 40 starts to operate. When the logic circuit 40 starts operating, an initial value is loaded into the output voltage adjustment circuit 30, and after a predetermined time, the data of the VDD adjustment value stored in the nonvolatile memory 48 is loaded. The output voltage adjustment circuit 30 selects a resistance value according to the data of the VDD adjustment value, thereby obtaining a desired voltage of VDD=1.8V.

[0044] Thus, in the regulator 10, the data of the adjustment value of the output voltage VDD is dynamically switched during the circuit operation. In addition, in the voltage divider circuit 20, switches SW1 to SW4 are provided in parallel with the resistors R1 to R4 for feedback, and parasitic capacitance exists between the gate and the drain and between the gate and the source in these switches SW1 to SW4. Figure 4 In the embodiment, the input voltage VD5 is used as the power supply of the drive circuits BF1 to BF4 of the switches SW1 to SW4.

[0045] And, by adjusting the switching of values, such as Figure 4 As shown in (1), when the adjustment signals AS1 to AS4 from the logic circuit 40 change, the voltage levels of the control signals CS1 to CS4 based on the adjustment signals AS1 to AS4 change. Furthermore, when the switches SW1 to SW4 controlled by the control signals CS1 to CS4 change from on to off or from off to on, the potential of the gate of the N-type transistor of each switch changes from VD5 to VSS or from VSS to VD5. Then, as Figure 4 As shown in (2), the change in gate potential is transmitted to the node NF of the feedback voltage VFB via parasitic capacitance between the gate and the drain and between the gate and the source. Figure 4 As shown in (3), the feedback voltage VFB unexpectedly fluctuates. After the unexpected feedback voltage VFB fluctuates, Figure 4The operational amplifier OP of (4) controls the output voltage VDD with delay, so the result is as follows Figure 4 As shown in (5), the output voltage VDD of the regulator 10 also fluctuates, and a condition such as output ringing (ringing) occurs, which is a state in which the output is unstable. For example, when VD5 outputted by the HV regulator is used as the power supply of the regulator 10 for VDD, while the output of VDD, which is the load of VD5, fluctuates, Figure 4 As shown in (6), the voltage level of VD5 fluctuates, and the output voltages of VDD and VD5 fluctuate with each other, thereby causing a situation in which the voltages of VD5 and VDD do not converge.

[0046] In this regard, Figure 1 , Figure 2 In the present embodiment, the power supply of the inverters IV11 to IV24, which are the driving circuits that output control signals to the switches SW1 to SW4, is VDD. Therefore, when the adjustment value of the output voltage VDD changes dynamically, the feedback voltage VFB fluctuates via the parasitic capacitance between the gate and source and the parasitic capacitance between the gate and drain of the switches SW1 to SW4, but since there is no circuit loop that causes VD5 and VDD to interfere with each other, the voltage of VDD converges easily. In addition, in the present embodiment, the switches SW1 to SW4 that short-circuit the feedback resistor are composed of P-type transistors and N-type transistors. In this way, even if the power supply of the output voltage adjustment circuit 30 is changed to VDD lower than VD5, the switches SW1 to SW4 that short-circuit the feedback resistor can obtain the desired on-resistance characteristics. For example, when Figure 4 When switches SW1 to SW4 are composed only of N-type transistors as in the comparative example, there is a possibility that the on-resistance of the switch at the node NVD close to VDD becomes too high or the switch is not properly turned on. However, this situation can be prevented if the switch is composed of a pair of P-type transistors and N-type transistors.

[0047] Figure 5 Yes means Figure 4 FIG. 1 is a diagram of signal waveforms at each node in a comparative example. Figure 5 AS[6:0] corresponds to the following Figure 7 The adjustment signals AS1 to AS7, CS correspond to the control signals CS1 to CS7, XCS1 to XCS7. Figure 5In B1 of FIG. 1 , the adjustment signal AS[6:0] changes by reading the initial value from the initial value register 42 and the adjustment value from the nonvolatile memory 48. As a result, as shown in B2, the gate voltage of the transistors NT1 to NT4 constituting the switches SW1 to SW4, that is, the voltage level of the control signal CS changes. This voltage change is transmitted via the parasitic capacitance between the gate and the source and between the gate and the drain of the transistors NT1 to NT4, thereby causing the feedback voltage VFB to fluctuate as shown in B3. In response to the fluctuation of the feedback voltage VFB, as shown in B4, the operational amplifier OP controls so that the output voltage VDD approaches 1.8V, which is the adjustment voltage. However, the fluctuation of VDD is transmitted to VD5 via the driving transistor TR, etc., and as shown in B5, VD5 also fluctuates. Furthermore, the fluctuation of VD5 shown in B5 is transmitted to the driving circuits BF1 to BF4 of the output voltage adjustment circuit 30 using VD5 as the power supply, and as shown in B6, the control signal CS fluctuates. This fluctuation causes the feedback voltage VFB to fluctuate via the parasitic capacitance, forming a circuit loop that interferes with each other such that VDD and VD5 fluctuate, and the fluctuation does not converge.

[0048] Figure 6 FIG. 4 is a diagram showing the signal waveforms of each node in this embodiment. Figure 6 In C1, the voltage of the control signal CS changes by reading the initial value from the initial value register 42 and the adjustment value from the nonvolatile memory 48. This voltage change is transmitted via the parasitic capacitance, thereby causing the feedback voltage VFB to fluctuate as shown in C3. In response to the fluctuation of the feedback voltage VFB, the operational amplifier OP controls the output voltage VDD so that it approaches 1.8V, which is the adjustment voltage, as shown in C4. In addition, in C5, VD5 fluctuates. However, in this embodiment, as shown in Figure 1 , Figure 2 As shown in FIG. 1 , VDD is provided to the output voltage adjustment circuit 30 instead of VD5 as the power supply, so as shown in C6, the fluctuation of the control signal CS caused by the fluctuation of VD5 will not occur. Figure 4 , Figure 5 As in the comparative example, a circuit loop is formed in which the fluctuations of VD5 and VDD interfere with each other, so that the fluctuations do not converge.

[0049] That is, the feedback control of the operational amplifier OP works to the fluctuation of the feedback voltage VFB, so that VDD becomes a constant voltage, but such feedback control does not work on VD5. Figure 4 , Figure 5As in the comparative example of FIG. 1 , when VD5, on which the feedback control of the operational amplifier OP does not work, is provided as the power supply of the output voltage adjustment circuit 30, the fluctuations of VD5 and VDD interfere with each other and do not converge. In contrast, in the present embodiment, VDD, on which the feedback control of the operational amplifier OP works, is provided as the power supply of the output voltage adjustment circuit 30. Figure 6 As shown, it is possible to prevent the fluctuations of VD5 and VDD from not converging.

[0050] 2. Voltage divider circuit

[0051] Figure 7 2 shows a specific configuration example of the voltage divider circuit 20. In addition, the voltage divider circuit 20 is not limited to Figure 7 The structure can be modified in various ways, such as omitting some of its structural elements, adding other structural elements, replacing some of its structural elements with other structural elements, etc.

[0052] like Figure 7 As shown, the plurality of resistors of the voltage divider circuit 20 include a first resistor group 21 and a second resistor group 22. The first resistor group is provided between a node NF of an output feedback voltage VFB and a node NS of VSS as a predetermined voltage node. In addition, the second resistor group 22 is provided between a node NVD of an output voltage VDD and a node NF of a feedback voltage VFB. Thus, by controlling the on / off of each switch provided in parallel with each resistor of the first resistor group 21 and each switch provided in parallel with each resistor of the second resistor group 22, the output voltage VDD can be set to a voltage corresponding to an adjustment value. In the present embodiment, the first resistor group 21 and the second resistor group 22 can be collectively referred to as feedback resistors.

[0053] For example, the first resistor group 21 has a plurality of resistors RA1 to RA7, and these resistors RA1 to RA7 are arranged in series between the node NF of the feedback voltage VFB and the node NS of VSS. Moreover, for each resistor of the resistors RA1, RA2, RA3, RA4, RA5, RA6, and RA7, switches SA1, SA2, SA3, SA4, SA5, SA6, and SA7 are arranged in parallel. In addition, the resistance values ​​of the resistors RA1, RA2, RA3, RA4, RA5, RA6, and RA7 are binary weighted such as r / 8, r / 4, r / 2, r, 2r, 4r, and 8r, respectively. Thus, by controlling the on / off of the switches SA1 to SA7 according to the adjustment signals AS1 to AS7, the resistance value of the first resistor group 21 can be set to a resistance value corresponding to the adjustment value of the binary data. In addition, as an example, the resistance value r is about 10 kΩ.

[0054] In addition, the second resistor group 22 has a plurality of resistors RB1 to RB7, which are arranged in series between the node NVD of the output voltage VDD and the node NF of the feedback voltage VFB. Furthermore, switches SB1, SB2, SB3, SB4, SB5, SB6, and SB7 are arranged in parallel with each of the resistors RB1, RB2, RB3, RB4, RB5, RB6, and RB7. In addition, the resistance values ​​of the resistors RB1, RB2, RB3, RB4, RB5, RB6, and RB7 are binary weighted, such as r / 8, r / 4, r / 2, r, 2r, 4r, and 8r, respectively. Thus, by controlling the on / off of the switches SB1 to SB7 according to the adjustment signals AS1 to AS7, the resistance value of the second resistor group 22 can be set to a resistance value corresponding to the adjustment value of the binary data.

[0055] And, in Figure 7 In the embodiment, the logic circuit 40 outputs the adjustment signal AS1 so that when the switch SA1 provided in parallel with the resistor RA1 in the first resistor group 21 becomes one of the on and off states, the switch SB1 provided in parallel with the resistor RB1 in the second resistor group 22 becomes the other of the on and off states. That is, the switch SA1 of the resistors in the first resistor group 21 and the switch SB1 of the resistors in the second resistor group 22 are exclusively turned on and off. For example, by inputting a positive logic control signal CS1 to the N-type transistor of the switch SA1 and the P-type transistor of the switch SB1, and inputting a negative logic control signal XCS1 to the P-type transistor of the switch SA1 and the N-type transistor of the switch SB1, such exclusive control can be performed.

[0056] In addition, the logic circuit 40 outputs the adjustment signal AS2 so that when the switch SA2 provided in parallel with the resistor RA2 in the first resistor group 21 is turned on or off, the switch SB2 provided in parallel with the resistor RB2 in the second resistor group 22 is turned on or off. That is, the switch SA2 and the switch SB2 are turned on or off exclusively. For example, by inputting a positive logic control signal CS2 to the N-type transistor of the switch SA2 and the P-type transistor of the switch SB2, and inputting a negative logic control signal XCS2 to the P-type transistor of the switch SA2 and the N-type transistor of the switch SB2, such exclusive control can be performed.

[0057] The switches SA3 to SA7 provided in parallel with the resistors RA3 to RA7 of the first resistor group 21 and the switches SB3 to SB7 provided in parallel with the resistors RB3 to RB7 of the second resistor group 22 are similarly controlled to be exclusively turned on and off by the adjustment signals AS3 to AS7. Here, the resistors RA1 to RA7 of the first resistor group 21 are the first resistors, and the switches SA1 to SA7 are the first switches. In addition, the resistors RB1 to RB7 of the second resistor group 22 are the second resistors, and the switches SB1 to SB7 are the second switches.

[0058] In this way, Figure 7 In the embodiment, the logic circuit 40 outputs adjustment signals AS1 to AS7, so that when the first switch provided in parallel with the first resistor in the first resistor group 21 becomes one of the states of being turned on and turned off, the second switch provided in parallel with the second resistor in the second resistor group 22 becomes the other of the states of being turned on and turned off. In this way, switch control can be implemented so that the total resistance value of the feedback resistors formed by the first resistor group 21 and the second resistor group 22 does not change. That is, in this embodiment, the total resistance value of the feedback resistors does not change by configuring the switches that are turned on and short-circuited and the switches that are turned off and opened in pairs for the first resistor group 21 and the second resistor group 22. As a result, the deviation of the consumption current can be reduced in consideration of the application of the circuit device 2 having the regulator 10.

[0059] For example, in the present embodiment, the first resistor of the first resistor group 21 and the second resistor of the second resistor group 22 are resistors of the same resistance value. For example, the resistor RA1 of the first resistor group 21 and the corresponding resistor RB1 of the second resistor group 22 are set to the same resistance value of r / 8. In addition, the resistor RA2 of the first resistor group 21 and the corresponding resistor RB2 of the second resistor group 22 are also set to the same resistance value of r / 4. In addition, the resistor RA3 of the first resistor group 21 and the corresponding resistor RB3 of the second resistor group 22 are also set to the same resistance value of r / 2. Similarly, the resistors RA4 to RA7 of the first resistor group 21 and the resistors RB4 to RB7 of the second resistor group 22 are also set to the same resistance value. In this way, for example, when the first switch of the first resistor group 21 is turned on and the resistance value of the first resistor group 21 decreases, the second switch of the second resistor group 22 is turned off, and the resistance value of the second resistor group 22 increases by the amount of the reduced resistance value, so the total resistance value does not change. When the first switch of the first resistor group 21 is turned off and the resistance value of the first resistor group 21 increases, the second switch of the second resistor group 22 is turned on and the resistance value of the second resistor group 22 decreases by the increased resistance value, so the total resistance value does not change.

[0060] In addition, Figure 7In the embodiment, the voltage divider circuit 20 includes a resistor RC3 connected in series with the first resistor group 21 and a resistor RC4 connected in series with the second resistor group 22. The resistor RC3 is the third resistor and the resistor RC4 is the fourth resistor. For example, the resistor RC3 is connected in series with the first resistor group 21 between the node NF and the node NS. The resistor RC4 is connected in series with the second resistor group 22 between the node NVD and the node NF. Moreover, the resistance values ​​of the resistors RC3 and RC4 are set so that the output voltage VDD becomes a given set voltage when all the switches of the voltage divider circuit 20 are turned on or off. For example, Figure 7 In the embodiment, the resistance value of the resistor RC3 is set to r / 8+58r, and the resistance value of the resistor RC4 is set to r / 8+45r.

[0061] As an example, in Figure 8 In the embodiment, when all the switches of the voltage divider circuit 20 are turned off, the resistance values ​​of the resistors RC3 and RC4 are set so that the resistance value r1 between the node NF and the node NS is about 731 kΩ and the resistance value r2 between the node NVD and the node NF is about 602 kΩ. As a result, the output voltage VDD of the regulator 10 becomes, for example, about 1.82 V. In addition, when all the switches of the voltage divider circuit 20 are turned on, the output voltage VDD of the regulator 10 becomes about 1.82 V. Figure 8 The resistance values ​​of the resistors RC3 and RC4 are set so that the resistance value r1 becomes approximately 574 kΩ and the resistance value r2 becomes approximately 445 kΩ. Thus, the output voltage VDD of the regulator 10 becomes approximately 1.77 V, for example.

[0062] For example, after the power is turned on, the output of the logic circuit 40 becomes unstable, so there may be a situation where all the switches of the voltage divider circuit 20 are turned off or all are turned on. Figure 7 When the resistors RC3 and RC4 are not connected in parallel with the switches as shown, the output voltage VDD of the regulator 10 may become a voltage that is significantly deviated from the target voltage such as 1.8 V. Then, when the output of the logic circuit 40 is determined and the switch is turned on or off according to the adjustment value, the output voltage VDD of the regulator 10 may change rapidly from the voltage that is significantly deviated from the target voltage to the voltage corresponding to the adjustment value. When such a situation occurs, it takes time for the output voltage VDD to be stabilized by the feedback control of the operational amplifier OP.

[0063] In this regard, Figure 7In the embodiment, resistors RC3 and RC4 are respectively provided in series with the first resistor group 21 and the second resistor group 22, and the resistance values ​​of the resistors RC3 and RC4 are set so that the output voltage VDD becomes a given set voltage when all the switches are turned on or off. In this way, even when the adjustment signal of the logic circuit 40 becomes unstable after the power is turned on, the output voltage VDD of the regulator 10 is set to a set voltage close to the target voltage. Therefore, it is possible to prevent the output voltage VDD of the regulator 10 from changing from a voltage that is greatly deviated from the target voltage to a voltage corresponding to the adjustment value.

[0064] In addition, Figure 7 In FIG. 1 , the voltage divider circuit 20 includes a switch SWC for disconnecting the feedback resistor provided between the first resistor group 21 and the node NS of VSS which is a predetermined voltage node. Figure 7 In the embodiment, the switch SWC is realized by, for example, an N-type transistor. When the switch SWC is turned off, the electrical connection between the first resistor group 21 and the node NS is cut off.

[0065] For example, in manufacturing Fig. 9 When a circuit device is used, the leakage current of a circuit using VDD as a power supply may be checked. In this case, for example, VDD is supplied to the node NVD from the outside by a tester or other testing device via a test connection pad (not shown) and the current flowing therethrough is measured to check the leakage current. When VDD is supplied to the node NVD from the outside in this way, if the current flows through the feedback resistor of the voltage divider circuit 20, the leakage current cannot be properly measured. In this case, Figure 7 In the embodiment, a switch SWC for cutting off the feedback resistor is provided between the first resistor group 21 and the node NS of VSS. Therefore, when checking leakage current, etc., by turning off the switch SWC, it is possible to prevent the current from flowing to VSS via the feedback resistor. Thus, it is possible to perform appropriate checks on leakage current, etc. of a circuit using VDD as a power supply.

[0066] In addition, the control signal of the switch SWC for cutting off the feedback resistor becomes a signal based on the input voltage VD5. Figure 7 In the embodiment, the input voltage VD5 is input as the control signal of the switch SWC. However, the control signal of the switch SWC is not limited to the input voltage VD5 itself, as long as it is based on the input voltage VD5. For example, after the power is turned on, when the switch SWC for cutting off the feedback resistor is turned off, the feedback voltage VFB set according to the resistance ratio of the feedback resistor of the voltage divider circuit 20 becomes unstable, and the appropriate output voltage VDD may not be output. For example, in Figure 8In the embodiment of the present invention, by using the resistors RC3 and RC4 without switches connected in parallel, the output voltage VDD of the regulator 10 is set to a given set voltage even when all switches of the voltage divider circuit 20 are turned on or off. However, if the switch SWC for cutting off the feedback resistor is turned off after the power is turned on, it may not be possible to set the set voltage appropriately.

[0067] In this regard, Figure 7 In the embodiment, the control signal of the switch SWC for cutting off the feedback resistor becomes a signal based on the input voltage VD5. Therefore, after the power is turned on, Figure 3 As shown, VD5 rises, thereby reliably turning on the switch SWC for cutting off the feedback resistor. Therefore, it is possible to prevent the switch SWC for cutting off the feedback resistor from turning off, cutting off the path of the feedback resistor, and causing the output voltage VDD of the regulator 10 to become an inappropriate voltage.

[0068] 3. Circuit device

[0069] Fig. 9 FIG. 2 shows a configuration example of a circuit device 2 including a regulator 10 according to the present embodiment. Fig. 9 An example of the structure of the circuit device 2 is shown. The circuit device 2 is not limited to Fig. 9 The structure can be modified in various ways, such as omitting some of the structural elements, adding other structural elements, replacing some of the structural elements with other structural elements, etc.

[0070] Fig. 9 This is an application example of a contactless power transmission system, in which the circuit device 2 as a power receiving control device performs control for contactlessly receiving the transmitted power from the power transmitting device 100. For example, a primary coil L1 is provided on the power transmitting device 100 side, and a secondary coil L2 is provided on the power receiving device side implemented by the circuit device 2. In addition, the power transmission driver of the power transmitting device 100 applies an AC voltage to the primary coil L1, thereby transmitting power from the primary coil L1 to the secondary coil L2 in a wireless manner, and the power receiving device implemented by the circuit device 2 receives the transmitted power. In addition, the circuit device 2 including the regulator 10 of this embodiment is not limited to the use of the contactless power transmission system, and can also be used for other purposes.

[0071] The circuit device 2 includes a rectifier circuit 50, regulators 10 and 12, a charging circuit 60, and a charging control circuit 62. In addition, the circuit device 2 can include a detection circuit 70 and a power supply circuit 80. The circuit device 2 is, for example, an IC (Integrated Circuit) manufactured by a semiconductor process, and is a semiconductor chip having circuit elements formed on a semiconductor substrate. The circuit elements are active elements such as transistors, and passive elements such as resistors and capacitors.

[0072] The rectifier circuit 50, which operates as a power receiving circuit, converts the AC voltages VC1 and VC2 induced in the secondary coil L2 into a DC rectified voltage VCC. The regulator 12 regulates the rectified voltage VCC to generate VD5. Thus, VD5, which is a stable constant voltage, can be generated based on the rectified voltage VCC obtained by rectifying the AC voltages VC1 and VC2. In addition, the rectifier circuit 50 and the regulator 12 are, for example, circuits composed of transistors with a high withstand voltage (HV). In addition, the circuits other than the rectifier circuit 50 and the regulator 12 in the circuit device 2 are, for example, circuits composed of transistors with a withstand voltage lower than HV.

[0073] The charging circuit 60 charges the battery 110 according to the input voltage VD5 from the regulator 12. The battery voltage VBT is, for example, the voltage of the electrode on the positive side of the battery 110. For example, the charging circuit 60 includes a charging transistor and a charging control circuit that controls the charging transistor. The charging transistor is, for example, provided between an input node of the input voltage VD5 and an output node of the battery voltage VBT. Furthermore, the charging control circuit controls the gate of the charging transistor, etc., to perform constant current charging (CC charging) and constant voltage charging (CV charging) of the battery 110. For example, the charging current of the charging transistor is detected by a detection resistor, etc., and the charging control circuit controls the gate of the charging transistor according to the detection result, thereby realizing constant current charging, etc.

[0074] The power supply circuit 80 operates based on the battery voltage VBT and performs a power supply operation to the power supply object 120. For example, the power supply circuit 80 provides the output voltage generated based on the battery voltage VBT, for example, as a power supply voltage to the power supply object 120. As an example, the power supply object 120 is a processing device such as a microcontroller. For example, the power supply circuit 80 includes a charge pump circuit, which performs a charge pump operation to step down the battery voltage VBT, and provides the output voltage after stepping down the battery voltage VBT to the power supply object 120. The power supply circuit 80 can also be called a discharge circuit of the battery 110.

[0075] The regulator 10 of the present embodiment regulates the input voltage VD5 and outputs the regulated voltage as the output voltage VDD. The output voltage VDD is supplied to the charging control circuit 62 and the detection circuit 70 as a power supply voltage.

[0076] The charging control circuit 62 controls the charging circuit 60. For example, the charging control circuit 62 controls the charging circuit 60 based on the detection result of the detection circuit 70. For example, the charging control circuit 62 performs a process for controlling the charging of the charging transistor and the like in the charging circuit 60.

[0077] The detection circuit 70 performs various detection processes in the circuit device 2. For example, the detection circuit 70 can detect and monitor the battery voltage VBT, detect and monitor the charging current, or perform temperature detection based on a signal from a temperature sensor provided inside or outside the circuit device 2. For example, the detection circuit 70 performs detection processing of voltages such as the battery voltage VBT and currents such as the charging current. The detection circuit 70 includes an A / D conversion circuit 72. The A / D conversion circuit 72 performs processing of A / D conversion of the voltage of the detection object of the detection circuit 70 into digital detection data. For example, the A / D conversion circuit 72 performs A / D conversion of the battery voltage VBT, or performs A / D conversion of the voltage after the charging current is converted into a voltage, and outputs digital detection data. The charging control circuit 62 controls the charging circuit 60 based on the digital detection data from the detection circuit 70.

[0078] Thus, the circuit device 2 of the present embodiment includes: a regulator 10; a charging circuit 60 that charges a charging object such as a battery 110 based on an input voltage VD5; and a charging control circuit 62 that controls the charging circuit 60. Furthermore, the output voltage VDD of the regulator 10 is used as a power supply voltage of the charging control circuit 62 or a power supply voltage of a detection circuit 70 used by the charging control circuit 62. In this way, a stable output voltage VDD with high voltage accuracy can be provided as a power supply voltage to the charging control circuit 62 and the detection circuit 70 that outputs the detection result to the charging control circuit 62. For example, in the case where a high A / D conversion accuracy is required for the A / D conversion circuit 72 of the detection circuit 70, it is necessary to provide an output voltage VDD with high voltage accuracy as a power supply voltage. In this regard, an output voltage adjustment circuit 30 is provided in the regulator 10 of the present embodiment, so that an output voltage VDD with high voltage accuracy can be provided to the A / D conversion circuit 72, etc. In addition, VDD is provided to the output voltage adjustment circuit 30 instead of VD5 as a power supply voltage. Therefore, as Figure 6 As described in the above, even when the adjustment value of the output voltage adjustment circuit 30 changes, it is possible to prevent the output voltage VDD from becoming unstable, and thus provide a stable output voltage VDD with high voltage accuracy.

[0079] As described above, the regulator of this embodiment adjusts the input voltage and outputs the output voltage, and the regulator includes: a voltage divider circuit that outputs the voltage obtained by dividing the output voltage as a feedback voltage; and an operational amplifier that compares the feedback voltage with a reference voltage. In addition, the regulator includes: a driving transistor that is arranged between the node of the input voltage and the node of the output voltage and is controlled based on the output of the operational amplifier; a logic circuit that outputs an adjustment signal of the output voltage; and an output voltage adjustment circuit that adjusts the output voltage based on the adjustment signal. In addition, the voltage divider circuit includes a plurality of resistors and a plurality of switches, each of the plurality of switches is arranged in parallel with each of the plurality of resistors, and the output voltage adjustment circuit outputs a control signal corresponding to the adjustment signal to the plurality of switches, and provides the output voltage as a power supply voltage to the output voltage adjustment circuit.

[0080] According to the present embodiment, the reference voltage and the feedback voltage obtained by dividing the output voltage by the voltage divider circuit are compared by the operational amplifier, and the driving transistor is controlled based on the output of the operational amplifier to output the output voltage. Moreover, the logic circuit outputs the adjustment signal of the output voltage, and the output voltage adjustment circuit adjusts the output voltage based on the adjustment signal. In addition, the voltage divider circuit includes a plurality of resistors and a plurality of switches, and provides the output voltage as the power supply voltage to the output voltage adjustment circuit that outputs the control signal corresponding to the adjustment signal to the plurality of switches. In this way, the output voltage adjustment circuit adjusts the output voltage based on the adjustment signal from the logic circuit, thereby being able to output an output voltage with high voltage accuracy. In addition, the output voltage adjustment circuit outputs the control signal as the power supply voltage instead of the input voltage, so even if the feedback voltage fluctuates due to the change of the control signal and the input voltage fluctuates, the fluctuation of the input voltage can be suppressed and transmitted to the output voltage adjustment circuit as the fluctuation of the power supply voltage. Therefore, it is possible to prevent the occurrence of a situation where the output of the regulator becomes unstable, and to output an output voltage with high voltage accuracy.

[0081] In addition, in the present embodiment, each of the plurality of switches may also be composed of an N-type transistor and a P-type transistor connected in parallel. Furthermore, the output voltage adjustment circuit may also include: a first inverter, which outputs a first control signal for controlling one of the N-type transistor and the P-type transistor; and a second inverter, which is input with the output of the first inverter and outputs a second control signal for controlling the other of the N-type transistor and the P-type transistor.

[0082] In this way, the on-resistance of the switch when it is turned on can be reduced, and the switch can be appropriately turned on by the control signal from the output voltage adjustment circuit.

[0083] Furthermore, in the present embodiment, the logic circuit may include an initial value register, and after a power-on reset, the adjustment signal may be output based on an initial value of the adjustment value of the output voltage from the initial value register.

[0084] In this way, after the power-on reset, the on and off of the switch can be appropriately controlled to set the output voltage to a voltage corresponding to the initial value of the adjustment value.

[0085] Furthermore, in the present embodiment, the logic circuit may output an adjustment signal based on the adjustment value of the output voltage read from the nonvolatile memory.

[0086] In this way, the on / off of the switch can be appropriately controlled based on the adjustment value stored in the nonvolatile memory, and the output voltage can be set to a voltage corresponding to the adjustment value.

[0087] Furthermore, in the present embodiment, the output voltage may be provided in common to the output voltage adjustment circuit and the logic circuit as the power supply voltage.

[0088] In this way, based on the output voltage generated by the regulator, the logic circuit can be operated to generate an adjustment signal, and the adjustment signal can be input to the output voltage adjustment circuit that operates using the output voltage as the power supply voltage.

[0089] In the present embodiment, the plurality of resistors may include a first resistor group provided between a feedback voltage node outputting a feedback voltage and a predetermined voltage node, and a second resistor group provided between a node outputting the voltage and the feedback voltage node.

[0090] In this way, by controlling the on / off of each switch provided in parallel with each resistor of the first resistor group and each switch provided in parallel with each resistor of the second resistor group, the output voltage can be set to a voltage corresponding to the adjustment value.

[0091] In addition, in this embodiment, the logic circuit can also output an adjustment signal so that when the first switch arranged in parallel with the first resistor in the first resistor group is turned on or off, the second switch arranged in parallel with the second resistor in the second resistor group is turned on or off.

[0092] In this way, it is possible to realize switching control in which the total resistance value of the feedback resistors of the first resistor group and the second resistor group does not change.

[0093] In addition, in the present embodiment, the first resistor and the second resistor may have the same resistance value.

[0094] Thus, when the switch of one resistor group is turned on and the resistance value of one resistor group decreases, the switch of the other resistor group is turned off and the resistance value of the other resistor group increases, so that the total resistance value does not change.

[0095] In addition, in this embodiment, the voltage divider circuit may include a third resistor arranged in series with the first resistor group and a fourth resistor arranged in series with the second resistor group, and the resistance values ​​of the third resistor and the fourth resistor are set so that the output voltage becomes a given set voltage when all multiple switches are turned on or off.

[0096] In this way, even when the adjustment signal of the logic circuit or the like becomes unstable, the output voltage of the regulator is set to a set voltage close to the target voltage.

[0097] In addition, in the present embodiment, the voltage dividing circuit may include a switch for disconnecting the feedback resistance provided between the first resistor group and the predetermined voltage node.

[0098] In this way, when checking leakage current or the like of a circuit to which an output voltage is supplied, by opening the switch for cutting off the feedback resistor, it is possible to prevent current from flowing through the feedback resistor.

[0099] In addition, in the present embodiment, the control signal of the switch for cutting off the feedback resistance may be a signal based on the input voltage.

[0100] In this way, when the input voltage rises after the power supply is turned on, the switch for cutting off the feedback resistance can be turned on reliably.

[0101] In addition, the circuit device of this embodiment may also include: the regulator described above; a charging circuit that charges a charging object based on an input voltage; and a charging control circuit that controls the charging circuit, and the circuit device provides an output voltage as a power supply voltage of the charging control circuit or a power supply voltage of a detection circuit used in the charging control circuit.

[0102] In this way, a stable output voltage V with high voltage accuracy can be provided as a power supply voltage to the charging control circuit and the detection circuit.

[0103] In addition, the present embodiment is described in detail as described above, but those skilled in the art can easily understand that various modifications can be made without substantially departing from the new matters and effects of the present invention. Therefore, such modifications are all included in the scope of the present invention. For example, in the specification or the accompanying drawings, a term recorded at least once with a different term in a broader sense or synonymous can be replaced with the different term in any part of the specification or the accompanying drawings. In addition, all combinations of the present embodiment and the modifications are also included in the scope of the present invention. In addition, the structure and operation of the regulator and the circuit device are not limited to the contents described in the present embodiment, and various modifications can be implemented.

Claims

1. A regulator, characterized in that: The regulator adjusts the input voltage and outputs the output voltage, and the regulator comprises: A voltage divider circuit, wherein the output voltage is obtained by dividing the output voltage as a feedback voltage; an operational amplifier that compares the feedback voltage with a reference voltage; a driving transistor disposed between a node of the input voltage and a node of the output voltage and controlled based on an output of the operational amplifier; A logic circuit, which outputs an adjustment signal of the output voltage; as well as an output voltage adjustment circuit, which adjusts the output voltage based on the adjustment signal, The voltage divider circuit comprises: Multiple resistors; as well as a plurality of switches, each of the plurality of switches being arranged in parallel with each of the plurality of resistors; The output voltage adjustment circuit outputs a control signal corresponding to the adjustment signal to the plurality of switches, The regulator provides the output voltage as a power supply voltage to the output voltage adjustment circuit.

2. The regulator according to claim 1, characterized in that Each of the plurality of switches is composed of an N-type transistor and a P-type transistor connected in parallel, The output voltage adjustment circuit comprises: a first inverter that outputs a first control signal for controlling one of the N-type transistor and the P-type transistor; and The second inverter receives the output of the first inverter and outputs a second control signal for controlling the other of the N-type transistor and the P-type transistor.

3. The regulator according to claim 1, characterized in that The logic circuit includes an initial value register, After a power-on reset, the logic circuit outputs the adjustment signal based on an initial value of the adjustment value of the output voltage from the initial value register.

4. The regulator according to claim 1, characterized in that The logic circuit outputs the adjustment signal based on the adjustment value of the output voltage read out from the nonvolatile memory.

5. The regulator according to claim 1, characterized in that The output voltage is provided to the output voltage adjustment circuit and the logic circuit as a power supply voltage.

6. The regulator according to claim 1, characterized in that The plurality of resistors include: a first resistor group provided between a feedback voltage node outputting the feedback voltage and a predetermined voltage node; and The second resistor group is provided between the output voltage node and the feedback voltage node.

7. The regulator according to claim 6, characterized in that The logic circuit outputs the adjustment signal so that when the first switch arranged in parallel with the first resistor in the first resistor group becomes one of an on state and an off state, the second switch arranged in parallel with the second resistor in the second resistor group becomes the other of an on state and an off state.

8. The regulator according to claim 7, characterized in that The first resistor and the second resistor have the same resistance value.

9. The regulator according to claim 6, characterized in that The voltage divider circuit comprises: a third resistor, which is connected in series with the first resistor group; and a fourth resistor, which is connected in series with the second resistor group; The resistance values ​​of the third resistor and the fourth resistor are set so that the output voltage becomes a predetermined set voltage when all of the plurality of switches are turned on or off.

10. The regulator according to claim 6, characterized in that The voltage dividing circuit includes a switch for cutting off feedback resistance provided between the first resistor group and the predetermined voltage node.

11. The regulator according to claim 10, characterized in that The control signal of the switch for cutting off the feedback resistance is a signal based on the input voltage.

12. A circuit device, characterized in that: The circuit arrangement comprises: A regulator as claimed in any one of claims 1 to 11; a charging circuit configured to charge a charging object based on the input voltage; and a charging control circuit, which controls the charging circuit, The circuit arrangement provides the output voltage as a supply voltage for the charge control circuit or as a supply voltage for a detection circuit of the charge control circuit.

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