Method, system and microcontroller unit for computing device clock management

Abstract

The invention relates to a method, a system and a microcontroller unit for computing device clock management. Systems and methods described herein fan out a source clock signal within an MCU to produce a plurality of clock signals. The system and method distributes a plurality of clock signals to a plurality of input / output (I / O) groups within the MCU, where each I / O group of the plurality of I / O groups corresponds to a different one of a plurality of power domains of the MCU. The system and method provide a plurality of clock signals to a plurality of peripheral devices coupled to a plurality of I / O groups.

Description

Technical Field

[0001] Aspects of the present disclosure generally relate to computing device clock management, and more particularly, to fanning out clock signals to different power domains using a microcontroller. The present disclosure also relates to a low-power clock multiplexer in a microcontroller with selectable power domain outputs. Background Art

[0002] Computing devices may use multiple power domains to control the power consumption of various components. A power domain is a grouping of components or subsystems that share a common power source and can be managed as a single unit in terms of power management. Power domains enable sophisticated power management based on the operational requirements and resource utilization of each power domain. By selectively powering on or off specific power domains, energy consumption can be optimized, resulting in extended battery life and improved overall power efficiency.

[0003] Another method for reducing power consumption involves using multiple clock domains, for example, a main clock domain and a low-power clock domain. The low-power clock domain uses a low-power clock, which is typically a low-frequency clock designed to operate with minimal power consumption. The low-power clock typically enables the computing device to have different operating modes to save energy, such as a deep sleep mode. In the deep sleep mode, the computing device can rely on the low-power clock to track time, to act as a watchdog timer, or a combination thereof. The low-power clock typically operates at a lower frequency than the main clock of the computing device and consumes very little power. Summary of the invention

[0004] One aspect of the present invention is a method performed by an electronic circuit within a microcontroller unit (MCU), the method comprising: fanning out a source clock signal within the MCU to generate multiple clock signals; distributing the multiple clock signals to multiple input / output (I / O) groups within the MCU, wherein each of the multiple I / O groups corresponds to a different power domain among multiple power domains of the MCU; and providing the multiple clock signals to multiple peripheral devices coupled to the multiple I / O groups.

[0005] Another aspect of the present invention is a system including a microcontroller unit (MCU), which is configured to: fan out a source clock signal to generate multiple clock signals; distribute the multiple clock signals to multiple input / output (I / O) groups within the MCU, wherein each of the multiple I / O groups corresponds to a different power domain among multiple power domains of the MCU; and provide the multiple clock signals to multiple peripheral devices coupled to the multiple I / O groups and external to the MCU.

[0006] Yet another aspect of the present invention is a microcontroller unit (MCU) configured to: fan out a source clock signal to generate multiple clock signals; distribute the multiple clock signals to multiple input / output (I / O) groups within the MCU, wherein each of the multiple I / O groups corresponds to a different power domain among multiple power domains of the MCU; and provide multiple clock signals to multiple peripheral devices coupled to the multiple I / O groups and external to the MCU. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The described embodiments and their advantages can be best understood by referring to the following description in conjunction with the accompanying drawings, which in no way limit any changes in form and detail that may be made to the described embodiments by those skilled in the art without departing from the spirit and scope of the described embodiments.

[0008] Figure 1 is a block diagram illustrating an example system for fanning out a source clock signal to multiple input / output (I / O) groups corresponding to multiple power domains according to some implementations of the present disclosure.

[0009] Figure 2 is a block diagram illustrating an example system for fanning out multiple source clock signals in multiple clock domains to multiple I / O groups corresponding to multiple power domains according to some embodiments of the present disclosure.

[0010] Figure 3 is a block diagram illustrating an example system including a signal booster coupled to a peripheral device for adjusting a fan-out clock signal according to some implementations of the present disclosure.

[0011] Figure 4 is a flow chart of a method of fanning out a source clock signal to multiple I / O groups corresponding to multiple power domains according to some embodiments of the present disclosure.

[0012] Figure 5 is a block diagram of an example communication device that may perform one or more of the operations described herein, according to some implementations of the present disclosure. DETAILED DESCRIPTION

[0013] As discussed above, a computing device can use power domains, clock domains, or a combination thereof to reduce overall power consumption. The challenge of implementing multiple power domains with multiple clock domains is that each power domain requires a separate clock source to be compatible with the power domain voltage level. For example, if a computing device has power domains for supply voltages of 3.3V, 1.8V, and 1.2V, the computing device also requires low-power clock sources for 3.3V, 1.8V, and 1.2V power domains. Unfortunately, each low-power clock source increases the bill of materials (BOM) cost of the computing device. The BOM cost is the total cost of all components used in the computing device, including microcontrollers, sensors, wireless communication modules, batteries, printed circuit boards (PCBs), and other components.

[0014] In addition, each low-power clock source requires space on the PCB. An important factor in PCB design is to reduce complexity by minimizing the number of components on the PCB. The fewer the number of components on the PCB, the simpler the design and the lower the overall cost. Unfortunately, installing multiple low-power clock sources on the PCB increases the size of the PCB and, in turn, increases the BOM cost.

[0015] The present disclosure solves the above-mentioned and other deficiencies by using electronic circuits within a microcontroller unit (MCU) to generate multiple clock signals from a source clock signal and fan out the multiple clock signals to multiple power domains. The method distributes the multiple clock signals to multiple input / output (I / O) groups within the MCU. Each of the multiple I / O groups corresponds to a different power domain. The method then provides multiple clock signals to multiple peripheral devices coupled to the multiple I / O groups operating in the multiple power domains.

[0016] In some embodiments, the source clock signal is a low power clock, and when one or more of the plurality of peripheral devices are operating in a low power state, each of the plurality of clock signals operates as a low power clock to one or more of the plurality of peripheral devices. In some embodiments, each of the plurality of power domains is based on a specification corresponding to the plurality of peripheral devices.

[0017] In some embodiments, the method uses a first source clock signal and a second source clock signal to generate a plurality of first clock signals and a plurality of second clock signals, respectively. The method distributes the plurality of first clock signals and the plurality of second clock signals to a plurality of I / O groups operating in a plurality of power domains, and provides the plurality of first clock signals and the plurality of second clock signals to a plurality of peripheral devices coupled to the plurality of I / O groups.

[0018] In some embodiments, the method turns off power to the first peripheral device, and then turns off one of a plurality of clock signals corresponding to the first peripheral device in response to turning off power to the first peripheral device. In some embodiments, the MCU includes a multiplexer to fan out a source clock signal to generate a plurality of clock signals. In some embodiments, the source clock signal is generated external to the MCU.

[0019] As discussed herein, the present disclosure provides a method for improving the operation of a computer system by simplifying clock domain management using an MCU. In addition, the present disclosure provides improvements in the technical field of computing devices by reducing the number of clock sources and reducing the size and complexity of PCBs to reduce the BOM cost of computing devices.

[0020] Figure 1 is a block diagram illustrating an example system for fanning out a source clock signal to multiple input / output (I / O) groups corresponding to multiple power domains according to some implementations of the present disclosure.

[0021] The wireless communication system 100 includes a microcontroller unit (MCU) 110, which includes multiple I / O groups 115, 120, and 125 to accommodate different power domains corresponding to peripheral devices 175, 180, 185, and 190. For example, the power domains can correspond to 3.3V VDD, 1.8V VDD, and 1.2V VDD. In some embodiments, the power domains can correspond to 1.7V to 5.5V VDD, 3.0V VDD, 3.4V VDD, or other voltage levels / ranges. In some embodiments, the I / O groups 115, 120, and 125 are coupled to GPIO (general purpose input / output) pins that enable the MCU 110 to couple to peripheral devices 175, 180, 185, and 190 and perform digital input and output operations. The GPIO pins can be used to interface with a wide range of peripheral devices such as GPS devices, image signal processors (ISPs), WiFi / Bluetooth combination devices, etc. In some embodiments, the wireless communication system 100 may include more than 100 peripheral devices. Figure 1 The peripheral devices shown in FIG. 5 may be more or fewer peripheral devices.

[0022] Source clock 130 is external to MCU 110 and generates a source clock signal that is fed into oscillator 135. In some embodiments, source clock 130 is a crystal that generates an analog source clock signal, and oscillator 135 converts the analog source clock signal into a digital source clock signal. In some embodiments, source clock 130 is internal to MCU 110 (see 130 for more details). Figure 3 and the corresponding text).

[0023] The output of the oscillator 135 is fed into the buffer 140, and the output of the buffer 140 is fed into the multiplexer 145. The controller 150 determines which of the outputs of the multiplexer 145 will fan out the source clock signal. In some embodiments, the controller 150 identifies the state of the peripheral devices 175, 180, 185, and 190 (e.g., active state, low power state, etc.) and feeds the corresponding clock signal to its respective buffer 155, 160, 165, and 170. In some embodiments, the oscillator 135, the buffer 140, and the multiplexer 145 operate in a low power domain (e.g., deep sleep mode).

[0024] I / O group A 115 includes a buffer 155 and can operate in a power domain with a 3.3V VDD (voltage drain to drain, power supply voltage). Buffer 155 conditions a clock signal 157 from one of the outputs of multiplexer 145 (e.g., adjusts the voltage level up / down to the power domain voltage, etc.). Clock signal 157 is fed into peripheral device 175, and peripheral device 175 uses clock signal 157 accordingly, for example, for a low power clock signal when peripheral device 175 is in a low power state.

[0025] Similarly, I / O group B 120 includes a buffer 160 and may operate in a power domain with a 1.2 V VDD. Buffer 160 generates a clock signal 162 from one of the outputs of multiplexer 145. Clock signal 162 is fed into peripheral device 180, and peripheral device 180 uses clock signal 162 accordingly, for example, for a low power clock signal when peripheral device 180 is in a low power state.

[0026] I / O group C 125 includes buffers 165 and 170 and can operate in a power domain with a 1.8V VDD. Buffer 165 generates a clock signal 167 from one of the outputs of multiplexer 145. Clock signal 167 is fed into peripheral device 185, and peripheral device 185 uses clock signal 167 accordingly, for example, for low-power clock signal when peripheral device 185 is in a low-power state. Buffer 170 generates a clock signal 172 from one of the outputs of multiplexer 145. Clock signal 172 is fed into peripheral device 190, and peripheral device 190 uses clock signal 172 accordingly, for example, for low-power clock signal when peripheral device 190 is in a low-power state.

[0027] Figure 2 is a block diagram illustrating an example system for fanning out multiple source clock signals in multiple clock domains to multiple input / output (I / O) groups corresponding to multiple power domains according to some embodiments of the present disclosure.

[0028] Figure 2 Relative to Figure 1 Another clock domain is added to the MCU 110 . Figure 2 MCU 110 is shown coupled to peripheral devices 175, 180, 185, and 190 through I / O group A 115, I / O group B 120, and I / O group C 125. Source clock 130 feeds into oscillator 135, which is coupled to buffer 140 and produces an input to multiplexer 145. Multiplexer 145 fans out the source clock signal to buffers 155, 160, 165, and 170.

[0029] MCU 110 also employs another clock domain that uses a source clock 200, such as a main system clock, that operates at a frequency different from source clock 130. Source clock 200 is fed into oscillator 205, which generates a second source clock signal that is fed into buffer 210. Buffer 210 provides an input to multiplexer 215 controlled by controller 150. Multiplexer 215 fans out the second source clock signal to buffers 220, 225, 230, and 235. Figure 2 As shown in , the outputs of these buffers are fed to peripheral devices. In some embodiments, source clock 130, source clock 200, or a combination thereof can be internal to MCU 110 (see for more details). Figure 3 and the corresponding text).

[0030] Figure 3 is a block diagram illustrating an example system including a signal booster coupled to a peripheral device for adjusting a fan-out clock signal according to some implementations of the present disclosure.

[0031] Figure 3 The system shown in Figure 1 , except that the wireless communication system 100 includes signal boosters 300, 310, 315, and 320. In some embodiments, an ultra-low power (ULP) host operates in the wireless communication system 100. The MCU 110 can then be in low-power operation (including interrupt processing) to reduce the power consumption of the entire system when the peripheral devices are powered on / off based on the MCU 110 instructions. In these embodiments, the clock signals 157, 162, 167, and 172 may not be robust enough to support their corresponding power domains. In this way, the wireless communication system 100 can use signal boosters 300, 310, 315, and 320 to boost the clock signals 157, 162, 167, and 172 when they are passed to their corresponding high-power domain peripheral devices.

[0032] In some embodiments, Figure 3As shown in , the source clock 130 is inside the MCU 110. For example, the source clock 130 can be an internal low-power oscillator (ILO), an internal master oscillator (IMO) or a combination thereof. The ILO is a built-in clock source designed to provide a clock signal for the internal operation (such as timing, synchronization and data processing) of the device. The ILO is usually used as a low-power alternative to an external crystal oscillator or other high-frequency clock sources and is optimized for low power consumption. The IMO is an internal clock source that is responsible for generating the master clock signal for the overall operation (including the execution of instructions, data processing and timing functions) of the drive device. The IMO is usually operated at a frequency determined by the internal oscillator circuit system of the MCU 110 or the integrated circuit. The IMO is used as an independent clock source, thereby eliminating the need for an external crystal oscillator or clock generator in the circuit design.

[0033] Figure 4 4 is a flow chart of a method 400 for fanning out a source clock signal to multiple input / output (I / O) groups corresponding to multiple power domains according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, programmable logic, processor, processing device, central processing unit (CPU), system on chip (SoC), etc.), software (e.g., instructions running / executing on a processing device), firmware (e.g., microcode), or a combination thereof. In some embodiments, as Figures 1 to 3 and Figure 5 As shown in , at least a portion of the method 400 may be executed by the controller 150 , the processor 502 , the processing device 505 , or a combination thereof.

[0034] Reference Figure 4 , method 400 illustrates example functionality used by various embodiments. Although specific functional blocks ("blocks") are disclosed in method 400, such blocks are examples. That is, embodiments are well suited to performing various other blocks or variations of blocks listed in method 400. It should be understood that the blocks in method 400 may be performed in an order different from that presented, and not all of the blocks in method 400 may be performed.

[0035] Reference Figure 4 , method 400 begins at block 410, where processing logic fans out a source clock signal within the MCU to generate a plurality of clock signals. In some embodiments, the source clock signal is a first source clock signal corresponding to a first clock domain, and the plurality of clock signals are a plurality of first clock signals. In some embodiments, processing logic further fans out a second source clock signal corresponding to a second clock domain within the MCU to generate a plurality of second clock signals. In some embodiments, the first source clock signal and the second source clock signal operate at different clock frequencies (e.g., different clock domains).

[0036] At block 420, processing logic distributes the plurality of clock signals to a plurality of input / output (I / O) groups within MCU 110 corresponding to different power domains of MCU 110. In some implementations, processing logic also distributes a plurality of second clock signals to a plurality of I / O groups within the MCU.

[0037] At block 430, the processing logic provides a plurality of clock signals to a plurality of peripheral devices coupled to the plurality of I / O groups. In some embodiments, the processing logic provides a plurality of second clock signals to the plurality of peripheral devices coupled to the plurality of I / O groups. In some embodiments, based on the provided clock signals, the peripheral devices use the clock signals as a low power clock in a deep sleep mode. In some embodiments, the peripheral devices use the clock signals as a master clock signal in an operational mode.

[0038] In some implementations, the source clock signal is a low power clock, and when one or more of the plurality of peripheral devices operate in a low power state, each of the plurality of clock signals operates as a low power clock to the peripheral device.

[0039] In some embodiments, each of the plurality of power domains is based on one of a plurality of peripheral device specifications corresponding to a plurality of peripheral devices. In some embodiments, the processing logic shuts off power to a first peripheral device and then correspondingly shuts off one of a plurality of clock signals corresponding to the first peripheral device. In some embodiments, the MCU includes a multiplexer to fan out a source clock signal to generate a plurality of clock signals. In some embodiments, the source clock signal is generated external to the MCU.

[0040] Figure 5 5 is a block diagram of an example communication device 500 that can perform one or more of the operations described herein according to some embodiments of the present disclosure. The communication device 500 may include and / or operate in whole or in part as described with respect to Figures 1 to 4 The communication device 500 may be in the form of a computer system (e.g., a wireless communication system) within which a set of instructions may be executed to cause the communication device 500 to perform any one or more of the methods discussed herein. The communication device 500 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the communication device 500 may operate as a server machine or a client machine in a server-client network environment, or as a peer machine in a P2P (or distributed) network environment.

[0041] The communication device 500 may be an Internet of Things (IoT) device, a server computer, a client computer, a personal computer (PC), a tablet computer, a set-top box (STB), a voice control hub (VCH), a personal digital assistant (PDA), a mobile phone, a network device, a network router, a switch or bridge, a television, a speaker, a remote control, a monitor, a handheld multimedia device, a handheld video player, a handheld gaming device, or a control panel or any other machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by the machine. In addition, although only a single communication device 500 is shown, the term "device" should also be taken to include any collection of machines that independently or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0042] The communication device 500 is shown to include a processor 502. In an embodiment, the communication device 500 and / or the processor 502 may include a processing device 505, such as a system on chip (SoC) processing device. Alternatively, the communication device 500 may include one or more other processing devices known to those of ordinary skill in the art, such as a microcontroller unit (e.g., MCU110), a microprocessor or a central processing unit, an application processor, a host controller, a controller, a dedicated processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc. The bus system 501 may include a communication block (not shown) for communicating with internal or external components such as an embedded controller or an application processor via a communication interface 509 and / or the bus system 501.

[0043] The components of the communication device 500 may reside on a common carrier substrate, such as, for example, an IC die substrate, a multi-chip module substrate, etc. Alternatively, the components of the communication device 500 may be one or more separate ICs and / or discrete components.

[0044] The memory system 504 may include volatile memory and / or non-volatile memory that can communicate with each other via the bus system 501. The memory system 504 may include, for example, random access memory (RAM) and program flash memory. The RAM may be static RAM (SRAM), and the program flash memory may be a non-volatile storage device that can be used to store firmware (e.g., a control algorithm that can be executed by the processor 502 to implement the operations described herein). The memory system 504 may include instructions 503 that, when executed, perform the methods described herein. Some portions of the memory system 504 may be dynamically allocated to provide caching, buffering, and / or other memory-based functions.

[0045] The memory system 504 may include a drive unit that provides a machine-readable medium on which one or more instruction sets 503 (e.g., software) implementing any one or more of the methods or functions described herein may be stored. The instructions 503 may also reside completely or at least partially in other memory devices of the memory system 504 and / or in the processor 502 during their execution by the communication device 500, which in some embodiments constitutes a machine-readable medium. The instructions 503 may also be sent or received over a network via the communication interface 509.

[0046] Although in some embodiments the machine-readable medium is a single medium, the term "machine-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable medium" should also be taken to include any medium that can store or encode a set of instructions that is executed by a machine and causes the machine to perform any one or more of the example operations described herein. Thus, the term "machine-readable medium" should be taken to include, but is not limited to, solid-state memories and optical and magnetic media.

[0047] The communication device 500 is also shown to include a display interface 506 (e.g., a liquid crystal display (LCD), a touch screen, a cathode ray tube (CRT), and software and hardware support for display technology), an audio interface 508 (e.g., a microphone, a speaker, and software and hardware support for microphone input / output and speaker input / output). The communication device 500 is also shown to include a user interface 510 (e.g., a keyboard, buttons, switches, a touch pad, a touch screen, and software and hardware support for a user interface).

[0048] Unless otherwise expressly stated, terms such as "fanning", "distribution", "providing", "flipping", etc. refer to actions and processes performed or implemented by computing devices that manipulate and transform data represented as physical (electronic) quantities within registers and memories of computing devices into other data similarly represented as physical quantities in memories or registers of computing devices or other such information storage, transmission or display devices. In addition, the terms "first" and "second" as used herein are intended to be used as labels to distinguish different elements and do not necessarily have an ordinal meaning according to their numerical designations.

[0049] The examples described herein also relate to an apparatus for performing the operations described herein. The apparatus may be specially constructed for the desired purpose, or it may include a general-purpose computing device selectively programmed by a computer program stored in a computing device. Such a computer program may be stored in a computer-readable non-transitory storage medium.

[0050] The methods and illustrative examples described herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used in accordance with the teachings described herein, or it may prove convenient to construct more specialized equipment to perform the required method steps. The structures required for various such systems will appear as set forth in the above description.

[0051] The above description is intended to be illustrative rather than restrictive. Although the present disclosure has been described with reference to specific illustrative examples, it will be appreciated that the present disclosure is not limited to the described examples. The scope of the present disclosure should be determined with reference to the appended claims and the full range of equivalents to which these claims are assigned.

[0052] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises", "comprising", "having", and / or "containing", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof. Therefore, the terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting.

[0053] It should also be noted that in some alternative implementations, the functions / actions may not occur in the order shown in the drawings. For example, depending on the functions / actions involved, two figures shown in succession may actually be executed substantially simultaneously or may sometimes be executed in the reverse order.

[0054] Although method operations are described in a particular order, it should be understood that other operations may be performed between the described operations, that the described operations may be adjusted so that they occur at slightly different times, or that the described operations may be distributed in a system that allows the processing operations to occur at various intervals associated with the processing.

[0055] Various units, circuits, or other components may be described or claimed as being "configured to" or "configurable to" perform one or more tasks. In such contexts, the phrases "configured to" or "configurable to" are used to represent a structure by indicating that the unit / circuit / component includes a structure (e.g., a circuit system) that performs one or more tasks during operation. In this way, even if the specified unit / circuit / component is not currently operational (e.g., not turned on), it can be said that the unit / circuit / component is configured to perform a task, or can be configured to perform a task. Units / circuits / components used with the "configured to" or "configurable to" language include hardware, such as circuits, memory storing program instructions that can be executed to implement operations, etc. The statement that a unit / circuit / component is "configured to" perform one or more tasks or "configurable to" perform one or more tasks expressly indicates that it is not intended to invoke 35 U.S.C. 112, paragraph 6, with respect to the unit / circuit / component. Additionally, "configured to" or "configurable to" may include a general purpose structure (e.g., a general purpose circuit system) that is manipulated by software and / or firmware (e.g., an FPGA or general purpose processor executing software) to operate in a manner capable of performing the tasks in question. "Configured to" may also include adjusting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture a device (e.g., an integrated circuit) suitable for implementing or performing one or more tasks. It is expressly stated that "configurable to" is not intended to apply to blank media, an unprogrammed processor or an unprogrammed general purpose computer, or an unprogrammed programmable logic device, an unprogrammed programmable gate array, or other unprogrammed device unless accompanied by a programmed medium that imparts the ability for the unprogrammed device to be configured to perform the disclosed functions.

[0056] For the purpose of illustration, the foregoing description has been described with reference to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. In view of the above teachings, many modifications and variations are feasible. The embodiments are selected and described in order to best illustrate the principles of these embodiments and their practical application, so that those skilled in the art can best utilize these embodiments and various modifications that may be suitable for the specific purpose envisioned. Therefore, the present embodiments are considered to be illustrative rather than restrictive, and the present disclosure is not limited to the details given herein, but these details may be modified within the scope of the appended claims and their equivalents.

Claims

1. A method performed by an electronic circuit in a microcontroller unit MCU, the method comprising: Fanning out a source clock signal within the MCU to generate a plurality of clock signals; Distributing the plurality of clock signals to a plurality of input / output I / O groups within the MCU, wherein each of the plurality of I / O groups corresponds to a different power domain of a plurality of power domains of the MCU; as well as The plurality of clock signals are provided to a plurality of peripheral devices coupled to the plurality of I / O groups.

2. The method according to claim 1, wherein: The source clock signal is a first source clock signal corresponding to a first clock domain, and the plurality of clock signals are a plurality of first clock signals, the method further comprising: fanning out a second source clock signal corresponding to a second clock domain within the MCU to generate a plurality of second clock signals, wherein the first source clock signal and the second source clock signal operate at different clock frequencies; distributing the plurality of second clock signals to the plurality of I / O groups; and The plurality of second clock signals are provided to the plurality of peripheral devices coupled to the plurality of I / O groups.

3. The method according to claim 1, wherein: The source clock signal is a low power clock, and each of the plurality of clock signals operates as a low power clock to one or more of the plurality of peripheral devices when one or more of the plurality of peripheral devices operates in a low power state.

4. The method according to claim 1, wherein: Each power domain of the plurality of power domains is based on one of a plurality of device specifications corresponding to the plurality of peripheral devices.

5. The method according to claim 1, further comprising: shutting off power to a first peripheral device among the plurality of peripheral devices; as well as In response to power being turned off to the first peripheral device, one of the plurality of clock signals corresponding to the first peripheral device is turned off.

6. The method according to claim 1, wherein: The MCU includes a multiplexer to fan out the source clock signal to generate the plurality of clock signals.

7. The method according to claim 1, wherein: The source clock signal is generated outside the MCU.

8. A system comprising a microcontroller unit (MCU), wherein the MCU is configured to: Fanning out a source clock signal to generate multiple clock signals; The plurality of clock signals are distributed to a plurality of input / output I / O groups within the MCU, wherein: Each of the plurality of I / O groups corresponds to a different power domain of the plurality of power domains of the MCU; as well as The plurality of clock signals are provided to a plurality of peripheral devices coupled to the plurality of I / O groups and external to the MCU.

9. The system according to claim 8, wherein: The source clock signal is a first source clock signal corresponding to a first clock domain, and the multiple clock signals are multiple first clock signals, and the MCU is further configured to: fanning out a second source clock signal corresponding to a second clock domain within the MCU to generate a plurality of second clock signals, wherein the first source clock signal and the second source clock signal operate at different clock frequencies; distributing the plurality of second clock signals to the plurality of I / O groups; and The plurality of second clock signals are provided to the plurality of peripheral devices coupled to the plurality of I / O groups.

10. The system according to claim 8, further comprising: One or more clock signal enhancers that adjust a voltage level of one or more of the plurality of clock signals before the one or more of the plurality of clock signals are sent to one or more of the plurality of peripheral devices.

11. The system according to claim 8, wherein: Each power domain of the plurality of power domains is based on one of a plurality of device specifications corresponding to the plurality of peripheral devices.

12. The system according to claim 8, wherein: The MCU is also configured to: turning off power to a first peripheral device among the plurality of peripheral devices; and Based on turning off power to the first peripheral device, one of the plurality of clock signals corresponding to the first peripheral device is turned off.

13. The system according to claim 8, wherein: The MCU includes a multiplexer to fan out the source clock signal to generate the plurality of clock signals.

14. The system according to claim 8, wherein: The source clock signal is generated outside the MCU.

15. A microcontroller unit MCU, which is configured to: Fanning out a source clock signal to generate multiple clock signals; The plurality of clock signals are distributed to a plurality of input / output I / O groups within the MCU, wherein: Each of the plurality of I / O groups corresponds to a different power domain of the plurality of power domains of the MCU; as well as The plurality of clock signals are provided to a plurality of peripheral devices coupled to the plurality of I / O groups and external to the MCU.

16. The MCU according to claim 15, wherein: The source clock signal is a first source clock signal corresponding to a first clock domain, and the multiple clock signals are multiple first clock signals, and the MCU is further configured to: fanning out a second source clock signal corresponding to a second clock domain within the MCU to generate a plurality of second clock signals, wherein the first source clock signal and the second source clock signal operate at different clock frequencies; distributing the plurality of second clock signals to the plurality of I / O groups; and The plurality of second clock signals are provided to the plurality of peripheral devices coupled to the plurality of I / O groups.

17. The MCU according to claim 15, wherein: The source clock signal is a low power clock, and each of the plurality of clock signals operates as a low power clock to one or more of the plurality of peripheral devices when one or more of the plurality of peripheral devices operates in a low power state.

18. The MCU according to claim 15, wherein: Each power domain of the plurality of power domains is based on one of a plurality of device specifications corresponding to the plurality of peripheral devices.

19. The MCU according to claim 15, wherein: The MCU is also configured to: turning off power to a first peripheral device among the plurality of peripheral devices; and Based on turning off power to the first peripheral device, one of the plurality of clock signals corresponding to the first peripheral device is turned off.

20. The MCU according to claim 15, wherein: The MCU includes a multiplexer to fan out the source clock signal to generate the plurality of clock signals.

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