NAND-Flash Memory Access Method and Device Based on NFI Interface Protocol

Abstract

The present application discloses a method for accessing a NAND-Flash memory based on the NFI interface protocol, which is used to solve the problems that due to different designers of the existing Controller and PHY parts, in order to achieve the interconnection and access between the two, it is necessary to specifically design the corresponding hardware circuit and memory access method each time, which in turn leads to a reduction in the R & D efficiency of the chip, an increase in the design cost, and a significant reduction in the efficiency of memory access. The method includes: determining the target to be accessed and the access type corresponding to the received access request; based on the NFI interface protocol, according to the access target and the access type, determining the interaction signal and control timing corresponding to the access request, wherein the NFI interface protocol defines the general interface, the corresponding interaction signal set, timing, and interaction behavior between the Controller and the physical layer port PHY; controlling the interaction signal according to the control timing to achieve the memory access to the target to be accessed.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a method and apparatus for accessing NAND-Flash memory based on the NFI interface protocol. Background Art

[0002] A solid state drive (SSD) consists of a controller and storage units (common storage units may include FLASH chips or DRAM chips). On the one hand, with the progress of NAND-Flash technology, the cost of SSDs based on NAND-Flash media is gradually decreasing. On the other hand, with the development of cloud computing and data centers, enterprise-level SSDs are increasingly widely used in servers and data centers.

[0003] In the prior art, an SSD mainly includes a controller chip, a cache chip (DRAM), and a flash chip (NAND-Flash). Among them, the controller chip mainly includes a front-end protocol interface (Interface Protocol IP), a NAND-Flash interface, a physical layer port (Physical, PHY), a controller, and a flash translation layer (FTL).

[0004] Currently, as the rate supported by the NAND-Flash I / O interface is getting higher and higher, the design requirements for the PHY of the controller chip are also getting higher and higher. To match the support rate of the NAND-Flash I / O interface, it is necessary to continuously increase the frequency of the PHY of the controller chip, and a stable power network is required to supply power to the increasingly high PHY frequency. However, on the other hand, the controller part of the controller chip does not need to use such a high frequency.

[0005] In this case, if the Controller and PHY are still designed as one entity, that is, there is no distinction between the controller and PHY parts in terms of IP, it will lead to the inability to clearly divide the clocks and power supplies of the controller part and the PHY part, and thus it is impossible to reduce power consumption through multi-clock domain and multi-voltage domain methods. On the other hand, this integrated design method of the Controller and PHY makes it impossible to separately protect the power supply and signals of the PHY part circuit.

[0006] In view of the above problems, the prior art can divide the Controller and the PHY into two parts. However, since the designers of the Controller and the PHY parts are often different, in order to enable the interconnection between the two for memory access, it is necessary to specifically design the corresponding hardware circuit and memory access method each time. This not only reduces the R & D efficiency of the chip, increases the design cost, but also greatly reduces the efficiency of memory access.

[0007] Therefore, how to provide the memory access efficiency of the chip while reducing the chip R & D efficiency and design cost has become a technical problem to be solved urgently at present. Summary of the Invention

[0008] The embodiment of the present application provides a NAND-Flash memory access method based on the NFI interface protocol, which is used to solve the problem that due to the different designers of the existing Controller and PHY parts, in order to achieve the interconnection access between the two, it is necessary to specifically design the corresponding hardware circuit and memory access method each time, thereby resulting in a reduction in the R & D efficiency of the chip, an increase in the design cost, and a significant reduction in the efficiency of memory access.

[0009] The embodiment of the present application also provides a NAND-Flash memory access device based on the NFI interface protocol, which is used to solve the problem that due to the different designers of the existing Controller and PHY parts, in order to achieve the interconnection access between the two, it is necessary to specifically design the corresponding hardware circuit and memory access method each time, thereby resulting in a reduction in the R & D efficiency of the chip, an increase in the design cost, and a significant reduction in the efficiency of memory access.

[0010] The embodiment of the present application also provides a NAND-Flash memory access device based on the NFI interface protocol, which is used to solve the problem that due to the different designers of the existing Controller and PHY parts, in order to achieve the interconnection access between the two, it is necessary to specifically design the corresponding hardware circuit and memory access method each time, thereby resulting in a reduction in the R & D efficiency of the chip, an increase in the design cost, and a significant reduction in the efficiency of memory access.

[0011] The embodiment of the present application also provides a computer-readable storage medium, which is used to solve the problem that due to the different designers of the existing Controller and PHY parts, in order to achieve the interconnection access between the two, it is necessary to specifically design the corresponding hardware circuit and memory access method each time, thereby resulting in a reduction in the R & D efficiency of the chip, an increase in the design cost, and a significant reduction in the efficiency of memory access.

[0012] The embodiment of the present application adopts the following technical solutions:

[0013] A NAND-Flash memory access method based on the NFI interface protocol, comprising: determining a target to be accessed and an access type corresponding to a received access request; based on the NFI interface protocol, determining an interaction signal and a control timing corresponding to the access request according to the access target and the access type, wherein the NFI interface protocol defines a general interface, a corresponding interaction signal set, a timing, and an interaction behavior between a controller Controller and a physical layer port PHY; controlling the interaction signal according to the control timing to implement memory access to the target to be accessed.

[0014] A NAND-Flash memory access device based on the NFI interface protocol, comprising: a request receiving unit configured to determine a target to be accessed and an access type corresponding to a received access request; an interaction signal determining unit configured to determine an interaction signal and a control timing corresponding to the access request based on the NFI interface protocol according to the access target and the access type, wherein the NFI interface protocol defines a general interface, a corresponding interaction signal set, a timing, and an interaction behavior between a controller Controller and a physical layer port PHY; and an access unit configured to control the interaction signal according to the control timing to implement memory access to the target to be accessed.

[0015] A NAND-Flash memory access device based on the NFI interface protocol, comprising:

[0016] a processor; and a memory arranged to store computer-executable instructions that, when executed, cause the processor to perform the following operations: determining a target to be accessed and an access type corresponding to a received access request; based on the NFI interface protocol, determining an interaction signal and a control timing corresponding to the access request according to the access target and the access type, wherein the NFI interface protocol defines a general interface, a corresponding interaction signal set, a timing, and an interaction behavior between a controller Controller and a physical layer port PHY; controlling the interaction signal according to the control timing to implement memory access to the target to be accessed.

[0017] A computer-readable storage medium stores one or more programs. When the one or more programs are executed by an electronic device including a plurality of application programs, the electronic device is caused to perform the following operations: determining a target to be accessed and an access type corresponding to a received access request; based on the NFI interface protocol, determining an interaction signal and a control timing corresponding to the access request according to the access target and the access type, where the NFI interface protocol defines a general interface, a corresponding set of interaction signals, a timing, and an interaction behavior between a Controller and a physical layer port PHY; controlling the interaction signal according to the control timing to implement memory access to the target to be accessed.

[0018] The above at least one technical solution adopted in the embodiments of the present application can achieve the following beneficial effects:

[0019] By using the NAND-Flash memory access method based on the NFI interface protocol provided in the embodiments of the present application, a set of general NFI interface protocols for between a NAND-Flash Controller and a PHY is defined. After determining the target to be accessed and the access type corresponding to the received access request, the interaction signal and the control timing corresponding to the access request can be determined based on this general NFI interface protocol, and then the interaction signal can be controlled according to the control timing to implement memory access to the target to be accessed, greatly improving the access efficiency; at the same time, using this general NFI interface protocol can implement the interconnection operation between NAND-Flash Controllers and PHYs of different manufacturers, avoiding the need to design corresponding hardware circuits and memory access methods for each different manufacturer, greatly improving the chip R & D efficiency and reducing the design cost. Description of the Drawings

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0021] Figure 1 It is a schematic flowchart of a specific process of a NAND-Flash memory access method based on the NFI interface protocol provided by an embodiment of the present application;

[0022] Figure 2 It is a schematic diagram of interface signal interaction of a NAND-Flash memory access method based on the NFI interface protocol provided by an embodiment of the present application;

[0023] Figure 3 It is a schematic diagram of interface signal interaction of a NAND-Flash memory access method based on the NFI interface protocol provided by an embodiment of the present application;

[0024] Figure 4 A timing diagram of the interaction between the NFI Command Interface and the NAND interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0025] Figure 5 A schematic diagram of the interaction of interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0026] Figure 6 A timing diagram of the interaction between the NFI Command Interface and the NAND interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0027] Figure 7 A schematic diagram of the interaction of interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0028] Figure 8 A timing diagram of the interaction between the NFI Command Interface and the NAND interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0029] Figure 9 A timing diagram of the interaction between the NFI Command Interface and the NAND interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0030] Figure 10 A schematic diagram of the interaction of interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0031] Figure 11 A timing diagram of the interaction between the NFI Command Interface and the NAND interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0032] Figure 12 A timing diagram of the interaction between the NFI Command Interface and the NAND interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0033] Figure 13 A schematic diagram of the interaction of interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0034] Figure 14 A timing diagram of the interaction between the NFI Command Interface and the NAND interface signals based on the NFI interface protocol provided by an embodiment of this application;

[0035] Figure 15A timing diagram of signal interaction between the NFI Command Interface and the NAND interface based on the NFI interface protocol provided by an embodiment of the present application;

[0036] Figure 16 A schematic diagram of interface signal interaction based on the NFI interface protocol provided by an embodiment of the present application;

[0037] Figure 17 A timing diagram of signal interaction between the NFI Command Interface and the NAND interface based on the NFI interface protocol provided by an embodiment of the present application;

[0038] Figure 18 A timing diagram of signal interaction between the NFI Command Interface and the NAND interface based on the NFI interface protocol provided by an embodiment of the present application;

[0039] Figure 19 A schematic diagram of interface signal interaction based on the NFI interface protocol provided by an embodiment of the present application;

[0040] Figure 20 A timing diagram of signal interaction between the NFI Command Interface and the NAND interface based on the NFI interface protocol provided by an embodiment of the present application;

[0041] Figure 21 A timing diagram of signal interaction between the NFI Command Interface and the NAND interface based on the NFI interface protocol provided by an embodiment of the present application;

[0042] Figure 22 A schematic diagram of interface signal interaction based on the NFI interface protocol provided by an embodiment of the present application;

[0043] Figure 23 A timing diagram of signal interaction between the NFI Command Interface and the NAND interface based on the NFI interface protocol provided by an embodiment of the present application;

[0044] Figure 24 A specific structural schematic diagram of a NAND-Flash memory access device based on the NFI interface protocol provided by an embodiment of the present application;

[0045] Figure 25 A specific structural schematic diagram of a NAND-Flash memory access device based on the NFI interface protocol provided by an embodiment of the present application. Detailed implementation manners

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments of this application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the scope of protection of this application.

[0047] The following will detail the technical solutions provided by each embodiment of this application in conjunction with the drawings.

[0048] A NAND-Flash memory access method based on the NFI interface protocol provided by an embodiment of this application is used to solve the problem that since the designers of the existing Controller and PHY parts are different, in order to achieve the interconnection and access between the two, it is necessary to specifically design the corresponding hardware circuit and memory access method each time, which in turn leads to a reduction in the R & D efficiency of the chip, an increase in the design cost, and a significant reduction in the efficiency of memory access.

[0049] The specific implementation process schematic diagram of the NAND-Flash memory access method based on the NFI interface protocol provided by this application is as Figure 1 shown, and mainly includes the following steps:

[0050] Step 11, determine the target to be accessed and the access type corresponding to the received access request.

[0051] In the embodiment of this application, the target to be accessed determined according to the access request may be, for example, a specific NAND granule in the NAND-Flash.

[0052] Step 12, based on the NFI interface protocol, determine the interaction signals and control timing corresponding to the access request according to the access target and access type determined by executing Step 11.

[0053] In the embodiment of this application, a set of general interface protocols for the NAND-Flash PHY interface (NAND-Flash PHY interface, NFI) is defined. Through this NFI interface protocol, the general interface, the corresponding set of interaction signals, timing, and interaction behaviors between the controller Controller and the physical layer port PHY are defined. Based on this NFI interface protocol, even if the design manufacturers of the Controller and PHY parts are different, the interconnection between the two can be achieved based on this NFI interface protocol for memory access, avoiding the need to specifically design the corresponding hardware circuit and memory access method for different manufacturers each time, greatly improving the R & D efficiency of the chip and reducing the design cost.

[0054] In addition, it should be noted here that the NFI interface protocol defined in the embodiments of the present application can be applied to legacySDR protocol, ONFi (Open NAND-Flash Interface) protocol, Toggle protocol, and the latest JEDC230F, JEDC230G, and SCA protocols.

[0055] In one implementation, the set of interaction signals in the NFI interface protocol mainly includes the following categories:

[0056] Type a, global interface signal set:

[0057] In one implementation, the interface signals and interaction directions included in the global interface signal set provided by the embodiments of the present application are as Figure 2 shown, and specifically include the following interface signals:

[0058] a-1, clock signal nfi_clock, used to indicate the corresponding clock of the NFI bus processing unit in the Controller and PHY. In the embodiments of the present application, the width of the clock signal nfi_clock is 1.

[0059] a-2, reset signal nfi_reset, used to indicate the corresponding reset of the bus processing unit in the Controller and PHY. In the embodiments of the present application, the width of the reset signal nfi_reset is 1.

[0060] Type b, command signal set:

[0061] Among them, the interface signals in the command signal set correspond to the NFI command interface (Command Interface). Specifically, the interface signals and interaction directions included in the command signal set provided by the embodiments of the present application are as Figure 3 shown, and specifically include the following interface signals:

[0062] b-1, chip select signal nfi_cen, used to control the I / O interface CE (chip enable, flash CE pin) line of the NAND-Flash, associated with the chip enable interface of the NAND die. In the embodiments of the present application, the width of the chip select signal nfi_cen is equal to the width of the flash CE pin.

[0063] b-2, command send signal nfi_cle, used to control the I / O interface CLE line of the NAND-Flash, associated with the command latch enable interface of the NAND die. In the embodiments of the present application, the width of the command send signal nfi_cle is 4.

[0064] b-3. Send the address signal nfi_ale to control the ALE line of the I / O interface of the NAND-Flash, which is associated with the address latch enable interface of the NAND die. In the embodiment of the present application, the width of the address signal nfi_ale is 4.

[0065] b-4. Send the write signal nfi_wen to control the WEN line of the I / O interface of the NAND-Flash, which is associated with the write enable interface of the NAND die. In the embodiment of the present application, the width of the write signal nfi_wen is 4.

[0066] b-5. Send the write protection signal nfi_wpn to control the WPn line of the I / O interface of the NAND-Flash, which is associated with the write protection interface of the NAND die. In the embodiment of the present application, the width of the write protection signal nfi_wpn is equal to the width of the WP pin.

[0067] In the embodiment of the present application, taking the command latch command as an example, the timing relationship between the NFI Command Interface and the NAND interface signals is as Figure 4 shown. Define the delay delay from the NFI interface to the NAND interface as t cmd_delay .

[0068] Type c, read / write signal set. Among them, the read / write signal set further includes the following four signal subsets, which are respectively:

[0069] Type c1, write control signal subset. The interface signals in this command signal set correspond to the NFI Write Data Interface. The interface signals and interaction directions included in the write control signal subset provided in the embodiment of the present application are as Figure 5 shown. Specifically, it includes the following interface signals:

[0070] c1-1. Write enable signal nfi_wrdata_en, which is used to indicate that data is written into the memory. The width of the write enable signal nfi_wrdata_en is 1.

[0071] c1-2. Direction control signal nfi_wrdata, which is used to indicate the data write direction. The width of the direction control signal nfi_wrdata is equal to the width of the written data.

[0072] c1-3, the DBI write direction control signal nfi_wrdata_dbi, is used to control the DBI line of the I / O interface of the NAND-Flash. Here, DBI refers to the Data Bus Inversion pin (fully named Data Bus Inversion, DBI pin), and the width of the DBI write direction control signal nfi_wrdata_dbi is 4.

[0073] c1-4, the DQS write direction control signal nfi_wdqs, is used to control the DQS / DQSn differential signal of the I / O interface of the NAND-Flash. Here, DQS refers to the Bi-directional Data Strobe pin (DQS pin), which is used for signal synchronization between the memory and the memory controller, and the width of the DQS write direction control signal nfi_wdqs is 4.

[0074] In the embodiment of the present application, the timing relationship between the NFI Write Data Interface and the NAND interface signals is as Figure 6 shown, where the delay delay from the NFI interface to the NAND interface is defined as twrlat.

[0075] Type c2, the SDR read control signal subset. The interface signals in this SDR read control signal subset correspond to the NFI SDR Read Data Interface. The interface signals and interaction directions included in the SDR read control signal subset provided in the embodiment of the present application are as Figure 7 shown, and specifically include the following interface signals:

[0076] c2-1, the SDR read enable signal nfi_sdr_rddata_en, is used to indicate that data is read from the memory, and the width of the SDR read enable signal nfi_sdr_rddata_en is 1.

[0077] c2-2, the SDR read data signals nfi_sdr_rddata, nfi_sdr_rddata_dbi, are used to indicate the data read by SDR.

[0078] Among them, the width of the nfi_sdr_rddata signal is 8, and the width of the nfi_sdr_rddata_dbi signal is 1.

[0079] c2-3, the SDR read data valid flag nfi_sdr_rddata_vld, is used to indicate the validity of the data read by SDR, and the width of the nfi_sdr_rddata_vld signal is 1.

[0080] In the embodiment of the present application, the timing relationship between the NFI SDR Read Data Interface and the NAND interface signals is as Figure 8 and Figure 9 shown, where Figure 8 represents the timing diagram of the NFI SDR Read Data Interface command transmission, Figure 9 represents the timing diagram of the NFI SDR Read Data Interface data reception, and the delay from the NAND interface returning data to the NFI interface receiving data is defined as t sdr_rdlat .

[0081] Type c3, a subset of the DDR read control signals. The interface signals in this subset of the DDR read control signals correspond to the NFI DDR read data interface (NFI DDR Read Data Interface). The interface signals and interaction directions included in the subset of the DDR read control signals provided in the embodiment of the present application are as Figure 10 shown, and specifically include the following interface signals:

[0082] c3-1, differential line control signal nfi_ren, used to control the REn / RE differential line of the I / O interface of the NAND-Flash. The width of the differential line control signal nfi_ren is 4.

[0083] c3-2, read enable signal nfi_rddata_en, used to indicate that data is read from the memory. The width of the read enable signal nfi_rddata_en is 1.

[0084] c3-3, read data signals nfi_rddata, nfi_rddata_dbi, used to indicate the read data.

[0085] Among them, the width of the nfi_rddata signal is equal to the width of the read data, and the width of the nfi_rddata_dbi signal is 4

[0086] c3-4, read data valid flag nfi_rddata_vld, used to indicate the validity of the read data. The width of the read data valid flag nfi_rddata_vld is 1.

[0087] In the embodiment of the present application, the timing relationship between the NFI DDR Read Data Interface and the NAND interface signals is as Figure 11 and Figure 12 shown, where Figure 11 represents the timing diagram of the NFI DDR Read Data Interface command transmission,Figure 12 It represents the timing diagram of NFI DDR Read Data Interface data reception. The delay from the data returned by the NAND interface to the data received by the NFI interface is defined as t ddr_rdlat 。

[0088] Type c4, a subset of SCA interface read control signals. The interface signals in this subset of SCA interface read control signals correspond to the NFI SCA read data interface (NFI SCA Read Data Interface). The interface signals and interaction directions included in the subset of SCA interface read control signals provided in the embodiments of the present application are as Figure 13 shown, and specifically include the following interface signals:

[0089] c4-1, SCA read enable signal nfi_sca_rddata_en, used to indicate that data is read from the memory. The width of the SCA read enable signal nfi_sca_rddata_en is 1.

[0090] c4-2, SCA read data signal nfi_sca_rddata, used to indicate the data read by the SCA. The width of the SCA read data signal nfi_sca_rddata is 8.

[0091] c4-3, SCA read data valid flag nfi_sca_rddata_vld, used to indicate the validity of the data read by the SCA. The width of the SCA read data valid flag nfi_sca_rddata_vld is 1.

[0092] In the embodiments of the present application, the timing relationship between the NFI SCA Read Data Interface and the NAND interface signals is as Figure 14 and Figure 15 shown, where Figure 14 represents the timing diagram of NFI SCA Read Data Interface command transmission, Figure 15 represents the timing diagram of NFI SCA Read Data Interface data reception. The delay from the data returned by the NAND interface to the data received by the NFI interface is defined as t sca_rdlat 。

[0093] Type d, update signal set:

[0094] Among them, the interface signals in this update signal set correspond to the NFI update interface (NFI Update Interface).

[0095] In one implementation, the interface signals and interaction directions included in the update signal set provided by the embodiments of the present application are as follows Figure 16 shown, specifically including the following interface signals:

[0096] d-1, Controller update request signal nfi_ctrlupd_req, an update request sent from the Controller to the PHY, and the width of the nfi_ctrlupd_req signal is 1.

[0097] d-2, Controller update response signal nfi_ctrlupd_ack, an update response sent from the PHY to the Controller, and the width of the nfi_ctrlupd_ack signal is 1.

[0098] d-3, PHY update request signal nfi_phyupd_req, an update request sent from the PHY to the Controller, and the width of the nfi_phyupd_req signal is 1.

[0099] d-4, PHY update response signal nfi_phyupd_ack, an update response sent from the Controller to the PHY, and the width of the nfi_phyupd_ack signal is 1.

[0100] d-5, PHY update type signal nfi_phyupd_type, used to indicate the update type of the PHY, and the width of the nfi_phyupd_type signal is 2.

[0101] In the embodiments of the present application, the timing relationship of the Controller for update is as follows Figure 17 shown, where the time from the update request (update request) initiated by the Controller to the PHY feedback response (response) is defined as t ctrlupd_min .

[0102] In the embodiments of the present application, the timing relationship of the PHY for update is as follows Figure 18 shown, where the time from the update request (update request) initiated by the PHY to the Controller feedback response (response) is defined as t phyupd_resp .

[0103] Type e, status signal set:

[0104] Among them, the interface signals in the status signal set correspond to the NFI Status Interface.

[0105] The interface signals and interaction directions included in the status signal concentration provided by the embodiments of the present application are as follows Figure 19 shown, and specifically include the following interface signals:

[0106] e-1, PHY initialization enable signal nfi_init_start, used to indicate the start of PHY initialization, and the width of the nfi_init_start signal is 1.

[0107] e-2, initialization completion signal nfi_init_complete, used to indicate the completion of PHY initialization, and the width of the nfi_init_complete signal is 1.

[0108] e-3, initialization configuration information nfi_init_info, and the width of the nfi_init_info signal is 2.

[0109] e-4, PHY status information nfi_status, and the width of the nfi_status signal is 2.

[0110] e-5, PHY interrupt signal nfi_int, and the width of the nfi_int signal is 1.

[0111] In the embodiments of the present application, the timing relationship of the initialization (Initial) state is as follows Figure 20 shown, the initialization of the PHY is triggered by the nfi_init_start signal, and the initialization completion status is fed back by the nfi_init_complete signal.

[0112] In the embodiments of the present application, the timing relationship of the interrupt (Error) state is as follows Figure 21 shown, the interrupt signal is initiated by the nfi_int signal, and the interrupt (error) information can be fed back through the nfi_status signal.

[0113] Type f, low-power signal set:

[0114] Among them, the interface signals in the low-power signal set correspond to the NFI low-power interface.

[0115] The interface signals and interaction directions included in the low-power signal concentration provided by the embodiments of the present application are as follows Figure 22 shown, and specifically include the following interface signals:

[0116] f-1, low-power request signal nfi_lp_req, sent from the Controller to the PHY for low-power mode request, and the width of the nfi_lp_req signal is 1.

[0117] f-2. The low-power response signal nfi_lp_ack is sent from the PHY to the Controller for low-power mode response. The width of the nfi_lp_ack signal is 1.

[0118] f-3. The low-power exit signal nfi_lp_wakeup is used to control the time to exit the low-power mode. The width of the nfi_lp_wakeup signal is 2.

[0119] In the embodiment of the present application, the timing relationship of the low-power request is as Figure 23 shown. The time from the low-power request signal (low power request) initiated by the Controller to the low-power response signal (response) fed back by the PHY is defined as t lp_resp , and at the same time, the time from the Controller exiting the low-power mode to the PHY exiting the low-power mode is defined as t lp_wakeup .

[0120] In the embodiment of the present application, the access types may include reading data and writing data. For these two types of access, the access process of the NAND flash memory is composed of several processes such as sending commands, sending addresses, sending data, and reading data. According to the above interface signal set, the interface signals corresponding to different processes can be determined. Then, after determining the target to be accessed and the access type, the interaction signals and control timing corresponding to the access request can be determined.

[0121] Step 13. Control the interaction signals according to the control timing determined by executing Step 12 to implement the memory access to the target to be accessed.

[0122] By using the NAND-Flash memory access method based on the NFI interface protocol provided in the embodiment of the present application, a set of general NFI interface protocols for NAND-Flash Controller and PHY is defined. After determining the target to be accessed and the access type corresponding to the received access request, the interaction signals and control timing corresponding to the access request can be determined based on this general NFI interface protocol. Then, the interaction signals can be controlled according to the control timing to implement the memory access to the target to be accessed, which greatly improves the access efficiency. At the same time, using this general NFI interface protocol can realize the interconnection operation between NAND-Flash Controllers and PHYs of different manufacturers, avoiding the need to design corresponding hardware circuits and memory access methods for each different manufacturer, greatly improving the chip R & D efficiency and reducing the design cost.

[0123] In one embodiment, the embodiment of the present application further provides a NAND-Flash memory access device based on the NFI interface protocol, which is used to solve the problem that since the designers of the existing Controller and PHY parts are different, in order to realize the interconnection and access between the two, it is necessary to specifically design the corresponding hardware circuit and memory access method each time, which in turn leads to a reduction in the R & D efficiency of the chip, an increase in the design cost, and a significant reduction in the efficiency of memory access. The specific structural schematic diagram of the NAND-Flash memory access device based on the NFI interface protocol is as shown in Figure 24 shown, and includes: a request receiving unit 31, an interaction signal determining unit 32, and an access unit 33.

[0124] Among them, the request receiving unit 31 is used to determine the target to be accessed and the access type corresponding to the received access request;

[0125] The interaction signal determining unit 32 is used to determine the interaction signal and control timing corresponding to the access request based on the NFI interface protocol according to the access target and the access type, wherein the NFI interface protocol defines the general interface, the corresponding interaction signal set, timing, and interaction behavior between the Controller and the physical layer port PHY;

[0126] The access unit 33 is used to control the interaction signal according to the control timing to realize the memory access to the target to be accessed.

[0127] In one embodiment, the interface signal set may specifically include: a global interface signal set, a command signal set, a read / write signal set, an update signal set, a status signal set, and a low-power signal set.

[0128] In one embodiment, the interface signals in the global interface signal set specifically include: a clock signal nfi_clock, which is used to indicate the clock corresponding to the bus processing unit in the Controller and the PHY; a reset signal nfi_reset, which is used to indicate the reset corresponding to the bus processing unit in the Controller and the PHY.

[0129] In one embodiment, the interface signals in the command signal set specifically include: a chip select signal nfi_cen for controlling the CE line of the I / O interface of the NAND-Flash; a command send signal nfi_cle for controlling the CLE line of the I / O interface of the NAND-Flash; an address send signal nfi_ale for controlling the ALE line of the I / O interface of the NAND-Flash; a write signal nfi_wen for controlling the WEN line of the I / O interface of the NAND-Flash; and a write protection signal nfi_wpn for controlling the WPn line of the I / O interface of the NAND-Flash.

[0130] In one embodiment, the read / write signal set may specifically include: a write control signal subset, a single data rate (SDR) read control signal subset, a double data rate (DDR) read control signal subset, and an SCA interface read control signal subset.

[0131] In one embodiment, the interface signals in the write control signal subset may specifically include: a write enable signal nfi_wrdata_en for indicating data writing to the memory; a direction control signal nfi_wrdata for indicating the data writing direction; a DBI write direction control signal nfi_wrdata_dbi for controlling the DBI line of the I / O interface of the NAND-Flash; and a DQS write direction control signal nfi_wdqs for controlling the DQS / DQSn differential signal of the I / O interface of the NAND-Flash.

[0132] In one embodiment, the interface signals in the SDR read control signal subset may specifically include: an SDR read enable signal nfi_sdr_rddata_en for indicating data reading from the memory; SDR read data signals nfi_sdr_rddata and nfi_sdr_rddata_dbi for indicating the data read by SDR; and an SDR read data valid flag nfi_sdr_rddata_vld for indicating the validity of the data read by SDR.

[0133] In one embodiment, the interface signals in the DDR read control signal subset may specifically include: a differential line control signal nfi_ren for controlling the REn / RE differential line of the I / O interface of the NAND-Flash; a read enable signal nfi_rddata_en for indicating data reading from the memory; read data signals nfi_rddata and nfi_rddata_dbi for indicating the data read; and a read data valid flag nfi_rddata_vld for indicating the validity of the read data.

[0134] In one implementation, the interface signals in the SCA interface read control signal subset may specifically include: the SCA read enable signal nfi_sca_rddata_en, which is used to indicate that data is read from the memory; the SCA read data signal nfi_sca_rddata, which is used to indicate the data read by the SCA; and the SCA read data valid flag nfi_sca_rddata_vld, which is used to indicate the validity of the data read by the SCA.

[0135] In one implementation, the interface signals in the update signal subset may specifically include: the Controller update request signal nfi_ctrlupd_req, which is an update request sent by the Controller to the PHY; the Controller update response signal nfi_ctrlupd_ack, which is an update response sent by the PHY to the Controller; the PHY update request signal nfi_phyupd_req, which is an update request sent by the PHY to the Controller; the PHY update response signal nfi_phyupd_ack, which is an update response sent by the Controller to the PHY; and the PHY update type signal nfi_phyupd_type, which is used to indicate the update type of the PHY.

[0136] In one implementation, the interface signals in the status signal subset may specifically include: the PHY initialization enable signal nfi_init_start, which is used to indicate that the PHY starts initialization; the initialization completion signal nfi_init_complete, which is used to indicate that the PHY initialization is completed; the initialization configuration information nfi_init_info; the PHY status information nfi_status; and the PHY interrupt signal nfi_int.

[0137] In one implementation, the interface signals in the low-power signal subset may specifically include: the low-power request signal nfi_lp_req, which is sent by the Controller to the PHY for a low-power mode request; the low-power response signal nfi_lp_ack, which is sent by the PHY to the Controller for a low-power mode response; and the low-power exit signal nfi_lp_wakeup, which is used to control the time to exit the low-power mode.

[0138] By using the NAND-Flash memory access device based on the NFI interface protocol provided in the embodiments of the present application, a set of general NFI interface protocols for the NAND-Flash Controller and the PHY are defined. After determining the target to be accessed and the access type corresponding to the received access request, the interaction signals and control timing corresponding to the access request can be determined based on the general NFI interface protocol, and then the interaction signals can be controlled according to the control timing to achieve the memory access to the target to be accessed, greatly improving the access efficiency. At the same time, using the general NFI interface protocol can realize the interconnection operation between NAND-Flash Controllers and PHYs of different manufacturers, avoiding the need to specifically design corresponding hardware circuits and memory access methods for different manufacturers each time, greatly improving the chip R & D efficiency and reducing the design cost.

[0139] Figure 25 It is a schematic structural diagram of an electronic device according to an embodiment of the present application. Please refer to Figure 25 , at the hardware level, the electronic device includes a processor, and optionally also includes an internal bus, a network interface, and a memory. Among them, the memory may include internal memory, such as high-speed random access memory (Random-Access Memory, RAM), and may also include non-volatile memory, such as at least one disk memory, etc. Of course, the electronic device may also include other hardware required for other services.

[0140] The processor, network interface, and memory can be interconnected through the internal bus, and the internal bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 25 only a bidirectional arrow is used in

[0141] The memory is used to store programs. Specifically, the program may include program code, and the program code includes computer operation instructions. The memory may include internal memory and non-volatile memory, and provide instructions and data to the processor.

[0142] The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a NAND-Flash memory access device based on the NFI interface protocol at the logical level. The processor executes the program stored in the memory and is specifically used to perform the following operations: determining the target to be accessed and the access type corresponding to the received access request; based on the NFI interface protocol, determining the interaction signal and control timing corresponding to the access request according to the access target and the access type, where the NFI interface protocol defines the general interface, the corresponding set of interaction signals, timing, and interaction behavior between the controller (Controller) and the physical layer port (PHY); controlling the interaction signal according to the control timing to achieve memory access to the target to be accessed.

[0143] As described in the present application Figure 25 The method executed by the NAND-Flash memory access electronic device based on the NFI interface protocol disclosed in the above embodiments can be applied to or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor or by instructions in software form. The above processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed by the hardware decoding processor, or by a combination of the hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0144] Of course, in addition to the software implementation, the electronic device of the present application does not exclude other implementation manners, such as logic devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, and may also be hardware or a logic device.

[0145] An embodiment of the present application also provides a computer-readable storage medium storing one or more programs, where the one or more programs include instructions, and when the instructions are executed by a portable electronic device including a plurality of application programs, the portable electronic device can be enabled to execute Figure 1 the method of the illustrated embodiment, and specifically used to perform the following operations:

[0146] Determine the target to be accessed and the access type corresponding to the received access request; based on the NFI interface protocol, determine the interaction signal and control timing corresponding to the access request according to the access target and the access type, where the NFI interface protocol defines the general interface between a Controller and a physical layer port PHY, the corresponding interaction signal set, timing, and interaction behavior; control the interaction signal according to the control timing to implement memory access to the target to be accessed.

[0147] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0148] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for realizing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0149] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction means that implements the function specified in one or more of the blocks and / or processes, and / or processes Figure 1 one or more of the processes and / or blocks Figure 1 specified in the block or blocks.

[0150] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable apparatus provide steps for implementing the function specified in one or more of the processes and / or blocks Figure 1 one or more of the processes and / or blocks Figure 1 specified in the block or blocks.

[0151] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.

[0152] The memory may include non-permanent memory in the computer-readable medium, random access memory (RAM) and / or non-volatile memory such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0153] Computer-readable media includes both permanent and non-permanent, removable and non-removable media implemented by any method or technology for storing information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile discs (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transitory media such as modulated data signals and carrier waves.

[0154] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

[0155] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, system or computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0156] The above are only the embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A method for accessing NAND Flash memory based on the NFI interface protocol, characterized in that Including: Determine the target to be accessed and the access type corresponding to the received access request; Based on the NFI interface protocol, determine the interaction signal and control timing corresponding to the access request according to the access target and the access type, where the NFI interface protocol defines the general interface between the Controller and the physical layer port PHY, the corresponding interface signal set, timing, and interaction behavior; the NFI interface protocol is applicable to legacy SDR protocol, ONFi protocol, Toggle protocol, JEDC230F protocol, and SCA protocol; the interface signal set includes: global interface signal set, command signal set, write control signal subset, single data rate (SDR) read control signal subset, double data rate (DDR) read control signal subset, and SCA interface read control signal subset, update signal set, status signal set, and low-power signal set; the interface signals in the global interface signal set include: clock signal nfi_clock, which is used to indicate the clock corresponding to the bus processing unit in the Controller and the PHY; reset signal nfi_reset, which is used to indicate the reset corresponding to the bus processing unit in the Controller and the PHY; the interface signals in the write control signal subset include: write enable signal nfi_wrdata_en, which is used to indicate data writing to the memory; direction control signal nfi_wrdata, which is used to indicate the data writing direction; DBI write direction control signal nfi_wrdata_dbi, which is used to control the DBI line of the I / O interface of the NAND Flash; DQS write direction control signal nfi_wdqs, which is used to control the DQS / DQSn differential signal of the I / O interface of the NAND Flash. Control the interaction signal according to the control timing to implement memory access to the target to be accessed.

2. The method according to claim 1, characterized in that, The interface signals in the command signal set include: Chip select signal nfi_cen, which is used to control the CE line of the I / O interface of the NAND Flash; Command send signal nfi_cle, which is used to control the CLE line of the I / O interface of the NAND Flash; Address send signal nfi_ale, which is used to control the ALE line of the I / O interface of the NAND Flash; Write signal nfi_wen, which is used to control the WEN line of the I / O interface of the NAND Flash; Write protection signal nfi_wpn, which is used to control the WPn line of the I / O interface of the NAND Flash.

3. The method according to claim 1, wherein The interface signals in the SDR read control signal subset include: SDR read enable signal nfi_sdr_rddata_en, which is used to indicate data reading from the memory; SDR read data signals nfi_sdr_rddata, nfi_sdr_rddata_dbi, which are used to indicate the data read by SDR. The SDR read data valid flag nfi_sdr_rddata_vld is used to indicate the validity of the data read by the SDR.

4. The method according to claim 1, wherein The interface signals in the DDR read control signal subset include: The differential line control signal nfi_ren is used to control the REn / RE differential lines of the I / O interface of the NAND Flash; The read enable signal nfi_rddata_en is used to indicate that data is read out from the memory; The read data signals nfi_rddata and nfi_rddata_dbi are used to indicate the read data; The read data valid flag nfi_rddata_vld is used to indicate the validity of the read data.

5. The method according to claim 1, wherein The interface signals in the SCA interface read control signal subset include: The SCA read enable signal nfi_sca_rddata_en is used to indicate reading information from the CA bus and control the transmission direction of the ALE / CLE signals in the SCA mode; The SCA read data signal nfi_sca_rddata is used to indicate the data read by the SCA; The SCA read data valid flag nfi_sca_rddata_vld is used to indicate the validity of the data read by the SCA.

6. The method according to claim 1, wherein The interface signals in the update signal subset include: The Controller update request signal nfi_ctrlupd_req is an update request sent by the Controller to the PHY; The Controller update response signal nfi_ctrlupd_ack is an update response sent by the PHY to the Controller; The PHY update request signal nfi_phyupd_req is an update request sent by the PHY to the Controller; The PHY update response signal nfi_phyupd_ack is an update response sent by the Controller to the PHY; The PHY update type signal nfi_phyupd_type is used to indicate the update type of the PHY.

7. The method according to claim 1, characterized in that The interface signals in the status signal subset include: The PHY initialization enable signal nfi_init_start is used to indicate the start of the PHY initialization; The initialization complete signal nfi_init_complete is used to indicate the completion of the PHY initialization; The initialization configuration information nfi_init_info; The PHY status information nfi_status; The PHY interrupt signal nfi_int.

8. The method according to claim 1, wherein The interface signals in the low power consumption signal subset include: The low power consumption request signal nfi_lp_req is sent by the Controller to the PHY for a low power consumption mode request; The low power consumption response signal nfi_lp_ack is sent by the PHY to the Controller for a low power consumption mode response; The low power consumption exit signal nfi_lp_wakeup is used to control the time to exit the low power consumption mode.

9. A NAND Flash memory access device based on the NFI interface protocol, characterized in that, Include: A request receiving unit, configured to determine a target to be accessed and an access type corresponding to a received access request; An interaction signal determining unit, configured to determine an interaction signal and a control timing corresponding to the access request based on the NFI interface protocol according to the access target and the access type, where the NFI interface protocol defines a general interface, a corresponding interaction signal set, a timing, and an interaction behavior between a Controller and a physical layer port PHY; the NFI interface protocol is applicable to legacy SDR protocols, ONFi protocols, Toggle protocols, JEDC230F protocols, and SCA protocols; the interface signal set includes: a global interface signal set, a command signal set, a write control signal subset, a single data rate SDR read control signal subset, a double data rate DDR read control signal subset, and an SCA interface read control signal subset, an update signal set, a status signal set, and a low-power signal set; the interface signals in the global interface signal set include: a clock signal nfi_clock, configured to indicate a clock corresponding to a bus processing unit in the Controller and the PHY; a reset signal nfi_reset, configured to indicate a reset corresponding to a bus processing unit in the Controller and the PHY; the interface signals in the write control signal subset include: a write enable signal nfi_wrdata_en, configured to indicate data writing into a memory; a direction control signal nfi_wrdata, configured to indicate a data writing direction; a DBI write direction control signal nfi_wrdata_dbi, configured to control an I / O interface DBI line of the NAND Flash; a DQS write direction control signal nfi_wdqs, configured to control an I / O interface DQS / DQSn differential signal of the NAND Flash; An access unit, configured to control the interaction signal according to the control timing to implement a memory access to the target to be accessed.

10. A NAND Flash memory access device based on an NFI interface protocol, comprising: A processor; A memory arranged to store computer-executable instructions, the executable instructions, when executed, causing the processor to execute the NAND Flash memory access method according to any one of claims 1-8.

11. A computer-readable storage medium, the computer-readable storage medium storing one or more programs, the one or more programs, when executed by an electronic device including a plurality of application programs, causing the electronic device to execute the NAND Flash memory access method according to any one of claims 1-8.

Images