Bubble sorting circuit, method, computer device and medium

Abstract

The present application relates to the field of computer technology and provides a bubble sorting circuit, method, computer device and medium. The bubble sorting circuit of the present application not only replaces the serial comparison sorting in the prior art with parallel comparison sorting, thereby having higher sorting efficiency, but also reduces the consumption of hardware resources by optimizing the logic implementation of the bubble sorting algorithm, and can maintain high sorting efficiency and sorting performance even when the number of maximum sorting elements is high, which is conducive to improving system performance and resource utilization.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a bubble sorting circuit, method, computer device and medium. Background Art

[0002] In the field of artificial intelligence and digital image processing, a large number of numerical sorting is required, such as sorting the grayscale value, brightness value, etc. of pixels. The sorting algorithm arranges a string of data in a specific order. It is not only the basic building block of computer science, but also the core component of data analysis, information retrieval, and various efficient computing applications. The bubble sort algorithm is a commonly used sorting algorithm. The basic operation of the bubble sort algorithm is to compare two elements and swap their positions if they are in the wrong order. In the prior art, the hardware implementation of the bubble sort algorithm is to repeatedly traverse the same array from beginning to end, and each traversal compares two adjacent elements and swaps positions when the order is wrong. Therefore, it is necessary to compare and sort in a serial manner, so that each traversal can sort the largest element to the end of the array, and can also sort the smallest element to the end of the array as needed. In order to achieve a complete sorting result, a number of comparators equal to the square of the difference between the number of the largest sorted elements minus one is required, so there is a lower space complexity, that is, only one additional space is needed to store the intermediate value during the exchange. However, the bubble sort algorithm and corresponding hardware implementation of the prior art, whether in ascending or descending order, rely on serial comparison and sorting, which results in a time complexity that is proportional to the square of the number of the largest sorted elements. Therefore, with the development of machine vision technology, the number of elements in the array that need to be sorted is increasing, and at the same time, the requirements for the running speed of the overall algorithm are getting higher and higher. The bubble sort algorithm and corresponding hardware implementation of the prior art are limited by the limitations of the basic principle of serial operation, and can only improve the overall speed by increasing the maximum clock frequency, that is, shortening the time for each comparison of adjacent elements, but the improvement effect is limited. In addition, as the number of the largest sorted elements increases, a sufficient number of comparators need to be provided, but only one of these comparators is working at the same time in the case of serial operation, and the other comparators are in an idle state, which results in a large number of resources occupied and low resource utilization, which is not conducive to improving system performance.

[0003] To this end, the present application provides a bubble sort circuit, method, computer device and medium, which not only replaces the serial comparison sort in the prior art with parallel comparison sort, thereby having higher sorting efficiency, but also reduces hardware resource consumption by optimizing the logical implementation of the bubble sort algorithm. Even when the maximum number of sorting elements is high, it can maintain high sorting efficiency and sorting performance, which is beneficial to improving system performance and resource utilization. Summary of the invention

[0004] In the first aspect, the present application provides a bubble sort circuit. The bubble sort circuit comprises: a first number of basic sorting units, wherein each of the first number of basic sorting units comprises a second number of comparison switches, the comparison switches are used to compare two elements input into the comparison switches and then output the two elements in a preset sorting manner, each of the first number of basic sorting units equally divides the second number of comparison switches into a first-level sorting circuit and a second-level sorting circuit, the first number of basic sorting units are connected step by step according to a first sequence, the first-level sorting circuit and the second-level sorting circuit in the basic sorting units of the same level in the first sequence satisfy a first corresponding relationship, and the output of the first-level sorting circuit in the basic sorting units of the same level is output to the second-level sorting circuit in the basic sorting units of the same level according to a first re-combination order based on the first corresponding relationship. A sorting circuit, wherein the second-level sorting circuit in the basic sorting unit of the previous level in the first sequence satisfies the second corresponding relationship with the first-level sorting circuit in the basic sorting unit of the next level, and the second-level sorting circuit in the basic sorting unit of the previous level is output to the first-level sorting circuit of the basic sorting unit of the next level according to a second re-combination order based on the second corresponding relationship; and a final-level sorting unit, wherein the final-level sorting unit includes a third-level sorting circuit having half of the second number of comparison switches, the second-level sorting circuit in the basic sorting unit of the last level in the first sequence satisfies the second corresponding relationship with the third-level sorting circuit in the final-level sorting unit, and the second-level sorting circuit in the basic sorting unit of the last level in the first sequence is output to the third-level sorting circuit in the final-level sorting unit according to a second re-combination order based on the second corresponding relationship.

[0005] Through the first aspect of the present application, not only is the serial comparison sorting in the prior art replaced by parallel comparison sorting, thereby having higher sorting efficiency, but also the hardware resource consumption is reduced by optimizing the logical implementation of the bubble sorting algorithm. Even when the maximum number of sorting elements is high, high sorting efficiency and sorting performance can be maintained, which is beneficial to improving system performance and resource utilization.

[0006] In a possible implementation manner of the first aspect of the present application, the preset sorting manner is to sort the larger element of the two elements input to the comparison switch first and to sort the smaller element of the two elements input to the comparison switch last.

[0007] In a possible implementation manner of the first aspect of the present application, the preset sorting manner is to sort the smaller element of the two elements input to the comparison switch first and to sort the larger element of the two elements input to the comparison switch last.

[0008] In a possible implementation manner of the first aspect of the present application, the first-level sorting circuit and the second-level sorting circuit included in each of the first number of basic sorting units respectively perform comparison and sorting in parallel.

[0009] In a possible implementation of the first aspect of the present application, all comparison switches in the first-level sorting circuit included in each of the first number of basic sorting units compare the elements of their respective inputs in parallel and output them according to the preset sorting method, and all comparison switches in the second-level sorting circuit included in each of the first number of basic sorting units compare the elements of their respective inputs in parallel and output them according to the preset sorting method.

[0010] In a possible implementation of the first aspect of the present application, all comparison switches in the third-level sorting circuit in the final-level sorting unit compare their respective input elements in parallel and output them according to the preset sorting method.

[0011] In a possible implementation of the first aspect of the present application, each comparison switch in the bubble sort circuit is configured through a register so that the preset sorting method can be adjusted to achieve ascending order or descending order.

[0012] In a possible implementation manner of the first aspect of the present application, each comparison switch in the bubble sort circuit supports sorting of unsigned numbers or signed numbers.

[0013] In a possible implementation manner of the first aspect of the present application, each comparison switch in the bubble sort circuit supports sorting data in multiple bases, including binary, decimal, and hexadecimal.

[0014] In a possible implementation of the first aspect of the present application, the bubble sort circuit is used to sort multiple elements to be sorted to obtain a bubble sort result of the multiple elements to be sorted, and the multiple elements to be sorted are input to the first-level sorting circuit in the first-level basic sorting unit in the first order, and the output of the third-level sorting circuit in the last-level sorting unit is the bubble sort result of the multiple elements to be sorted.

[0015] In a possible implementation of the first aspect of the present application, the first number and the second number are both determined based on the number of the multiple elements to be sorted, the number of comparison switches included in the first-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number, and the number of comparison switches included in the second-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number.

[0016] In a possible implementation of the first aspect of the present application, the number of the multiple elements to be sorted is N, N is an even number greater than or equal to 4, N is expressed as 2 to the power of M, M is a positive integer greater than or equal to 2, the first number is 2 to the power of M minus 1 minus 1, the second number is N, the number of comparison switches included in the first-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of N, the number of comparison switches included in the second-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of N, and the number of comparison switches included in the third-level sorting circuit of the final-level sorting unit is half of N.

[0017] In a possible implementation manner of the first aspect of the present application, N is 4, 8, 16 or 32.

[0018] In a possible implementation of the first aspect of the present application, when the number of the multiple elements to be sorted is an odd number, an equivalent array of elements to be sorted having an even number is obtained by adding 0 elements to the multiple elements to be sorted, and the bubble sort result of the equivalent array of elements to be sorted is used to determine the bubble sort result of the multiple elements to be sorted.

[0019] In a possible implementation of the first aspect of the present application, the first corresponding relationship indicates a first arrangement order starting from the first element to the last element, in which every two elements in order are output by the same comparison switch, wherein the first recombinant order based on the first corresponding relationship includes: reordering the first element in the first arrangement order before the last element in the first arrangement order, thereby obtaining an adjusted first arrangement order, in which every two elements in order are input to the same comparison switch.

[0020] In a possible implementation manner of the first aspect of the present application, the first arrangement order is elements (B1, B2, B3, B4, B5, B6, B7, B8), and the elements B1 and B2, B3 and B4, B5 and B6, B7 and B8 in the first arrangement order are each output by the same comparison switch, and the adjusted first arrangement order is elements (B2, B3, B4, B5, B6, B7, B1, B8), and the elements B2 and B3, B4 and B5, B6 and B7, B1 and B8 in the adjusted first arrangement order are each input to the same comparison switch.

[0021] In a possible implementation of the first aspect of the present application, the second corresponding relationship indicates a second arrangement order starting from the first element to the last element, and every two elements in the second arrangement order are output by the same comparison switch, wherein the second recombinant order based on the second corresponding relationship includes: reordering the previous element of the last element in the second arrangement order before the first element in the second arrangement order, thereby obtaining an adjusted second arrangement order, and every two elements in the adjusted second arrangement order are input to the same comparison switch.

[0022] In a possible implementation manner of the first aspect of the present application, the second arrangement order is elements (C1, C2, C3, C4, C5, C6, C7, C8), and the element C1 and element C2, element C3 and element C4, element C5 and element C6, element C7 and element C8 in the second arrangement order are each output by the same comparison switch, and the adjusted second arrangement order is elements (C7, C1, C2, C3, C4, C5, C6, C8), and the element C7 and element C1, element C2 and element C3, element C4 and element C5, element C6 and element C8 in the adjusted second arrangement order are each input to the same comparison switch.

[0023] In a possible implementation manner of the first aspect of the present application, the bubble sort circuit is applied to sort the grayscale values ​​of pixels in a digital image processing task.

[0024] In the second aspect, the present application provides a bubble sorting method. The bubble sorting method comprises: connecting a first number of basic sorting units step by step according to a first order, and finally connecting the last-level sorting unit, so as to construct a bubble sorting circuit, wherein each of the first number of basic sorting units comprises a second number of comparison switches, and the comparison switches are used to compare two elements input into the comparison switches and then output the two elements according to a preset sorting method, and each of the first number of basic sorting units divides the second number of comparison switches equally into a first-level sorting circuit and a second-level sorting circuit, and the first number of basic sorting units are connected step by step according to the first order, and the first-level sorting circuit and the second-level sorting circuit in the basic sorting units of the same level in the first order satisfy a first corresponding relationship, and the output of the first-level sorting circuit in the basic sorting units of the same level is output to the second-level sorting circuit in the basic sorting units of the same level according to a first re-combination order based on the first corresponding relationship, and the basic sorting units of the previous level in the first order are connected step by step according to the first order. The second-level sorting circuit in the sorting unit satisfies the second corresponding relationship with the first-level sorting circuit of the basic sorting unit of the next level, and the second-level sorting circuit in the basic sorting unit of the previous level is output to the first-level sorting circuit of the basic sorting unit of the next level according to the second re-combination order based on the second corresponding relationship, the last-level sorting unit includes a third-level sorting circuit having half of the second number of comparison switches, the second-level sorting circuit in the basic sorting unit of the last level in the first sequence and the third-level sorting circuit in the last-level sorting unit satisfy the second corresponding relationship, and the second-level sorting circuit in the basic sorting unit of the last level in the first sequence is output to the third-level sorting circuit in the last-level sorting unit according to the second re-combination order based on the second corresponding relationship; a plurality of elements to be sorted are input to the first-level sorting circuit in the basic sorting unit of the first level in the first sequence, and then the output of the third-level sorting circuit in the last-level sorting unit is used as the bubble sort result of the plurality of elements to be sorted.

[0025] Through the second aspect of the present application, not only is parallel comparison sorting used to replace the serial comparison sorting in the prior art, thereby achieving higher sorting efficiency, but also the logical implementation of the bubble sorting algorithm is optimized to reduce hardware resource consumption. Even when the maximum number of sorting elements is high, high sorting efficiency and sorting performance can be maintained, which is beneficial to improving system performance and resource utilization.

[0026] In a possible implementation of the second aspect of the present application, the first number and the second number are both determined based on the number of the multiple elements to be sorted, the number of comparison switches included in the first-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number, and the number of comparison switches included in the second-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number.

[0027] In a possible implementation of the second aspect of the present application, the first corresponding relationship indicates a first arrangement order starting from the first sorted element to the last sorted element, and every two elements in order in the first arrangement order are output by the same comparison switch, wherein the first recombinant order based on the first corresponding relationship includes: reordering the first sorted element in the first arrangement order before the last sorted element in the first arrangement order, thereby obtaining an adjusted first arrangement order, and every two elements in order in the adjusted first arrangement order are input to the same comparison switch.

[0028] In a possible implementation of the second aspect of the present application, the second corresponding relationship indicates a second arrangement order starting from the first element to the last element, and every two elements in the second arrangement order are output by the same comparison switch, wherein the second recombinant order based on the second corresponding relationship includes: reordering the previous element of the last element in the second arrangement order before the first element in the second arrangement order, thereby obtaining an adjusted second arrangement order, and every two elements in the adjusted second arrangement order are input to the same comparison switch.

[0029] In a third aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0030] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which, when executed on a computer device, enable the computer device to execute a method according to any one of the implementation modes of any of the above aspects.

[0031] In a fifth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic diagram of a bubble sorting circuit provided in an embodiment of the present application;

[0034] Figure 2 Provided in the embodiments of this application Figure 1 A schematic diagram of a first corresponding relationship in the bubble sort circuit and a first re-combination order based on the first corresponding relationship;

[0035] Figure 3 Provided in the embodiments of this application Figure 1 A schematic diagram of a second corresponding relationship in the bubble sort circuit and a second re-combination order based on the second corresponding relationship;

[0036] Figure 4 A schematic diagram of a bubble sorting method provided in an embodiment of the present application;

[0037] Figure 5 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0039] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0040] Figure 1 A schematic diagram of a bubble sorting circuit provided in an embodiment of the present application. Figure 1As shown, the bubble sort circuit 100 includes a plurality of basic sorting units, including a basic sorting unit A103, a basic sorting unit B105, and a basic sorting unit C107. The bubble sort circuit 100 also includes a final-level sorting unit 102. Each of the plurality of basic sorting units includes 8 comparison switches, and each comparison switch is used to compare two elements input into the comparison switch and output the two elements according to a preset sorting method. Each basic sorting unit divides the 8 comparison switches equally into a first-level sorting circuit and a second-level sorting circuit, that is, the first-level sorting circuit and the second-level sorting circuit each have 4 comparison switches. Specifically, the basic sorting unit A103 includes a first-level sorting circuit A110 and a second-level sorting circuit A120; the basic sorting unit B105 includes a first-level sorting circuit B130 and a second-level sorting circuit B140; the basic sorting unit C107 includes a first-level sorting circuit C150 and a second-level sorting circuit C160. The plurality of basic sorting units are connected level by level according to the first order, as shown in FIG. Figure 1 As shown, the basic sorting unit A103 is the first basic sorting unit in the first sequence, and then the basic sorting unit A103 is followed by the basic sorting unit B105, and the basic sorting unit B105 is followed by the basic sorting unit C107. A first corresponding relationship is satisfied between the first-level sorting circuit and the second-level sorting circuit in the basic sorting units of the same level in the first sequence, and the output of the first-level sorting circuit in the basic sorting units of the same level is output to the second-level sorting circuit in the basic sorting units of the same level according to a first re-combination order based on the first corresponding relationship. A second corresponding relationship is satisfied between the second-level sorting circuit in the basic sorting units of the previous level in the first sequence and the first-level sorting circuit in the basic sorting units of the next level, and the second-level sorting circuit in the basic sorting units of the previous level is output to the first-level sorting circuit in the basic sorting units of the next level according to a second re-combination order based on the second corresponding relationship.

[0041] See also Figure 1The basic sorting unit A103 includes a first-level sorting circuit A110 and a second-level sorting circuit A120, wherein the first-level sorting circuit A110 includes four comparison switches, namely, a comparison switch A111 of the first-level sorting circuit A110, a comparison switch B112 of the first-level sorting circuit A110, a comparison switch C113 of the first-level sorting circuit A110, and a comparison switch D114 of the first-level sorting circuit A110. The second-level sorting circuit A120 includes four comparison switches, namely, a comparison switch A121 of the second-level sorting circuit A120, a comparison switch B122 of the second-level sorting circuit A120, a comparison switch C123 of the second-level sorting circuit A120, and a comparison switch D124 of the second-level sorting circuit A120. Continue to refer to Figure 1 , after the basic sorting unit A103 is the basic sorting unit B105, therefore, the basic sorting unit A103 is the basic sorting unit of the previous level, and relatively, the basic sorting unit B105 is the basic sorting unit of the next level. The basic sorting unit B105 includes a first-level sorting circuit B130 and a second-level sorting circuit B140. Among them, the first-level sorting circuit B130 includes 4 comparison switches, namely, the comparison switch A131 of the first-level sorting circuit B130, the comparison switch B132 of the first-level sorting circuit B130, the comparison switch C133 of the first-level sorting circuit B130, and the comparison switch D134 of the first-level sorting circuit B130. The second-stage sorting circuit B140 includes four comparison switches, namely, comparison switch A141 of the second-stage sorting circuit B140, comparison switch B142 of the second-stage sorting circuit B140, comparison switch C143 of the second-stage sorting circuit B140, and comparison switch D144 of the second-stage sorting circuit B140. Figure 1 , after the basic sorting unit B105 is the basic sorting unit C107, therefore, the basic sorting unit B105 is the basic sorting unit of the previous level, and relatively, the basic sorting unit C107 is the basic sorting unit of the next level. The basic sorting unit C107 includes a first-level sorting circuit C150 and a second-level sorting circuit C160. Among them, the first-level sorting circuit C150 includes 4 comparison switches, namely, the comparison switch A151 of the first-level sorting circuit C150, the comparison switch B152 of the first-level sorting circuit C150, the comparison switch C153 of the first-level sorting circuit C150, and the comparison switch D154 of the first-level sorting circuit C150. The second-stage sorting circuit C160 includes four comparison switches, namely, comparison switch A161 of the second-stage sorting circuit C160, comparison switch B162 of the second-stage sorting circuit C160, comparison switch C163 of the second-stage sorting circuit C160, and comparison switch D164 of the second-stage sorting circuit C160.

[0042] See also Figure 1 ,from Figure 1 It can be seen that the first-level sorting circuit and the second-level sorting circuit in the same-level basic sorting unit in the first sequence satisfy the first corresponding relationship, and the output of the first-level sorting circuit in the same-level basic sorting unit is output to the second-level sorting circuit in the same-level basic sorting unit according to the first re-combination order based on the first corresponding relationship. Specifically, for the first-level sorting circuit and the second-level sorting circuit in the same-level basic sorting unit, the first-level sorting circuit A110 and the second-level sorting circuit A120 of the basic sorting unit A103 satisfy the first corresponding relationship, and the output of the first-level sorting circuit A110 is output to the second-level sorting circuit A120 according to the first re-combination order based on the first corresponding relationship. The first-level sorting circuit B130 and the second-level sorting circuit B140 of the basic sorting unit B105 satisfy the first corresponding relationship, and the output of the first-level sorting circuit B130 is output to the second-level sorting circuit B140 according to the first re-combination order based on the first corresponding relationship. The first level sorting circuit C150 and the second level sorting circuit C160 of the basic sorting unit C107 satisfy a first corresponding relationship, and the output of the first level sorting circuit C150 is output to the second level sorting circuit C160 according to a first re-combination order based on the first corresponding relationship. Figure 1 As shown, each comparison switch is used to compare the two elements input to the comparison switch and then output the two elements in a preset sorting manner. Therefore, each comparison switch has two input interfaces for receiving two elements, and two output interfaces for outputting the results of comparing and sorting the two received elements, which may be in ascending order or descending order, depending on the pre-configuration of the comparison switch. Figure 1 There are also subsequent figures, which set a first recombination order based on the first correspondence relationship on the basis of the first correspondence relationship, and then direct the output of the first-level sorting circuit in the basic sorting unit of the same level that satisfies the first correspondence relationship to the input of the second-level sorting circuit, including directing the output of a specific comparison switch to the input of a specific comparison switch. In this way, by determining the first recombination order based on the first correspondence relationship, and optimizing how the output of the first-level sorting circuit in the basic sorting unit of the same level is directed to the input of the second-level sorting circuit based on the first recombination order, parallel comparison sorting is supported, that is, all comparison switches in the first-level sorting circuit can compare and sort their respective inputs in parallel and then output them, and all comparison switches in the second-level sorting circuit can compare and sort their respective inputs in parallel and then output them. In this way, unlike the serial comparison sorting in the prior art, the first recombination order is used to compare and sort the first-level sorting circuit in the first-level sorting circuit. Figure 1Taking the bubble sort circuit shown as an example, the bubble sort circuit provided in the embodiment of the present application can maintain high sorting efficiency and sorting performance without relying on a high clock frequency.

[0043] Continue reading Figure 1 ,from Figure 1 It can be seen that the second-level sorting circuit in the previous basic sorting unit in the first order and the first-level sorting circuit in the next basic sorting unit in the first order satisfy the second corresponding relationship, and the second-level sorting circuit in the previous basic sorting unit is output to the first-level sorting circuit of the next basic sorting unit in accordance with the second re-combination order based on the second corresponding relationship. Specifically, the basic sorting unit A103 is followed by the basic sorting unit B105, so the basic sorting unit A103 is the previous basic sorting unit, and the basic sorting unit B105 is the next basic sorting unit. The second-level sorting circuit A120 in the previous basic sorting unit, i.e., the basic sorting unit A103, and the first-level sorting circuit B130 in the next basic sorting unit, i.e., the basic sorting unit B105, satisfy the second corresponding relationship, and the output of the second-level sorting circuit A120 in the previous basic sorting unit, i.e., the basic sorting unit A103, is output to the first-level sorting circuit B130 in the next basic sorting unit, i.e., the basic sorting unit B105, in accordance with the second re-combination order based on the second corresponding relationship. After the basic sorting unit B105 is the basic sorting unit C107, therefore, the basic sorting unit B105 is the basic sorting unit of the previous level, and correspondingly, the basic sorting unit C107 is the basic sorting unit of the next level. The second level sorting circuit B140 in the basic sorting unit of the previous level, i.e., the basic sorting unit B105, and the first level sorting circuit C150 in the basic sorting unit of the next level, i.e., the basic sorting unit C107, satisfy a second corresponding relationship, and the output of the second level sorting circuit B140 in the basic sorting unit of the previous level, i.e., the basic sorting unit B105, is output to the first level sorting circuit C150 in the basic sorting unit of the next level, i.e., the basic sorting unit C107, according to the second re-combination order based on the second corresponding relationship. Figure 1 As shown, each comparison switch is used to compare the two elements input to the comparison switch and then output the two elements in a preset sorting manner. Therefore, each comparison switch has two input interfaces for receiving two elements, and two output interfaces for outputting the results of comparing and sorting the two received elements, which may be in ascending order or descending order, depending on the pre-configuration of the comparison switch. Figure 1There are also subsequent figures, which set a second re-combination order based on the second corresponding relationship based on the second corresponding relationship, and then guide the output of the second-level sorting circuit in the previous basic sorting unit that satisfies the second corresponding relationship to the input of the first-level sorting circuit of the next basic sorting unit, including guiding the output of a specific comparison switch to the input of a specific comparison switch. In this way, by determining the second re-combination order based on the second corresponding relationship, and optimizing how the output of the second-level sorting circuit in the previous basic sorting unit is guided to the input of the first-level sorting circuit of the next basic sorting unit based on the second re-combination order, parallel comparison sorting is supported, and multiple basic sorting units are connected step by step according to the first order, and finally connected to the last-level sorting unit, thereby realizing the hardware implementation of the bubble sort algorithm based on parallel sorting.

[0044] Continue reading Figure 1 The bubble sorting circuit 100 further includes a final-level sorting unit 102. The final-level sorting unit 102 includes a third-level sorting circuit 190 having half the second number of comparison switches, the second-level sorting circuit in the last-level basic sorting unit in the first sequence and the third-level sorting circuit 190 in the final-level sorting unit 102 satisfy the second corresponding relationship, and the second-level sorting circuit in the last-level basic sorting unit in the first sequence is output to the third-level sorting circuit 190 in the final-level sorting unit 102 according to the second re-combination order based on the second corresponding relationship. The third-level sorting circuit 190 includes four comparison switches, namely, a comparison switch A191 of the third-level sorting circuit 190, a comparison switch B192 of the third-level sorting circuit 190, a comparison switch C193 of the third-level sorting circuit 190, and a comparison switch D194 of the third-level sorting circuit 190. Here, the plurality of basic sorting units include a basic sorting unit A103, a basic sorting unit B105, and a basic sorting unit C107. Among them, the last level basic sorting unit in the first sequence is the basic sorting unit C107. Therefore, the second level sorting circuit C160 in the last level basic sorting unit in the first sequence, that is, the basic sorting unit C107, and the third level sorting circuit 190 in the final level sorting unit 102 satisfy the second corresponding relationship, and the second level sorting circuit C160 in the last level basic sorting unit in the first sequence, that is, the basic sorting unit C107, is output to the third level sorting circuit 190 in the final level sorting unit 102 according to the second re-combination order based on the second corresponding relationship. In this way, parallel comparison sorting is achieved.

[0045] See also Figure 1 , Figure 1The bubble sort circuit 100 shown is based on the example that the maximum number of sorting elements is 8, that is, it is assumed that the bubble sort algorithm needs to be performed on 8 elements to be sorted, and finally the bubble sort result of the 8 elements to be sorted is output. In order to achieve a complete sorting result, the hardware implementation based on serial comparison sorting in the prior art requires comparators with the number of squares of the difference between the number of the maximum sorting elements minus one. Here, the maximum number of sorting elements is 8, and the difference between the number of the maximum sorting elements minus one is 7. Therefore, the hardware implementation based on serial comparison sorting in the prior art requires 7 squared, that is, a total of 49 comparators, and requires a complex insertion pipeline to load data, and multiple rounds of traversal. Each round of traversal can only be compared and sorted by comparators one by one through a high-speed clock frequency, and finally the largest or smallest element is sorted to the end of the sequence. Different from the hardware implementation based on serial comparison sorting in the prior art, the bubble sort circuit provided in the embodiment of the present application is based on Figure 1 Taking the bubble sort circuit 100 shown as an example, not only does it replace the serial comparison sort in the prior art with parallel comparison sort, thereby having a higher sorting efficiency, but it also reduces hardware resource consumption by optimizing the logic implementation of the bubble sort algorithm, and can maintain a high sorting efficiency and sorting performance even when the maximum number of sorting elements is high, which is beneficial to improving system performance and resource utilization. Figure 1 For example, in order to output the bubble sort result of 8 elements to be sorted, the hardware implementation based on serial comparison sort in the prior art requires a total of 49 comparators. Figure 1 The bubble sort circuit 100 based on parallel comparison sorting requires a total of 28 comparison switches, and data can be conveniently inserted by simply inserting the pipeline, and the parallel comparison sorting can be controlled by a global clock.

[0046] Continue reading Figure 1 , Figure 1 The bubble sort circuit 100 shown in the figure takes the maximum number of sorting elements as 8 as an example, that is, it is assumed that the bubble sort algorithm needs to be performed on 8 elements to be sorted. For the maximum number of sorting elements of other values, such as 16 or 32, it can be Figure 1 The bubble sort circuit 100 shown in the figure is expanded to meet the requirements of other even numbers of maximum sorting elements. For an odd number of maximum sorting elements, a 0-filling method can be used, that is, adding elements with a value of 0 to the element set to be sorted, so as to perform bubble sorting under an even number of maximum sorting elements. In addition, the bubble sort circuit provided in the embodiment of the present application is based on Figure 1Taking the bubble sort circuit 100 shown as an example, it can not only flexibly adapt to the number of maximum sorting elements of other values, but also can greatly save hardware resources and improve sorting efficiency. As mentioned above, in order to achieve a complete sorting result, the hardware implementation based on serial comparison sorting in the prior art requires a number of comparators equal to the square of the difference between the number of maximum sorting elements minus one. Here, suppose the number of the multiple elements to be sorted is N, N is an even number greater than or equal to 4, N is expressed as 2 to the Mth power, M is a positive integer greater than or equal to 2, the first number is 2 to the Mth power minus 1 minus 1, the second number is N, the number of comparison switches included in the first-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of N, the number of comparison switches included in the second-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of N, and the number of comparison switches included in the third-level sorting circuit of the final-level sorting unit is half of N. Therefore, for the maximum number of sorting elements being N, N being expressed as 2 to the Mth power, the bubble sort circuit provided in the embodiment of the present application is based on Figure 1 Taking the bubble sort circuit 100 shown in FIG. 1 as an example, the number of basic sorting units required is 2 to the power of M minus 1 minus 1, which can be expressed as: M-1 -1. The number of all comparison switches included in each basic sorting unit is N, and is equally divided into the first-level sorting circuit and the second-level sorting circuit of the basic sorting unit of the same level. The number of the final-level sorting unit is maintained at 1, and the number of all comparison switches included in the third-level sorting circuit in the final-level sorting unit is half of N. Table 1 below illustrates how the bubble sorting circuit provided in the embodiment of the present application saves hardware resources:

[0047] Table 1

[0048]

[0049] See also Figure 1 From Table 1, it can be seen that the bubble sorting circuit provided in the embodiment of the present application is Figure 1Taking the bubble sort circuit 100 shown as an example, it can not only flexibly adapt to the number of maximum sorting elements of other values, but also can greatly save hardware resources and improve sorting efficiency. Compared with the hardware implementation based on serial comparison sorting in the prior art, the hardware implementation based on serial comparison sorting requires the number of comparators equal to the square of the difference between the number of maximum sorting elements and one, so when the number of maximum sorting elements is 4, the number of comparators is 3 squared, that is, 9; when the number of maximum sorting elements is 8, the number of comparators is 7 squared, that is, 49; when the number of maximum sorting elements is 16, the number of comparators is 15 squared, that is, 225; when the number of maximum sorting elements is 32, the number of comparators is 31 squared, that is, 961. It can be seen that as the number of maximum sorting elements increases, a sufficient number of comparators needs to be provided, and because the hardware implementation based on serial comparison sorting in the prior art requires a number of comparators that is proportional to the square of the number of maximum sorting elements, when the number of maximum sorting elements is high, a lot of hardware resources need to be occupied. Moreover, among these comparators, only one comparator is working at the same time when running in series, while the other comparators are idle, which results in a large number of occupied resources and low resource utilization, which is not conducive to improving system performance. The bubble sort circuit provided in the embodiment of the present application is based on Figure 1 Taking the bubble sort circuit 100 shown as an example, even when the number of maximum sorting elements is relatively high, it can maintain relatively high sorting efficiency and sorting performance, which is beneficial to improving system performance and resource utilization.

[0050] In conclusion, Figure 1 The bubble sort circuit shown not only replaces the serial comparison sort in the prior art with a parallel comparison sort, thereby having a higher sorting efficiency, but also reduces hardware resource consumption by optimizing the logical implementation of the bubble sort algorithm. It can maintain a high sorting efficiency and sorting performance even when the maximum number of sorting elements is high, which is beneficial to improving system performance and resource utilization.

[0051] Figure 2 Provided in the embodiments of this application Figure 1 Schematic diagram of the first corresponding relationship in the bubble sort circuit and the first re-combination order based on the first corresponding relationship. Figure 1Taking the basic sorting unit A103 in the bubble sorting circuit shown as an example, the basic sorting unit A103 includes a first-level sorting circuit A110 and a second-level sorting circuit A120, wherein the first-level sorting circuit A110 includes four comparison switches, namely, comparison switch A111 of the first-level sorting circuit A110, comparison switch B112 of the first-level sorting circuit A110, comparison switch C113 of the first-level sorting circuit A110, and comparison switch D114 of the first-level sorting circuit A110. The second-level sorting circuit A120 includes four comparison switches, namely, comparison switch A121 of the second-level sorting circuit A120, comparison switch B122 of the second-level sorting circuit A120, comparison switch C123 of the second-level sorting circuit A120, and comparison switch D124 of the second-level sorting circuit A120. A first correspondence relationship is satisfied between the first-level sorting circuit and the second-level sorting circuit in the same-level basic sorting unit in the first sequence, and the output of the first-level sorting circuit in the same-level basic sorting unit is output to the second-level sorting circuit in the same-level basic sorting unit according to a first re-combination order based on the first correspondence relationship. Specifically, for the first-level sorting circuit and the second-level sorting circuit in the same-level basic sorting unit, a first correspondence relationship is satisfied between the first-level sorting circuit A110 and the second-level sorting circuit A120 of the basic sorting unit A103, and the output of the first-level sorting circuit A110 is output to the second-level sorting circuit A120 according to a first re-combination order based on the first correspondence relationship.

[0052] See also Figure 2 It can be seen that the first-level sorting circuit A110 and the second-level sorting circuit A120 of the basic sorting unit A103 satisfy the first corresponding relationship, and the comparison switches of the first-level sorting circuit A110 and the second-level sorting circuit A120 also correspond to each other according to the first corresponding relationship. Each comparison switch is used to compare the two elements input to the comparison switch and output the two elements according to a preset sorting method. Therefore, each comparison switch has two input interfaces for receiving two elements, and two output interfaces for outputting the results of comparing and sorting the two received elements, which may be in ascending order or descending order, depending on the pre-configuration of the comparison switch. Combined with Figure 1 and Figure 2, on the basis of the first corresponding relationship, a first recombination order based on the first corresponding relationship is set, and then the output of the first-level sorting circuit in the basic sorting unit of the same level that satisfies the first corresponding relationship is directed to the input of the second-level sorting circuit, including directing the output of a specific comparison switch to the input of a specific comparison switch. In this way, by determining the first recombination order based on the first corresponding relationship, and optimizing how the output of the first-level sorting circuit in the basic sorting unit of the same level is directed to the input of the second-level sorting circuit based on the first recombination order, parallel comparison sorting is supported, that is, all comparison switches in the first-level sorting circuit can compare and sort their respective inputs in parallel and then output them, and all comparison switches in the second-level sorting circuit can compare and sort their respective inputs in parallel and then output them. In this way, unlike the serial comparison sorting in the prior art, the first recombination order is used to compare and sort the first-level sorting circuit in the first-level sorting circuit. Figure 1 Taking the bubble sort circuit shown as an example, the bubble sort circuit provided in the embodiment of the present application can maintain high sorting efficiency and sorting performance without relying on a high clock frequency.

[0053] Continue reading Figure 2 , the first corresponding relationship indicates a first arrangement order starting from the first element to the last element, in which every two elements in order are output by the same comparison switch, wherein the first re-combination order based on the first corresponding relationship includes: re-ordering the first element in the first arrangement order before the last element in the first arrangement order, thereby obtaining an adjusted first arrangement order, in which every two elements in order are input to the same comparison switch. In this way, assuming that the first arrangement order is elements (B1, B2, B3, B4, B5, B6, B7, B8), the elements B1 and B2, B3 and B4, B5 and B6, B7 and B8 in the first arrangement order are each output by the same comparison switch, and the adjusted first arrangement order is elements (B2, B3, B4, B5, B6, B7, B1, B8), and the elements B2 and B3, B4 and B5, B6 and B7, B1 and B8 in the adjusted first arrangement order are each input to the same comparison switch.

[0054] Figure 3 Provided in the embodiments of this application Figure 1 Schematic diagram of the second corresponding relationship in the bubble sort circuit and the second re-combination order based on the second corresponding relationship. Figure 1The second-level sorting circuit A120 of the basic sorting unit A103 and the first-level sorting circuit B130 of the basic sorting unit B105 are taken as examples. The basic sorting unit B105 is located after the basic sorting unit A103, so the basic sorting unit A103 is the basic sorting unit of the previous level, and the basic sorting unit B105 is the basic sorting unit of the next level. The second-level sorting circuit A120 includes four comparison switches, namely, the comparison switch A121 of the second-level sorting circuit A120, the comparison switch B122 of the second-level sorting circuit A120, the comparison switch C123 of the second-level sorting circuit A120, and the comparison switch D124 of the second-level sorting circuit A120. The first-level sorting circuit B130 includes four comparison switches, namely, comparison switch A131 of the first-level sorting circuit B130, comparison switch B132 of the first-level sorting circuit B130, comparison switch C133 of the first-level sorting circuit B130, and comparison switch D134 of the first-level sorting circuit B130. The second-level sorting circuit in the previous-level basic sorting unit in the first sequence satisfies the second corresponding relationship with the first-level sorting circuit in the next-level basic sorting unit, and the second-level sorting circuit in the previous-level basic sorting unit is output to the first-level sorting circuit of the next-level basic sorting unit according to the second re-combination order based on the second corresponding relationship. Specifically, a second corresponding relationship is satisfied between the second-level sorting circuit A120 in the basic sorting unit of the previous level, i.e., the basic sorting unit A103, and the first-level sorting circuit B130 in the basic sorting unit of the next level, i.e., the basic sorting unit B105, and an output of the second-level sorting circuit A120 in the basic sorting unit of the previous level, i.e., the basic sorting unit A103, is output to the first-level sorting circuit B130 in the basic sorting unit of the next level, i.e., the basic sorting unit B105, in a second recombination order based on the second corresponding relationship.

[0055] See also Figure 3 It can be seen that the second-level sorting circuit A120 of the basic sorting unit A103 and the first-level sorting circuit B130 of the basic sorting unit B105 satisfy the second corresponding relationship, and the comparison switches of the second-level sorting circuit A120 of the basic sorting unit A103 and the first-level sorting circuit B130 of the basic sorting unit B105 also correspond to each other according to the first corresponding relationship. Each comparison switch is used to compare the two elements input to the comparison switch and output the two elements according to a preset sorting method. Therefore, each comparison switch has two input interfaces for receiving two elements, and two output interfaces for outputting the results of comparing and sorting the two received elements, which may be in ascending order or descending order, depending on the pre-configuration of the comparison switch. Combined with Figure 1 and Figure 3 , based on the second corresponding relationship, a second re-combination order based on the second corresponding relationship is set, and then the output of the second-level sorting circuit in the previous basic sorting unit that satisfies the second corresponding relationship is directed to the input of the first-level sorting circuit of the next basic sorting unit, including directing the output of a specific comparison switch to the input of a specific comparison switch. In this way, by determining the second re-combination order based on the second corresponding relationship, and optimizing how the output of the second-level sorting circuit in the previous basic sorting unit is directed to the input of the first-level sorting circuit of the next basic sorting unit based on the second re-combination order, parallel comparison sorting is supported, and multiple basic sorting units are connected step by step according to the first order, and finally connected to the last-level sorting unit, thereby realizing the hardware implementation of the bubble sort algorithm based on parallel sorting.

[0056] Continue reading Figure 3 , the second corresponding relationship indicates a second arrangement order starting from the first element to the last element, in which every two elements in sequence are output by the same comparison switch, wherein the second re-combination order based on the second corresponding relationship includes: re-ordering the previous element of the last element in the second arrangement order before the first element in the second arrangement order, thereby obtaining an adjusted second arrangement order, in which every two elements in sequence are input to the same comparison switch. In this way, assuming that the second arrangement order is elements (C1, C2, C3, C4, C5, C6, C7, C8), the element C1 and element C2, element C3 and element C4, element C5 and element C6, element C7 and element C8 in the second arrangement order are each output by the same comparison switch, and the adjusted second arrangement order is elements (C7, C1, C2, C3, C4, C5, C6, C8), and the element C7 and element C1, element C2 and element C3, element C4 and element C5, element C6 and element C8 in the adjusted second arrangement order are each input to the same comparison switch.

[0057] See also Figure 1 , Figure 2 and Figure 3 , the following uses the 8 elements to be sorted as an example to demonstrate how the result of the bubble sort algorithm is achieved. Assume that the 8 elements to be sorted are the array to be sorted (2, 3, 5, 4, 1, 8, 7, 6). If they are sorted in descending order, that is, the largest element is sorted to the end, then the bubble sort result of the array to be sorted should be the array (1, 2, 3, 4, 5, 6, 7, 8). The following uses multiple tables to demonstrate Figure 1 , Figure 2 and Figure 3The bubble sort circuit shown in the figure replaces the serial comparison sort in the prior art with parallel comparison sort, thereby having higher sorting efficiency, and also reduces the consumption of hardware resources by optimizing the logic implementation of the bubble sort algorithm. It can also maintain high sorting efficiency and sorting performance when the maximum number of sorting elements is high, which is beneficial to improving system performance and resource utilization. The following table 2 illustrates how the bubble sort circuit replaces the serial comparison sort in the prior art with parallel comparison sort, thereby having higher sorting efficiency, and also reduces the consumption of hardware resources by optimizing the logic implementation of the bubble sort algorithm, and also maintains high sorting efficiency and sorting performance when the maximum number of sorting elements is high. Figure 1 The operation of the basic sorting unit A103 is shown as follows:

[0058] Table 2

[0059]

[0060] Combined with Table 2, it can be seen that the first-level sorting circuit A110 and the second-level sorting circuit A120 in the basic sorting unit A103 satisfy the first corresponding relationship, and the comparison switches of the first-level sorting circuit A110 and the second-level sorting circuit A120 also correspond to each other according to the first corresponding relationship. Figure 1 and Figure 2 , it can be seen that the first re-combination order based on the first corresponding relationship is set on the basis of the first corresponding relationship, and then the output of the first-level sorting circuit in the same-level basic sorting unit that satisfies the first corresponding relationship is directed to the input of the second-level sorting circuit, including directing the output of a specific comparison switch to the input of a specific comparison switch. Specifically, the first element in the first arrangement order is re-arranged before the last element in the first arrangement order, thereby obtaining an adjusted first arrangement order, in which every two elements in the adjusted first arrangement order are input to the same comparison switch in order. Here, the first element in the first arrangement order is B1 (2), and the first element is B1 (2) and is re-arranged before the last element in the first arrangement order, that is, B8 (7), so as to obtain the adjusted first arrangement order. Then, based on the adjusted first arrangement order, the elements B2 and B3, the elements B4 and B5, the elements B6 and B7, and the elements B1 and B8 in the adjusted first arrangement order are each input to the same comparison switch. In this way, the output result of the second-stage sorting circuit A120 is obtained.

[0061] Continuing with Table 2, the second level sorting circuit A120 of the basic sorting unit A103 and the first level sorting circuit B130 of the basic sorting unit B105 satisfy the second corresponding relationship, and the output of the second level sorting circuit A120 in the previous level basic sorting unit, i.e., the basic sorting unit A103, is output to the first level sorting circuit B130 of the next level basic sorting unit, i.e., the basic sorting unit B105, according to the second re-combination order based on the second corresponding relationship. Figure 1and Figure 3 , it can be seen that the second recombination order based on the second corresponding relationship is set on the basis of the second corresponding relationship, and then the output of the second-level sorting circuit in the basic sorting unit of the previous level that satisfies the second corresponding relationship is directed to the input of the first-level sorting circuit of the basic sorting unit of the next level, including directing the output of a specific comparison switch to the input of a specific comparison switch. In this way, the second recombination order is determined on the basis of the second corresponding relationship, and how the output of the second-level sorting circuit in the basic sorting unit of the previous level is directed to the input of the first-level sorting circuit of the basic sorting unit of the next level is optimized based on the second recombination order. Specifically, the second corresponding relationship indicates a second arrangement order starting from the first element to the last element, and in the second arrangement order, every two elements in order are output by the same comparison switch, wherein the second recombination order based on the second corresponding relationship includes: reordering the previous element of the last element in the second arrangement order before the first element in the second arrangement order, thereby obtaining an adjusted second arrangement order. Here, the previous element of the last element in the second arrangement order is C7 (2), and the previous element of the last element in the second arrangement order, that is, C7 (2), is arranged before the first element in the second arrangement order, that is, C1 (3), so as to obtain the adjusted second arrangement order. Then, based on the adjusted second arrangement order, the element C7 and the element C1, the element C2 and the element C3, the element C4 and the element C5, and the element C6 and the element C8 in the adjusted second arrangement order are respectively input into the same comparison switch. The following is illustrated by Table 3 Figure 1 The operation of the basic sorting unit B105 is shown as follows:

[0062] Table 3

[0063]

[0064] In conjunction with Table 3, it can be seen that by determining the first recombination order based on the first corresponding relationship, and optimizing how the output of the first-level sorting circuit in the basic sorting unit of the same level is directed to the input of the second-level sorting circuit based on the first recombination order, parallel comparison sorting is supported, that is, all comparison switches in the first-level sorting circuit can compare and sort their respective inputs in parallel and output them, and all comparison switches in the second-level sorting circuit can compare and sort their respective inputs in parallel and output them. In addition, by determining the second recombination order based on the second corresponding relationship, and optimizing how the output of the second-level sorting circuit in the basic sorting unit of the previous level is directed to the input of the first-level sorting circuit of the basic sorting unit of the next level based on the second recombination order, parallel comparison sorting is supported, and multiple basic sorting units are connected step by step according to the first order, and finally connected to the last-level sorting unit, thereby realizing the hardware implementation of the bubble sort algorithm based on parallel sorting. The following is illustrated by Table 4. Figure 1 The operation of the basic sorting unit C107 is shown:

[0065] Table 4

[0066]

[0067] Combined with Table 4, it can be seen that by determining the first recombination order based on the first corresponding relationship, and optimizing how the output of the first-level sorting circuit in the same-level basic sorting unit is directed to the input of the second-level sorting circuit based on the first recombination order, parallel comparison sorting is supported, that is, all comparison switches in the first-level sorting circuit can compare and sort their respective inputs in parallel and output them, and all comparison switches in the second-level sorting circuit can compare and sort their respective inputs in parallel and output them. In addition, by determining the second recombination order based on the second corresponding relationship, and optimizing how the output of the second-level sorting circuit in the previous-level basic sorting unit is directed to the input of the first-level sorting circuit of the next-level basic sorting unit based on the second recombination order, parallel comparison sorting is supported, and multiple basic sorting units are connected step by step according to the first order, and finally connected with the last-level sorting unit, thereby realizing the hardware implementation of the bubble sort algorithm based on parallel sorting.

[0068] See also Figure 1 , the third-level sorting circuit 190 input to the final-level sorting unit 102 is the array (1, 2, 3, 4, 5, 6, 7, 8). Therefore, it can be seen that the output result of the final-level sorting unit 102 is the bubble sort result of the array to be sorted, that is, the array (1, 2, 3, 4, 5, 6, 7, 8). It should be understood that the bubble sorting circuit provided in the embodiment of the present application is based on Figure 1Taking the bubble sort circuit 100 shown as an example, it can not only flexibly adapt to the number of maximum sorting elements of other values, but also can greatly save hardware resources and improve sorting efficiency. Compared with the hardware implementation based on serial comparison sorting in the prior art, the hardware implementation based on serial comparison sorting requires the number of comparators equal to the square of the difference between the number of maximum sorting elements and one, so when the number of maximum sorting elements is 4, the number of comparators is 3 squared, that is, 9; when the number of maximum sorting elements is 8, the number of comparators is 7 squared, that is, 49; when the number of maximum sorting elements is 16, the number of comparators is 15 squared, that is, 225; when the number of maximum sorting elements is 32, the number of comparators is 31 squared, that is, 961. It can be seen that as the number of maximum sorting elements increases, a sufficient number of comparators needs to be provided, and because the hardware implementation based on serial comparison sorting in the prior art requires a number of comparators that is proportional to the square of the number of maximum sorting elements, when the number of maximum sorting elements is high, a lot of hardware resources need to be occupied. Moreover, among these comparators, only one comparator is working at the same time when running in series, while the other comparators are idle, which results in a large number of occupied resources and low resource utilization, which is not conducive to improving system performance. The bubble sort circuit provided in the embodiment of the present application is based on Figure 1 Taking the bubble sort circuit 100 shown as an example, even when the maximum number of sorting elements is high, it can maintain high sorting efficiency and sorting performance, which is beneficial to improving system performance and resource utilization.

[0069] In a possible implementation, the preset sorting method is to sort the larger element of the two elements input to the comparison switch in front and the smaller element of the two elements input to the comparison switch in the back. In this way, not only the serial comparison sorting in the prior art is replaced by parallel comparison sorting, thereby having higher sorting efficiency, but also the logic implementation of the bubble sorting algorithm is optimized to reduce hardware resource consumption, and even when the number of the maximum sorting elements is high, a high sorting efficiency and sorting performance can be maintained, which is conducive to improving system performance and resource utilization.

[0070] In a possible implementation, the preset sorting method is to sort the smaller of the two elements input to the comparison switch in front and the larger of the two elements input to the comparison switch in the back. In this way, not only the serial comparison sorting in the prior art is replaced by parallel comparison sorting, thereby having higher sorting efficiency, but also the logic implementation of the bubble sorting algorithm is optimized to reduce hardware resource consumption, and even when the number of the maximum sorting elements is high, a high sorting efficiency and sorting performance can be maintained, which is conducive to improving system performance and resource utilization.

[0071] In a possible implementation, the first-level sorting circuit and the second-level sorting circuit included in each of the first number of basic sorting units respectively compare and sort in parallel. In some embodiments, all the comparison switches in the first-level sorting circuit included in each of the first number of basic sorting units compare the elements inputted in parallel and output them according to the preset sorting mode, and all the comparison switches in the second-level sorting circuit included in each of the first number of basic sorting units compare the elements inputted in parallel and output them according to the preset sorting mode. In some embodiments, all the comparison switches in the third-level sorting circuit in the final-level sorting unit compare the elements inputted in parallel and output them according to the preset sorting mode. In this way, not only the serial comparison sorting in the prior art is replaced by parallel comparison sorting, thereby having higher sorting efficiency, but also the hardware resource consumption is reduced by optimizing the logic implementation of the bubble sorting algorithm, and the high sorting efficiency and sorting performance can be maintained even when the number of maximum sorting elements is high, which is conducive to improving system performance and resource utilization.

[0072] In a possible implementation, each comparison switch in the bubble sort circuit is configured through a register so that the preset sorting mode can be adjusted to achieve ascending or descending order. In this way, flexible switching is achieved through register configuration.

[0073] In a possible implementation, each comparison switch in the bubble sort circuit supports sorting unsigned numbers or signed numbers. In this way, diversified support for input environments is achieved. In this way, support for multiple bases of input data is achieved. In a possible implementation, each comparison switch in the bubble sort circuit supports sorting data in multiple bases, and the multiple bases include binary, decimal and hexadecimal. In this way, it is helpful to adapt to complex application environments.

[0074] In a possible implementation, the bubble sorting circuit is used to sort a plurality of elements to be sorted so as to obtain a bubble sorting result of the plurality of elements to be sorted, the plurality of elements to be sorted are input to the first-level sorting circuit in the first-level basic sorting unit in the first order, and the output of the third-level sorting circuit in the last-level sorting unit is the bubble sorting result of the plurality of elements to be sorted. In some embodiments, the first number and the second number are both determined based on the number of the plurality of elements to be sorted, the number of comparison switches included in the first-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number, and the number of comparison switches included in the second-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number. In this way, not only the serial comparison sorting in the prior art is replaced by parallel comparison sorting, thereby having a higher sorting efficiency, but also the hardware resource consumption is reduced by optimizing the logic implementation of the bubble sorting algorithm, and a high sorting efficiency and sorting performance can be maintained even when the maximum number of sorting elements is high, which is conducive to improving system performance and resource utilization.

[0075] In a possible implementation, the number of the multiple elements to be sorted is N, N is an even number greater than or equal to 4, N is expressed as 2 to the power of M, M is a positive integer greater than or equal to 2, the first number is 2 to the power of M minus 1 minus 1, the second number is N, the number of comparison switches included in the first-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of N, the number of comparison switches included in the second-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of N, and the number of comparison switches included in the third-level sorting circuit of the final-level sorting unit is half of N. In some embodiments, N is 4, 8, 16 or 32. In this way, it is conducive to flexible expansion to various numbers of total numbers of elements to be sorted.

[0076] In a possible implementation, when the number of the multiple elements to be sorted is an odd number, an equivalent array of elements to be sorted having an even number is obtained by adding 0 elements to the multiple elements to be sorted, and the bubble sort result of the equivalent array of elements to be sorted is used to determine the bubble sort result of the multiple elements to be sorted. In this way, it is conducive to flexible expansion to various total numbers of elements to be sorted.

[0077] In a possible implementation, the first correspondence relationship indicates a first arrangement order starting from the first element to the last element, in which every two elements in the first arrangement order are output by the same comparison switch, wherein the first re-combination order based on the first correspondence relationship includes: re-ordering the first element in the first arrangement order before the last element in the first arrangement order, thereby obtaining an adjusted first arrangement order, in which every two elements in the adjusted first arrangement order are input to the same comparison switch. In this way, by determining the first re-combination order based on the first correspondence relationship, and optimizing how the output of the first-level sorting circuit in the same-level basic sorting unit is directed to the input of the second-level sorting circuit based on the first re-combination order, parallel comparison sorting is supported, that is, all comparison switches in the first-level sorting circuit can compare and sort their respective inputs in parallel and output them, and all comparison switches in the second-level sorting circuit can compare and sort their respective inputs in parallel and output them. In this way, unlike the serial comparison sorting in the prior art, the first re-combination order is used to optimize how the output of the first-level sorting circuit in the same-level basic sorting unit is directed to the input of the second-level sorting circuit. Figure 1 Taking the bubble sort circuit shown as an example, the bubble sort circuit provided in the embodiment of the present application can maintain high sorting efficiency and sorting performance without relying on a high clock frequency.

[0078] In some embodiments, the first arrangement order is elements (B1, B2, B3, B4, B5, B6, B7, B8), and the elements B1 and B2, B3 and B4, B5 and B6, B7 and B8 in the first arrangement order are each output by the same comparison switch, and the adjusted first arrangement order is elements (B2, B3, B4, B5, B6, B7, B1, B8), and the elements B2 and B3, B4 and B5, B6 and B7, B1 and B8 in the adjusted first arrangement order are each input to the same comparison switch. Thus, by determining the first recombining order based on the first corresponding relationship, and optimizing how the output of the first-level sorting circuit in the same-level basic sorting unit is directed to the input of the second-level sorting circuit based on the first recombining order, parallel comparison sorting is supported, that is, all comparison switches in the first-level sorting circuit can compare and sort their inputs in parallel and then output them, and all comparison switches in the second-level sorting circuit can compare and sort their inputs in parallel and then output them. Thus, unlike the serial comparison sorting in the prior art, the first-level sorting circuit can be used to compare and sort the inputs of the first-level sorting circuit in parallel. Figure 1 Taking the bubble sort circuit shown as an example, the bubble sort circuit provided in the embodiment of the present application can maintain high sorting efficiency and sorting performance without relying on a high clock frequency.

[0079] In a possible implementation, the second corresponding relationship indicates a second arrangement order starting from the first element to the last element, in which every two elements in the second arrangement order are output by the same comparison switch, wherein the second re-combination order based on the second corresponding relationship includes: re-ordering the previous element of the last element in the second arrangement order before the first element in the second arrangement order, thereby obtaining an adjusted second arrangement order, in which every two elements in the second arrangement order are input to the same comparison switch. In this way, by determining the second re-combination order based on the second corresponding relationship, and optimizing how the output of the second-level sorting circuit in the basic sorting unit of the previous level is directed to the input of the first-level sorting circuit of the basic sorting unit of the next level based on the second re-combination order, parallel comparison sorting is supported, and multiple basic sorting units are connected step by step according to the first order, and finally connected with the last-level sorting unit, thereby realizing the hardware implementation of the bubble sort algorithm based on parallel sorting.

[0080] In some embodiments, the second arrangement order is elements (C1, C2, C3, C4, C5, C6, C7, C8), and the element C1 and element C2, element C3 and element C4, element C5 and element C6, element C7 and element C8 in the second arrangement order are each output by the same comparison switch, and the adjusted second arrangement order is elements (C7, C1, C2, C3, C4, C5, C6, C8), and the element C7 and element C1, element C2 and element C3, element C4 and element C5, element C6 and element C8 in the adjusted second arrangement order are each input to the same comparison switch. In this way, by determining the second recombination order based on the second corresponding relationship, and optimizing how the output of the second-level sorting circuit in the basic sorting unit of the previous level is directed to the input of the first-level sorting circuit of the basic sorting unit of the next level based on the second recombination order, parallel comparison sorting is supported, and multiple basic sorting units are connected step by step according to the first order, and finally connected to the last-level sorting unit, thereby realizing the hardware implementation of the bubble sort algorithm based on parallel sorting.

[0081] In a possible implementation, the bubble sort circuit is applied to grayscale value sorting of pixels in digital image processing tasks, which is helpful to meet the application requirements of machine vision technology, where the number of elements in the array to be sorted is increasing, and the running speed of the overall algorithm is required to be higher and higher.

[0082] Figure 4 A schematic diagram of a bubble sorting method provided in an embodiment of the present application. Figure 4 As shown, the bubble sort method includes the following steps.

[0083] Step S401: connect a first number of basic sorting units step by step according to a first order, and finally connect the final sorting units, so as to construct a bubble sort circuit.

[0084] Step S403: inputting a plurality of elements to be sorted into the first-level sorting circuit in the first-level basic sorting unit in the first order, and then taking the output of the third-level sorting circuit in the last-level sorting unit as the bubble sorting result of the plurality of elements to be sorted.

[0085] Wherein, each of the first number of basic sorting units includes a second number of comparison switches, and the comparison switch is used to compare two elements input into the comparison switch and output the two elements according to a preset sorting method. Each of the first number of basic sorting units equally divides the second number of comparison switches into a first-level sorting circuit and a second-level sorting circuit. The first number of basic sorting units are connected step by step according to the first sequence. The first-level sorting circuit and the second-level sorting circuit in the basic sorting units of the same level in the first sequence satisfy a first corresponding relationship, and the output of the first-level sorting circuit in the basic sorting units of the same level is output to the second-level sorting circuit in the basic sorting units of the same level according to a first re-combination order based on the first corresponding relationship. The second-level sorting circuit in the basic sorting unit of the previous level in the first sequence satisfies the second corresponding relationship with the first-level sorting circuit in the basic sorting unit of the next level, and the second-level sorting circuit in the basic sorting unit of the previous level is output to the first-level sorting circuit of the basic sorting unit of the next level according to the second re-combination order based on the second corresponding relationship, the last-level sorting unit includes a third-level sorting circuit having half of the second number of comparison switches, the second-level sorting circuit in the basic sorting unit of the last level in the first sequence satisfies the second corresponding relationship with the third-level sorting circuit in the last-level sorting unit, and the second-level sorting circuit in the basic sorting unit of the last level in the first sequence is output to the third-level sorting circuit in the last-level sorting unit according to the second re-combination order based on the second corresponding relationship.

[0086] Figure 4 The bubble sorting method shown not only replaces the serial comparison sorting in the prior art with parallel comparison sorting, thereby having higher sorting efficiency, but also reduces hardware resource consumption by optimizing the logical implementation of the bubble sorting algorithm. It can maintain high sorting efficiency and sorting performance even when the maximum number of sorting elements is high, which is beneficial to improving system performance and resource utilization.

[0087] In a possible implementation, the first number and the second number are both determined based on the number of the multiple elements to be sorted, the number of comparison switches included in the first-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number, and the number of comparison switches included in the second-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number. In this way, not only the serial comparison sorting in the prior art is replaced by parallel comparison sorting, thereby having higher sorting efficiency, but also the hardware resource consumption is reduced by optimizing the logic implementation of the bubble sorting algorithm, and a high sorting efficiency and sorting performance can be maintained even when the maximum number of sorting elements is high, which is conducive to improving system performance and resource utilization.

[0088] In a possible implementation, the first correspondence relationship indicates a first arrangement order starting from the first element to the last element, in which every two elements in the first arrangement order are output by the same comparison switch, wherein the first re-combination order based on the first correspondence relationship includes: re-ordering the first element in the first arrangement order before the last element in the first arrangement order, thereby obtaining an adjusted first arrangement order, in which every two elements in the adjusted first arrangement order are input to the same comparison switch. In this way, by determining the first re-combination order based on the first correspondence relationship, and optimizing how the output of the first-level sorting circuit in the same-level basic sorting unit is directed to the input of the second-level sorting circuit based on the first re-combination order, parallel comparison sorting is supported, that is, all comparison switches in the first-level sorting circuit can compare and sort their respective inputs in parallel and output them, and all comparison switches in the second-level sorting circuit can compare and sort their respective inputs in parallel and output them. In this way, unlike the serial comparison sorting in the prior art, the first re-combination order is used to optimize how the output of the first-level sorting circuit in the same-level basic sorting unit is directed to the input of the second-level sorting circuit. Figure 1 Taking the bubble sort circuit shown as an example, the bubble sort circuit provided in the embodiment of the present application can maintain high sorting efficiency and sorting performance without relying on a high clock frequency.

[0089] In a possible implementation, the second corresponding relationship indicates a second arrangement order starting from the first element to the last element, in which every two elements in the second arrangement order are output by the same comparison switch, wherein the second re-combination order based on the second corresponding relationship includes: re-ordering the previous element of the last element in the second arrangement order before the first element in the second arrangement order, thereby obtaining an adjusted second arrangement order, in which every two elements in the second arrangement order are input to the same comparison switch. In this way, by determining the second re-combination order based on the second corresponding relationship, and optimizing how the output of the second-level sorting circuit in the basic sorting unit of the previous level is directed to the input of the first-level sorting circuit of the basic sorting unit of the next level based on the second re-combination order, parallel comparison sorting is supported, and multiple basic sorting units are connected step by step according to the first order, and finally connected with the last-level sorting unit, thereby realizing the hardware implementation of the bubble sort algorithm based on parallel sorting.

[0090] Figure 5 : is a structural diagram of a computing device provided in an embodiment of the present application, and the computing device 500 includes: one or more processors 510, a communication interface 520 and a memory 530. The processor 510, the communication interface 520 and the memory 530 are interconnected via a bus 540. Optionally, the computing device 500 may also include an input / output interface 550, and the input / output interface 550 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 500 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 510 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the computing device 500 performing various operations can refer to the specific details in the above-mentioned embodiments, such as the processor 510 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 500 may be used to implement part or all of the functions of one or more components in the above-mentioned device embodiment. In addition, the communication interface 520 may be specifically used to perform the communication functions necessary to implement the functions of these devices and components, and the processor 510 may be specifically used to perform the processing functions necessary to implement the functions of these devices and components.

[0091] It should be understood that Figure 5The computing device 500 may include one or more processors 510, and the multiple processors 510 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 510 may form a processor sequence or a processor array, or the multiple processors 510 may be divided into a main processor and an auxiliary processor, or the multiple processors 510 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 5 The computing device 500 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 500 may include Figure 5 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0092] The processor 510 may have a variety of specific implementation forms. For example, the processor 510 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 510 may also be a single-core processor or a multi-core processor. The processor 510 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 510 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 520 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0093] The memory 530 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 530 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 530 may also be used to store program codes and data, so that the processor 510 calls the program codes stored in the memory 530 to execute some or all of the operation steps in the above method embodiments, or to execute the corresponding functions in the above device embodiments. Figure 5 Show more or fewer components, or have different component configurations.

[0094] The bus 540 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 540 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 540 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0095] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0096] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0097] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0098] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0099] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A bubble sort circuit, characterized in that: The bubble sort circuit comprises: A first number of basic sorting units, wherein each of the first number of basic sorting units comprises a second number of comparison switches, the comparison switches being used to compare two elements input into the comparison switches and then output the two elements in a preset sorting manner, each of the first number of basic sorting units equally divides the second number of comparison switches into a first-level sorting circuit and a second-level sorting circuit, the first number of basic sorting units are connected step by step according to a first sequence, the first-level sorting circuits and the second-level sorting circuits in the same level of basic sorting units in the first sequence satisfy a first corresponding relationship, and the outputs of the first-level sorting circuits in the same level of basic sorting units are output to the second-level sorting circuits in the same level of basic sorting units according to a first recombination order based on the first corresponding relationship, the second-level sorting circuits in the previous level of basic sorting units in the first sequence satisfy a second corresponding relationship with the first-level sorting circuits in the next level of basic sorting units, and the second-level sorting circuits in the previous level of basic sorting units are output to the first-level sorting circuits in the next level of basic sorting units according to a second recombination order based on the second corresponding relationship; and a final-stage sorting unit, wherein the final-stage sorting unit comprises a third-stage sorting circuit having half the second number of comparison switches, the second-stage sorting circuit in the last-stage basic sorting unit in the first sequence and the third-stage sorting circuit in the final-stage sorting unit satisfy the second corresponding relationship, and the second-stage sorting circuit in the last-stage basic sorting unit in the first sequence is output to the third-stage sorting circuit in the final-stage sorting unit according to a second re-combination order based on the second corresponding relationship, The first-level sorting circuit and the second-level sorting circuit included in each of the first number of basic sorting units respectively perform comparison and sorting in parallel, The first corresponding relationship indicates a first arrangement order starting from the first element to the last element, in which every two elements in the first arrangement order are output by the same comparison switch, wherein the first re-combination order based on the first corresponding relationship includes: re-ordering the first element in the first arrangement order before the last element in the first arrangement order, thereby obtaining an adjusted first arrangement order, in which every two elements in the first arrangement order are input to the same comparison switch, The second corresponding relationship indicates a second arrangement order starting from the first element to the last element, in which every two elements in order are output by the same comparison switch, wherein the second re-combination order based on the second corresponding relationship includes: re-ordering the previous element of the last element in the second arrangement order before the first element in the second arrangement order, thereby obtaining an adjusted second arrangement order, in which every two elements in order are input to the same comparison switch.

2. The bubble sort circuit according to claim 1, characterized in that: The preset sorting method is to sort the larger element of the two elements input into the comparison switch in front and to sort the smaller element of the two elements input into the comparison switch in the back.

3. The bubble sort circuit according to claim 1, characterized in that: The preset sorting method is to sort the smaller element of the two elements input into the comparison switch in front and to sort the larger element of the two elements input into the comparison switch in the back.

4. The bubble sort circuit according to claim 1, characterized in that: All comparison switches in the first-level sorting circuit included in each of the first number of basic sorting units compare the elements of their respective inputs in parallel and output them according to the preset sorting method, and all comparison switches in the second-level sorting circuit included in each of the first number of basic sorting units compare the elements of their respective inputs in parallel and output them according to the preset sorting method.

5. The bubble sort circuit according to claim 1, characterized in that: All comparison switches in the third-level sorting circuit in the final-level sorting unit compare the elements inputted respectively in parallel and then output them according to the preset sorting method.

6. The bubble sort circuit according to claim 1, characterized in that: Each comparison switch in the bubble sort circuit is configured through a register so that the preset sorting mode can be adjusted to achieve ascending order or descending order.

7. The bubble sort circuit according to claim 1, characterized in that: Each comparison switch in the bubble sort circuit supports sorting unsigned numbers or signed numbers.

8. The bubble sort circuit according to claim 1, characterized in that: Each comparison switch in the bubble sort circuit supports sorting data in multiple bases, including binary, decimal and hexadecimal.

9. The bubble sort circuit according to claim 1, characterized in that: The bubble sort circuit is used to sort multiple elements to be sorted to obtain bubble sort results of the multiple elements to be sorted. The multiple elements to be sorted are input to the first-level sorting circuit in the first-level basic sorting unit in the first order, and the output of the third-level sorting circuit in the last-level sorting unit is the bubble sort result of the multiple elements to be sorted.

10. The bubble sort circuit according to claim 9, characterized in that: Both the first number and the second number are determined based on the number of the multiple elements to be sorted, the number of comparison switches included in the first-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number, and the number of comparison switches included in the second-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number.

11. The bubble sort circuit according to claim 9, characterized in that: The number of the multiple elements to be sorted is N, N is an even number greater than or equal to 4, N is expressed as 2 to the power of M, M is a positive integer greater than or equal to 2, the first number is 2 to the power of M minus 1 minus 1, the second number is N, the number of comparison switches included in the first-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of N, the number of comparison switches included in the second-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of N, and the number of comparison switches included in the third-level sorting circuit of the final-level sorting unit is half of N.

12. The bubble sort circuit according to claim 11, characterized in that: N is 4, 8, 16, or 32.

13. The bubble sort circuit according to claim 11, characterized in that: When the number of the multiple elements to be sorted is an odd number, an equivalent array of elements to be sorted having an even number is obtained by adding 0 elements to the multiple elements to be sorted, and the bubble sort result of the equivalent array of elements to be sorted is used to determine the bubble sort result of the multiple elements to be sorted.

14. The bubble sort circuit according to claim 1, characterized in that: The first arrangement order is elements (B1, B2, B3, B4, B5, B6, B7, B8), and the elements B1 and B2, B3 and B4, B5 and B6, B7 and B8 in the first arrangement order are each output by the same comparison switch, and the adjusted first arrangement order is elements (B2, B3, B4, B5, B6, B7, B1, B8), and the elements B2 and B3, B4 and B5, B6 and B7, B1 and B8 in the adjusted first arrangement order are each input to the same comparison switch.

15. The bubble sort circuit according to claim 1, characterized in that: The second arrangement order is elements (C1, C2, C3, C4, C5, C6, C7, C8), and the element C1 and element C2, element C3 and element C4, element C5 and element C6, element C7 and element C8 in the second arrangement order are each output by the same comparison switch, and the adjusted second arrangement order is elements (C7, C1, C2, C3, C4, C5, C6, C8), and the element C7 and element C1, element C2 and element C3, element C4 and element C5, element C6 and element C8 in the adjusted second arrangement order are each input to the same comparison switch.

16. The bubble sort circuit according to claim 10, characterized in that: The bubble sort circuit is applied to gray value sorting of pixels in digital image processing tasks.

17. A bubble sorting method, characterized in that: The bubble sorting method is implemented by a bubble sorting circuit according to any one of claims 1 to 16, and the bubble sorting method comprises: A first number of basic sorting units are connected level by level according to a first sequence, and finally connected to a final-level sorting unit, so as to construct a bubble sorting circuit, wherein each of the first number of basic sorting units includes a second number of comparison switches, and the comparison switches are used to compare two elements input into the comparison switches and output the two elements according to a preset sorting method, and each of the first number of basic sorting units equally divides the second number of comparison switches into a first-level sorting circuit and a second-level sorting circuit, and the first number of basic sorting units are connected level by level according to the first sequence, and a first corresponding relationship is satisfied between the first-level sorting circuit and the second-level sorting circuit in the basic sorting units of the same level in the first sequence, and the output of the first-level sorting circuit in the basic sorting units of the same level is output to The second-level sorting circuits in the basic sorting units of the same level, the second-level sorting circuits in the basic sorting units of the previous level in the first sequence and the first-level sorting circuits in the basic sorting units of the next level satisfy a second corresponding relationship, and the second-level sorting circuits in the basic sorting units of the previous level are output to the first-level sorting circuits of the basic sorting units of the next level according to a second re-combination order based on the second corresponding relationship, the last-level sorting unit comprises a third-level sorting circuit having half of the second number of comparison switches, the second-level sorting circuits in the basic sorting units of the last level in the first sequence and the third-level sorting circuits in the last-level sorting unit satisfy the second corresponding relationship, and the second-level sorting circuits in the basic sorting units of the last level in the first sequence are output to the third-level sorting circuits in the last-level sorting unit according to a second re-combination order based on the second corresponding relationship; A plurality of elements to be sorted are input to a first-level sorting circuit in a first-level basic sorting unit in the first order, and then an output of a third-level sorting circuit in a last-level sorting unit is used as a bubble sorting result of the plurality of elements to be sorted.

18. The bubble sorting method according to claim 17, characterized in that: Both the first number and the second number are determined based on the number of the multiple elements to be sorted, the number of comparison switches included in the first-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number, and the number of comparison switches included in the second-level sorting circuit of each basic sorting unit in the first number of basic sorting units is half of the second number.

19. A computer device, characterized in that: The computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the method according to any one of claims 17 to 18 when executing the computer program.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method of any one of claims 17 to 18.

Images