Multi-interface expansion circuit

Abstract

The invention discloses a multi-interface expansion circuit. A plurality of external interfaces are expanded on a small-size core board for equipment connection and data communication. Comprising an SOM-7569 core board, a native signal interface COM-E is arranged on the core board, and the COM-E is accessed to an Ethernet interface after passing through a network control chip to realize native network connection; the core board is connected with the Ethernet control chip to realize network port expansion connection; the core board is connected with the HDMI signal adjusting chip to realize a function of externally connecting a display; the core board is connected with the CAN control chip to realize CAN communication; a serial communication interface of the core board is connected with the RS-232 interface transceiver chip to realize RS232 serial communication; a USB serial signal of the core board is connected with the USB to serial port chip, is converted into a TTL serial port circuit, and then is connected with the RS485 level transceiver to realize RS485 communication. The multi-interface expansion circuit disclosed by the invention can realize various kinds of communication including four-path Ethernet communication and CAN, RS232 and RS485 communication, and has good popularization value.

Description

Technical Field

[0001] The invention belongs to the technical field of extended communication, and in particular relates to a multi-interface extension circuit for a computer hardware system. Background Art

[0002] Industrial electronic products are developing towards miniaturization and integration. Some industrial intelligent products have relatively high requirements on their own size, such as photogrammetry cameras, binocular measurement systems, etc. These products need to realize functions such as image acquisition, image calculation, processing, and display projection. However, due to the high requirements on the appearance size of the product itself, it is impossible to put a PC, industrial computer or laptop into the product, so a multi-interface expansion circuit needs to be studied urgently. Summary of the invention

[0003] In view of the above-mentioned defects, the present invention provides a multi-interface expansion circuit, which designs different hardware interfaces with the help of a core board with a specific configuration, builds a complete workstation platform, and realizes the functions of computer communication, collection and calculation.

[0004] A multi-interface expansion circuit comprises a SOM-7569 core board, wherein COM-E on the core board is provided with a native signal pin GBE0, and GBE0 is connected to an Ethernet interface after passing through a network transformer to realize native network connection; a PCIE pin of the core board is connected to an Ethernet control chip to realize network port expansion connection; a DDIX pin of the core board is connected to an HDMI signal adjustment chip to realize an external display function; a serial signal SER1 pin of the core board is connected to a CAN control chip to realize CAN communication; a serial communication SER0 pin of the core board is connected to an RS-232 interface transceiver chip to realize RS232 serial communication; a USB serial signal of the core board is connected to a serial port chip to be converted into a TTL serial port circuit, and then connected to an RS485 level transceiver to realize RS485 communication.

[0005] Preferably, the native network connection is: the native signal interface COM-E end GBE0_MDI3-, GBE0_MDI3+, GBE0_MDI2-, GBE0_MDI2+, GBE0_MDI1-, GBE0_MDI1+, GBE0_MDI0- and GBE0_MDI0+ pins are connected to the multiple TD+ / - pins of the network transformer, and the multiple TX+ / - pins of the network transformer are connected to the RJ pins of the Ethernet interface.

[0006] Preferably, the Ethernet control chip is a WGI210-IT chip, and four Ethernet control chips are used to realize four-way Ethernet expansion: the PCIE_TX_P / N and PCIE_RX_P / N pins of the core board are respectively connected to the PE_RP / N and PE_TP / N pins of WGI210-IT, and the PECLKP / N pin of WGI210-IT is connected to the reference clock signal PCIE1 / 2 / 3 / 4_CLK_+ / -. The MDIO / IIC interface of the WGI210-IT chip is used to configure the physical layer transceiver register, and the four WGI210-IT control chips are used to unify the timing, wherein the reference clock PCIE1 / 2 / 3 / 4_CLK_+ / - of the four-way chip is four pairs of differential clock signals, which are used to connect the high-speed serial communication interface of the computer motherboard and the external device.

[0007] As a preferred embodiment, a four-way output differential buffer chip ICS9DB104 is used as a clock expansion chip. The input pin SRC_IN of the ICS9DB104 chip is connected to the standard clock signal PCIE CLK REF to output four reference clock signals PCIE1_CLK_+ / -, PCIE2_CLK_+ / -, PCIE3_CLK_+ / -, and PCIE4_CLK_+ / -, respectively, to the PECLKP / N of the four WGI210-IT chips. The four-way differential transmit and receive links PCIE_TX1 / 2 / 3 / 4 and PCIE_RX1 / 2 / 3 / 4 of the core board COM-E interface are connected to the PE_RP / N PE_TP / N of the four WGI210-IT chips, and the core board is connected to the SMBus bus SMB_CLK / DAT corresponding to the WGI210-IT to expand the signals required for the four-way Ethernet.

[0008] Preferably, an isolation chip H5007 is provided between the Ethernet interface and the Ethernet control chip WGI210-IT, the mac address pin of WGI210-IT is connected to the FLASH chip SST25VF080B, the mac address of I210 is written into the FLASH configuration file and burned, so that the macs of the four Ethernet control chips can be managed by the developer.

[0009] Preferably, the HDMI signal adjustment chip is IP4786CZ32, the four pairs of TMS pins of IP4786CZ32 are respectively connected to the four sets of data differential pair signals DDIX_PAIR+ / - of the 7569 core board, the external clock signal DDC_CLK_SYS pin and the external data signal DDC_DAT_SYS pin of IP4786CZ32 are respectively connected to the DDI_CTRL_AUX+ / - of the 7569 core board, and the hot-swappable DDI1_DP_HPD signal is provided for access by the external controller.

[0010] Preferably, the CAN control chip is TJA1051T, based on the serial signal SER1_TX and SER1_RX expansion in the core board, the CAN transceiver chip TJA1051T is connected to obtain a set of CAN_P and CAN_N differential CAN signals, and the differential CAN signals are connected to a three-core plug to communicate with the outside world.

[0011] Preferably, the RS-232 interface transceiver chip is an SP3232 driver, the SER0_RX and SER0_TX pins of the core board provide a set of serial communication signals and are connected to the R1OUT and T1IN pins of the SP3232, the R1IN and T1OUT pins of the driver output a set of RS232 level signals RS232_RX1 and RS232_TX1, and the RS232 level signal is connected to a three-core plug to realize the mutual conversion between RS232 and TTL levels.

[0012] Preferably, the USB to serial port chip is a CH340E chip, and the RS485 level transceiver is a MAX485. Based on the two universal USB signals USB2_Z_P / USB2_Z_N and USB3_Z_P / USB3_Z_N on the core board, they are converted into TTL levels through the CH340E chip, and the TTL levels are connected to the MAX485 chip, which directly converts the TTL levels into A and B differential signals of the 485 bus for external input and output, and several MAX485s are connected to the 485 bus at the same time to form a network.

[0013] Preferably, two USB2.0 and / or two USB3.0 interfaces are expanded on the core board, and the expansion of USB2.0 is as follows: a series common-mode choke is added to the two USB signals USB4+ / - and USB5+ / - signals provided at the COM-E end of the core board, and then connected to the USB2.0 socket; and the expansion of USB3.0 is as follows: a series common-mode choke is added to the USB0+ / - and USB1+ / - provided at the COM-E end of the core board, and two pairs of ultra-high-speed data transceiver signals SSTX and SSRX signals, and then divided into two USB3.0 channels and connected to the socket.

[0014] The beneficial effects of the present invention are:

[0015] The present invention designs different hardware interfaces based on the SOM-7569 core board to build a complete workstation platform to realize the functions of computer communication, collection and calculation. The expansion circuit disclosed in the novel can realize four-way Ethernet connection, external display, CAN communication, RS232 serial communication and RS485 communication, and is suitable for most application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below.

[0017] Figure 1 This is a schematic diagram of the core board COM-E interface of an embodiment of the present invention;

[0018] Figure 2 It is a connection diagram of native network signals in the core board COM-E interface of an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of an expansion circuit according to an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of a four-way Ethernet expansion according to an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of an HDMI design principle of an embodiment of the present invention;

[0022] Figure 6 It is a schematic diagram of the design of a CAN controller according to an embodiment of the present invention;

[0023] Figure 7 It is a design principle diagram of mutual conversion between RS232 and TTL level of one embodiment of the present invention;

[0024] Figure 8 It is a schematic diagram of a core board expansion 485 bus according to an embodiment of the present invention;

[0025] Fig. 9 It is a two-way USB2.0 expansion design diagram of an embodiment of the present invention;

[0026] Fig.10 This is a schematic diagram of a two-way USB 3.0 expansion principle of an embodiment of the present invention;

[0027] Fig.11 This is a two-way USB 3.0 expansion connection diagram of an embodiment of the present invention;

[0028] Fig.12 is an interface layout diagram of a multilayer board according to an embodiment of the present invention;

[0029] Fig.13 is a structural distribution diagram of a stack of 8-layer boards according to an embodiment of the present invention;

[0030] Fig.14 is a PCB design layout flow chart of an embodiment of the present invention;

[0031] Fig.15 It is an installation diagram of an expansion circuit board and a core board according to an embodiment of the present invention;

[0032] Fig.16 It is a schematic diagram of the actual use of the expansion board of an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] The embodiment of the present invention is based on Advantech's high-performance core board SOM-7569, and expands five Gigabit Ethernet ports, two universal USB3.0 interfaces, two universal USB2.0 interfaces, one CAN interface, two RS485 interfaces, one RS232 interface and one HDMI display interface. The above-mentioned expansion interfaces and the CPU, memory, hard disk and other devices of the high-performance core board itself together constitute a complete image acquisition and processing workstation, which can realize functions such as camera image acquisition and image processing.

[0035] The core board SOM-7569 is used as the core of the workstation platform, and related interface expansion and design work is done on its basis. Advantech's SOM-7569 core board module is equipped with the latest Intel Atom E3900& processor, supports up to 8GB single-channel DDR3L onboard memory, and has higher memory bandwidth for better performance. The SOM-7569 core board provides LVDS and HDMI display interfaces, and its internal resource signals such as Gigabit Ethernet, LVDS, USB transmission and hundreds of other signals are connected to the outside through the COM Express Mini module. Therefore, in order to use the SOM-7569 core board to realize network communication and external display functions, it is necessary to use its COM Express Mini module (COM-E) interface to design external expansion circuits. The size of the SOM-7569 core board and the COM-E interface are as follows: Figure 1 shown.

[0036] All external interface signals of the core board are led out from the COM-E interface. The COM-E interface is a slot, divided into left and right sides, represented by A and B respectively, each with 110 pins, a total of 220 pins. Its specific definition is as follows Table 1:

[0037] Table 1 Core board pin definition

[0038]

[0039]

[0040]

[0041] 1. Multi-channel Gigabit Ethernet

[0042] The SOM-7569 core board itself does not have any network interface. The interface signal must be found from the COM-E interface and used for expansion. There is a native network signal in the COM-E interface signal that can be directly led to the Gigabit network port. The native signals that can be directly led are GBE0_MDI3-, GBE0_MDI3+, GBE0_MDI2-, GBE0_MDI2+, GBE0_MDI1-, GBE0_MDI1+, GBE0_MDI0- and GBE0_MDI0+. The circuit is designed so that the native signal is connected to the network interface after passing through a network transformer.

[0043] like Figure 2 As shown,

[0044] The network transformer has several TD+ / - interfaces and several TX+ / - interfaces. A pair of GBE0 positive and negative interfaces are connected to a pair of network transformer positive and negative TD interfaces, and the TX+ / - interfaces of the network transformer are connected to the Ethernet interface. GBE0_MDI3- and GBE0_MDI3+ are connected to a pair of TD- and TD+, respectively, and the corresponding TX- and TX+ interfaces are connected to the 7th and 8th pins of the Ethernet interface; similarly, GBE0_MDI2- and GBE0_MDI2+ are connected to a pair of TD- and TD+, respectively, and the corresponding TX- and TX+ interfaces are connected to the 5th and 6th pins of the Ethernet interface; GBE0_MDI1- and GBE0_MDI1+ are connected to a pair of TD- and TD+, respectively, and the corresponding TX- and TX+ interfaces are connected to the 3rd and 4th pins of the Ethernet interface; GBE0_MDI0- and GBE0_MDI0+ are connected to a pair of TD- and TD+, respectively, and the corresponding TX- and TX+ interfaces are connected to the 1st and 2nd pins of the Ethernet interface.

[0045] This application has a total of five Gigabit Ethernet channels. In addition to the original one, the remaining four channels need to be implemented by designing an expansion circuit. In order to achieve the expansion of multiple network ports, it is necessary to first select a network port control chip. This application uses Intel's WGI210-IT Ethernet control chip, which provides a Gigabit Ethernet data link layer controller and physical layer interface. The operating voltage is 3.3V, the operating temperature is -40℃ to 105℃, supports PCIE2.1 interface, the data transmission rate reaches 2.5TGT / s, supports jumbo frame mode, provides Gigabit Ethernet media access controller (MAC), physical layer transceiver (PHY), provides SPI interface, can be externally connected to Flash as the boot ROM of the chip, provides SMBus interface as a channel managed by the processor, and provides MDIO / IIC interface to configure the physical layer transceiver register. The use of four WGI210-IT control chips must unify the timing of the four chips, the most important of which is the reference clock PCIE_CLK_REF+ / - of the four chips. PCIE_CLK_REF+ / - is a pair of differential clock signals, which is used as a basic clock signal to connect the high-speed serial communication interface of the computer motherboard and external devices. The four-way Ethernet chip I210 needs a unified reference clock as the basic clock signal for operation, and the COM-E interface of the core board only provides one external reference clock signal PCI_CLK_REF+ / -. This application uses ICS9DB104, a four-output differential buffer chip, as a clock expansion chip to expand four reference clock signals PCIE1_CLK_+ / -, PCIE2_CLK_+ / -, PCIE3_CLK_+ / -, PCIE4_CLK_+ / -. The expansion circuit schematic is as follows Figure 3 shown.

[0046] After the basic reference clock is generated, the four-way differential transmit and receive links PCIE1 / 2 / 3 / 4_TX / RX and SMBus bus SMB_CLK / DAT of the 7569COM-E port are used to expand four-way Ethernet MDI differential signals, which are compatible with 100BASE-T, 100BASE-TX and 10BASE-T transmission. Considering that the Ethernet cable will be mixed with common-mode interference signals during the transmission process, this application uses the H5007 chip as an isolation device between the Ethernet interface and the Ethernet controller i210. The H5007 chip is an Ethernet transformer with a turns ratio of 1:1, which can not only play the role of electrical isolation and common-mode suppression, but also improve the signal strength and increase the transmission distance of Ethernet. In addition, SST25VF080B is used as the FLASH chip, and the mac address of i210 is written into the FLASH configuration file and burned, so that the macs of the four I210 Ethernet control chips can be managed by the developer.

[0047] The principle of four-way Ethernet expansion is as follows Figure 4 As shown:

[0048] The expansion of four Ethernet channels is realized through a SOM-7569 core board. The connection between the SOM-7569 core board and the Ethernet control chip WGI210-IT (hereinafter referred to as I210) is as follows:

[0049] The PCIE_TX0-, PCIE_TX0+, PCIE_RX0-, and PCIE_RX0+ pins of the SOM-7569 core board are respectively connected to the PE_Rn, PE_Rp, PE_Tn, and PE_Tp pins of the I210 that implements the first extension, and correspondingly, the PCIE_TX1-, PCIE_TX1+, PCIE_RX1-, and PCIE_RX1+ pins of the SOM-7569 core board are respectively connected to the PE_Rn, PE_Rp, PE_Tn, and PE_Tp pins of the I210 that implements the second extension; and so on. The clock line pin SMB_CLK, data line pin SMB_DAT, and warning line pin SMB_ALERT of the SOM-7569 core board are respectively connected to the SMB_CLK, SMB_DAT, and SMB_ALERT pins corresponding to the I210 that implements the first and second extensions to realize the connection of the SMBus system management bus, and so on. At the same time, the PECLKn and PECLKp of the first extended I210 are respectively connected to the reference clock signals PCIE1_CLK_+ (PCIE1_CLK_P) and PCIE1_CLK- (PCIE1_CLK_N), and the PECLKn and PECLKp of the second extended I210 are respectively connected to the reference clock signals PCIE2_CLK_+ (PCIE2_CLK_P) and PCIE2_CLK-

[0050] (PCIE2_CLK_N), and so on, to expand four Ethernet MDI differential signals.

[0051] The connection between the Ethernet control chip I210, the isolation device H5007, and the Ethernet interface RJ45 is as follows:

[0052] The industrial communication protocol MDI pin of each I210 is connected to the input pin TD of the H5007, and the output pin TX of the H5007 is connected to the Ethernet interface RJ45. Specifically, the four pairs of pins MDI_PLUS[0], MDI_MINUS[0], MDI_PLUS[1], MDI_MINUS[1], MDI_PLUS[2], MDI_MINUS[2], MDI_PLUS[3], MDI_MINUS[3], MDI_PLUS[4], MDI_MINUS[4] of the I210 are respectively connected to the four pairs of pins TD1+ / -, TD2+ / -, TD3+ / -, TD4+ / - of the H5007; the four pairs of pins TX1+ / -, TX2+ / -, TX3+ / -, TX4+ / - of the H5007 are respectively connected to the four pairs of pins DA+ / -, DB+ / -, DC+ / -, DD+ / - of the RJ45.

[0053] The connection between Ethernet control chip I210 and FLASH chip SST25VF080B is:

[0054] The NVM pins used to output the mac address of I210 are connected to the corresponding pins of the FLASH chip. Specifically, NVM_CS_N, NVM_SI, NVM_SO, and NVM_SK are respectively connected to CE#, SO, SI, and SCK of the SST25VF080B chip to write the mac address into the FLASH configuration file and burn it, so that the macs of the four i210 Ethernet control chips can be managed by the developer.

[0055] (2)HDMI interface

[0056] The full name of HDMI interface is High Definition Multimedia Interface (HDMI), which is a fully digital video and sound transmission interface that can send uncompressed audio and video signals. HDMI can be used for set-top boxes, DVD players, personal computers, televisions, game consoles, integrated amplifiers, digital audio and televisions and other devices. HDMI can send audio and video signals at the same time. Since the audio and video signals use the same wire, the installation difficulty of the system line is greatly simplified. The workstation developed by this application uses an HDMI interface to be connected to an external display. The 7569 core board provides four sets of HDMI data differential pair signals DDIX_PAIR0+ / -, clock signals DDI0_CTRL_AUX_+ / -, hot plug DDI1_DP_HPD and other signals for external controller access. In the present embodiment, the HDMI controller uses a highly integrated HDMI signal adjustment chip IP4786CZ32 to realize the function of an external display. IP4786CZ32 adopts a simple interface design concept and has a unique transmission line clamp architecture, which reduces the peak clamp voltage during ESD shock and has strong ESD protection capabilities. In addition, this chip integrates an overcurrent limiting 5V LDO solution, which meets the HDMI1.4 overcurrent protection requirements. Figure 5 As shown:

[0057] The TMS pin of the HDMI signal adjustment chip IP4786CZ32 is connected to the four sets of data differential pair signals DDIX_PAIR+ / - of the 7569 core board. The external clock signal DDC_CLK_SYS pin and the external data signal DDC_DAT_SYS pin of IP4786CZ32 are respectively connected to the DDI_CTRL_AUX+ / - of the 7569 core board. The hot-swap DDI1_DP_HPD signal is provided for access by the external controller.

[0058] (3) CAN and RS232 interfaces

[0059] CAN (Controller Area Network) is an ISO internationally standardized serial communication protocol. It is a multi-master serial communication bus. The basic design specifications require high bit rate, high resistance to electromagnetic interference, and high real-time performance. It is widely used in industrial automation, ships, medical equipment, industrial equipment, etc. The 7569 core board does not have a dedicated CAN interface signal. This application uses the serial signal SER1_TX and SER1_RX extensions in the 7569 core board to design a set of CAN_P and CAN_N differential CAN signals. The design schematic is shown in the figure below. The control chip used is TJA1051T, which is a CAN transceiver chip that provides a physical interface between the buses of the CAN controller, can achieve reliable and high-speed data transmission, with a maximum rate of up to 1Mbps and has thermal protection, short-circuit protection, and low power consumption mode functions. A set of CAN_P and CAN_N signals generated by TJA1051T are connected to a three-core plug to communicate with the outside world. Figure 6 As shown,

[0060] The TXD and RXD pins of TJA1051T are connected to the serial signals SER1_TX and SER1_RX in the 7569 core board. The CANH and CANL pins of TJA1051T output a group of CAN_P and CAN_N signals. The CAN_P and CAN_N signals are connected to the three-core plug P6 to realize CAN communication.

[0061] RS232 is a technical standard for serial binary data exchange interface between data terminal equipment and data communication equipment. RS232 level refers to the signal voltage of RS232 interface, which uses negative logic level, that is, -15V~-3V represents logic "1", and +3V~+15V represents logic "0". Typical RS-232 signals swing between positive and negative levels. When sending data, the transmitting end driver outputs positive level at +5~+15V and negative level at -5~-15V. The receiver's typical working level is +3~+12V and -3~-12V. 7569 core board provides a set of serial communication signals SER0_RX and SER0_TX, but this set of transceivers is TTL level. If RS232 level needs to be generated, a conversion chip is needed to realize the conversion between RS232 and TTL levels. This design uses SP3232 chip to complete this function. SP3232 is a powerful RS-232 transceiver chip that can realize serial data conversion and transmission. It contains a dedicated on-chip charge pump circuit that can generate 2×Vcc RS-232 voltage level from a power supply voltage of +3.0V to +5.5V.

[0062] The SP3222E / 3232E driver can maintain a data rate of up to 235Kbps when fully loaded. The design schematic diagram of the conversion between RS232 and TTL levels is shown in the figure. Figure 7 As shown:

[0063] A set of serial communication signals SER0_RX and SER0_TX of the 7569 core board are connected to the R1OUT and T1IN pins of the SP3222E / 3232E driver respectively. The R1IN and T1OUT pins of the SP3222E / 3232E driver output a set of RS232 level signals RS232_RX1 and RS232_TX1. RS232_RX1 and RS232_TX1 are connected to the three-core plug P7 to realize the mutual conversion between RS232 and TTL levels, thereby realizing RS232 communication.

[0064] (4) Two RS485 bus interfaces

[0065] Compared with the RS232 communication interface, the RS485 communication interface has its unique advantages. The RS232 interface can only realize point-to-point communication, does not have networking function, and the maximum transmission distance can only reach tens of meters, which cannot meet the requirements of long-distance communication. RS485 solves these problems. The data signal adopts differential transmission mode, which can effectively solve the common mode interference problem. The maximum distance can reach 1200 meters, and multiple transceiver devices are allowed to be connected to the same bus for networking to realize multi-machine communication. Multiple transceivers are allowed to be connected to the bus. From the existing RS485 chip, there are drivers for 32, 64, 128, 256 and other different devices. In the RS485 communication network, the master-slave communication mode is generally used, that is, one host with multiple slaves. The master device is usually a PC. One master device is allowed to exist in the device network, and the rest are all slave devices to establish a one-to-many device network control. The 7659 core board used in the project does not have a directly available RS485 signal, but the core board has multiple USB serial signals. This application implements the function of expanding two RS485 buses by designing a circuit that converts USB serial signals to RS485. The two pairs of USB2_Z_P / USB2_Z_N and USB3_Z_P / USB3_Z_N signals on the 7659 core board are used and implemented through the CH340E chip and the MAX485 chip. CH340 can realize the USB to TTL serial port circuit. CH340E is a USB to serial port chip, compatible with USB 2.0, using a hardware full-duplex interface, with a built-in transceiver buffer, and supports a communication baud rate between 50bps and 2Mbps. In addition, CH340E has a built-in clock and does not require an external crystal oscillator, so it has the characteristics of simple circuit design, and only requires very few peripheral circuits to realize communication between USB and TTL serial ports. In this design, CH340E gets TTL level and then connects to MAX485 chip. MAX485 is an RS485 level transceiver, which contains an input signal receiver R and an output signal driver D. It can directly convert TTL level into A and B differential signals of 485 bus for external input and output. Multiple MAX485 can be connected to 485 bus to form a network. The schematic diagram of core board expansion 485 bus is as follows Figure 8 As shown:

[0066] The two pairs of universal USB signals USB2_Z_P / USB2_Z_N and USB3_Z_P / USB3_Z_N on the 7659 core board are connected to the UD+ / - pins of the two CH340s respectively. The CH340 converts the input USB signal into a TTL serial port circuit, and after obtaining the TTL level, it is connected to the MAX485 chip. The RXD and TXD of each CH340 are connected to the RO and DI pins of the MAX485 chip respectively. The MAX485 chip converts the input TTL level into the A and B differential signals of the 485 bus, and inputs and outputs them from pins A and B.

[0067] (5) USB2.0 and USB3.0 interfaces

[0068] In response to the needs of development and use of different projects, this application has expanded two USB2.0 and two USB3.0 interfaces on the 7659 core board. The extended USB2.0 interface is designed using the two USB signals (USB4+ / - and USB5+ / -) available on COM-E. In order to reduce EMI electromagnetic interference, a series common-mode choke is added to the derived USB4+ / - and USB5+ / - signals. The signal after the common-mode choke is directly connected to the USB2.0 socket. This two-way USB2.0 socket is defined by this application itself, adopts a direct-plug package, and has a fool-proof design. This form of design occupies less space and the connection is more reliable to install. The expansion design of the two-way USB2.0 is as follows Fig. 9 shown.

[0069] Similar to the design of two USB2.0 ports, two USB3.0 ports are also designed on the core board.

[0070] USB3.0 is developed on the basis of USB2.0. It has obvious differences in transmission speed and structural characteristics while maintaining a certain degree of compatibility. Different from USB2.0 in structure, USB3.0 adds two pairs of ultra-high-speed data transmission and reception signals SSTX and SSRX in addition to one pair of transceivers, so that the transmission speed can reach 625MS / s in ultra-high-speed mode. The 7569 core board itself has two pairs of SSTX and SSRX high-speed transmission signals for USB3.0, and there are 8 pairs of differential signals for USB2.0, which can easily design two-way USB3.0 expansion.

[0071] Use the 7569 core board's USB_SSRX0_+ / -, USB_SSTX0_+ / - and USB0_P_+ / - to design one USB3.0 interface, and USB_SSRX1_+ / -, USB_SSTX1_+ / - and USB1_P_+ / - to design another USB3.0 interface. Similar to USB2.0, each signal passes through a series common-mode choke to reduce electromagnetic interference. After passing through the common-mode choke, it is divided into two USB3.0 channels, one is USB_Z_SSRX0_+ / -, USB_Z_SSTX0_+ / - and USB0_Z_P_+ / -, and the other is USB_Z_SSRX1_+ / -, USB_Z_SSTX1_+ / - and USB1_Z_P_+ / -. Finally, design a unified 19-core straight-insert anti-foolproof plug to unify the two USB3.0 interfaces, and the 19-core anti-foolproof plug is defined by yourself. The schematic diagram of the two-channel USB3.0 expansion is as follows Fig.10 , Fig.11 As shown:

[0072] (6) Multi-layer PCB circuit board design

[0073] Since there are many signals in this design, including many high-speed signals and differential signals, and the project requires the size of the circuit board to be as small as possible, a multi-layer board design is used in the design process of the PCB board, and the designed stacking structure is used to reduce EMI electromagnetic interference and improve signal integrity. This application adopts an 8-layer board stacking design method. The interface layout of the multi-layer board is as follows Fig.12 As shown, the structure distribution of the 8-layer stack is as follows Fig.13 As shown, from bottom to top, they are Bottom signal layer, GND layer, signal layer 2, GND layer, inner electrical layer, signal layer 1, GND layer, and Top signal layer.

[0074] This application uses four layers as signal layers, namely: the top layer, the third layer (signal layer 1), the sixth layer (signal layer 2) and the bottom layer, and the other four layers are set as the power layer and the bottom layer respectively. The stacked structure of this 8-layer board has the following advantages: the power layer and the ground layer are fully coupled; each signal layer is directly adjacent to the ground layer and is effectively isolated from other signal layers, and is not easy to cause crosstalk; the top signal layer and the bottom signal layer are connected to the ground by copper cladding and separated by the ground layer, which should be preferred for some high-speed signal lines that do not require vias; in addition, signal layer 2 is separated by two layers of ground, which is an ideal high-speed signal routing layer, and should be preferred for high-speed signal lines that need to change layers.

[0075] The PCB design of this project adopts the following methods in the specific layout:

[0076] (1) According to the functional characteristics of the platform, a modular layout strategy is adopted to reduce the loop area by placing the same functional devices nearby. Circuits of different signal types are placed separately, such as analog signals and digital signals. In the design of the PCB of this platform, the modules can be divided into: Gigabit Ethernet module, USB module, RS232 / RS485 communication module, power supply and other modules.

[0077] (2) The PCB of this platform needs to load the 7569 core board based on COM-E. In the design, the position of the 220-core COM-E interface is first determined, and other module devices are placed around it. All other interfaces are placed close to the edge of the circuit board to facilitate external plugging and unplugging. All interfaces except COM-E are defined by this design, and their packages are designed to be plugged in directly upward. This installation does not take up space, and the external connection is safe and reliable, with strong confidentiality.

[0078] (3) The capacitor or inductor filter network of each module circuit is placed in the principle of proximity. A 0.1μF to 10μF filter capacitor is placed at the power supply pin of each chip to improve the stability of power supply.

[0079] (4) For high-speed circuit core boards, key interface signals such as PCIE clock and USB are all differential signals. These signals are required to be parallel, equal in length, equidistant and preferably on the same signal layer. The equidistant is to ensure uniform and continuous impedance of the differential line; the purpose of equal length is to ensure the correctness of the timing. The differential signals should be as close as possible to reduce the wiring distance. The connection between high-speed signals should be simulated for impedance matching, and appropriate resistors should be connected in series.

[0080] (5) For clock signals, the routing channel of the clock signal should be considered from the beginning of wiring. When routing clock signal lines, the routing of clock signal lines with the same frequency and the same purpose should be controlled to be of equal length. At the same time, from the perspective of electromagnetic compatibility, the clock line routing should be as short as possible. When routing, the clock signal line is laid on the layer closest to the ground layer and farthest from the power layer. The BOTTOM layer below the crystal oscillator is not allowed to be routed. The crystal oscillator circuit of the circuit designed in this system, including the crystal oscillator circuit of the Ethernet controller, should be as close to the chip as possible to prevent it from being on the PCB, as far away from interference sources such as I / O lines as possible, and should be routed on the inner layer as much as possible.

[0081] During the wiring process, there are also some wiring rules and tips to follow. Whether it is a high-speed or low-speed signal line, it should be as short as possible to avoid loss caused by too long lines. High-speed signal lines should be routed on the inner signal layer as much as possible. When routing, the corners of the line should be obtuse instead of right angles or sharp angles to prevent impedance discontinuity and signal reflection caused by wiring. When routing the power line, try to use a wider line or directly lay copper. Using a wider line or pulling copper foil can enhance the noise resistance of the circuit and prevent large currents that may pass through. The width of the ground line should be wider than the power line. It is best to use a large area of ​​copper as the ground line. Copper is laid on the part of the PCB without devices and connected to the ground through punching to use as the ground line. This can shorten the current loop and reduce the impedance of the ground line. Most of the power and ground are connected to the inner power layer of the power supply through wide copper and multiple vias. The use of a large area of ​​copper can better ensure the power supply's noise resistance. At the same time, the power supply first passes through a series of parallel filter capacitors and then reaches the chip's use pins, which can minimize the impact of low-frequency ripple and high-frequency noise on the power supply.

[0082] The differential signal lines in the design all appear in pairs. The characteristic impedance requirements between them are relatively high. According to the design requirements of Advantech's industrial computer board, the network signal line should be 100 ohms, and other signal lines such as USB signal lines and PCIE signal lines should be 85 ohms. The impedance control of this design uses the JLC08161H-2116 standard stacking model to define the spacing between each layer, copper foil thickness, material and other parameters. The JLC impedance calculation tool is used to obtain the line width and line spacing required for the target impedance. In addition, the HDMI signal line should not only ensure equal length wiring within the differential pair, but also ensure equal length wiring between each differential pair to ensure stable signal transmission.

[0083] The PCB design layout process is as follows Fig.14 The steps are as follows: S1, design the stacking layout of the eight-layer board; S2, determine the position of the COM-E port in the PCB board; S3, modularize the components in the schematic diagram to layout the interfaces and plug-ins; S4, layout the key core module chips; S5, layout the resistors, capacitors and other devices around each module; S6, adjust the overall layout; S7, finally make fine adjustments to the local layout.

[0084] After the layout was completed, the packages of all devices were checked, and the layout drawings were printed out at a 1:1 size and compared with the size of the actual devices.

[0085] (7) Installation of expansion circuit board and core board

[0086] like Fig.15As shown, the size of the expansion board of this design is 108mm (length) x103mm (width). The expansion board and the core board are a two-layer plug-in structure. The expansion circuit board is designed with COM-E 220 core pins, and the core board is designed with COM-E 220 core holes. They are connected up and down through the 3-6318491-6 connector. This design is adopted to save space and to maximize the use of the COM-E port resources of the 7569 core board itself. According to this design, an image workstation with five Gigabit Ethernet ports, two universal USB3.0 interfaces, two universal USB2.0 interfaces, one CAN interface, two RS485 interfaces, one RS232 interface and one HDMI display interface has a size of only 108mmx103mm (the size of the expansion board), which realizes the design requirements of a small-volume and multi-interface graphic workstation.

[0087] This expansion board is actually used in several product hardware platforms with measurement marking functions, such as Fig.16 The figure shows a schematic diagram of a 3D projection product, with a projector in the middle and two CMOS cameras on each side forming a binocular photography system. An industrial computer composed of an expansion board and a core board is installed in it to collect CMOS camera images and project the calculated results. The entire host is only 108mmx105mm in size. Although it is small in size, it realizes all the functions required by the host.

[0088] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A multi-interface expansion circuit, characterized in that: It includes a SOM-7569 core board, on which COM-E is provided with a native signal pin, which is connected to the Ethernet interface after passing through a network control chip to realize native network connection; the core board is connected to the Ethernet control chip to realize network port expansion connection; the core board is connected to an HDMI signal adjustment chip to realize an external display function; the serial signal of the core board is connected to a CAN control chip to realize CAN communication; the serial communication interface of the core board is connected to an RS-232 interface transceiver chip to realize RS232 serial communication; the USB serial signal of the core board is connected to a USB to serial port chip, converted into a TTL serial port circuit, and then connected to an RS485 level transceiver to realize RS485 communication.

2. The multi-interface expansion circuit according to claim 1, characterized in that: The native network connection is: the native pins GBE0_MDI3-, GBE0_MDI3+, GBE0_MDI2-, GBE0_MDI2+, GBE0_MDI1-, GBE0_MDI1+, GBE0_MDI0- and GBE0_MDI0+ of the native signal interface COM-E end are connected to the TD pin of the network transformer, and the TX pin of the network transformer is connected to the RJ pin of the Ethernet interface.

3. The multi-interface expansion circuit according to claim 1, characterized in that: Ethernet control chip is WGI210-IT chip, based on one core board and four Ethernet control chips to achieve four-way Ethernet expansion: the PCIE_TX_P / N and PCIE_RX_P / N pins of the core board are respectively connected to The PE_RP / N and PE_TP / N pins of WGI210-IT are connected, and the PECLKP / N of WGI210-IT The pins are connected to the reference clock signal PCIE1 / 2 / 3 / 4_CLK_+ / -. The MDIO / IIC interface of the WGI210-IT chip is used to configure the physical layer transceiver registers. Four WGI210-IT control chips are used to unify the timing. The reference clock PCIE1 / 2 / 3 / 4_CLK_+ / - of the four chips are four pairs of differential clock signals, which are used to connect the high-speed serial communication interface of the computer motherboard and external devices.

4. The multi-interface expansion circuit according to claim 3, characterized in that: A four-channel output differential buffer chip ICS9DB104 is used as a clock expansion chip. The input pin SRC_IN of the ICS9DB104 chip is connected to the standard clock signal PCIE CLK REF to output four reference clock signals PCIE1_CLK_+ / -, PCIE2_CLK_+ / -, PCIE3_CLK_+ / -, and PCIE4_CLK_+ / -, which are respectively given to the PECLKP / N of the four WGI210-IT chips; the four-channel differential transmit and receive links PCIE_TX1 / 2 / 3 / 4 and PCIE_RX1 / 2 / 3 / 4 of the core board COM-E interface are connected to the PE_RP / N PE_TP / N of the four WGI210-IT chips, and the core board is connected to the SMBus bus SMB_CLK / DAT corresponding to the WGI210-IT to expand the signals required for the four-channel Ethernet.

5. The multi-interface expansion circuit according to claim 3 or 4, characterized in that: An isolation chip H5007 is installed between the Ethernet interface and the Ethernet control chip WGI210-IT. The mac address pin of WGI210-IT is connected to the FLASH chip SST25VF080B, and the mac address of I210 is written into the FLASH. The configuration file is burned so that the macs of the four Ethernet control chips can be managed by the developer.

6. The multi-interface expansion circuit according to claim 1, characterized in that: The HDMI signal adjustment chip is IP4786CZ32. The four pairs of TMS pins of IP4786CZ32 are connected to the four sets of data differential pair signals DDIX_PAIR+ / - of the 7569 core board respectively. The external clock signal of IP4786CZ32 The DDC_CLK_SYS pin and the external data signal DDC_DAT_SYS pin are respectively connected to the DDI_CTRL_AUX+ / - of the 7569 core board, and the hot-swap DDI1_DP_HPD signal is provided for access by the external controller.

7. The multi-interface expansion circuit according to claim 1, characterized in that: The CAN control chip is TJA1051T. Based on the serial signal SER1_TX and SER1_RX expansion in the core board, the CAN transceiver chip TJA1051T is connected to obtain a set of CAN_P and CAN_N differential CAN signals. The differential CAN signals are connected to a three-core plug to communicate with the outside world.

8. The multi-interface expansion circuit according to claim 1, characterized in that: The RS-232 interface transceiver chip is an SP3232 driver. The SER0_RX and SER0_TX pins of the core board provide a set of serial communication signals and are connected to the R1OUT and T1IN pins of the SP3232. The R1IN and T1OUT pins of the driver output a set of RS232 level signals RS232_RX1 and RS232_TX1. The RS232 level signal is connected to a three-pin plug to achieve mutual conversion between RS232 and TTL levels.

9. The multi-interface expansion circuit according to claim 1, characterized in that: The USB to serial port chip is a CH340E chip, and the RS485 level transceiver is a MAX485. Based on the two universal USB signals USB2_Z_P / USB2_Z_N and USB3_Z_P / USB3_Z_N on the core board, they are converted into TTL levels through the CH340E chip, and the TTL levels are connected to the MAX485 chip, which directly converts the TTL levels into A and B differential signals of the 485 bus for external input and output. Several MAX485s are connected to the 485 bus at the same time to form a network.

10. The multi-interface expansion circuit according to claim 1, characterized in that: Two USB2.0 and / or two USB3.0 interfaces are expanded on the core board. The expansion of USB2.0 is as follows: a series common-mode choke is added to the two USB signals USB4+ / - and USB5+ / - provided at the COM-E end of the core board and then connected to the USB2.0 socket; the expansion of USB3.0 is as follows: a series common-mode choke is added to the USB0+ / - and USB1+ / - provided at the COM-E end of the core board and two pairs of ultra-high-speed data transceiver signals SSTX and SSRX, and then the signals are divided into two USB3.0 channels and connected to the socket.

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