A method and system for half-duplex inter-chip SPI access to registers

Abstract

The present invention discloses a method and system for half-duplex inter-chip SPI access to registers in the field of information communication, which is used for the master-side FPGA to perform read and write operations on the slave-side FPGA. The master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register; the method includes a write state and / or a read state; in the write state, the ARM processor issues a write instruction, which reaches the slave-side FPGA through the data link and PCB traces, and finally writes to the corresponding address of the slave-side register; in the read state, the ARM processor issues a read instruction, which reaches the slave-side FPGA through the data link and PCB traces, passes through the data link, finally reads the data at the corresponding address of the slave-side register, then passes through the reverse data link, returns to the master-side FPGA through the PCB traces, and finally is sent back to the ARM processor through the data link; the present invention can realize the function of the master-side FPGA to read and write registers of the slave-side FPGA.

Description

Technical Field

[0001] The present invention relates to the field of information and communication technologies, and in particular, to a method and system for half-duplex inter-chip SPI access to registers. Background Art

[0002] In some customized wireless communication products, due to the control of multiple peripherals, high-speed port transmission, and digital intermediate frequency signal processing, from the perspective of economic cost, a high-end FPGA chip with an ARM is often discarded, and two low-end FPGAs are used to work together. One is the master FPGA with an ARM, and the other is the slave FPGA without an ARM. The master FPGA is used to control peripherals and transmit high-speed data, while the slave FPGA is used to process digital intermediate frequency signals and develop some functions that do not require software cooperation. However, the absence of an ARM means that there is no GP bus available for calling, thus unable to implement the basic function of registers. Registers play a crucial role both in the early debugging and in the later problem positioning. Therefore, it is particularly important to develop a register system that can meet the debugging and problem positioning needs of technicians on the platform where the master FPGA cooperates with the slave FPGA. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a method and system for half-duplex inter-chip SPI access to registers. The master-side FPGA with an ARM processor realizes the function of reading and writing registers from the slave-side FPGA without an ARM processor through the serial general-purpose interface SPI protocol.

[0004] To achieve the above purpose, the present invention is implemented by the following technical solutions:

[0005] In a first aspect, the present invention provides a method for half-duplex inter-chip SPI access to registers, which is used to perform read and write operations on a slave-side FPGA without an ARM processor through a master-side FPGA with a built-in ARM processor. The master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes a slave-side SPI interface and a slave-side register interconnected; the method includes a write state and / or a read state.

[0006] In the write state, obtain the write data and write address output by the ARM processor, and successively convert them into protocol data of the AXI4 protocol via the connector, convert them into interface data composed of write enable, write data, and write address via the converter, convert them into predefined register data via the master-side register, convert them into serial data of the SPI protocol via the master-side SPI interface, convert them into predefined register data via the slave-side SPI interface, identify the write enable, write address, and write data via the slave-side register, and store the write data in the write address;

[0007] In the read state, obtain the read address output by the ARM processor, and successively convert it into protocol data of the AXI4 protocol via the connector, convert it into interface data composed of read enable and read address via the converter, convert it into predefined register data via the master-side register, convert it into serial data of the SPI protocol via the master-side SPI interface, convert it into predefined register data via the slave-side SPI interface, identify the read enable and read address via the slave-side register, and obtain the read data corresponding to the read address; send the read data back to the ARM processor in the reverse direction along the transmission path.

[0008] Optionally, in the write state, based on the handshake criterion of the AXI4 protocol: when the converter is ready, the converter sends the ready signals of the write address channel and write data channel to the connector, indicating that the converter is ready. At this time, the connector sends the write address and write data to the converter; when the connector is ready, the connector sends the ready signal of the write reply channel to the converter, indicating that the connector is ready. At this time, the converter sends the write reply data to the connector;

[0009] According to the protocol data of the AXI4 protocol obtained by the converter, align the write address and write data at the same moment and send them to the master-side register, and at the same time send the write enable to the master-side register.

[0010] Optionally, in the write state,

[0011] Define the SPI write enable register, including the SPI write enable address and its corresponding SPI write enable signal. The high and low levels of the SPI write enable signal respectively indicate that the write enable is valid and invalid;

[0012] Define the read / write judgment register, including the read / write judgment address and its corresponding read / write judgment signal. The high and low levels of the read / write judgment signal respectively indicate the read state and write state;

[0013] Define the SPI write address register, including the address of the SPI write address and its corresponding SPI write address signal. The SPI write address signal is 16 bits, indicating that the maximum transmission bit width is 16-bit address;

[0014] Define the SPI write data register, including the address of the SPI write data and its corresponding SPI write data signal. The SPI write data signal is 32 bits, indicating that the maximum bit width of the data to be transmitted is 32 bits.

[0015] According to the interface data consisting of write enable, write data and write address obtained by the master side register, the read / write judgment signal is set to a low level, the write address is used as the SPI write address signal, the write data is used as the SPI write data signal, and the SPI write enable signal is set to a high level.

[0016] Optionally, in the write state, when the SPI write enable signal is high, the working logic of the master side SPI interface is triggered:

[0017] Set the SPI chip select signal to a low level, and at the unit clock cycle position of 10 system clocks, demultiply the connected system clock by 10 times, set the SPI clock, and use the rising edge sampling of the SPI clock. Since it is necessary to transmit a 1-bit read / write judgment signal, a 16-bit SPI write address signal, and a 32-bit SPI write data signal to the slave-side FPGA, the transmitted SPI clock needs to last for 49 SPI unit clock cycles;

[0018] At the position of the unit clock cycle of 5 system clocks of the SPI chip select signal, set the setup time and hold time of the collected data to 50%, and use the shift register method to send 49 bits of read and write judgment signal, SPI write address signal, and SPI write data signal in sequence through the SPI MOSI bus. When the last 1 bit of write data signal is sent, the chip select signal is set to a high level after the hold time is met, completing the operation of slave-side FPGA transmission of write address and write data.

[0019] Optionally, in the write state, the working logic of the slave side SPI interface is:

[0020] When the chip select signal is set to a low level, at the rising edge of the SPI clock, it is determined whether the received read / write determination signal is a low level. If so, the 16-bit SPI write address signal and the 32-bit SPI write data signal received through the SPI MOSI bus are cached and transmitted to the slave side register, and the write enable is output to the slave side register.

[0021] In a second aspect, the present invention provides a half-duplex system for accessing registers between chips via SPI, which is used to perform read and write operations on a slave-side FPGA without an ARM processor through a master-side FPGA with a built-in ARM processor. The master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register; the system includes a write status execution module and / or a read status execution module;

[0022] The write status execution module is used to, in the write status, obtain the write data and write address output by the ARM processor, convert them into protocol data in the AXI4 protocol via the connector in sequence, convert them into interface data composed of a write enable, write data, and write address via the converter, convert them into predefined register data via the master-side register, convert them into serial data in the SPI protocol via the master-side SPI interface, convert them into predefined register data via the slave-side SPI interface, identify the write enable, write address, and write data via the slave-side register, and store the write data in the write address;

[0023] The read status execution module is used to, in the read status, obtain the read address output by the ARM processor, convert it into protocol data in the AXI4 protocol via the connector in sequence, convert it into interface data composed of a read enable and a read address via the converter, convert it into predefined register data via the master-side register, convert it into serial data in the SPI protocol via the master-side SPI interface, convert it into predefined register data via the slave-side SPI interface, identify the read enable and the read address via the slave-side register, and obtain the read data corresponding to the read address; and transmit the read data back to the ARM processor in the reverse direction along the transmission path.

[0024] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0025] A method and system for half-duplex inter-chip SPI access to registers provided by the present invention. 1) A master-side FPGA carrying an ARM processor is used to read and write registers of a slave-side FPGA without an ARM processor through the serial general interface SPI protocol, thus avoiding the economic cost brought by implementing all ARM functions on a high-end FPGA and reducing the development cost. 2) When implementing the transmission of data and addresses, the AXI4 protocol is used to convert to a simpler custom interface of enable, address, and data, and then to the SPI protocol, realizing the interconnection of the AXI4 protocol and the SPI protocol, which is more flexible and endows the system with the ability to adapt to more scenarios. 3) By dividing the specific modules of the master-side FPGA and the slave-side FPGA and implementing the functions of the specific modules, the system logic is enhanced, and at the same time, it is convenient to capture data at breakpoints after problems occur during debugging, enhancing the development efficiency. 4) Using the SPI protocol, the master FPGA realizes the register reading of the slave FPGA. Only simple PCB traces are required, and no actual SPI devices are needed to complete the register reading function, reducing the complexity of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. is a schematic structural diagram of a half-duplex inter-chip SPI access register provided by an embodiment of the present invention;

[0027] Figure 2 FIG. is a schematic diagram of the write state process of a half-duplex inter-chip SPI access register provided by an embodiment of the present invention;

[0028] Figure 3 FIG. is a schematic diagram of the read state process of a half-duplex inter-chip SPI access register provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and should not be used to limit the protection scope of the present invention.

[0030] Embodiment 1:

[0031] An embodiment of the present invention provides a method for half-duplex inter-chip SPI access to registers, which is used to perform read and write operations on a slave-side FPGA without an ARM processor through a master-side FPGA with an ARM processor. As Figure 1 shown, the master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register.

[0032] As Figure 2As shown, in the write state, the write data and write address output by the ARM processor are obtained, and are successively converted into protocol data of the AXI4 protocol via a connector, converted into interface data composed of a write enable, write data, and write address via a converter, converted into predefined register data via a master-side register, converted into serial data of the SPI protocol via a master-side SPI interface, converted into predefined register data via a slave-side SPI interface, the write enable, write address, and write data are identified via a slave-side register, and the write data is stored in the write address.

[0033] In the direction of writing data from the master-side FPGA to the slave-side FPGA, the required write address and write data are written to the connector through the PS. The write address and write data are the logic corresponding to the master-side register controlling the master-side SPI interface, specifically involving the SPI write enable signal, SPI read / write judgment signal, SPI write address signal, and SPI write data signal. It is necessary to perform a write data operation on the master-side register at the above specific address.

[0034] For example: In the master-side FPGA, the base address of the master-side register is defined as 0x0, the offset address of the SPI write enable signal is 0x20, the offset address of the read / write judgment signal is 0x21, the offset address of the SPI write address signal is 0x22, and the offset address of the write data signal is 0x23. The signal corresponding to the address 0x20 is the SPI write enable signal, which is used to trigger the logic of the master-side SPI interface. The signal corresponding to the address 0x21 is the SPI read / write judgment signal, which is used to distinguish the read / write state. The signal corresponding to the address 0x22 is the SPI write address signal, which is the 16-bit SPI write address signal actually written into the MOSI bus of the master-side SPI interface. The signal corresponding to the address 0x23 is the SPI write data signal, which is the 32-bit SPI write data signal actually written into the MOSI bus of the master-side SPI interface.

[0035] Convert the data stream of the AXI4 protocol received by the converter from the connector into interface data composed of write enable, write address, and write data, and output it to the master-side register. Since the data received by the converter is the data specified by the AXI4 protocol, and its write logic includes a write address channel, a write data channel, and a write response channel, according to the handshake criterion specified by the AXI4 protocol, when the converter is ready, the ready signals of the write address channel and the write data channel are respectively sent to the connector to indicate that the converter is ready. At this time, the write data valid signal and the write data signal, as well as the write address valid signal and the write address signal sent by the connector are received, and at the same time, the write response ready signal of the connector is waited for. When the write response ready signal is captured, it indicates that the connector is ready, and the write response valid signal and the write response signal of the converter are sent to the connector. Align the write address and the write data at the same moment and output them, and output the write enable at this moment. At this time, the conversion of the AXI4 protocol into a simple interface connected to the master-side register composed of a write enable signal, a write address signal, and a write data signal is completed, and it is output to the master-side register.

[0036] In the write state,

[0037] Define the SPI write enable register, including the SPI write enable address and its corresponding SPI write enable signal. The high and low levels of the SPI write enable signal respectively indicate that the write enable is valid and the write enable is invalid;

[0038] Define the read / write judgment register, including the read / write judgment address and its corresponding read / write judgment signal. The high and low levels of the read / write judgment signal respectively indicate the read state and the write state;

[0039] Define the SPI write address register, including the address of the SPI write address and its corresponding SPI write address signal. The SPI write address signal is 16 bits, indicating an address with a maximum transfer bit width of 16 bits;

[0040] Define the SPI write data register, including the address of the SPI write data and its corresponding SPI write data signal. The SPI write data signal is 32 bits, indicating data with a maximum transfer bit width of 32 bits;

[0041] According to the interface data composed of write enable, write data and write address obtained by the master side register, the read / write judgment signal is set to a low level, the write address is used as the SPI write address signal, the write data is used as the SPI write data signal, and the SPI write enable signal is set to a high level. Since the transmission of the read / write judgment signal, SPI write address signal and SPI write data signal specified in the SPI protocol is transmitted through the master-sender slave-receive MOSI bus, it is necessary to control the timing of SPI transmission to complete the transmission of address and data, that is, to complete the control of SPI logic by controlling the write enable signal, SPI read / write judgment bit, SPI write address signal and SPI write data signal in the master side register. First, in ARM, a low-level read / write judgment bit is sent to the address of the SPI read / write judgment signal, and then an SPI write address signal is sent to the SPI write address, and then an SPI write data signal is sent to the address of the SPI write data, and then a high-level SPI write enable signal is sent to the address of the SPI write enable, and finally a low-level SPI write enable signal is sent to the address of the SPI write enable. The above operation represents a complete process in which the master FPGA sends the write address and write data to the slave FPGA through the SPI protocol. The above operations reach the master-side register after passing through the connector and converter, and the master-side register directly outputs the SPI read / write judgment signal, SPI write address signal, SPI write data signal and write enable signal to the master-side SPI interface.

[0042] In the write state, when the SPI write enable signal is high, the working logic of the master side SPI interface is triggered:

[0043] Set the SPI chip select signal to a low level, and at the unit clock cycle position of 10 system clocks, divide the connected system clock by 10 times. If the system clock is 100Mhz, the SPI clock is 10Mhz. Set the SPI clock and use the rising edge sampling of the SPI clock. Since it is necessary to transmit a 1-bit read / write judgment signal, a 16-bit SPI write address signal, and a 32-bit SPI write data signal to the slave-side FPGA, the transmitted SPI clock needs to last for 49 SPI unit clock cycles. At the unit clock cycle position of 5 system clocks of the SPI chip select signal, set the setup time and hold time of the collected data to 50%. Use the shift register method to send 49 bits of the read / write judgment signal, SPI write address signal, and SPI write data signal in sequence through the SPI MOSI bus. When the last 1-bit write data signal is sent, the chip select signal is set to a high level after the hold time is satisfied, completing the operation of the slave-side FPGA transmission of the write address and write data.

[0044] In the write state, the working logic of the slave SPI interface is:

[0045] When the chip select signal is set to low level, at the rising edge of the SPI clock, it is judged whether the received read / write judgment signal is low level. If so, the 16-bit SPI write address signal and 32-bit SPI write data signal received through the MOSI bus of the SPI are cached, transmitted to the slave register, and at the same time, a write enable is output to the slave register. If the read / write judgment signal is not low level, no logical operation is performed.

[0046] In the slave register, the write address and write data are identified, and the write data is stored in the write address. In the slave register, the required register signals and their corresponding addresses are defined. This address and data correspond to those in the write instruction initiated by the ARM of the master FPGA, and correspond to the write address and write data transmitted in the slave SPI interface. When the write enable is high level, the data corresponding to the address is identified and stored in the data signal corresponding to the address.

[0047] As Figure 3 shown, in the read state, the read address output by the ARM processor is obtained, and is successively converted into protocol data of the AXI4 protocol via the connector, converted into interface data composed of a read enable and a read address via the converter, converted into predefined register data via the master register, converted into serial data of the SPI protocol via the master SPI interface, converted into predefined register data via the slave SPI interface, the read enable and read address are identified via the slave register, and the read data corresponding to the read address is obtained; the read data is transmitted back to the ARM processor in the reverse direction along the transmission path.

[0048] The working principle of the read state is similar to that of the write state:

[0049] In the direction of reading data from the master FPGA to the slave FPGA, the required read address is written to the connector through the ARM processor and the read data sent back by the connector is waited for. This address and data correspond to the logic of the master register controlling the master SPI interface, specifically involving the SPI read enable signal, SPI read / write judgment bit signal, SPI read address signal and SPI read data signal, and a write data operation needs to be performed on the address of the specific master register. Since the data format output from the GP port of the ARM processor is AXI3, it needs to be converted from AXI3 to AXI4 through the connector.

[0050] Convert the data in AXI4 protocol received by the converter into interface data composed of read enable and read address. Since the data of the connector received by the converter is the data specified by the AXI4 protocol and its read logic includes a read address channel and a read data channel, according to the handshake criterion specified by the AXI4 protocol, when the converter is ready, send the ready signal of the read address channel to the connector, indicating that the converter is ready. Then the converter receives the read address valid signal and the read address signal sent by the connector. When the connector is ready to read data, it sends a ready signal to the converter and waits for the read data sent back by the converter. However, only when the read address passes through the complete data link, it is finally sent back to the connector. Output the read address and its corresponding read enable at the same time, and wait for the input read data and its corresponding read enable. At this time, the conversion of the AXI4 protocol to a simple interface connected to the master-side register, composed of a read enable signal, a read address signal, and a read data signal, is completed and output to the master-side register.

[0051] Define the read / write judgment, read address, and read enable of SPI in the master-side register, and sequentially send the corresponding signals to the master-side SPI module in order. Define a read enable register in the master-side register, the read enable signal corresponding to the read enable address, high level indicates that the read enable is valid, and low level indicates that the read enable is invalid; define a read / write judgment register, the read / write judgment signal corresponding to the read / write judgment address, high level indicates the read state, and low level indicates the write state; define a register for the SPI read address, the SPI read address signal, defined as 16 bits, indicating that the maximum bit width that can be transmitted is 16 bit; define a register for the SPI read data, the SPI read data signal, defined as 32 bits, indicating that the maximum bit width that can be transmitted is 32 bit. Since the read / write judgment signal and the read address signal specified by the SPI protocol are transmitted through MOSI, while the transmission of the read data signal is through MISO, that is, it is necessary to complete the transmission of the address and data by operating the timing of the SPI transmission, that is, to control the read address control of the SPI logic by controlling the read enable signal, the read / write judgment signal, and the read address signal in the master-side register, and then complete the reading of the data corresponding to the address by receiving the read data signal sent back by the master-side SPI interface. First, send a high-level read / write judgment bit to the address of the read / write judgment signal in the ARM processor, then send the SPI read address signal to the SPI read address, then send a high-level SPI read enable signal to the address of the SPI read enable, and finally send a low-level SPI read enable signal to the address of the SPI read enable, and then wait for the read data signal sent back by the master-side SPI interface, indicating a complete read data process. The above operations pass through the connector and the converter to reach the master-side register, and the master-side register directly outputs the read / write judgment signal, the read address signal, and the read enable signal to the master-side SPI module, waiting for the read data signal input by the master-side SPI interface.

[0052] Convert the read address received by the master - side SPI interface from the parallel data of the master - side register to the serial data of the SPI protocol, and output it to the SPI - related pins on the FPGA. When the SPI read enable signal is at a high level, trigger the logic of the master - side SPI interface. First, pull down the CS chip - select signal of the SPI. Then, at the position of the unit clock cycle that is 10 system clocks apart, divide the incoming system clock by ten to set the SPI clock. That is, sample using the rising edge of the clock. Since it is necessary to transmit a 1 - bit read - write judgment signal and a 16 - bit read - address signal, a total of 17 bits, and at the same time, it is also necessary to receive a 32 - bit read - data signal transmitted from the slave FPGA, and during the intermediate time slot between sending and receiving, the SPI clock needs to maintain 1 unit clock cycle of the SPI clock as the processing delay of the slave FPGA, so the transmitted SPI clock needs to last for 50 unit clock cycles of the SPI. Then, at the position of the unit clock cycle that is 5 system clocks apart from the chip - select signal of the SPI, set both the setup time and hold time of the sampled data to 50%. In turn, use the shift - register method to receive 17 bits of the read - write judgment signal and the read - address signal through the MOSI signal of the master - transmitting and slave - receiving SPI in sequence. After waiting for a complete SPI clock cycle, receive the 32 - bit read - data longitudinally transmitted from the MISO of the slave FPGA. When the reception of the last 1 - bit read - data signal is completed and the hold time is satisfied, pull up the chip - select signal. At this time, the transmission operation of the read address and the read data is completed.

[0053] In the slave - side FPGA, convert the received SPI data from the SPI serial data to the parallel data of the slave - side register. When the chip - select signal is pulled down, at the first rising edge of the SPI clock, first determine whether the received read - write judgment signal is at a high level. If it is, then at each rising edge of the subsequent SPI clock, cache the 16 - bit serial read - address bits. When the cached read address and the read enable indicating the validity of the read address are output to the slave - side register at the same time, wait for the read - data signal input from the slave - side register; if not, no logical operation is performed.

[0054] In the slave - side register, identify the data corresponding to the read address and output the read data to the slave - side SPI interface. In the slave - side register, define the register signals to be used and their corresponding addresses. This address and data correspondence is in the read instruction initiated by the ARM processor of the master - side FPGA, corresponding to the read address and read data transmitted in the slave - side SPI interface. When the read enable is at a high level, identify the data corresponding to the address, retrieve the data, and at the same time output the high - level signal indicating the validity of the read data to the master - side SPI interface.

[0055] The data received by the master-side SPI interface is converted from parallel data to SPI serial data and output to the pins of the master-side FPGA related to SPI. When the logic of the master-side SPI interface reaches the point where it receives the 17-bit read / write judgment signal and read address signal transmitted by the master-side FPGA through MOSI and waits for a complete SPI clock cycle, the setup time and hold time of the acquired data are both set to 50%. And when the read enable is at a high level at this time, the 32-bit read data is converted from parallel data to serial data in the MSB (Most Significant Bit) manner from the high bit to the low bit, and the read data is sent to the master-side FPGA through the master receive and slave transmit MISO bus.

[0056] In the master-side FPGA, the data received by the master-side SPI interface is converted from the serial data of the SPI protocol to the parallel data of the master-side register and output to the master-side register. When the logic of the master-side SPI interface reaches the point where it sequentially outputs 17 bits through the master transmit and slave receive MOSI signal of SPI and waits for a complete SPI clock cycle, the 32-bit serial read data transmitted from the MISO bus of the slave-side FPGA is cached in the MSB manner. When the reception of the last 1-bit read data signal is completed and the hold time is satisfied, the chip select signal is pulled high. At this time, the cached 32-bit parallel data and the read enable valid signal are transmitted to the master-side register.

[0057] The read address and read enable received by the master-side register are converted into data in the AXI4 protocol and output to the converter. When the read data preparation signal sent by the connector is at a high level, the 32-bit parallel data and the read data valid signal received by the master-side register from the master-side SPI module are sent to the connector and finally sent to the ARM processor.

[0058] Embodiment 2:

[0059] Based on the method for half-duplex inter-chip SPI access register provided in Embodiment 1, the embodiment of the present invention provides a system for half-duplex inter-chip SPI access register, which is used to perform read and write operations on the slave-side FPGA without an ARM processor through the master-side FPGA with a built-in ARM processor. The master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register; the system includes a write status execution module and / or a read status execution module;

[0060] The write state execution module is used to obtain the write data and write address output by the ARM processor in the write state, and successively convert them into protocol data of the AXI4 protocol via the connector, convert them into interface data composed of write enable, write data, and write address via the converter, convert them into predefined register data via the master-side register, convert them into serial data of the SPI protocol via the master-side SPI interface, convert them into predefined register data via the slave-side SPI interface, identify the write enable, write address, and write data via the slave-side register, and store the write data in the write address;

[0061] The read state execution module is used to obtain the read address output by the ARM processor in the read state, and successively convert them into protocol data of the AXI4 protocol via the connector, convert them into interface data composed of read enable and read address via the converter, convert them into predefined register data via the master-side register, convert them into serial data of the SPI protocol via the master-side SPI interface, convert them into predefined register data via the slave-side SPI interface, identify the read enable and read address via the slave-side register, and obtain the read data corresponding to the read address; transmit the read data back to the ARM processor in the reverse direction along the transmission path.

[0062] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0063] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for realizing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0064] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means realizes the functions in the process Figure 1One or more processes and / or boxes Figure 1 The functions specified in one box or more boxes.

[0065] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one process Figure 1 One or more processes and / or boxes Figure 1 The steps of the functions specified in one box or more boxes.

[0066] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A method for half-duplex inter-chip SPI access register, characterized in that: Used to perform read and write operations on a slave-side FPGA without an ARM processor through a master-side FPGA with an ARM processor, the master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register; the method includes a write state and / or a read state; In the write state, the write data and write address output by the ARM processor are obtained, and are converted into protocol data of the AXI4 protocol via the connector in sequence, and are converted into interface data consisting of write enable, write data and write address via the converter, and are converted into predefined register data via the master-side register, and are converted into serial data of the SPI protocol via the master-side SPI interface, and are converted into predefined register data via the slave-side SPI interface, and the write enable, write address and write data are identified via the slave-side register, and the write data is stored in the write address; In the read state, the read address output by the ARM processor is obtained, and is converted into protocol data of the AXI4 protocol via the connector, converted into interface data consisting of a read enable and a read address via the converter, converted into predefined register data via the master-side register, converted into serial data of the SPI protocol via the master-side SPI interface, converted into predefined register data via the slave-side SPI interface, and the read enable and the read address are identified via the slave-side register to obtain the read data corresponding to the read address; the read data is transmitted back to the ARM processor along the transmission path in reverse; Among them, in the write state, Define the SPI write enable register, including the SPI write enable address and its corresponding SPI write enable signal. The high and low levels of the SPI write enable signal indicate whether the write enable is valid or invalid. Define a read / write judgment register, including a read / write judgment address and its corresponding read / write judgment signal. The high and low levels of the read / write judgment signal represent the read state and the write state respectively. Define the SPI write address register, including the SPI write address and its corresponding SPI write address signal. The SPI write address signal is 16 bits, indicating that the maximum transmission bit width is 16 bits. Define the SPI write data register, including the address of the SPI write data and its corresponding SPI write data signal. The SPI write data signal is 32 bits, indicating that the maximum bit width of the data to be transmitted is 32 bits. According to the interface data consisting of write enable, write data and write address obtained by the master register, the read / write judgment signal is set to a low level, the write address is used as the SPI write address signal, the write data is used as the SPI write data signal, and the SPI write enable signal is set to a high level; In the write state, when the SPI write enable signal is high, the working logic of the master side SPI interface is triggered: Set the SPI chip select signal to a low level, and at the unit clock cycle position of 10 system clocks, demultiply the connected system clock by 10 times, set the SPI clock, and use the rising edge sampling of the SPI clock. Since it is necessary to transmit a 1-bit read / write judgment signal, a 16-bit SPI write address signal, and a 32-bit SPI write data signal to the slave-side FPGA, the transmitted SPI clock needs to last for 49 SPI unit clock cycles; At the position of the unit clock cycle of 5 system clocks of the SPI chip select signal, set the setup time and hold time of the collected data to 50%, and use the shift register method to send 49 bits of read and write judgment signal, SPI write address signal, and SPI write data signal in sequence through the SPI MOSI bus. When the last 1 bit of write data signal is sent, the chip select signal is set to a high level after the hold time is met, completing the operation of slave-side FPGA transmission of write address and write data.

2. The method for half-duplex inter-chip SPI access register according to claim 1, characterized in that: In the write state, based on the handshake rule of the AXI4 protocol: when the converter is ready, the converter sends a ready signal of the write address channel and the write data channel to the connector, indicating that the converter is ready, and the connector sends the write address and write data to the converter; When the connector is ready, the connector sends a ready signal of the write reply channel to the converter, indicating that the connector is ready. At this time, the converter sends the write reply data to the connector; According to the protocol data of the AXI4 protocol obtained by the converter, the write address and the write data are aligned at the same time and sent to the master side register, and the write enable is sent to the master side register at the same time.

3. The method for half-duplex inter-chip SPI access register according to claim 1, characterized in that: In the write state, the working logic of the slave SPI interface is: When the chip select signal is set to a low level, at the rising edge of the SPI clock, it is determined whether the received read / write determination signal is a low level. If so, the 16-bit SPI write address signal and the 32-bit SPI write data signal received through the SPI MOSI bus are cached and transmitted to the slave side register, and the write enable is output to the slave side register.

4. A half-duplex inter-chip SPI access register system, characterized in that: The system is configured to execute the steps of the method for half-duplex inter-chip SPI access to registers as described in any one of claims 1 to 3, and is used to perform read and write operations on a slave-side FPGA without an ARM processor through a master-side FPGA with an ARM processor, wherein the master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register; the system includes a write status execution module and / or a read status execution module; The write state execution module is used to obtain the write data and write address output by the ARM processor in the write state, convert them into protocol data of the AXI4 protocol via the connector in sequence, convert them into interface data consisting of write enable, write data and write address via the converter, convert them into predefined register data via the master side register, convert them into serial data of the SPI protocol via the master side SPI interface, convert them into predefined register data via the slave side SPI interface, identify the write enable, write address and write data via the slave side register, and store the write data in the write address; The read state execution module is used to obtain the read address output by the ARM processor in the read state, convert it into protocol data of the AXI4 protocol via the connector, convert it into interface data consisting of a read enable and a read address via the converter, convert it into predefined register data via the master side register, convert it into serial data of the SPI protocol via the master side SPI interface, convert it into predefined register data via the slave side SPI interface, identify the read enable and the read address via the slave side register, and obtain the read data corresponding to the read address; The read data is transmitted back to the ARM processor along the transmission path.

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