An ACIM architecture circuit based on SRAM capable of realizing core interconnection

Abstract

The present invention discloses an ACIM architecture circuit based on SRAM that can realize inter-core interconnection, which is composed of a plurality of computing core circuits that communicate with each other, and the computing core circuit includes a DPW-CIM macro circuit based on a dual-port parallel weight read (DPW) strategy and a near memory extensible communication module (NM-eCM) circuit. The DPW-CIM macro circuit reads and writes the weights in the storage unit in SRAM mode; and performs multi-bit multiplication and addition operations through a dual-port parallel weight read strategy in CIM mode. The NM-eCM circuit realizes an interconnection network between DPW-CIM macro circuits by means of a "priority" judgment mechanism and adjacent broadcast communications. This architecture circuit is designed to improve the work efficiency, data throughput and general scalability of the ACIM architecture used to accelerate neural network calculations, and is suitable for inference acceleration tasks of neural network models of different scales.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to an ACIM architecture circuit based on SRAM that can realize inter-core interconnection. Background Art

[0002] Deep neural networks have been widely used in IoT and AI tasks. However, the classic von Neumann architecture system cannot meet the requirements of low latency and low power consumption due to the "memory wall" problem. In contrast, the compute-in-memory (CIM) architecture allows data to be processed directly in memory, making it a more suitable choice for AI edge devices. Currently, the CIM architecture based on static random access memory (SRAM) is under active development due to its high energy efficiency, high integration and flexible scalability.

[0003] For SRAM-based CIM architectures, the analog-in-memory-computation-in-one (ACIM) architecture has attracted much attention due to its high energy efficiency. However, from the early ACIM macros that only supported binary weight networks (BWNs) to the recent solutions designed for multi-bit networks, ACIM macros have always had a trade-off between array scale, accuracy, and area overhead. AI tasks tend to adopt high-throughput CIM macros, but expanding the memory array to meet this demand brings two major challenges: 1) It is difficult to maintain a reasonable signal margin; 2) The area and power consumption overhead caused by the analog-to-digital / digital-to-analog converter (ADC / DAC) is increased. However, these works still do not solve the problem of redundant information inside the computing unit circuit, and the robustness of input transmission is also weak.

[0004] To address these challenges, a compact 6T SRAM cell design combined with local computing circuits was proposed to optimize the computational efficiency of the array. Other research directions such as time domain and charge domain also attempt to improve computational efficiency, aiming to reduce the negative impact of the above problems.

[0005] In addition, AI accelerator architectures usually require custom topology designs for different neural network models, which results in additional design overhead. Some work wants to achieve flexible configuration of weight mapping and computing scale by simply combining a 4x4 CIM core array with an on-chip network. However, current research still lacks a universal interconnect communication scheme designed from the ACIM macro itself to achieve configurability in various neural network scales while avoiding additional design overhead. Summary of the invention

[0006] In view of the above, the present invention proposes an ACIM architecture circuit based on SRAM that can realize inter-core interconnection for multi-bit neural network computing and its related computing and communication methods, aiming to provide an efficient multi-bit multiplication and addition operation and data transmission mechanism, which can realize fast and stable inter-core interconnection and data processing between multiple computing cores, and is suitable for inference acceleration tasks of neural network models of different scales.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] In a first aspect, the present invention discloses an analog computing-in-memory (ACIM) architecture circuit based on SRAM that can realize inter-core interconnection, wherein the ACIM architecture circuit includes a plurality of identical computing core circuits that communicate with each other: the computing core circuit includes a dual-port parallel weight readout (DPW) CIM macro circuit (DPW-CIM macro circuit) and a near memory expandable communication module circuit (NM-eCM circuit);

[0009] The CIM macro circuit is used to perform a multiplication-addition (MAC) operation of multi-bit data, and the MAC operation is based on a dual-port parallel weighted reading strategy; the CIM macro circuit includes a dual-mode control circuit, a hybrid drive circuit, a calculation array circuit and a partial MAC value-weighted merging block (partial MAC value-weighted merging block, pMACV-WMB) circuit, and can operate in SRAM mode and CIM mode; wherein the dual-mode control circuit generates an internal control signal to adjust the working mode of the hybrid drive circuit, the hybrid drive circuit controls the calculation array circuit in the corresponding working mode, the calculation array circuit performs weight reading and writing or MAC operation, and the partial MAC value-weighted merging block circuit reads and converts the result of the calculation array circuit in the CIM mode;

[0010] The NM-eCM circuit is used to realize the interconnection, data transmission and summary calculation between the CIM macro circuits of different computing core circuits according to the set priority rules. The data transmission adopts the event-driven adjacent broadcast communication method, and the data is summarized and calculated in a binary tree structure of pairwise addition.

[0011] A second aspect of the present invention provides a multi-bit multiplication and addition calculation method based on the ACIM architecture circuit, which comprises the following steps:

[0012] 1) A single CIM macro circuit stores up to 4 different groups of multi-bit weights at a time in SRAM mode; each group of multi-bit weights contains multiple multi-bit weights, which are stored sequentially along the dual-bit weight parallel MAC calculation row; when storing, each multi-bit weight in the group will be stored separately in different dual-bit weight parallel MAC calculation rows in the form of 2 bits;

[0013] 2) In CIM mode, a single CIM macro circuit performs bit-by-bit multiplication of multi-bit input data and weights stored in 2-bit segments in multiple dual-port parallel weight reading calculation unit circuits at the same time. The results are automatically added on the GBL / GBLB pairs to obtain multiple sets of analog signals representing partial MAC operation values;

[0014] 3) Convert the analog signal into a digital signal result representing the complete MAC operation value through a partial MAC value weighted merging module circuit;

[0015] 4) The results of multiple CIM macro circuits are transmitted and added through the near-memory scalable communication module circuit to finally obtain the global calculation result.

[0016] A third aspect of the present invention provides an inter-core interconnection communication method using the ACIM architecture circuit, which comprises the following steps:

[0017] 1) Assigning a priority to each near-memory scalable communication module circuit;

[0018] 2) The low-priority near-memory scalable communication module circuit selects the calculation result of its corresponding CIM macro circuit as the result of the calculation core circuit for encoding, and sends it to the adjacent high-priority calculation core circuit through the interconnection network;

[0019] 3) The high-priority near-memory scalable communication module circuit waits to receive the result of the low-priority computing core circuit, and then decodes and adds it; the summed result is used as the result of the computing core circuit, and is encoded and sent to the computing core circuit with a relatively higher priority;

[0020] 4) The parallel calculation results of calculation kernel circuits of different priorities continuously flow from the low-priority calculation kernel circuit to the high-priority calculation kernel circuit, and finally the global calculation results are summarized in the highest-priority calculation kernel circuit.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The strategy of dual-port parallel weighted reading is adopted for in-memory MAC operation, which significantly improves the MAC calculation efficiency of multi-bit data; through the design of NM-eCM circuit and priority-controlled inter-core interconnection communication mechanism, fast and reliable data transmission and communication between computing cores are realized, and the general scalability of the ACIM computing core itself is improved; the present invention has significant advantages in efficient computing and data transmission, and can adapt to the high-throughput parallel computing requirements in computing scenarios of different scales. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the ACIM calculation core composed of the DPW-CIM macro circuit and the NM-eCM circuit provided by the present invention;

[0024] Figure 2 It is a schematic diagram of the circuit architecture of the DPW-CIM macro circuit provided by the present invention;

[0025] Figure 3 It is a schematic diagram of the operation of the DPW-LMC unit provided by the present invention in the SRAM / CIM mode;

[0026] Figure 4 It is the weight mapping of the pMACV calculation framework with 4-bit input and 8-bit weight provided by the present invention;

[0027] Figure 5 is a schematic diagram of a SAR ADC circuit for reading analog calculation results provided by the present invention;

[0028] Figure 6 It is a schematic diagram of an interconnection network connected to 16 computing core circuits provided by the present invention. DETAILED DESCRIPTION

[0029] The present invention is further described and illustrated below in conjunction with specific embodiments. The embodiments are merely exemplary of the present disclosure and do not define the scope of limitation. The technical features of each embodiment in this application may be combined accordingly without conflicting with each other.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein are only for the purpose of describing the present invention and are not intended to limit the present invention.

[0031] The present invention provides an ACIM architecture circuit based on SRAM that can realize inter-core interconnection for multi-bit neural network calculations and its related calculation and communication methods, and the present invention is further explained below with reference to the accompanying drawings and specific examples.

[0032] The ACIM architecture circuit of the present invention includes a plurality of identical computing core circuits that communicate with each other. Figure 1 As shown, the computing core circuit (ACIM Core) of the present invention includes a CIM macro circuit (DPW-CIM Macro) based on dual-port parallel weight reading and a near memory extensible communication module (NM-eCM). Among them, the CIM macro circuit of the present invention is used to perform MAC operations on multi-bit data, and the MAC operation is based on a dual-port parallel weight reading strategy. When the CIM macro circuit works in SRAM mode, it is used to write external input weight data into the computing array circuit or read weight data from the computing array circuit; when working in CIM mode, it is used to directly perform MAC operations on weights and input data in the computing array circuit. The near memory extensible communication module circuit is used to realize the interconnection and data transmission between the CIM macro circuits of different computing core circuits according to the set priority rules, wherein the data transmission adopts a binary tree structure in the form of event-driven.

[0033] like Figure 1 As shown, in an optional implementation of the present invention, the CIM macro circuit includes a dual-mode control circuit, a hybrid drive circuit, a computing array circuit composed of 4 dual-bit weight parallel MAC computing rows (dual-bit weight MAC computing row, DWMCR) and a partial MAC value weighted merging module circuit (pMACV-WMB), and can operate in SRAM mode and CIM mode. The dual-mode control circuit generates an internal control signal to adjust the working mode of the hybrid drive circuit. The hybrid drive circuit controls the computing array circuit in the corresponding working mode. The computing array circuit performs weight reading and writing and MAC operations. The partial MAC value weighted merging module circuit reads and converts the results of the computing array circuit in CIM mode. In a specific embodiment of the present invention, the hybrid drive circuit includes a global input drive module, a hybrid row drive circuit (HR-Driver) and an SRAM read-write drive circuit, as shown Figure 2 shown.

[0034] Each DWMCR contains 32 dual-port parallel weight read calculation unit circuits (DPW-LMC) for channel calculation, which are driven by 8 groups of WL pair drivers (WL pair driver, WLPD) and 2 global calculation bit line pair drivers (global BL / BLB driver, GBLD / GBLBD) in the HR-Driver, and read the corresponding pMAC values ​​through the 2 SAR ADC circuits in the pMACV-WMB.

[0035] In an optional embodiment of the present invention, the hybrid driving circuit is used to sample and write / read weight data in SRAM mode; in CIM mode, it is used to perform bit-by-bit rail-to-rail driving on input data and activate corresponding word lines to perform multi-bit MAC operations.

[0036] In an optional embodiment of the present invention, the calculation array circuit includes 4 dual-bit weight parallel MAC calculation rows, and the externally input 8-bit weight is divided into 4 segments of 2-bit data in SRAM mode and written into the 4 calculation rows of the calculation array circuit respectively; each of the calculation rows is composed of 32 dual-port parallel weight reading calculation unit circuits; the calculation unit circuits independently complete multiplication, and the results of each calculation unit circuit are naturally added on the global calculation bit line pair GBL / GBLB.

[0037] Furthermore, in the above embodiment, the computing unit circuit is composed of 8 6T SRAM cells and a local multiplication circuit, the 8 6T SRAM cells can store up to 4 groups of 2-bit weights, and the local multiplication circuit reads one group of weights, performs a bit-by-bit multiplication operation with external input data in MAC mode, and the calculation result is output to GBL / GBLB in the form of simulated discharge current, and finally represents the MAC operation result in the form of voltage drop.

[0038] In an optional embodiment of the present invention, the partial MAC value weighted merging module circuit includes a SAR ADC and a shift adder tree, the SAR ADC is used to convert an analog signal into a digital signal, and obtain a final calculation result through the shift adder tree.

[0039] Furthermore, in the above embodiment, the SAR ADC is composed of a sampling capacitor switch array, a dynamic comparator and a SAR logic circuit; the sampling capacitor switch array collects analog signals by lower plate sampling, and the SAR ADC obtains comparison results through charge redistribution and dynamic comparator successive comparisons, and feeds the results back to the SAR logic circuit to achieve step-by-step digital quantization.

[0040] Furthermore, in the above embodiment, the sampling capacitor switch array includes a MOM capacitor array with a distributed structure and a group of switch circuits; the charge redistribution of the upper board nodes of the MOM capacitor array is achieved by switching the switch circuits.

[0041] like Figure 3As shown, the DPW-LMC consists of 8 compact regular 6T SRAM cells and a local multiplication circuit (LMC) that can read 2-bit weights at the same time for bit-by-bit multiplication calculations. In the DPW-LMC, every two 6T SRAM cells are grouped together to store 2-bit weights (where the high 1-bit weight is stored in the inverse code, for example, weight 10 is stored as 00). The LMC includes 14 transistors (N1-N14), which support reading or writing weights of storage cells in SRAM mode, and single-cycle multi-bit bit-by-bit multiplication calculations in CIM mode. In SRAM mode and CIM mode, the signal lines, storage cells and transistors in the LMC involved in the work in the DPW-LMC are as follows Figure 3 Shown in red.

[0042] In SRAM mode, the SRAM read / write driver circuit takes over the global input bit line, and a single group of WL pairs is selected (CWLx and SWLx are a group of WL pairs, which control two transmission transistors in the 6T SRAM cell respectively, such as Figure 3 As shown in the figure, x=0~7), the weight write signal WWL=1 is controlled to activate N1 and N2 in the LMC circuit, so that the global input bit line, the local calculation bit line pair (LBL / LBLB) and the 6T SRAM cell form a path. The circuit then reads and writes the weight through this path.

[0043] In CIM mode, WWL=0, then the HR-Driver precharges GBL / GBLB to VDD, and only selects the CWL signal (such as CWL0 and CWL1) of the corresponding combined 6T SRAM cell, so that the selected 2-bit weight (W i [s+1:s], in Figure 3, W i [1:0] as an example) is transmitted to LBL, and the MSB is transmitted to LBLB to control the connection of N3~N6 (W i [s] or W i [s+1] = "1") and turn off (W i [s] or W i [s+1] = "0"). At the same time, the 4-bit input (8-bit input is processed by two consecutive cycles IN i [7:4] and IN i [3:0]) will be divided into IN i [0]~IN i[3], the discharge branch transistors (N7 / N9, N8 / N10, N11 / N13, N12 / N14) are controlled separately through the global input bit lines. The input is not represented as multiple analog levels in the traditional way, but directly controls the transistors with rail-to-rail signals. The local multiplication circuit generates In this case, IN i [1:0]×W i [s+1] and IN i [1:0]×W i The result of [s] will be output to the GBL line in the form of ground discharge and automatically accumulated to obtain IN i [1:0]×W i [s+1:s].IN i [3:2]×W i [s+1:s] can be obtained on the GBLB line in the same way and weighted to the correct order of magnitude in the pMACV-WCB. By using multiple such computing units to release charge on the GBL pair to form a voltage drop, up to 32 channels of accumulated computing results can be achieved on the GBL / GBLB.

[0044] The ACIM architecture circuit of the present invention is mainly used for neural network acceleration operation, specifically, it performs MAC operation on the weights in the convolution kernel of the intermediate layer of the neural network and the data input into the convolution kernel. Specifically, in the present invention, Figure 4 As shown, the 8-bit weight (W m,n [7:0]) are divided and stored in the four DWMCRs in a two-bit allocation manner. The entire calculation array circuit can store the weights of four different convolution kernels (m=0,1,2,3) and the weights of 32 channels (n=0~31) in this way.

[0045] When performing MAC operation, the HR-Driver circuit stops precharging the GBL pair and turns on the sampling switch of the SAR ADC. Then the DPW-LMC on the 32 channels is activated to read the weight W m,i [7:0] and 32 input IN i [3:0] (i=0~31) perform bit-by-bit multiplication respectively, and obtain 8 BWMs composed of 32 bit-by-bit multiplication results on 4 groups of GBL / GBLB lines m,i [k] Added pMACV m [k] (k=0~7), as shown in the following formula, where is the charge change generated by a single DPW-LMC unit on the GBL line (taking GBL as an example), is the total capacitance on the GBL / GBLB line (including sampling capacitance and parasitic capacitance):

[0046]

[0047]

[0048] After the SAR ADC in the pMACV-WCB completes sampling of the four groups of GBL / GBLB, the eight pMACV results are converted into digital signals and passed through the shift adder tree to obtain the final output result MACV close to full precision, as shown in the following formula: For each The weighted shift factor of is:

[0049]

[0050] Figure 5 The architecture of the distributed capacitance SAR ADC adopted by the present invention is shown, including 10 weighted capacitors ( , , )、1 bridge capacitor( )、10 switches( , , ), comparator and successive approximation logic circuit.

[0051] During the sampling phase, the input voltage across the comparator and connected, low side switch ( , ) connect the common mode voltage , high-side switch ( , ) Connect the global calculation bit line voltage After sampling is completed, and disconnect, , Switch to reference voltage , Switch to , through capacitive coupling, , and The voltage difference between the two is equivalent to the digital value of MACV. is the voltage corresponding to the equivalent digital value of the GBL node being 256. Entering the conversion phase, Switch to , .at this time The equivalent digital value is 128-MACV. If MACV>128, then Switch to , Switch to , and output ; If MACV<128, then Remain unchanged, Switch to , and output And so on, until the conversion is completed.

[0052] On the other hand, the computing core circuit (also referred to as computing core) of the present invention introduces a "priority" data routing mechanism to control the path of data transmission and calculation in the interconnected network composed of computing core circuits. Each computing core circuit is assigned a "priority" (1 st Minimum, 4 th The highest priority level), computing core circuits with the same "priority" always perform the same type of operations in parallel. After the "priority" is configured at the beginning of the work, the NM-eCM circuit in the computing core circuit waits for the data of the sampled DPW-CIM macro circuit, and determines the data flow direction according to the assigned "priority": if the "priority" is relatively low, the data will be encapsulated into packets and begin to be broadcast between adjacent computing core circuits, waiting to be received by nearby computing core circuits with higher priorities; if the "priority" is high, the data will stay in front of the adder tree to wait for the data received from the computing core circuit with a lower priority to complete the addition. In this process, data always flows from low "priority" to high "priority" until it is aggregated into the computing core circuit with the highest "priority" to form the final result, such as Figure 6 shown.

[0053] In an optional embodiment of the present invention, the NM-eCM includes a data interface circuit, a routing control circuit, a communication codec circuit and an adder tree circuit; the output of the CIM macro circuit is sampled and held through the data interface circuit, the routing control circuit determines the transmission path of the sampled signal, the communication codec circuit encodes or decodes the data transmitted between the computing core circuits, and the adder tree circuit is used to add the data from different computing core circuits.

[0054] The entire ACIM architecture circuit based on SRAM that can realize core interconnection described in the present invention constitutes a computing kernel interconnection network based on NM-eCM, which adopts a binary tree structure of two-by-two aggregation to realize the topological connection of data flow. At the same time, the effective data communication between the NM-eCM adopts an event-driven form to reduce unnecessary overhead in the interconnection communication. In this process, the data flow in the interconnection network is transmitted using 16-bit packet data. The first three bits are used as the response bit (handshake communication response), the broadcast identification bit (identifying the occurrence of data broadcast) and the M / L identification bit (marking whether the packet data is transmitted in the high MSB data or the low LSB data), and the remaining 13 bits are allocated to the transmission data, which is transmitted through the two packets before and after. The computing kernel interconnection network designed in this paper can connect up to 16 computing kernels, so up to 16 convolution kernel operation results can be output in parallel at the same time, or a computing scale of up to 2048x32 can be achieved.

[0055] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those of ordinary skill in the art, and the general principles defined in this application may be applied to other embodiments without departing from the spirit and scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown in this application, but is consistent with the widest scope of the principles and novel features disclosed herein.

Claims

1. An ACIM architecture circuit based on SRAM capable of realizing inter-core interconnection, characterized in that: The ACIM architecture circuit includes a plurality of identical computing core circuits that communicate with each other: the computing core circuit includes a CIM macro circuit for dual-port parallel weight reading and a near memory scalable communication module circuit; The CIM macro circuit is used to perform MAC operations on multi-bit data, and the MAC operations are based on a dual-port parallel weighted reading strategy; the CIM macro circuit includes a dual-mode control circuit, a hybrid drive circuit, a calculation array circuit, and a partial MAC value weighted merging module circuit, and can operate in SRAM mode and CIM mode; wherein the dual-mode control circuit generates an internal control signal to adjust the operating mode of the hybrid drive circuit, the hybrid drive circuit controls the calculation array circuit in the corresponding operating mode, the calculation array circuit performs weighted reading and writing or MAC operations, and the partial MAC value weighted merging module circuit reads and converts the results of the calculation array circuit in the CIM mode; The near memory scalable communication module circuit is used to realize the interconnection, data transmission and summary calculation between CIM macro circuits of different computing core circuits according to the set priority rules. The data transmission adopts the adjacent broadcast communication mode in the form of event-driven, and the data is summarized and calculated in a binary tree structure with two-by-two additions. When the CIM macro circuit operates in the SRAM mode, it is used to write externally input weight data into the calculation array circuit or read weight data from the calculation array circuit; When working in CIM mode, it is used to directly perform MAC operations between weights and input data in the calculation array circuit; The hybrid drive circuit is used to sample and write / read weight data in SRAM mode; and is used to perform bit-by-bit rail-to-rail drive on input data and activate corresponding word lines to perform multi-bit MAC operations in CIM mode.

2. The ACIM architecture circuit according to claim 1, characterized in that: The calculation array circuit includes 4 dual-bit weight parallel MAC calculation rows. The externally input 8-bit weight is divided into 4 segments of 2-bit data in SRAM mode and written into the 4 calculation rows of the calculation array circuit respectively; each of the calculation rows is composed of 32 dual-port parallel weight reading calculation unit circuits; the calculation unit circuits independently complete multiplication, and the results of each calculation unit circuit are naturally added on the global calculation bit line pair GBL / GBLB.

3. The ACIM architecture circuit according to claim 2, characterized in that: The calculation unit circuit is composed of 8 6T SRAM units and a local multiplication circuit. The 8 6T SRAM units can store up to 4 groups of 2-bit weights, and the local multiplication circuit reads one group of weights. In MAC mode, a bit-by-bit multiplication operation is performed with external input data. The calculation result is output to GBL / GBLB in the form of simulated discharge current, and finally the MAC operation result is characterized in the form of voltage drop.

4. The ACIM architecture circuit according to claim 1, characterized in that: The partial MAC value weighted merging module circuit includes a SAR ADC and a shift adder tree. The SAR ADC is used to convert an analog signal into a digital signal, and obtain a final calculation result through the shift adder tree.

5. The ACIM architecture circuit according to claim 4, characterized in that: The SAR ADC consists of a sampling capacitor switch array, a dynamic comparator and a SAR logic circuit; the sampling capacitor switch array collects analog signals by lower plate sampling, and the SAR ADC obtains comparison results through charge redistribution and dynamic comparator successive comparisons, and feeds the results back to the SAR logic circuit to achieve step-by-step digital quantization.

6. The ACIM architecture circuit according to claim 5, characterized in that: The sampling capacitor switch array comprises a MOM capacitor array with a distributed structure and a group of switch circuits; the charge redistribution of the upper board nodes of the MOM capacitor array is achieved by switching the switch circuits.

7. A multi-bit multiplication and addition calculation method based on the ACIM architecture circuit according to any one of claims 1 to 6, characterized in that: The following steps are involved: 1) A single CIM macro circuit stores up to 4 different groups of multi-bit weights at a time in SRAM mode; each group of multi-bit weights contains multiple multi-bit weights, which are stored sequentially along the dual-bit weight parallel MAC calculation row; when storing, each multi-bit weight in the group will be stored separately in different dual-bit weight parallel MAC calculation rows in the form of 2 bits; 2) In CIM mode, a single CIM macro circuit performs bit-by-bit multiplication of multi-bit input data and weights stored in 2-bit segments in multiple dual-port parallel weight reading calculation unit circuits at the same time. The results are automatically added on the GBL / GBLB pairs to obtain multiple sets of analog signals representing partial MAC operation values; 3) Convert the analog signal into a digital signal result representing the complete MAC operation value through a partial MAC value weighted merging module circuit; 4) The results of multiple CIM macro circuits are transmitted and added through the near-memory scalable communication module circuit to finally obtain the global calculation result.

8. An inter-core interconnection communication method based on the ACIM architecture circuit according to any one of claims 1 to 6, characterized in that: The following steps are involved: 1) Assigning a priority to each near-memory scalable communication module circuit; 2) The low-priority near-memory scalable communication module circuit selects the calculation result of its corresponding CIM macro circuit as the result of the calculation core circuit for encoding, and sends it to the adjacent high-priority calculation core circuit through the interconnection network; 3) The high-priority near-memory scalable communication module circuit waits to receive the result of the low-priority computing core circuit, and then decodes and adds it; the summed result is used as the result of the computing core circuit, and is encoded and sent to the computing core circuit with a relatively higher priority; 4) The parallel calculation results of calculation kernel circuits of different priorities continuously flow from the low-priority calculation kernel circuit to the high-priority calculation kernel circuit, and finally the global calculation results are summarized in the highest-priority calculation kernel circuit.

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