Task processing method, apparatus, and terminal device

Abstract

Embodiments of the present application provide a task processing method, device and terminal equipment. The method comprises: obtaining a task processing request, the task processing request being used to request processing of at least one first task of chip simulation and emulation; obtaining historical task processing information, the historical task processing information comprising at least one second task; determining a target task set according to the at least one first task and the at least one second task, the number of tasks included in the target task set being less than or equal to the number of the at least one first task; and processing the target task set according to the task processing request and the historical task processing information to obtain a simulation and emulation result of the chip. The efficiency of chip simulation and emulation is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the chip technical field, and in particular, to a task processing method and device and terminal equipment. BACKGROUND

[0002] After each module of the chip is designed, the functions of each module of the chip can be simulated to determine whether each module in the chip can normally run.

[0003] In actual application, each module of the chip can execute at least one task corresponding to the current case through a pre-set stimulus and running environment in the simulation application, and obtain the execution result of each task. According to the execution result of each task, the simulation result is determined. Thus, whether each module in the chip can normally run and implement the corresponding function is determined. In the above process, when there is a same task in two cases, if the stimulus and the running environment set this time are different from the last case, the simulation this time needs to repeatedly execute the same task as the last case, and cannot directly execute the task different from the last case according to the execution result of the same task of the last case, which results in low efficiency of chip simulation. SUMMARY

[0004] Embodiments of the present application provide a task processing method, device and terminal equipment to solve the problem of low efficiency of chip simulation.

[0005] In a first aspect, embodiments of the present application provide a task processing method, comprising:

[0006] Obtaining a task processing request, the task processing request being used to request processing of at least one first task of chip simulation;

[0007] Obtaining historical task processing information, the historical task processing information comprising at least one second task;

[0008] According to the at least one first task and the at least one second task, determining a target task set, the number of tasks included in the target task set being less than or equal to the number of the at least one first task;

[0009] According to the task processing request and the historical task processing information, processing the target task set to obtain a simulation result of the chip.

[0010] In a possible implementation, according to the at least one first task and the at least one second task, determining a target task set comprises:

[0011] In the at least one second task, determining at least one candidate task, the candidate task matching the first task;

[0012] determine a first associated task corresponding to each first task;

[0013] determine a second associated task corresponding to each candidate task;

[0014] determine the target task set from the at least one first task according to the at least one first associated task, the at least one candidate task, and the second associated task corresponding to each candidate task.

[0015] In a possible implementation, the determining of the target task set from the at least one first task according to the at least one first associated task, the at least one candidate task, and the second associated task corresponding to each candidate task includes:

[0016] for any one candidate task, determine a first task corresponding to the candidate task;

[0017] if the second associated task corresponding to the candidate task matches the first associated task corresponding to the first task, determine the candidate task as an intermediate task, and obtain at least one intermediate task;

[0018] the target task set includes tasks in the at least one first task other than the at least one intermediate task.

[0019] In a possible implementation, the historical task information further includes an execution time of each second task and level information corresponding to each second task; and processing the target task set according to the task processing request and the historical task processing information to obtain the simulation result of the chip includes:

[0020] determining an execution time of each intermediate task according to the execution time of each second task;

[0021] determining a target intermediate task from the at least one intermediate task, the target intermediate task being a task with the latest execution time;

[0022] determining level information of the target intermediate task from the level information corresponding to each second task;

[0023] processing the target task set according to the task processing request and the level information of the target intermediate task to obtain the simulation result of the chip.

[0024] In a possible implementation, the task processing request further includes at least one running parameter; and processing the target task set according to the task processing request and the level information of the target intermediate task to obtain the simulation result of the chip includes:

[0025] determining an execution time of each target task in the target task set;

[0026] determining a target time and at least one non-target time according to the execution time of each target task;

[0027] processing a target signal corresponding to the target time according to the level information of the target intermediate task to obtain target level information;

[0028] processing the target task set at the at least one non-target time according to the at least one running parameter and the target level information to obtain a simulation result of the chip;

[0029] The target time is a preset time, and the non-target time is an execution time other than the target time in the at least one execution time.

[0030] In a possible implementation, processing a target signal corresponding to the target time according to the level information of the target intermediate task to obtain target level information includes:

[0031] determining an intermediate signal corresponding to the target intermediate task and a target value of the intermediate signal at a first time according to the level information of the target intermediate task, the first time being an execution completion time of the target intermediate task;

[0032] if the intermediate signal matches the target signal, updating a first value of the target signal according to the target value to obtain the target level information, the target level information including a target value corresponding to the target signal and the target time.

[0033] In a possible implementation, processing the target task set at the at least one non-target time according to the at least one running parameter and the target level information to obtain the processing result includes:

[0034] for any one non-target time, determining a target task corresponding to the non-target time;

[0035] determining whether the target task exists a historical task, the historical task being a target task executed at a last execution time of a current time;

[0036] if yes, determining an execution result of the historical task, and processing the target task according to the at least one running parameter and the at least one execution result to obtain a processing result corresponding to the target task;

[0037] If not, the target task is processed according to the at least one running parameter and the target level information, and a processing result corresponding to the target task is obtained.

[0038] The simulation result of the chip includes the processing result corresponding to each target task in the target task set.

[0039] In a second aspect, an embodiment of the present application provides a task processing device, and the device comprises:

[0040] A first obtaining module is configured to obtain a task processing request, and the task processing request is used to request processing of at least one first task of chip simulation.

[0041] A second obtaining module is configured to obtain historical task processing information, and the historical task processing information includes at least one second task.

[0042] A determining module is configured to determine a target task set according to the at least one first task and the at least one second task, and the target task set includes a number of tasks less than or equal to a number of the at least one first task.

[0043] A processing module is configured to process the target task set according to the task processing request and the historical task processing information, and obtain a simulation result of the chip.

[0044] In a possible implementation, the determining module is specifically configured to:

[0045] In the at least one second task, at least one candidate task is determined, and the candidate task matches the first task.

[0046] A first associated task corresponding to each first task is determined.

[0047] A second associated task corresponding to each candidate task is determined.

[0048] According to the at least one first associated task, the at least one candidate task, and the second associated task corresponding to each candidate task, the target task set is determined in the at least one first task.

[0049] In a possible implementation, the determining module is specifically configured to:

[0050] For any one candidate task, a first task corresponding to the candidate task is determined.

[0051] If the second associated task corresponding to the candidate task matches the first associated task corresponding to the first task, the candidate task is determined as an intermediate task, and at least one intermediate task is obtained.

[0052] The target task set includes tasks in the at least one first task other than the at least one intermediate task.

[0053] In a possible implementation, the processing module is specifically configured to:

[0054] According to the execution time of each second task, the execution time of each intermediate task is determined.

[0055] Among the at least one intermediate task, a target intermediate task is determined, the target intermediate task being a task with the latest execution time.

[0056] Among the level information corresponding to each second task, the level information of the target intermediate task is determined.

[0057] According to the task processing request and the level information of the target intermediate task, the target task set is processed to obtain the simulation result of the chip.

[0058] In a possible implementation, the processing module is specifically configured to:

[0059] The execution time of each target task in the target task set is determined.

[0060] According to the execution time of each target task, a target time and at least one non-target time are determined.

[0061] According to the level information of the target intermediate task, a target signal corresponding to the target time is processed to obtain target level information.

[0062] According to the at least one running parameter and the target level information, the target task set is processed at the at least one non-target time to obtain the simulation result of the chip.

[0063] The target time is a preset time, and the non-target time is an execution time other than the target time among the at least one execution time.

[0064] In a possible implementation, the processing module is specifically configured to:

[0065] According to the level information of the target intermediate task, an intermediate signal corresponding to the target intermediate task and a target value of the intermediate signal at a first time are determined, the first time being an execution completion time of the target intermediate task.

[0066] If the intermediate signal matches the target signal, a first value of the target signal is updated according to the target value to obtain target level information, the target level information including a target value corresponding to the target signal and the target time.

[0067] In a possible implementation, the processing module is specifically configured to:

[0068] For any non-target time, determine a target task corresponding to the non-target time;

[0069] Determine whether the target task exists a historical task, the historical task being a target task executed at a last execution time of a current time;

[0070] If yes, determine an execution result of the historical task, and process the target task according to the at least one running parameter and the at least one execution result to obtain a processing result corresponding to the target task;

[0071] If no, process the target task according to the at least one running parameter and the target level information to obtain a processing result corresponding to the target task;

[0072] Determine that the simulation result of the chip includes the processing result corresponding to each target task in the target task set.

[0073] In a third aspect, the present application provides a chip, the chip storing a computer program, the computer program being executed by the chip to implement the method in any one of the first aspect.

[0074] In a fourth aspect, the present application provides a chip module, the chip module storing a computer program, the computer program being executed by the chip module to implement the method in any one of the first aspect.

[0075] In a fifth aspect, the present application provides a terminal device, including:

[0076] at least one processor; and

[0077] a memory in communication connection with the at least one processor; wherein

[0078] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method in any one of the first aspect.

[0079] In a sixth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to perform the method in any one of the first aspect.

[0080] In a seventh aspect, an embodiment of the present application provides a computer program product comprising a computer program, which, when executed by a processor, implements the method in any one of the first aspect.

[0081] The task processing method, device and terminal equipment provided by the embodiments of the present application can determine a target task set from at least one first task to be processed according to historical task processing information when a chip is simulated, and process each task in the target task set to obtain a simulation result of the chip. Since the number of tasks included in the target task set is less than or equal to the number of the at least one first task, the chip can directly process at least one task that has not been processed in a historical period in the at least one first task according to the historical task processing information. This avoids the need to repeatedly perform the same task as in the last case in the current simulation, and the situation that a task different from the last case cannot be directly executed according to the execution result of the same task in the last case. The efficiency of chip simulation is improved. BRIEF DESCRIPTION OF DRAWINGS

[0082] Figure 1 A schematic diagram of an application scenario provided by the embodiments of the present application is shown.

[0083] Figure 2 A flowchart of a task processing method provided by the embodiments of the present application is shown.

[0084] Figure 3 A process diagram of obtaining a task processing request provided by the embodiments of the present application is shown.

[0085] Figure 4 A flowchart of another task processing method provided by the embodiments of the present application is shown.

[0086] Figure 5A A process diagram of determining target level information provided by the embodiments of the present application is shown.

[0087] Figure 5B A process diagram of another determination of target level information provided by the embodiments of the present application is shown.

[0088] Figure 6A A process diagram of task processing in a running environment provided by the embodiments of the present application is shown.

[0089] Figure 6B A process diagram of another task processing in a running environment provided by the embodiments of the present application is shown.

[0090] Figure 7 A process diagram of task processing provided by an embodiment of the present application is shown in FIG. 1.

[0091] Figure 8 A structure diagram of a task processing apparatus provided by an embodiment of the present application is shown in FIG. 2.

[0092] Figure 9 A structure diagram of a terminal device provided by an embodiment of the present application is shown in FIG. 3. DETAILED DESCRIPTION

[0093] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, unless otherwise indicated, like numbers in the attached drawings refer to the same or similar elements. The following exemplary embodiments are described in enough detail to enable those skilled in the art to practice the application. It should be understood, however, that the detailed description is not intended to limit the application to the particular embodiments described herein. The exemplary embodiments can be employed in any suitable system.

[0094] It should be noted that, in this document, the terms "comprise", "comprising", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements recited, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0095] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards, and provide corresponding operation portal for user to choose authorization or refusal.

[0096] For ease of understanding, below, the application is described in conjunction with Figure 1 The application scenarios to which the embodiments of the present application are applied are described.

[0097] Figure 1 A diagram of the application scenario provided by an embodiment of the present application is shown in FIG. 1. Please refer to Figure 1 , which includes a terminal device 101. The terminal device 101 can be a computer. The terminal device 101 is provided with an application program, which can simulate the functions of each module in the chip through the application program to determine whether each module in the chip can operate normally.

[0098] In actual application process, each module of the chip can execute at least one task corresponding to the case through pre-set excitation and running environment in simulation application program, and obtain the execution result of each task. According to the execution result of each task, the simulation result is determined. Whether each module in the chip can normally run and realize the corresponding function is determined. In the above process, when there are the same tasks in two cases, if the excitation and running environment set this time are different, the simulation needs to repeatedly execute the same task as the last case, and cannot directly execute the task different from the last case according to the execution result of the same task of the last case, which leads to low efficiency of chip simulation.

[0099] In the embodiment of the application, when the chip is simulated, the target task set can be determined from the at least one first task to be processed according to the historical task processing information, and each task in the target task set is processed to obtain the simulation result of the chip. Since the number of tasks included in the target task set is less than or equal to the number of the at least one first task, the chip can directly process at least one task that has not been processed in the historical period in the at least one first task according to the historical task processing information. The simulation this time avoids the situation that the same task as the last case needs to be repeatedly executed, and the task different from the last case cannot be directly executed according to the execution result of the same task of the last case. The efficiency of chip simulation is improved.

[0100] The method shown in the application will be described below through specific embodiments. It should be noted that the following embodiments can exist independently or be combined with each other. For the same or similar content, it will not be repeated in different embodiments.

[0101] Figure 2 A flowchart of a task processing method provided in the embodiment of the application is shown. Please refer to Figure 2 The method can include:

[0102] S201, obtaining a task processing request.

[0103] The execution subject of the embodiment of the application can be a terminal device, a chip, a chip module or a task processing device provided in the terminal device, etc. The task processing device can be realized by software or by the combination of software and hardware. The terminal device can be a computer.

[0104] The task processing request is used to request to process at least one first task of chip simulation.

[0105] The user can determine the chip to be tested and the test case corresponding to each module in the chip in an application of the terminal device. The terminal device determines the test case and acquires at least one first task corresponding to the test case in response to the input selection operation of the user.

[0106] In the following, the process of acquiring the task processing request is described in combination with Figure 3 The process of acquiring the task processing request provided by the embodiments of the present application is shown in the following. Please refer to Figure 3 Figure 3 The interface 301 to the interface 302 can be a page provided by the terminal device. Please refer to the interface 301. The user clicks the icon corresponding to the simulation application in the terminal device, and the terminal device displays the operation page of the simulation application in response to the click operation of the user. The operation page includes a drop-down selection menu corresponding to the chip, a drop-down selection menu corresponding to at least one test case, and a text input box.

[0107] Please refer to the interface 302. The user determines the chip to be tested as chip A in the drop-down selection menu corresponding to the chip, determines the test case as case A2 in the drop-down selection menu corresponding to the test case 1, and clicks the confirm icon. The terminal device acquires at least one first task including task 1, task 2, task 3, task 6, and task 7 corresponding to the test case A2 in response to the input selection operation of the user. And determines that the task processing request includes at least one first task. The task processing request is used to request to process the tasks 1, 2, 3, 6, and 7 of the chip A simulation.

[0108] S202, acquire historical task processing information.

[0109] The historical task processing information includes at least one second task. The historical task processing information can also include the execution time of each second task, the level information corresponding to each second task, and the execution result of each second task.

[0110] The terminal device can generate the historical task processing information after the task execution is completed. And store the historical task processing information to the preset storage space of the terminal device. In this way, the historical task processing information can be acquired in the preset storage space when the chip simulation is performed next time.

[0111] S203, determine a target task set according to at least one first task and at least one second task.

[0112] The number of tasks included in the target task set is less than or equal to the number of at least one first task.

[0113] ​The target task set can be determined according to the at least one first task and the at least one second task in the following manner: in the at least one second task, at least one candidate task is determined, the candidate task matches the first task; a first associated task corresponding to each first task is determined; a second associated task corresponding to each candidate task is determined; and the target task set is determined in the at least one first task according to the at least one first associated task, the at least one candidate task, and the second associated task corresponding to each candidate task.

[0114] The tasks in the target task set are tasks that have not been executed in the historical period.

[0115] For example, the historical task processing information can be as shown in Table 1:

[0116] Table 1

[0117]

[0118]

[0119] According to the example, the at least one first task includes task 1, task 2, task 3, task 6, and task 7. In the at least one second task shown in Table 1, task 1, task 2, and task 3 are determined to match the first task, and the at least one candidate task includes task 1, task 2, and task 3. Since the second associated task corresponding to each candidate task matches the first associated task corresponding to the first task, task 1, task 2, and task 3 are not included in the target task set. The target task set includes task 6 and task 7.

[0120] S204, processing the target task set according to the task processing request and the historical task processing information to obtain a simulation result of the chip.

[0121] Before performing the simulation, the running environment of the simulation can be determined. The target task set is processed by a simulation application under the running environment to obtain a simulation result of the chip.

[0122] The running environment can be a running environment set by a user in real time, or a running environment used in the historical period. The present application does not make any limitation.

[0123] For example, according to the example, the target task set includes task 6 and task 7. When processing the target task set, at least one running parameter corresponding to the running environment is determined. The execution results of task 1 to task 3 are determined according to the historical task information. The target task set is processed according to the at least one running parameter and the execution results of task 1 to task 3 to obtain a simulation result of the chip.

[0124] The task processing method provided in the embodiments of the present application comprises: obtaining a task processing request; obtaining historical task processing information; determining a target task set according to at least one first task and at least one second task; and processing the target task set according to the task processing request and the historical task processing information to obtain a simulation result of a chip. Since the number of tasks included in the target task set is less than or equal to the number of the at least one first task, the chip can directly process at least one task that has not been processed in a historical period in the at least one first task according to the historical task processing information. This avoids the need to repeatedly perform the same task as in a previous case in the current simulation, and the situation that a task different from the previous case cannot be directly executed according to the execution result of the same task in the previous case. The efficiency of chip simulation is improved.

[0125] On the basis of any one of the above embodiments, the following will be described in combination with Figure 4 The detailed process of task processing is described.

[0126] Figure 4 The flowchart of another task processing method provided in the embodiments of the present application is shown in FIG. 4. As shown in FIG. 4, the method comprises the following steps. Figure 4 The method comprises the following steps.

[0127] S401, obtaining a task processing request.

[0128] It should be noted that the execution process of S401 can refer to S201, which will not be described here again.

[0129] S402, obtaining historical task processing information.

[0130] For example, the historical task processing information can be as shown in Table 2.

[0131] Table 2

[0132] Second task Second associated task Execution time Level information Task B1 Task B2 Time B1 Signal B;0 Task B2 Task B1, Task B3 Time B2 Signal B;1 Task B3 Task B2, Task B4 Time B3 Signal B;1 Task B4 Task B3, Task B5 Time B4 Signal B;1 Task B5 Task B4 Time B5 Signal B;0

[0133] The level information is used to indicate the level value of the signal in the execution process of the task. The level information comprises the signal and the level value corresponding to the signal.

[0134] S403, determining at least one candidate task in the at least one second task.

[0135] The candidate task matches the first task.

[0136] For example, it is assumed that the task processing request is used to request to process the tasks B1, B2, B3, B6 and B7 of the chip B simulation. According to the historical task processing information shown in Table 2, it can be determined that the at least one candidate task in the at least one second task shown in Table 2 comprises the tasks B1, B2 and B3.

[0137] S404, determine a first associated task corresponding to each first task.

[0138] The associated task can be determined according to an execution order. The associated task can be a task corresponding to a previous execution time of a current execution time of the task, and / or a task corresponding to a next execution time of the current execution time of the task.

[0139] For example, according to the execution time in Table 2, the execution order can be determined as task B1-task B5. For task B2, it is determined that the second associated task of task B2 includes task B1 and task B3. According to the execution order, it can be determined that task B1 is a task corresponding to a previous execution time of a current execution time of task B2. Task B3 is a task corresponding to a next execution time of the current execution time of task B2.

[0140] The execution order of the at least one first task can be determined according to a test case corresponding to the at least one first task.

[0141] For example, according to the example described above, it is determined that the at least one first task includes task B1, task B2, task B3, task B6, and task B7. According to the test case corresponding to the at least one first task, the execution order of the at least one first task is determined as task B1, task B2, task B3, task B6, and task B7. According to the execution order, the first associated task corresponding to each first task can be determined as shown in Table 3:

[0142] Table 3

[0143] First task First associated task Task B1 Task B2 Task B2 Task B1, Task B3 Task B3 Task B2, Task B6 Task B6 Task B3, Task B7 Task B7 Task B6

[0144] S405, determine a second associated task corresponding to each candidate task.

[0145] For example, according to Table 2 described above, the second associated task corresponding to each candidate task can be determined as shown in Table 4:

[0146] Table 4

[0147] Pending task Second associated task Task B1 Task B2 Task B2 Task B1, Task B3 Task B3 Task B2, Task B4

[0148] S406, determine a target task set in the at least one first task according to the at least one first associated task, the at least one candidate task, and the second associated task corresponding to each candidate task.

[0149] The target task set can be determined in the at least one first task according to the at least one first associated task, the at least one candidate task, and the second associated task corresponding to each candidate task in the following manner: for any candidate task, a first task corresponding to the candidate task is determined; if the second associated task corresponding to the candidate task matches the first associated task corresponding to the first task, the candidate task is determined as an intermediate task, and at least one intermediate task is obtained; and the target task set includes tasks in the at least one first task other than the at least one intermediate task.

[0150] If, in the first associated task corresponding to the first task, the first associated task corresponding to the first task is the same as the second associated task corresponding to the candidate task, it can be determined that the second associated task corresponding to the candidate task matches the first associated task corresponding to the first task.

[0151] For example, according to the example shown in the foregoing, it is determined that the at least one candidate task includes task B1, task B2, and task B3. For task B1, it is determined that the first associated task of task B1 is task B2, and the second associated task is task B2. Therefore, it can be determined that the second associated task corresponding to the candidate task matches the first associated task corresponding to the first task, and it can be determined that task B1 is an intermediate task.

[0152] For task B2, it is determined that the first associated task of task B2 is task B1 and task B3, and the second associated task is task B1 and task B3. Therefore, it can be determined that the second associated task corresponding to the candidate task matches the first associated task corresponding to the first task, and it can be determined that task B2 is an intermediate task.

[0153] For task B3, it is determined that the first associated task of task B3 is task B2 and task B4, and the second associated task of task B3 is task B2 and task B6. Since, in the first associated task corresponding to the first task, the first associated task corresponding to the first task is the same as the second associated task corresponding to the candidate task, it can be determined that the second associated task corresponding to the candidate task matches the first associated task corresponding to the first task. Therefore, it can be determined that task B3 is an intermediate task.

[0154] In summary, it can be determined that the at least one intermediate task includes task B1, task B2, and task B3. In the at least one first task, the first task other than the at least one intermediate task includes task B6 and task B7. Therefore, it can be determined that the target task set is task B6 and task B7.

[0155] S407, according to the execution time of each second task, determining the execution time of each intermediate task.

[0156] For example, according to the historical task processing information shown in Table 2, the execution time of each intermediate task can be determined as shown in Table 5:

[0157] Table 5

[0158] Intermediate task Execution time Task B1 Time B1 Task B2 Time B2 Task B3 Time B3

[0159] S408, among the at least one intermediate task, determining a target intermediate task.

[0160] The target intermediate task is the task with the latest execution time.

[0161] For example, according to the example shown in Table 5, it is determined that the execution time B3 is the latest, and the target intermediate task is task B3.

[0162] S409, in the level information corresponding to each second task, determining the level information of the target intermediate task.

[0163] For example, according to the example shown above, it is determined that the target intermediate task is task B3. According to Table 2, it is determined that the level information of the target intermediate task includes signal B; 1.

[0164] S410, according to the task processing request and the level information of the target intermediate task, processing the target task set to obtain the simulation result of the chip.

[0165] The task processing request further includes at least one running parameter.

[0166] The target task set can be processed according to the task processing request and the level information of the target intermediate task to obtain the simulation result of the chip by the following method: determining the execution time of each target task in the target task set; determining the target time and at least one non-target time according to the execution time of each target task; processing the target signal corresponding to the target time according to the level information of the target intermediate task to obtain the target level information; processing the target task set at the at least one non-target time according to the at least one running parameter and the target level information to obtain the simulation result of the chip. The target time is a preset time, and the non-target time is an execution time other than the target time in the at least one execution time.

[0167] The preset time can be the start time of processing the target task set, or any time set by the user during the simulation process. The present application does not make any limitation. The preset time can be set in advance and stored in the preset storage space of the terminal device.

[0168] The target signal can be processed according to the level information of the target intermediate task to obtain target level information in the following manner: according to the level information of the target intermediate task, a target intermediate signal corresponding to the target intermediate task and a target value corresponding to the target intermediate signal at a first time are determined, the first time being a time when the target intermediate task is executed; if the target intermediate signal matches the target signal, a first value of the target signal is updated according to the target value to obtain the target level information, the target level information including a target value corresponding to the target signal and the target time.

[0169] The state value of the signal at the execution time can be obtained to determine the level information. For example, the state value can be a register value, an input signal value of a model, an output signal value of a model, etc.

[0170] For example, according to the example shown in the above, it is determined that the level information of the target intermediate task includes signal B; 1. It can be determined that the signal corresponding to the target intermediate task is signal B, and the level value of signal B corresponding to the target intermediate task in the execution process is 1. Assuming that the execution completion time of the target intermediate task is time B31, it can be determined that the first time is time B31. Therefore, according to the level information of the target intermediate task, it can be determined that the target intermediate signal corresponding to the target intermediate task is signal B, and the target value of signal B corresponding to time B31 is 1.

[0171] In the following, the process of determining the target level information will be described in combination with Figure 5A - Figure 5B with the process of determining the target level information. Figure 5A A process diagram for determining the target level information provided by an embodiment of the present application is shown in FIG. 5. Please refer to FIG. 5, which includes an intermediate signal 501 and a target signal 502. It is assumed that the intermediate signal 501 is a signal A corresponding to task A3, and the intermediate signal 501 can be a register signal. The target signal 502 is a signal generated when a target task set is processed. It is determined that the completion time of task B3 is time A3, and the first time can be determined as time A3. According to the level information of the intermediate signal 501, it is determined that the level value of the intermediate signal 501 corresponding to time A3 is 0, and the target value 0 can be determined. The terminal device determines that the intermediate signal 501 is a register signal and the target signal 502 is a register signal, and it is determined that the intermediate signal 501 matches the target signal 502. Therefore, the terminal device updates the level value corresponding to the target time to the target value 0. That is, the level value of the target signal 501 at the target time is 0, and the target level information includes the target value 0 corresponding to the target signal 501 and the target time.

[0172] Figure 5AAnother process for determining target level information is provided in the embodiments of the present application. Please refer to FIG. 5, which includes an intermediate signal 503 and a target signal 504. It is assumed that the intermediate signal 503 is a signal A corresponding to task A4, and the intermediate signal 503 can be a register signal. The target signal 504 is a signal generated when a target task set is processed. The completion time of task A4 is time A4, and the first time can be determined as time A4. According to the level information of the intermediate signal 503, it is determined that the level value of the intermediate signal 503 corresponding to time A4 is 1, and the target value 1 can be determined. The terminal device determines that the intermediate signal 503 is a register signal and the target signal 504 is a register signal, and it is determined that the intermediate signal 503 and the target signal 504 match. Therefore, the terminal device updates the level value corresponding to the target time to the target value 1. That is, the level value of the target signal 503 at the target time is 1, and the target level information includes the target value 1 corresponding to the target signal 504 and the target time.

[0173] Optionally, the target signal and the target intermediate task can be determined at any time, and the target signal can be processed according to the level information of the target intermediate task to obtain the target level information. For example, according to the example shown in the above example, it can be determined that the target task set includes task B3, task B6 and task B7. At this time, the target intermediate task can be task B2. The level value of the signal corresponding to task B2 at time B2 can be obtained, and the target time is determined as the start time of executing task B3. If the target signal matches the signal corresponding to task B2, the level value of the target signal corresponding to the target time can be updated to the level value of the signal corresponding to task B2 at time B2. Subsequently, the target task set is processed at at least one non-target time according to at least one running parameter and the target level information to obtain the simulation result of the chip.

[0174] The target level information is obtained by updating the level value of the target signal, and the target level information can be determined when the target signal matches the intermediate signal. It does not need the same running environment, and can be performed between different running environment test cases, thereby improving the efficiency of simulation. And the level value of the updated source signal remains unchanged, and the intermediate logic affected by the source signal returns to the level value at the target time, which does not affect the verification quality. The test environment can be freely stimulated, the simulation acceleration effect depends on the corresponding reduced configuration excitation action when the target value of the intermediate signal is updated to the target value, and the user has a large customization space.

[0175] The simulation result of the chip can be obtained by processing the target task set according to the at least one running parameter and the target level information at the at least one non-target moment. For any non-target moment, a target task corresponding to the non-target moment is determined. It is judged whether the target task has a historical task, the historical task being a target task executed at a previous execution moment of the current moment. If yes, an execution result of the historical task is determined, and the target task is processed according to the at least one running parameter and the at least one execution result to obtain a processing result corresponding to the target task. If no, the target task is processed according to the at least one running parameter and the target level information to obtain a processing result corresponding to the target task. The simulation result of the chip includes the processing result corresponding to each target task in the target task set.

[0176] For example, according to the example shown in the above, the target task set is determined to be task B6 and task B7. For task B6 corresponding to execution moment B6, it is determined that task B6 does not have a historical task, and the target level information is determined to include a target signal and a target value corresponding to the target moment. Task B6 is processed according to the at least one running parameter and the target level information, and the processing result corresponding to the target task is result B6. For task B7 corresponding to execution moment B7, it is determined that the target task executed at the previous execution moment of task B7 is task B6. Therefore, it is determined that task B7 has a historical task, which is task B6. It is determined that the execution result of task B6 is result B6. Task B7 is processed according to the at least one running parameter and result B6, and the processing result corresponding to the target task is result B7. The simulation result of the chip includes result B6 and result B7.

[0177] The task processing method provided by the embodiments of the present application can be applied to test cases in the same running environment and different running environments. Next, the process of task processing will be described in combination with Figure 6A - Figure 6B

[0178] Figure 6A A process diagram of task processing in a running environment is provided in the embodiments of the present application. Please refer to Figure 6A , which includes case 1 and case 2. Case 1 includes tasks 1-5, and case 2 includes tasks 1-3, task 6 and task 7. The running environment of case 1 and the running environment of case 2 are both running environment 1. When the running environment of case 1 is the same as the running environment of case 2, and the simulation of case 2 is performed after the simulation of case 1 is completed, the method provided by the embodiments of the present application can be used to directly execute tasks 6 and 7 to obtain the simulation result of the chip without repeatedly executing tasks 1-3.

[0179] Figure 6B ​Another process schematic diagram of task processing in another operation environment provided by the embodiment of the present application is provided. Please refer to Figure 6B , which includes case 1 and case 2. Case 1 includes task 1 to task 5, and case 2 includes task 1 to task 3, task 6 and task 7. The operation environment of case 1 is operation environment 1, and the operation environment of case 2 is operation environment 2. When the operation environment of case 1 is different from the operation environment of case 2, and the simulation of case 2 is performed after the simulation of case 1 is completed, the method provided by the embodiment of the present application can be used to directly perform task 6 and task 7 without repeatedly performing task 1 to task 3, so as to obtain the simulation result of the chip.

[0180] After the simulation result of the chip is obtained, the simulation result of the chip is stored according to a preset storage path. The simulation result of the chip can also be displayed on a page of a terminal device or sent to a preset device.

[0181] It should be noted that the task processing method provided by the embodiment of the present application can be implemented by a script.

[0182] The task processing method provided by the embodiment of the present application obtains a task processing request. Historical task processing information is obtained. A target task set is determined according to at least one first task and at least one second task. The execution time of each intermediate task is determined according to the execution time of each second task. A target intermediate task is determined in the at least one intermediate task. The level information of the target intermediate task is determined in the level information corresponding to each second task. The target task set is processed according to the task processing request and the level information of the target intermediate task, so as to obtain the simulation result of the chip. In the above process, since the number of tasks included in the target task set is less than or equal to the number of the at least one first task, the chip can directly process at least one task that is not processed in the historical period in the at least one first task according to the historical task processing information. The present simulation avoids the need to repeatedly perform the same task as in the last case, and the situation that the task different from the last case cannot be directly executed according to the execution result of the same task in the last case. The efficiency of chip simulation is improved.

[0183] On the basis of any one of the above embodiments, the following will be described in combination with Figure 7 to illustrate the process of task processing.

[0184] Figure 7 The process schematic diagram of task processing provided by the embodiment of the present application is provided. Please refer to Figure 7, including a terminal device 701. The terminal device 701 can be a computer, and the terminal device 701 is provided with an application program. The chip can be simulated by the application program of the terminal device 701 to obtain a simulation result of the chip. The user can determine, in the application program of the terminal device 701, that the chip to be tested is a chip C, and determine that the test case corresponding to each module in the chip C is a case C. The application program of the terminal device 701 selects the operation of the user in response to the input to obtain at least one first task corresponding to the case C, including task C1, task C2 and task C4. And generate a task processing request, the task processing request is used to request to process the task C1, the task C2 and the task C4 of the chip C simulation.

[0185] The application program of the terminal device 701 obtains the historical task processing information in the preset storage space, which can be specifically shown in Table 6:

[0186] Table 6

[0187] Second task Second associated task Execution time Level information Task C1 Task C2 Time C1 Signal C;0 Task C2 Task C1, Task C3 Time C2 Signal C;1

[0188] The application program of the terminal device 701 determines that at least one candidate task includes task C1 and task C2 in at least one second task shown in Table 6. The application program of the terminal device 701 determines, according to the historical task processing information shown in Table 6, that the target task set includes task C4 in task C1, task C2 and task C4. The application program of the terminal device 701 determines, according to the historical task processing information shown in Table 6, that the target intermediate task is task C2, and the level information corresponding to task C2 includes signal C;1. The application program of the terminal device 701 determines that the signal corresponding to task C2 is signal C, and the level value corresponding to signal C in the execution process of task C2 is 1. The application program of the terminal device 701 determines that the execution completion time of task C2 is time C21, so the first time can be determined as time C21. Therefore, according to the level information of task C2, it can be determined that the intermediate signal corresponding to task C2 is signal C, and the target value of signal C corresponding to time C21 is 1.

[0189] The application program of the terminal device 701 determines a target time point as a start time point of executing task C4, and determines a non-target time point as a time point of executing task C4. The application program of the terminal device 701 determines that a target signal corresponding to the target time point is signal C, and can determine that the intermediate signal and the target signal match. At the target time point, the level value corresponding to signal C is updated to target value 1, and it is determined that the target level information includes the level value 1 corresponding to signal C and time point C4. The application program of the terminal device 701 acquires at least one running parameter corresponding to case C. The application program of the terminal device 701 determines that task C4 does not exist a historical task, and processes task C4 according to the at least one running parameter and the target level information, to obtain a processing result corresponding to the target task as result C4. The application program of the terminal device 701 determines that the simulation result of chip C includes result C4.

[0190] The task processing process provided by the embodiment of the application includes the following steps: a task processing request is acquired; historical task processing information is acquired; a target task set is determined according to at least one first task and at least one second task; an execution time point of each intermediate task is determined according to an execution time point of each second task; a target intermediate task is determined in the at least one intermediate task; level information of the target intermediate task is determined in level information corresponding to each second task; a chip simulation result is obtained by processing the target task set according to the task processing request and the level information of the target intermediate task. In the above process, the number of tasks included in the target task set is less than or equal to the number of the at least one first task, and the chip can directly process at least one task that is not processed in a historical period in the at least one first task according to the historical task processing information. The efficiency of chip simulation is improved.

[0191] Figure 8 The task processing device provided by the embodiment of the application is shown in a structural schematic diagram. Please refer to Figure 8 The task processing device 10 can include:

[0192] The first acquisition module 11 is configured to acquire a task processing request, and the task processing request is used to request to process at least one first task of chip simulation;

[0193] The second acquisition module 12 is configured to acquire historical task processing information, and the historical task processing information includes at least one second task;

[0194] The determination module 13 is configured to determine a target task set according to the at least one first task and the at least one second task, and the number of tasks included in the target task set is less than or equal to the number of the at least one first task.

[0195] The processing module 14 is configured to process the target task set according to the task processing request and the historical task processing information, and obtain the simulation result of the chip.

[0196] In a possible implementation, the determining module 13 is specifically configured to:

[0197] In the at least one second task, at least one candidate task is determined, and the candidate task matches the first task.

[0198] A first associated task corresponding to each first task is determined.

[0199] A second associated task corresponding to each candidate task is determined.

[0200] According to the at least one first associated task, the at least one candidate task, and the second associated task corresponding to each candidate task, the target task set is determined in the at least one first task.

[0201] In a possible implementation, the determining module 13 is specifically configured to:

[0202] For any candidate task, a first task corresponding to the candidate task is determined.

[0203] If the second associated task corresponding to the candidate task matches the first associated task corresponding to the first task, the candidate task is determined as an intermediate task, and at least one intermediate task is obtained.

[0204] The target task set includes tasks in the at least one first task, except the at least one intermediate task.

[0205] In a possible implementation, the processing module 14 is specifically configured to:

[0206] According to an execution time of each second task, an execution time of each intermediate task is determined.

[0207] In the at least one intermediate task, a target intermediate task is determined, and the target intermediate task is a task with the latest execution time.

[0208] In the level information corresponding to each second task, level information of the target intermediate task is determined.

[0209] According to the task processing request and the level information of the target intermediate task, the target task set is processed, and the simulation result of the chip is obtained.

[0210] In a possible implementation, the processing module 14 is specifically configured to:

[0211] determine an execution time of each target task in the target task set;

[0212] determine a target time and at least one non-target time according to the execution time of each target task;

[0213] process the target signal corresponding to the target time according to the level information of the target intermediate task to obtain target level information;

[0214] process the target task set at the at least one non-target time according to the at least one running parameter and the target level information to obtain the simulation result of the chip;

[0215] The target time is a preset time, and the non-target time is an execution time other than the target time in the at least one execution time.

[0216] In a possible implementation, the processing module 14 is specifically configured to:

[0217] determine an intermediate signal corresponding to the target intermediate task and a target value of the intermediate signal at a first time according to the level information of the target intermediate task, the first time being an execution completion time of the target intermediate task;

[0218] if the intermediate signal matches the target signal, update a first value of the target signal according to the target value to obtain the target level information, the target level information including a target value corresponding to the target signal and the target time.

[0219] In a possible implementation, the processing module 14 is specifically configured to:

[0220] for any one non-target time, determine a target task corresponding to the non-target time;

[0221] determine whether the target task exists a historical task, the historical task being a target task executed at a last execution time of a current time;

[0222] if yes, determine an execution result of the historical task, and process the target task according to the at least one running parameter and the at least one execution result to obtain a processing result corresponding to the target task;

[0223] if no, process the target task according to the at least one running parameter and the target level information to obtain a processing result corresponding to the target task;

[0224] The simulation result of the chip determines a processing result corresponding to each target task in the target task set.

[0225] The task processing apparatus provided by the embodiments of the present application can execute the technical solutions shown in the method embodiments, and the implementation principles and beneficial effects are similar, which will not be repeated here.

[0226] Figure 9 A structural schematic diagram of a terminal device provided by the embodiments of the present application is provided. Referring to FIG. 20, the terminal device 20 can include a memory 21 and a processor 22. Exemplarily, the memory 21 and the processor 22 are connected with each other through a bus 23. Figure 9

[0227] The memory 21 is configured to store program instructions.

[0228] The processor 22 is configured to execute the program instructions stored in the memory, so as to enable the terminal device 20 to execute the method shown in the method embodiments.

[0229] The terminal device provided by the embodiments of the present application can execute the technical solutions shown in the method embodiments, and the implementation principles and beneficial effects are similar, which will not be repeated here.

[0230] The embodiments of the present application further provide a computer readable storage medium, which stores computer execution instructions. When the computer execution instructions are executed by a processor, the computer execution instructions are used to implement the method.

[0231] The embodiments of the present application further provide a computer program product, which includes a computer program. When the computer program is executed by a processor, the computer program can implement the method.

[0232] All or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware. The foregoing program can be stored in a readable memory. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the foregoing memory (storage medium) includes a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk, a solid state disk, a magnetic tape, a floppy disk, an optical disc and any combination thereof.

[0233] ​The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the computer or other programmable data processing apparatus generate a device that implements the functions specified in the flowcharts and / or block diagrams. Figure One one or more flows and / or blocks. Figure One one or more flows and / or blocks.

[0234] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction devices that implement the functions specified in the flowcharts and / or block diagrams. Figure One one or more flows and / or blocks. Figure One one or more flows and / or blocks.

[0235] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide a process for implementing the functions specified in the flowcharts and / or block diagrams. Figure One one or more flows and / or blocks. Figure One one or more flows and / or blocks.

[0236] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

[0237] In the present application, the term "comprising" and its variants can refer to non-limiting inclusion; the term "or" and its variants can refer to "and / or". In the present application, the terms "first", "second", etc. are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. In the present application, "multiple" refers to two or more. "And / or", which describes the relationship between the associated objects, means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the front and rear associated objects.

Claims

1. A task processing method, characterized in that, include: Obtain a task processing request, wherein the task processing request is used to request processing at least one first task of chip simulation. Obtain historical task processing information, wherein the historical task processing information includes at least one second task; Based on the at least one first task and the at least one second task, a target task set is determined, wherein the number of tasks included in the target task set is less than or equal to the number of the at least one first task; Based on the task processing request and the historical task processing information, the target task set is processed to obtain the simulation results of the chip. The historical task processing information also includes the execution time of each second task and the level information corresponding to each second task. Based on the task processing request and the historical task processing information, the target task set is processed to obtain the simulation results of the chip, including: Determine the execution time of each intermediate task based on the execution time of each second task; Among the at least one intermediate task, a target intermediate task is determined, which is the task with the latest execution time; In the level information corresponding to each second task, determine the level information of the target intermediate task; Based on the task processing request and the level information of the target intermediate task, the target task set is processed to obtain the simulation results of the chip.

2. The method according to claim 1, characterized in that, Based on the at least one first task and the at least one second task, a set of target tasks is determined, including: In the at least one second task, at least one candidate task is determined, the candidate task being matched with the first task; Determine the first associated task corresponding to each first task; Determine the second associated task for each candidate task; The target task set is determined from the at least one first associated task, the at least one candidate task, and the second associated task corresponding to each candidate task.

3. The method according to claim 2, characterized in that, Based on the at least one first associated task, the at least one candidate task, and a second associated task corresponding to each candidate task, the target task set is determined from the at least one first task, including: For any candidate task, determine the first task corresponding to the candidate task; If the second associated task corresponding to the candidate task matches the first associated task corresponding to the first task, then the candidate task is determined to be an intermediate task, and at least one intermediate task is obtained. The target task set is determined to include tasks other than the at least one intermediate task from the at least one first task.

4. The method according to any one of claims 1-3, characterized in that, The task processing request also includes at least one operating parameter; based on the task processing request and the level information of the target intermediate task, the target task set is processed to obtain the simulation results of the chip, including: Determine the execution time of each target task in the set of target tasks; Based on the execution time of each target task, determine the target time and at least one non-target time; Based on the level information of the intermediate task, the target signal corresponding to the target time is processed to obtain the target level information; Based on the at least one operating parameter and the target level information, the target task set is processed at the at least one non-target time to obtain the simulation results of the chip; Wherein, the target time is a preset time, and the non-target time is any execution time other than the target time among the at least one execution time.

5. The method according to claim 4, characterized in that, Based on the level information of the target intermediate task, the level signal corresponding to the target time is processed to obtain the target level information, including: Based on the level information of the target intermediate task, determine the intermediate signal corresponding to the target intermediate task and the target value corresponding to the intermediate signal at a first moment, where the first moment is the execution completion time of the target intermediate task; If the intermediate signal matches the target signal, then the first value of the target signal is updated according to the target value to obtain the target level information, which includes the target signal and the target value corresponding to the target time.

6. The method according to claim 4, characterized in that, Based on the at least one operating parameter and the target level information, the target task set is processed at at least one non-target time to obtain the simulation results of the chip, including: For any non-target time, determine the target task corresponding to the non-target time; Determine whether the target task has a historical task, wherein the historical task is the target task executed at the previous execution time of the current time. If so, the execution result of the historical task is determined, and the target task is processed according to the at least one running parameter and the at least one execution result to obtain the processing result corresponding to the target task; If not, the target task is processed according to the at least one operating parameter and the target level information to obtain the processing result corresponding to the target task; The simulation results of the chip are determined to include the processing results corresponding to each target task in the target task set.

7. A task processing device, characterized in that, The device includes: The first acquisition module is used to acquire a task processing request, wherein the task processing request is used to request the processing of at least one first task of chip simulation. The second acquisition module is used to acquire historical task processing information, which includes at least one second task. A determining module is configured to determine a target task set based on the at least one first task and the at least one second task, wherein the number of tasks included in the target task set is less than or equal to the number of the at least one first task; The processing module is configured to process the target task set according to the task processing request and the historical task processing information to obtain the simulation results of the chip. The historical task processing information further includes the execution time of each second task and the level information corresponding to each second task. The processing of the target task set according to the task processing request and the historical task processing information to obtain the simulation results of the chip includes: Determine the execution time of each intermediate task based on the execution time of each second task; Among the at least one intermediate task, a target intermediate task is determined, which is the task with the latest execution time; In the level information corresponding to each second task, determine the level information of the target intermediate task; Based on the task processing request and the level information of the target intermediate task, the target task set is processed to obtain the simulation results of the chip.

8. A terminal device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, in, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 6.

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