Methods, apparatus, electronic devices and storage media for determining silicon interposer routing patterns

Abstract

The present application provides a method, device, electronic device and storage medium for determining the routing mode of a silicon interposer, obtaining basic information of a silicon interposer; establishing a routing mode framework of a silicon interposer based on the basic information of the silicon interposer, and generating multiple groups of scan parameters for variables in the routing mode framework of the silicon interposer; solving the RLGC model corresponding to the routing mode framework of the silicon interposer under each group of scan parameters; establishing a complete end-to-end netlist according to each RLGC model; performing time domain simulation based on the end-to-end netlist corresponding to each group of scan parameters, and obtaining corresponding time domain simulation results; collecting the time domain simulation results corresponding to all groups of scan parameters; and determining the optimal routing mode of the silicon interposer according to multiple time domain simulation results. This method can efficiently obtain the optimal routing mode of the silicon interposer without relying on subjective conditions.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a method, device, electronic device and storage medium for determining a routing mode of a silicon interposer. Background Art

[0002] High-performance computing systems require high-speed, high-bandwidth high-bandwidth memory (HBM) and D2D interconnection support, and the advanced packaging of CoWoS-S uses a silicon interposer to perform high-speed interconnection of HBM, D2D and other interfaces. In order to ensure good signal integrity (SI) performance, this parallel high-speed routing not only needs to consider routing loss, but also the impact of crosstalk between routing. Usually, routing optimization is in a contradiction between loss and crosstalk, so it is crucial to find the optimal routing method.

[0003] In related technologies, SI engineers will first determine a rough plan based on experience, and then use 2D electromagnetic field tools to do some simple scans to obtain some fragmented results as the basis for subsequent layout engineers to do wiring, and then use post-simulation results to determine whether the wiring meets the requirements and whether optimization and iteration are required.

[0004] In the method of determining the routing method of the silicon interposer in the related art, the fragmentation and incompleteness of the preliminary simulation results cannot directly obtain the global optimal solution. It is necessary to rely on the personal experience of SI engineers and more optimization iterations to obtain the best routing method. This implementation method has strong subjective dependence and low efficiency. Summary of the invention

[0005] In view of this, the present application provides a method, device, electronic device and storage medium for determining a silicon interposer routing method, which can efficiently obtain an optimal silicon interposer routing method without relying on subjective conditions.

[0006] To solve the above technical problems, the technical solution of this application is implemented as follows:

[0007] In one embodiment, a method for determining a silicon interposer routing mode is provided, the method comprising:

[0008] Obtaining basic information of the silicon interposer; the basic information includes the number of metal layers and the number of layers where the signal is located;

[0009] Establishing a silicon interposer routing mode framework based on the silicon interposer basic information, and generating multiple groups of scan parameters for variables in the silicon interposer routing mode framework;

[0010] Solve the RLGC model corresponding to the silicon interposer routing mode framework under each set of scan parameter conditions;

[0011] According to each of the RLGC models, a complete end-to-end netlist is established respectively;

[0012] Performing time domain simulation based on the end-to-end netlist corresponding to each group of scan parameters to obtain corresponding time domain simulation results;

[0013] Collect the time domain simulation results corresponding to the scan parameters of all groups;

[0014] An optimal silicon interposer routing method is determined according to the multiple time domain simulation results.

[0015] Wherein, each of the time domain simulation results is an eye diagram, and determining the optimal silicon interposer routing method according to the multiple time domain simulation results includes:

[0016] Determine a set of eye width and eye height according to each of the eye diagrams;

[0017] Calculate the size of an eye according to each set of eye widths and eye heights;

[0018] Selecting the scan parameters corresponding to the eye diagram whose eye width is greater than a preset width threshold, whose eye height is greater than a preset height threshold, and whose calculated eye size is the largest;

[0019] A silicon interposer routing scheme is generated based on the selected scan parameters and the silicon interposer routing scheme framework as an optimal silicon interposer routing scheme.

[0020] Each of the eye diagrams is an eye diagram corresponding to a signal located in the middle of a signal layer during a corresponding time domain simulation process.

[0021] in,

[0022] If the signal occupies multiple layers in the silicon interposer routing mode framework, an eye diagram corresponding to the signal-occupied layer with the smallest eye size is selected.

[0023] The generating of multiple groups of scan parameters for the variables in the silicon interposer routing mode framework includes:

[0024] Obtaining a scan parameter range that satisfies the process and design requirements for variables in the silicon interposer routing framework;

[0025] A plurality of groups of scan parameters are generated by selecting parameter values ​​within the scan parameter range according to a set step size.

[0026] The scan parameters include:

[0027] Signal routing repetition period, ground width of the reference layer, signal width of the signal layer, and isolation ground width of the signal layer.

[0028] According to each of the RLGC models, a complete end-to-end netlist is established, including:

[0029] Generate a corresponding input end model and an output end model according to each of the RLGC models;

[0030] Based on the RLGC model, the input-end model and the output-end model, and by adding excitations, a complete end-to-end netlist corresponding to each RLGC model is generated.

[0031] In another embodiment, a device for determining a routing mode of a silicon interposer is provided, the device comprising:

[0032] An acquisition unit, used to acquire basic information of the silicon interposer; the basic information includes the number of metal layers and the number of layers where the signal is located;

[0033] A generating unit, configured to establish a silicon interposer routing mode framework based on the silicon interposer basic information, and generate multiple groups of scan parameters for variables in the silicon interposer routing mode framework;

[0034] A solving unit, used for solving the RLGC model corresponding to the silicon interposer routing mode framework under each set of scan parameter conditions;

[0035] A building unit, used for building a complete end-to-end netlist according to each of the RLGC models;

[0036] A simulation unit, configured to perform time domain simulation based on the end-to-end netlist corresponding to each group of scan parameters to obtain corresponding time domain simulation results;

[0037] A collecting unit, used for collecting time domain simulation results corresponding to the scan parameters of all groups;

[0038] A determination unit is used to determine an optimal silicon interposer routing method according to the multiple time domain simulation results.

[0039] In another embodiment, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method for determining a silicon interposer routing method when executing the program.

[0040] In another embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, a method for determining a routing mode of a silicon interposer is implemented.

[0041] It can be seen from the above technical solution that in the above embodiment, a silicon interposer routing mode framework is initially established, and multiple sets of scan parameters are given for the variables therein to realize multiple silicon interposer routing modes, and finally the optimal silicon interposer routing mode is determined by time domain simulation for each silicon interposer routing mode. This solution can efficiently obtain the optimal silicon interposer routing mode without relying on subjective conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 A schematic diagram of a process for determining a silicon interposer routing method in an embodiment of the present application;

[0044] Figure 2 A schematic diagram of a flow chart for determining another silicon interposer routing method in an embodiment of the present application;

[0045] Figure 3 This is a schematic diagram of a silicon interposer wiring method framework in an embodiment of the present application;

[0046] Figure 4 It is a structural schematic diagram of the relationship between three models used for simulation in an embodiment of the present application;

[0047] Figure 5 This is a schematic diagram of the structure of a device for determining a silicon interposer routing method in an embodiment of the present application;

[0048] Figure 6 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe the order or precedence of the objects. It should be understood that the data used in this way can be interchanged where appropriate, so that the implementation of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] The selection of traditional silicon-interposer routing needs to consider the number of metal layers (Metal) to be used. Generally speaking, manufacturers will provide 3-layer, 4-layer and 5-layer metal process options, and 5-layer metal will provide the best SI performance. After determining how many layers of metal process to use, it is necessary to determine how many layers the signal needs to occupy, whether it is 2 layers or 3 layers. If it is a 2-layer signal routing, then it is 2 / 4-layer routing or 3 / 5-layer routing. If it is determined to use 2 / 4-layer routing, it is also necessary to determine the specific method of signal layer routing, whether it is SSS, GSG, or GSSG, etc. If it is GSG, then it is also necessary to determine the line width of the signal routing, the line width of the isolation ground routing, etc., so there are many possibilities and combinations.

[0052] Generally, SI engineers will first determine the approximate solution based on experience and then use 2D electromagnetic field tools to do some simple scans to obtain some fragmented results as the basis for subsequent layout engineers to route. Then, the post-simulation results will be used to determine whether the layout meets the requirements and whether optimization and iteration are required. In this method of determining the routing of the silicon interposer, the fragmentation and incompleteness of the pre-simulation results cannot directly obtain the global optimal solution. The SI engineer's personal experience and more optimization iterations are needed to obtain the best routing method. This implementation method is highly subjective and inefficient.

[0053] Based on the above technical problems, a method for determining a silicon interposer routing method is provided in an embodiment of the present application. A silicon interposer routing method framework for avoiding routing crosstalk is initially established, and multiple sets of scan parameters are given for the variables therein to implement multiple silicon interposer routing methods. Finally, the optimal silicon interposer routing method is determined by performing time domain simulation on each silicon interposer routing method. This solution can efficiently obtain the optimal silicon interposer routing method without relying on subjective conditions.

[0054] The following is a detailed description of the process of determining the silicon interposer routing method in the embodiment of the present application in conjunction with the accompanying drawings.

[0055] See also Figure 1 , Figure 1 This is a schematic diagram of a silicon interposer routing method determination process in an embodiment of the present application. The specific steps are:

[0056] Step 101, obtaining basic information of a silicon interposer; the basic information includes the number of metal layers and the number of layers where signals are located.

[0057] The number of metal layers indicates how many layers of metal technology are used; such as 3 layers, 4 layers, 5 layers, etc.

[0058] The layer number where the signal is located indicates how many layers the signal occupies and on which metal layer the signal routing needs to be performed; for example, if the signal occupies 2 layers and a 5-layer metal process is used, then the routing will be done on the 2 / 4 layer or the 3 / 5 layer.

[0059] Step 102 : establishing a silicon interposer routing mode framework based on the silicon interposer basic information, and generating multiple groups of scan parameters for variables in the silicon interposer routing mode framework.

[0060] In this step, the parameters such as signal routing repetition period, ground width of reference layer, signal width of signal layer and isolation ground width of signal layer in the silicon interposer routing mode framework established based on the basic information of silicon interposer are all variables, that is, the specific values ​​of these parameters are uncertain.

[0061] These parameters are referred to as scan parameters here. The generation of these parameters is given in the following determination method in the embodiment of this application, but is not limited to this determination method. As long as these parameters can be determined as comprehensively as possible to make the candidate silicon interposer routing methods more comprehensive and complete, it is conducive to selecting the optimal silicon interposer routing method.

[0062] Generate multiple sets of scan parameters for variables in the silicon interposer routing framework, including:

[0063] The first step is to obtain the scan parameter range allowed by the process and design for the variables in the silicon interposer routing method framework;

[0064] For the four parameters of signal routing repetition period, ground width of the reference layer, signal width of the signal layer and isolation ground width of the signal layer, corresponding parameter ranges are obtained based on the ranges allowed by the process and the design; that is, the parameter ranges of the four parameters are obtained.

[0065] The second step is to select parameter values ​​within the scan parameter range according to the set step size to generate multiple groups of scan parameters.

[0066] The step size set here can be set according to the specific application. The step sizes set for the four parameters can be the same or different. If the computing power of the computing device allows, multiple parameters can be selected with a smaller step size to obtain a more accurate silicon interposer routing method.

[0067] For example, for the four parameters of signal routing repetition period, reference layer ground width, signal layer signal width and signal layer isolation ground width, each parameter corresponds to 4 parameter values, so 4×4×4×4=256 groups of scan parameters can be generated.

[0068] Step 103 , solving the RLGC model corresponding to the silicon interposer routing framework under each set of scan parameter conditions.

[0069] Under each set of scan parameter conditions, a transmission line (RLGC) model can be generated based on the silicon interposer routing method framework, that is, a corresponding silicon interposer routing method, which can be used for time domain simulation.

[0070] Step 104 , establishing a complete end-to-end netlist according to each RLGC model.

[0071] When performing time domain simulation, not only the RLGC model is needed, but also the corresponding input model and output model need to be generated to complete the time domain simulation.

[0072] Step 105 , performing time domain simulation based on the end-to-end netlist corresponding to each group of scan parameters to obtain corresponding time domain simulation results.

[0073] Step 106, collecting time domain simulation results corresponding to all groups of scan parameters.

[0074] Step 107 , determining an optimal silicon interposer routing method according to multiple time domain simulation results.

[0075] In this embodiment, a silicon interposer routing method framework is initially established, and multiple sets of scan parameters are given for the variables therein to implement multiple silicon interposer routing methods. Finally, the optimal silicon interposer routing method is determined by time domain simulation of each silicon interposer routing method. This solution can efficiently obtain the optimal silicon interposer routing method without relying on subjective conditions. Usually, the crosstalk and loss between routings in the initially established silicon interposer routing method framework are relatively large. The optimal silicon interposer routing method obtained by the implementation method of this application is to find a routing method with a balance between smaller crosstalk and smaller loss.

[0076] In another example, each time domain simulation result is an eye diagram, and determining the optimal silicon interposer routing method according to the multiple time domain simulation results in step 107 includes:

[0077] Determine a set of eye width and eye height according to each eye diagram;

[0078] Calculate the size of an eye based on each set of eye width and eye height;

[0079] Select the scan parameters corresponding to the eye diagram whose eye width is greater than a preset width threshold, whose eye height is greater than a preset height threshold, and whose calculated eye size is the largest;

[0080] A silicon interposer routing pattern is generated based on the selected scan parameters and a silicon interposer routing pattern framework as an optimal silicon interposer routing pattern.

[0081] Each eye diagram is an eye diagram corresponding to a signal located in the middle of a signal layer during a corresponding time domain simulation process.

[0082] If the signal occupies multiple layers in the silicon interposer routing mode framework, the eye diagram corresponding to the signal occupied layer with the smallest eye size is selected.

[0083] In another example,

[0084] In step 104, a complete end-to-end netlist is established according to each RLGC model, including:

[0085] Generate corresponding input-end model and output-end model according to each RLGC model;

[0086] Based on the RLGC model, input-end model and output-end model, and adding incentives, a complete end-to-end netlist corresponding to each RLGC model is generated.

[0087] See also Figure 2 , Figure 2 This is a schematic diagram of another silicon interposer routing method determination process in an embodiment of the present application. The specific steps are:

[0088] Step 201, obtaining basic information of the silicon interposer; the basic information includes the number of metal layers and the number of layers where the signal is located.

[0089] The number of metal layers indicates how many layers of metal technology are used; such as 3 layers, 4 layers, 5 layers, etc.

[0090] The layer number where the signal is located indicates how many layers the signal occupies and on which metal layer the signal routing needs to be performed; for example, if the signal occupies 2 layers and a 5-layer metal process is used, then the routing will be done on the 2 / 4 layer or the 3 / 5 layer.

[0091] Step 202 : establishing a silicon interposer routing mode framework based on the silicon interposer basic information, and generating multiple groups of scan parameters for variables in the silicon interposer routing mode framework.

[0092] In this step, the parameters such as signal routing repetition period, ground width of reference layer, signal width of signal layer and isolation ground width of signal layer in the silicon interposer routing mode framework established based on the basic information of silicon interposer are all variables, that is, the specific values ​​of these parameters are uncertain.

[0093] These parameters are referred to as scan parameters here. The following determination method is given in the embodiment of this application to generate these parameters, but it is not limited to this determination method. As long as these parameters can be determined as comprehensively as possible, the candidate silicon interposer routing method can be more comprehensive and complete, which is conducive to selecting the optimal silicon interposer routing method:

[0094] Generate multiple sets of scan parameters for variables in the silicon interposer routing framework, including:

[0095] The first step is to obtain the scan parameter range allowed by the process and design for the variables in the silicon interposer routing method framework;

[0096] For the four parameters of signal routing repetition period, ground width of the reference layer, signal width of the signal layer and isolation ground width of the signal layer, corresponding parameter ranges are obtained based on the ranges allowed by the process and the design; that is, the parameter ranges of the four parameters are obtained.

[0097] The second step is to select parameter values ​​within the scan parameter range according to the set step size to generate multiple groups of scan parameters.

[0098] The step size set here can be set according to the specific application. The step sizes set for the four parameters can be the same or different. If the computing power of the computing device allows, multiple parameters can be selected with a smaller step size to obtain a more accurate silicon interposer routing method.

[0099] For example, for the four parameters of signal routing repetition period, reference layer ground width, signal layer signal width and signal layer isolation ground width, each parameter corresponds to 4 parameter values, so 4×4×4×4=256 groups of scan parameters can be generated.

[0100] Step 203 , solving the RLGC model corresponding to the silicon interposer routing framework under each set of scan parameter conditions.

[0101] Under each set of scan parameter conditions, an RLGC model can be generated based on the silicon interposer routing method framework, that is, a corresponding silicon interposer routing method, which can be used for time domain simulation.

[0102] Step 204 , establishing a complete end-to-end netlist according to each RLGC model.

[0103] When performing time domain simulation, not only the RLGC model is needed, but also the corresponding input end model and output end model need to be generated to complete the time domain simulation. Therefore, the specific implementation of this step is as follows:

[0104] Generate corresponding input-end model and output-end model according to each RLGC model;

[0105] Based on the RLGC model, input-end model and output-end model, and adding incentives, a complete end-to-end netlist corresponding to each RLGC model is generated.

[0106] Based on each complete end-to-end netlist, a time domain simulation can be performed.

[0107] Step 205 , performing time domain simulation based on the end-to-end netlist corresponding to each group of scan parameters to obtain corresponding time domain simulation results; the time domain simulation results are eye diagrams.

[0108] An eye diagram is obtained for each set of scan parameters, and each eye diagram is an eye diagram corresponding to a signal located in the middle of a signal layer during a corresponding time domain simulation process.

[0109] If the signal occupies multiple layers in the silicon interposer routing mode framework, the eye diagram corresponding to the signal occupied layer with the smallest eye size is selected.

[0110] Step 206: Collect eye diagrams corresponding to all groups of scan parameters.

[0111] Step 207: determine a set of eye widths and eye heights according to each eye diagram, and calculate the size of an eye according to each set of eye widths and eye heights.

[0112] The eye size is the product of the eye width and the eye height.

[0113] Step 208 , selecting a scan parameter corresponding to an eye diagram whose eye width is greater than a preset width threshold, whose eye height is greater than a preset height threshold, and whose calculated eye size is the largest.

[0114] The selected eye diagram meets the following three conditions:

[0115] The eye width is greater than a preset width threshold;

[0116] The eye height is greater than the preset height threshold;

[0117] The eye size is maximum when the eye width and eye height are met.

[0118] Step 209 , generating a silicon interposer routing scheme based on the selected scan parameters and the silicon interposer routing scheme framework as an optimal silicon interposer routing scheme.

[0119] In this embodiment of the present application, a silicon interposer routing method framework is preliminarily established, and then multiple silicon interposer routing methods are obtained as candidate methods by giving multiple sets of scan parameters that meet the process and design for the variables therein, and finally corresponding input end models and output end models are established for each silicon interposer routing method to form a complete end-to-end netlist, so as to perform time domain simulation to obtain the eye diagram corresponding to each silicon interposer routing method, and select the optimal silicon interposer routing method based on the eye diagram. This scheme can efficiently obtain the optimal silicon interposer routing method without relying on subjective conditions. Usually, the crosstalk and loss between the routings in the preliminarily established silicon interposer routing method framework are relatively large. The optimal silicon interposer routing method obtained by the implementation method of the present application is to find a routing method with a balance between smaller crosstalk and smaller loss.

[0120] The following is a process of determining the routing method of the silicon interposer with reference to the accompanying drawings and specific examples. Specifically:

[0121] The first step is to obtain basic information of the silicon interposer, which includes: 5 metal layers, two layers occupied by signals, and the third and fifth layers are signal-occupied layers.

[0122] The second step is to establish a silicon interposer routing framework based on the basic information of the silicon interposer.

[0123] The crosstalk and loss between the traces in the silicon interposer routing scheme are balanced.

[0124] See also Figure 3 , Figure 3 This is a schematic diagram of a silicon interposer routing method framework in an embodiment of the present application. Taking the GSG routing method as an example, Figure 3 The basic information of the silicon interposer is given (5 metal layers, signals occupy two layers, and the 3rd and 5th layers are signal-occupied layers), white boxes represent signals, black boxes represent metals, and the specific values ​​of the relevant variable scan parameters (signal routing repetition period, reference layer ground width, signal layer signal width, and signal layer isolation ground width) are not given. Figure 3 The framework in is only a schematic representation. Figure 3 For the sake of example, the signal and metal are separated one by one to avoid crosstalk.

[0125] In the third step, multiple sets of scan parameters are generated for the variables in the silicon interposer routing method framework.

[0126] For the four parameters of signal routing repetition period, ground width of reference layer, signal width of signal layer and isolation ground width of signal layer, corresponding parameter ranges are obtained based on the ranges allowed by process and design respectively; that is, parameter ranges of the four parameters are obtained;

[0127] A step size is set for each parameter, and specific parameter values ​​are collected within the acquired parameter range, so that there is a set of parameter values ​​for each parameter. The step size set for each parameter can be the same or different. If the computing power of the computing device allows, a smaller step size can be selected to obtain more possible parameters, and these parameters can be determined as comprehensively and accurately as possible, making the candidate silicon interposer routing methods more comprehensive and complete, which is conducive to selecting the optimal silicon interposer routing method.

[0128] Assuming that M parameter values ​​are selected for the signal routing repetition period, N parameter values ​​are selected for the ground width of the reference layer, L parameter values ​​are selected for the signal width of the signal layer, and K parameter values ​​are selected for the isolation ground width of the signal layer, M×N×L×K groups of scan parameters can be generated.

[0129] The fourth step is to solve the RLGC model corresponding to the silicon interposer routing framework under each set of scan parameter conditions.

[0130] A GLGC model is generated for each set of scan parameters, so M×N×L×K sets of scan parameters can generate M×N×L×K RLGC models.

[0131] Step 5: According to each RLGC model, a complete end-to-end netlist is established.

[0132] When performing time domain simulation, not only the RLGC model is needed, but also the corresponding input end model and output end model need to be generated to complete the time domain simulation. Therefore, the specific implementation of this step is as follows:

[0133] Generate corresponding input-end model and output-end model according to each RLGC model;

[0134] Based on the RLGC model, input-end model and output-end model, and adding incentives, a complete end-to-end netlist corresponding to each RLGC model is generated.

[0135] See also Figure 4 , Figure 4 It is a structural diagram of the relationship between the three models used for simulation in the embodiment of the present application. Figure 4 In the RLGC model, the signals corresponding to the 3rd and 5th layers occupy the layer, the input end model inputs the corresponding signals of these two layers, the output end model outputs the corresponding signals of these two layers, and the excitation is added at the input end.

[0136] Since there are 4 signals corresponding to the third layer in the RLGC model, the signal input and output are performed through 4 input terminals and 4 output terminals; there are 3 signals corresponding to the fifth layer, so the signal input and output are performed through 3 input terminals and 3 output terminals. The signals are represented by white boxes in the figure.

[0137] Figure 4 All the contents are stored in the form of a netlist as a complete end-to-end netlist corresponding to a RLGC model. Time domain simulation can be performed through a simulator based on the contents of the netlist.

[0138] Step 6: Perform time domain simulation based on the end-to-end netlist corresponding to each set of scan parameters to obtain corresponding time domain simulation results; the time domain simulation results are eye diagrams.

[0139] See Figure 4 In the example, each signal corresponding to each output port will generate an eye diagram, such as Figure 4 In the position shown by V in the middle, in the embodiment of the present application, the eye diagram corresponding to the signal in the middle is selected for each layer of signal, that is, the eye diagram corresponding to the relatively middle signal is selected, such as the eye diagram corresponding to the signal L5-2 is selected for the 5th layer signal, and the eye diagram corresponding to the signal L3-2 or the signal L3-3 is selected for the 3rd layer signal;

[0140] For a time domain simulation result, if the signal occupies multiple layers, multiple eye diagrams will be selected; at this time, the implementation method provided in the embodiment of the present application is to select the eye diagram corresponding to the signal occupied layer with the smallest eye size, assuming Figure 4 The eye diagram corresponding to the signal L3-2 is selected for the layer 3 signal, and the eye diagram corresponding to the signal L5-2 is selected for the layer 5 signal, and the eye diagram with the smaller eye in the two eye diagrams is selected as the simulation result of the time domain simulation.

[0141] Step 7. Collect eye diagrams corresponding to all groups of scan parameters.

[0142] M×N×L×K groups of scan parameters correspond to M×N×L×K eye diagrams, which are collected and an optimal eye diagram is selected.

[0143] Step 8. Determine a set of eye widths and eye heights according to each eye diagram, and calculate the size of an eye according to each set of eye widths and eye heights.

[0144] The eye size is the product of the eye width and the eye height.

[0145] Step 9: Select the scan parameters corresponding to the eye diagram whose eye width is greater than a preset width threshold, whose eye height is greater than a preset height threshold, and whose calculated eye size is the largest.

[0146] The selected eye diagram meets the following three conditions:

[0147] The eye width is greater than a preset width threshold;

[0148] The eye height is greater than the preset height threshold;

[0149] The eye size is maximum when the eye width and eye height are met.

[0150] Step 10. Generate a silicon interposer routing method based on the selected scan parameters and the silicon interposer routing method framework as an optimal silicon interposer routing method.

[0151] In the embodiment of the present application, when selecting scan parameters, all possible values ​​allowed by the process and design are selected, so that the simulation data is more comprehensive, that is, the set of candidate silicon interposer routing methods is more complete, avoiding the omission of the optimal silicon interposer routing method, which is of great significance for guiding the early design of routing methods.

[0152] It also reduces the number of SI high-speed channel design iterations and verifications, reduces the number of reworks, and can select the optimal silicon interposer routing method in one process, thereby speeding up product acceptance and reducing labor costs.

[0153] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present disclosure, and will not be described in detail here.

[0154] Based on the same inventive concept, an embodiment of the present application also provides a device for determining a silicon interposer routing method. Figure 5 , Figure 5 This is a schematic diagram of the structure of a device for determining the routing mode of a silicon interposer in an embodiment of the present application. The device includes:

[0155] An acquisition unit 501 is used to acquire basic information of a silicon interposer; wherein the basic information includes the number of metal layers and the number of layers where the signal is located;

[0156] A generating unit 502 is used to establish a silicon interposer routing mode framework based on the silicon interposer basic information, and generate multiple groups of scan parameters for variables in the silicon interposer routing mode framework;

[0157] A solving unit 503, used for solving the RLGC model corresponding to the silicon interposer routing mode framework under each set of scan parameter conditions;

[0158] A building unit 504 is used to build a complete end-to-end netlist according to each RLGC model;

[0159] The simulation unit 505 is used to perform time domain simulation based on the end-to-end netlist corresponding to each group of scan parameters to obtain corresponding time domain simulation results;

[0160] A collecting unit 506, used to collect time domain simulation results corresponding to all groups of scan parameters;

[0161] The determination unit 507 is used to determine the optimal silicon interposer routing method according to multiple time domain simulation results.

[0162] In another embodiment,

[0163] The determination unit 507 is specifically used for determining the optimal silicon interposer routing method according to multiple time domain simulation results when each time domain simulation result is an eye diagram, and determining a group of eye widths and eye heights according to each eye diagram; calculating the size of an eye according to each group of eye widths and eye heights; selecting the scan parameters corresponding to the eye diagram with an eye width greater than a preset width threshold, an eye height greater than a preset height threshold, and a calculated eye size of the largest; and generating a silicon interposer routing method based on the selected scan parameters and a silicon interposer routing method framework as the optimal silicon interposer routing method.

[0164] In another embodiment, each eye diagram is an eye diagram corresponding to a signal located in the middle of a signal layer during a corresponding time domain simulation process.

[0165] If the signal occupies multiple layers in the silicon interposer routing mode framework, the eye diagram corresponding to the signal occupied layer with the smallest eye size is selected.

[0166] In another embodiment,

[0167] The generation unit 502 is specifically used to generate multiple groups of scan parameters for the variables in the silicon interposer routing mode framework, obtain the scan parameter range that meets the process and design requirements for the variables in the silicon interposer routing mode framework; and generate multiple groups of scan parameters by selecting parameter values ​​within the scan parameter range according to the set step size.

[0168] In another embodiment,

[0169] The scan parameters include: signal routing repetition period, ground width of the reference layer, signal width of the signal layer, and isolation ground width of the signal layer.

[0170] In another embodiment,

[0171] Establishing unit 504 is specifically used to establish a complete end-to-end netlist according to each RLGC model, generate a corresponding input-end model and an output-end model according to each RLGC model; based on the RLGC model, the input-end model and the output-end model, and adding incentives, generate a complete end-to-end netlist corresponding to each RLGC model.

[0172] The units in the above-mentioned embodiments may be integrated into one body or deployed separately; they may be combined into one unit or further divided into multiple sub-units.

[0173] In another embodiment, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, a method for determining a silicon interposer routing method can be implemented.

[0174] In another embodiment, a computer-readable storage medium is provided, on which computer instructions are stored. When the instructions are executed by a processor, a method for determining a routing mode of a silicon interposer can be implemented.

[0175] Figure 6 Schematic diagram of the physical structure of an electronic device provided by an embodiment of the present invention. Figure 6 As shown, the electronic device may include: a processor (Processor) 610, a communication interface (Communications Interface) 620, a memory (Memory) 630 and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 communicate with each other through the communication bus 640. The processor 610 may call the logic instructions in the memory 630 to execute the following method:

[0176] Obtain basic information of the silicon interposer; wherein the basic information includes the number of metal layers and the number of layers where the signal is located;

[0177] A silicon interposer routing mode framework is established based on basic information of the silicon interposer, and multiple groups of scan parameters are generated for variables in the silicon interposer routing mode framework;

[0178] Solve the RLGC model corresponding to the silicon interposer routing framework under each set of scan parameter conditions;

[0179] According to each RLGC model, a complete end-to-end netlist is established;

[0180] Perform time domain simulation based on the end-to-end netlist corresponding to each group of scan parameters to obtain corresponding time domain simulation results;

[0181] Collect the time domain simulation results corresponding to all groups of scan parameters;

[0182] Determine the optimal silicon interposer routing method based on multiple time-domain simulation results.

[0183] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0184] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0185] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0186] The flow chart and block diagram in the accompanying drawings of the present application show the possible architecture, function and operation of the system, method and computer program product according to the various embodiments disclosed in the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the box can also occur in the order of the standards in different figures. For example, the boxes represented by two connections can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0187] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims disclosed in this application may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in this application. In particular, without departing from the spirit and teachings of this application, the features described in the various embodiments and / or claims of this application may be combined and / or combined in a variety of ways, and all of these combinations and / or combinations fall within the scope disclosed in this application.

[0188] Specific embodiments are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas, and is not used to limit the present application. For those skilled in the art, changes can be made in the specific implementation methods and application scopes according to the ideas, spirits and principles of the present invention, and any modifications, equivalent substitutions, improvements, etc. made therein should be included in the scope of protection of this application.

Claims

1. A method for determining a silicon interposer routing method, characterized in that: The method comprises: Obtaining basic information of the silicon interposer; the basic information includes the number of metal layers and the number of layers where the signal is located; A silicon interposer routing framework is established based on the basic information of the silicon interposer, and multiple groups of scan parameters are generated for variables in the silicon interposer routing framework; wherein each group of scan parameters includes: a signal routing repetition period, a ground width of a reference layer, a signal width of a signal layer, and an isolation ground width of a signal layer; Solve the RLGC model corresponding to the silicon interposer routing mode framework under each set of scan parameter conditions; According to each of the RLGC models, a complete end-to-end netlist is established respectively; Performing time domain simulation based on the end-to-end netlist corresponding to each group of scan parameters to obtain corresponding time domain simulation results; Collect the time domain simulation results corresponding to the scan parameters of all groups; Determining an optimal silicon interposer routing method according to a plurality of the time domain simulation results; Wherein, each of the time domain simulation results is an eye diagram, and determining the optimal silicon interposer routing method according to the multiple time domain simulation results includes: Determine a set of eye width and eye height according to each of the eye diagrams; Calculate the size of an eye according to each set of eye widths and eye heights; Selecting the scan parameters corresponding to the eye diagram whose eye width is greater than a preset width threshold, whose eye height is greater than a preset height threshold, and whose calculated eye size is the largest; A silicon interposer routing scheme is generated based on the selected scan parameters and the silicon interposer routing scheme framework as an optimal silicon interposer routing scheme.

2. The method according to claim 1, characterized in that Each of the eye diagrams is an eye diagram corresponding to a signal located in the middle of a signal layer during a corresponding time domain simulation process.

3. The method according to claim 2, characterized in that If the signal occupies multiple layers in the silicon interposer routing mode framework, an eye diagram corresponding to the signal-occupied layer with the smallest eye size is selected.

4. The method according to claim 1, characterized in that The generating of multiple groups of scan parameters for variables in the silicon interposer routing mode framework includes: Obtaining a scan parameter range that satisfies the process and design requirements for variables in the silicon interposer routing framework; A plurality of groups of scan parameters are generated by selecting parameter values ​​within the scan parameter range according to a set step size.

5. The method according to any one of claims 1 to 4, characterized in that: According to each of the RLGC models, a complete end-to-end netlist is established, including: Generate a corresponding input end model and an output end model according to each of the RLGC models; Based on the RLGC model, the input-end model and the output-end model, and by adding excitations, a complete end-to-end netlist corresponding to each RLGC model is generated.

6. A device for determining a silicon interposer routing method, characterized in that: The device comprises: An acquisition unit, used to acquire basic information of the silicon interposer; the basic information includes the number of metal layers and the number of layers where the signal is located; A generating unit, configured to establish a silicon interposer routing mode framework based on the silicon interposer basic information, and generate multiple groups of scan parameters for variables in the silicon interposer routing mode framework; wherein each group of the scan parameters includes: a signal routing repetition period, a ground width of a reference layer, a signal width of a signal layer, and an isolation ground width of a signal layer; A solving unit, used for solving the RLGC model corresponding to the silicon interposer routing mode framework under each set of scan parameter conditions; A building unit, used for building a complete end-to-end netlist according to each of the RLGC models; A simulation unit, configured to perform time domain simulation based on the end-to-end netlist corresponding to each group of scan parameters to obtain corresponding time domain simulation results; A collecting unit, used for collecting time domain simulation results corresponding to the scan parameters of all groups; A determination unit, configured to determine an optimal silicon interposer routing method according to a plurality of the time domain simulation results; Among them, the determination unit, when each of the time domain simulation results is an eye diagram, is specifically used to determine the optimal silicon interposer routing method based on multiple time domain simulation results, and to determine a group of eye widths and eye heights according to each eye diagram; calculate the size of an eye according to each group of eye widths and eye heights; select the scan parameters corresponding to the eye diagram whose eye width is greater than a preset width threshold, whose eye height is greater than a preset height threshold, and whose calculated eye size is the largest; and generate a silicon interposer routing method based on the selected scan parameters and the silicon interposer routing method framework as the optimal silicon interposer routing method.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 5 is implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method described in any one of claims 1 to 5 is implemented.

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