Display device and driving method thereof

Abstract

The invention relates to a display device and a driving method thereof, and belongs to the technical field of display, and the display device comprises a display panel, a display driving chip and a power management integrated circuit; a first output end of the power management integrated circuit is electrically connected with a first voltage signal line in a frame area in the display panel through the display driving chip, and the first voltage signal line is electrically connected with the gate driving circuit; the power management integrated circuit comprises a comparison module and an adjusting module, the first comparison end of the comparison module is electrically connected with the first voltage signal line through a first connecting line, the second comparison end of the comparison module is electrically connected with the first output end of the power management integrated circuit, and the feedback end of the comparison module is electrically connected with the input end of the adjusting module. The output end of the adjusting module is electrically connected with the first output end of the power management integrated circuit. The driving method is used for driving the display device. The display problem of bright and dark cross grains of the display device under low-gray-scale display can be effectively improved, and the display quality can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display device and a driving method thereof. Background Art

[0002] Organic Light-Emitting Diode (OLED) is a current-type organic light-emitting device, which refers to a device that emits light through carrier injection and recombination of organic semiconductor materials and luminescent materials under the drive of an electric field. OLED has become one of the research hotspots in the display field because of its excellent color saturation, contrast and response speed, and because its material is thinner, transparent, flexible, and can realize a variety of designs.

[0003] As end customers' requirements for display performance (such as refresh rate, resolution, display brightness, etc.) continue to increase, LTPO screen technology has emerged. LTPO (Low Temperature Polycrystalline Oxide) is a combination of the mainstream LTPS (low temperature polycrystalline silicon) and IGZO (indium gallium zinc oxide) solutions of OLED screens. The minimum refresh rate of LTPO screen technology can be 1Hz. A lower refresh rate will bring lower power consumption, and a large amount of electricity can be saved by reducing the refresh rate.

[0004] However, in the prior art, display devices using LTPO technology are prone to regular light and dark horizontal stripes when actually displaying low brightness and low grayscale, which greatly affects the display quality.

[0005] Therefore, providing a display device and a driving method thereof that can improve the display problem of horizontal stripes and enhance the display quality is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0006] In order to solve the above technical problems, the present disclosure provides a display device and a driving method thereof, which are used to solve the problem that the display device in the prior art is prone to regular bright and dark horizontal stripes when displaying at low brightness and low grayscale, resulting in the display quality not being effectively improved.

[0007] The present disclosure provides a display device, including a display panel, a display driver chip and a power management integrated circuit; the display panel includes a frame area, and the frame area includes a gate driver circuit and a first voltage signal line;

[0008] The first output terminal of the power management integrated circuit is electrically connected to the input pin of the display driver chip, the output pin of the display driver chip is electrically connected to one end of the first voltage signal line, and the other end of the first voltage signal line is electrically connected to the first voltage signal terminal of the gate drive circuit;

[0009] The power management integrated circuit includes a comparison module and a regulation module; the first comparison end of the comparison module is electrically connected to the first voltage signal line through a first connecting line, the second comparison end of the comparison module is electrically connected to the first output end of the power management integrated circuit, the feedback end of the comparison module is electrically connected to the input end of the regulation module, and the output end of the regulation module is electrically connected to the first output end of the power management integrated circuit.

[0010] Based on the same inventive concept, the present disclosure also provides a method for driving a display device, the driving method being used to drive the above-mentioned display device; the driving method comprises:

[0011] In a display period of a display frame of the display panel, an actual first voltage signal transmitted on the first voltage signal line is transmitted to a first comparison terminal of a comparison module of the power management integrated circuit through a first connection line, a second comparison terminal of the comparison module receives a preset first voltage signal output by a first output terminal of the power management integrated circuit, and the comparison module compares the actual first voltage signal with the preset first voltage signal to obtain an error value;

[0012] The feedback end of the comparison module feeds back the error value to the input end of the adjustment module for electrical connection, and the adjustment is performed through the adjustment module. The output end of the adjustment module transmits the adjusted compensated first voltage signal to the first output end of the power management integrated circuit.

[0013] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0014] The display device disclosed in the present invention electrically connects the first voltage signal line of the display panel frame area to the first connection line, and sets a comparison module and an adjustment module in the power management integrated circuit. The comparison module compares the real-time voltage on the first voltage signal line of the display panel frame area with the preset voltage output by the first output terminal of the power management integrated circuit in real time. In the case of an error, the adjustment module is used to adjust and compensate, and finally the adjustment and compensation are output to the display panel through the first output terminal of the power management integrated circuit. Even if the falling edge of the EM signal in different areas at different times enters the porch area during the driving scanning display of the display panel, the SPX signal coupling amount required by the pixel circuit of the display panel can be a fixed voltage value, and the display brightness of different areas of the display panel can also be unaffected, which can effectively improve the display problem of bright and dark horizontal stripes of the display device under low grayscale display, which is conducive to improving the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 It is a schematic diagram of an electrical connection structure between a pixel circuit and a light-emitting element of a display device in the prior art;

[0018] Figure 2 yes Figure 1 Related timing diagrams:

[0019] Figure 3 yes Figure 1 and Figure 2 Schematic diagram of a display device having a horizontal stripe phenomenon;

[0020] Figure 4 is a schematic diagram of a planar structure of a display device provided by an embodiment of the present invention;

[0021] Figure 5 is another schematic diagram of a planar structure of a display device provided by an embodiment of the present invention;

[0022] Figure 6 is another schematic diagram of a planar structure of a display device provided by an embodiment of the present invention;

[0023] Figure 7 is another schematic diagram of a planar structure of a display device provided by an embodiment of the present invention;

[0024] Figure 8 is another schematic diagram of a planar structure of a display device provided by an embodiment of the present invention;

[0025] Fig. 9 yes Figure 8 A schematic diagram of an electrical connection structure between a pixel circuit and a light-emitting element;

[0026] Fig.10 yes Figure 8 A schematic diagram of another electrical connection structure between the pixel circuit and the light emitting element;

[0027] Fig.11 It is a flowchart of a method for driving a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0029] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0030] Please refer to Figure 1-Figure 3 , Figure 1 It is a schematic diagram of an electrical connection structure between a pixel circuit and a light-emitting element of a display device in the prior art. Figure 2 yes Figure 1 The relevant timing diagram of Figure 3 yes Figure 1 and Figure 2 Schematic diagram of the horizontal stripe phenomenon on the display device. It can be understood that Figure 1 The display device using LTPO technology in the prior art includes a display panel, and the display panel generally includes an electrical connection structure of a pixel circuit and an OLED light-emitting element. Figure 1 It can be seen that the pixel circuit includes 8 transistors (transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8) and 1 capacitor (capacitor Cst), wherein transistor T4 and transistor T5 electrically connected to the gate of transistor T3 are both N-type metal oxide transistors, such as IGZO (indium gallium zinc oxide) transistors, and the remaining transistors are P-type LTPS (low temperature polysilicon) transistors. That is, transistor T4 and transistor T5 are turned on when the gate potential is high, and the gate potential of the remaining transistors is turned on when the gate potential is low. Figure 1 The potential of the N4 node in the provided pixel circuit is the anode potential of the OLED light-emitting element, which determines the magnitude of the current flowing through the OLED light-emitting element. Figure 1 The transistor T8 in the provided pixel circuit is used to adjust the bias state of the transistor T3. It should be noted that the present disclosure does not elaborate on the connection structure and working principle of the above pixel circuit, and the specific explanation of the LTPO technology in the related art can be referred to for understanding.

[0031] In the OLED display device using LTPO technology, the gate control signals of transistor T4 and transistor T5 are S2N signal and S1N signal respectively, and the switching level of S1N signal and S2N signal is VGH2 level / VGL2 level (VGH2 level is an effective signal for controlling the conduction of transistor T4 and transistor T5), and the gate control signals of the remaining transistors are EM signal, SP signal and SPX signal respectively, and the switching level of EM signal, SP signal and SPX signal is VGH1 level / VGL1 level (VGL1 level is an effective signal for controlling the conduction of other transistors except transistor T4 and transistor T5). VGH1 level and VGL1 level, VGH2 level and VGL2 level are respectively generated and provided by the signal routing of the border area of ​​the display panel through the gate drive circuit (GOA, Gate onArray). And since the EM signal, SP signal and SPX signal required by the pixel circuit are all PMOS circuits, the gate drive circuit is connected to the output pin of the driver chip, and the driver chip IC will output the low potential VGL1 level to the gate drive circuit. The gate drive circuit signal is transmitted in stages (since the gate drive circuit generally includes a cascaded shift register circuit), the signal input of each row of pixel circuits is input through the output of the previous stage, and the signal input of the first stage is generated by the driver chip IC configuration, so it can be understood that the EM signal, SP signal and SPX signal required by the pixel circuit are also transmitted in stages.

[0032] The display panel generally includes a display area (active area) and a porch area (this area is used to prepare for some voltage conversion, and can also be understood as a display blanking area. In display technology, it refers to the area on the display screen used for synchronization signal transmission, rather than the area used to display images. Generally, the active area is followed by the porch area. The porch area is a specific time period when the display device displays an image. During this period, no valid image information is displayed, but it is used for the transmission and processing of synchronization signals to ensure the correct synchronization and stable operation of the display device). The porch area is fixed, so during the display period, different areas of the display panel will have corresponding EM signals falling in the porch area, which will cause light and dark horizontal stripes. Specifically, such as Figure 2As shown in the relevant timing diagram, TE high level represents the porch area, EM(1) and EM(2) represent the EM signal timing of the EM signal scanning in different areas in sequence, and SPX(1) and SPX(2) represent the SPX signal timing of the SPX signal scanning in different areas in sequence. In area ②, the falling edge of the EM(2) signal is in the porch area, that is, the falling edge of the EM(2) signal in this area is inside the porch area. For the display area (active area) of the display panel, the VGL1 signal has one less load to jump down, the overall load current of VGL1 becomes smaller, the VGL1 value is relatively lower than the original setting value, and the difference between VGH1 and VGL1 becomes relatively larger; since the EM signal and the SPX signal share the VGL1 voltage generated by the gate drive circuit, once the difference between VGH1 and VGL1 becomes relatively larger, the SPX signal jumps high and the coupling amount becomes more, the N4 node potential is higher, and the brightness is brighter. In area ①, the falling edge of the EM(1) signal is not in the porch area, that is, the falling edge of the EM(1) signal in this area is not in the porch area. For the active area of ​​the display panel, the VGL1 signal has an additional load that jumps down. The overall load current of VGL1 increases, and the VGL1 value is relatively higher than the original setting value. The difference between VGH1 and VGL1 becomes relatively smaller. Since the EM signal and the SPX signal share the VGL1 voltage generated by the gate drive circuit, once the difference between VGH1 and VGL1 becomes relatively smaller, the SPX signal jumps high and the coupling amount becomes less, the N4 node potential is low, and the brightness is dim. The final display screen is presented Figure 3 The display device 111 ′ in the prior art shown is prone to regular bright and dark horizontal stripes.

[0033] From the above, it can be seen that when the display device using LTPO technology in the prior art displays low brightness and low grayscale, the state of the falling edge of the EM signal entering and exiting the porch area is different at different times, and the VGL1 voltage has a potential fluctuation in units of the EM signal period. Since the EM signal, SP signal, and SPX signal all share the VGL1 voltage generated by the gate drive circuit, the SPX signal coupling amount also fluctuates periodically, resulting in light and dark horizontal stripes on the low grayscale screen.

[0034] Based on the above problems, the present application proposes a display device and a driving method thereof, which can improve the display problem of horizontal stripes and enhance the display quality. Specific embodiments of the display device and the driving method thereof proposed in the present application are described in detail as follows.

[0035] Please refer to Figure 4 , Figure 41 is a schematic diagram of a planar structure of a display device provided by an embodiment of the present invention. A display device 111 provided by this embodiment includes a display panel 10, a display driver chip 20 and a power management integrated circuit 30; the display panel 10 includes a frame area NA, and the frame area NA includes a gate drive circuit 101 and a first voltage signal line 102;

[0036] The first output terminal 30-out1 of the power management integrated circuit 30 is electrically connected to the input pin IN-pin of the display driver chip 20, the output pin OUT-pin of the display driver chip 20 is electrically connected to one end of the first voltage signal line 102, and the other end of the first voltage signal line 102 is electrically connected to the first voltage signal terminal 1011 of the gate drive circuit 101;

[0037] The power management integrated circuit 30 includes a comparison module 301 and an adjustment module 302; the first comparison terminal 3011 of the comparison module 301 is electrically connected to the first voltage signal line 102 through the first connection line L1, the second comparison terminal 3012 of the comparison module 301 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30, the feedback terminal 3013 of the comparison module 301 is electrically connected to the input terminal 302-in of the adjustment module 302, and the output terminal 302-out of the adjustment module 302 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30.

[0038] Specifically, the display device 111 provided in this embodiment may be an OLED display device, and the display device 111 includes a display panel 10, that is, the display panel 10 may be an OLED display panel. The display area AA of the display panel 10 may include a pixel circuit and an OLED light-emitting element. Optionally, the pixel circuit designed for the display panel 10 in this embodiment may be a pixel circuit using LTPO technology (see Figure 1 The display device 111 further includes a display driver chip 20 and a power management integrated circuit 30. The display driver chip 20 can be understood as a DDIC (Display Driver Integrated Circuit, DDIC), which is mainly used to control the display panel 10, drive the display panel 10 through electrical signals, transmit display drive data, cooperate with the display panel 10 to achieve lightness, flexibility and foldability, and provide a wide color gamut and high-fidelity display signal.

[0039] Optionally, the display driver chip 20 and the display panel 10 can be electrically connected by binding through a flexible circuit board. It is understandable that the present embodiment does not limit the electrical connection method of the display driver chip 20 and the display panel 10, and the specific understanding can be made by referring to the binding method of the display driver chip 20 and the display panel 10 in the related art. It is understandable that the final structure of the display device 111 can be a structure in which the display driver chip 20 is located on the backlight side of the display panel 10 through the bending of the flexible circuit board, thereby minimizing the overall size of the display device 111 and avoiding the display driver chip 20 from occupying the space of the device.

[0040] The power management integrated circuit 30 of this embodiment can be understood as a PMIC (Power Management IC), which is mainly used to power the display device, that is, the power supply of the display panel 10 for display work, the power supply of the display driver chip 20 for controlling the display drive signal, and other power supply requirements of the modules included in the display device 111 are all provided by the power management integrated circuit 30. Figure 1 The gate control potential for controlling whether the transistor is turned on or off in the pixel circuit of the display panel shown in the figure can be provided to the display driver chip 20 through the power management integrated circuit 30, and then transmitted to the display panel 10 through the output pin of the display driver chip 20. For example, the first output terminal 30-out1 of the power management integrated circuit 30 outputs the VGL1 signal required by the pixel circuit of the display panel 10. The VGL1 signal is used to control Figure 1 The effective signal that turns on the transistors other than the transistor T4 and the transistor T5.

[0041] The first output terminal 30-out1 of the power management integrated circuit 30 is electrically connected to the input pin IN-pin of the display driver chip 20, and the output pin OUT-pin of the display driver chip 20 is electrically connected to one end of the first voltage signal line 102. The first voltage signal line 102 is routed in the frame area NA of the display panel 10. The frame area NA of the display panel 10 also includes a gate drive circuit 101. The other end of the first voltage signal line 102 is electrically connected to the first voltage signal terminal 1011 of the gate drive circuit 101. Thus, the first output terminal 30-out1 of the power management integrated circuit 30 outputs a low-level signal, which is introduced through the input pin IN-pin of the display driver chip 20, and output to the first voltage signal line 102 in the frame area NA of the display panel 10 through the output pin OUT-pin of the display driver chip 20, and then introduced into the gate drive circuit 101 through the first voltage signal terminal 1011 of the gate drive circuit 101. The gate drive circuit 101 generates a VGL1 signal required by the pixel circuit of the display area AA of the display panel 10 and outputs it to the pixel circuit to control Figure 1 The other transistors except transistor T4 and transistor T5 are turned on.

[0042] It is understandable that the VGL1 signal required by the pixel circuit of the display area AA of the display panel 10 of this embodiment is directly output by the first output terminal 30-out1 of the power management integrated circuit 30, and there is no need for the internal circuit of the display driver chip 20 to adjust the signal, which is beneficial to saving the power consumption of the display driver chip 20.

[0043] It is understandable that the present embodiment is only described by taking the output end of the power management integrated circuit 30 including the first output end 30 - out1 as an example. In specific implementation, the output end of the power management integrated circuit 30 includes but is not limited to the first output end 30 - out1 .

[0044] Since the EM signal, SP signal and SPX signal in the pixel circuit of the display device all share the VGL1 voltage outputted from the first output terminal 30-out1 of the power management integrated circuit 30 and generated by the gate driving circuit, when low brightness and low grayscale are displayed, the falling edge of the EM signal enters and exits the porch area at different times, resulting in a potential fluctuation of the VGL1 voltage in units of the EM signal period, thereby causing the SPX signal coupling amount to also fluctuate periodically, resulting in the appearance of bright and dark horizontal stripes on the low grayscale screen.

[0045] In order to solve the above problems, the power management integrated circuit 30 of this embodiment includes a comparison module 301 and an adjustment module 302; wherein the comparison module 301 can be a comparator, the first comparison terminal 3011 and the second comparison terminal 3012 of the comparison module 301 can be understood as two comparison signal input terminals of the comparator, and the feedback terminal 3013 of the comparison module 301 can be understood as a comparison signal output terminal. The first comparison terminal 3011 of the comparison module 301 of the present embodiment is electrically connected to the first voltage signal line 102 in the frame area NA of the display panel 10 through the first connection line L1. It can be understood that the first comparison terminal 3011 of the comparison module 301 is electrically connected to the first voltage signal line 102 in the frame area NA of the display panel 10 through the first connection line L1. It can be an indirect electrical connection, such as indirectly realizing the electrical connection of the first comparison terminal 301 of the comparison module 301 of the power management integrated circuit 30 with the first voltage signal line 102 in the frame area NA of the display panel 10 through the first connection line L1 through the pin of the display driver chip 20, or it can be a direct electrical connection between the first connection line L1 and the first voltage signal line 102, and the comparison in the present embodiment is not limited. The first comparison terminal 3011 of the comparison module 301 is electrically connected to the first voltage signal line 102 in the border area NA of the display panel 10 through the first connection line L1, so that the real-time voltage on the first voltage signal line 102 running in the border area NA of the display panel 10 can be transmitted to the first comparison terminal 3011 of the comparison module 301 through the first connection line L1; and the second comparison terminal 3012 of the comparison module 301 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30, that is, the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30 can be directly transmitted to the second comparison terminal 3012 of the comparison module 301 in the power management integrated circuit 30, and the comparison module 301 can compare the real-time voltage on the first voltage signal line 102 running in the border area NA of the display panel 10 with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30 in real time to obtain an error voltage.The feedback terminal 3013 of the comparison module 301 is electrically connected to the input terminal 302-in of the adjustment module 302, and the output terminal 302-out of the adjustment module 302 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30. If the feedback result obtained by the feedback terminal 3013 of the comparison module 301, that is, the error voltage exceeds the preset range, the adjustment module 302 can adjust the control parameters inside the power management integrated circuit 30 according to the error voltage, and adjust the output voltage of the first output terminal 30-out1 of the power management integrated circuit 30, so that after adjustment and compensation, the output voltage of the first output terminal 30-out1 of the power management integrated circuit 30 can ensure that the VGL1 level of the EM signal falling edge entering the porch area at different times remains unchanged, thereby making the coupling amount of the SPX signal fixed, and the display brightness of different areas of the display panel 10 can also be unaffected, effectively improving the display problem of bright and dark horizontal stripes of the display device under low grayscale display, which is conducive to improving the display quality.

[0046] The display device 111 of the present embodiment electrically connects the first voltage signal line 102 of the frame area NA of the display panel 10 to the first connection line L1, and sets a comparison module 301 and an adjustment module 302 in the power management integrated circuit 30. The comparison module 301 compares and contrasts the real-time voltage on the first voltage signal line 102 of the frame area NA of the display panel 10 with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30 in real time. In the event of an error, the adjustment module 302 performs adjustment and compensation. Finally, the adjusted and compensated voltage is output to the display panel through the first output terminal 30-out1 of the power management integrated circuit 30. Even if the falling edges of EM signals in different regions at different times enter the porch area differently during the process of driving and scanning the display panel 10, the SPX signal coupling amount required by the pixel circuit of the display panel 10 can be a fixed voltage value, and the display brightness of different regions of the display panel 10 can be effectively guaranteed not to be affected, thereby greatly improving the display problem of bright and dark horizontal stripes of the display device under low grayscale display, thereby improving the display quality.

[0047] It should be noted that, in this embodiment Figure 4 The structure included in the display device 111 is only an example of the electrical connection relationship between them, and does not represent the actual setting structure. When it is implemented specifically, it can be based on the actual setting position, shape and other structures of the product. When it is implemented specifically, the structure of the display device 111 includes but is not limited to this, and also includes other structures, such as the connector between the power management integrated circuit 30 and the display driver chip 20. The structure of the display panel 20 can be understood by referring to the structure of the OLED display panel in the related technology.

[0048] Optionally, the comparison module 301 in this embodiment can be a comparator structure, and the comparator can be composed of a differential amplifier, which has two input terminals (a positive input terminal and a negative input terminal) and an output terminal, the two input terminals are the first comparison terminal 3011 and the second comparison terminal 3012 in this embodiment, and the output terminal is the feedback terminal 3013 in this embodiment. For example, the first comparison terminal 3011 is the negative input terminal, and the second comparison terminal 3012 is the positive input terminal. When the voltage of the positive input terminal is higher than that of the negative input terminal, the output voltage is a high level, and when the voltage of the negative input terminal is higher than that of the positive input terminal, the output voltage is a low level. According to the feedback result of the feedback terminal 3013, the adjustment module 302 can perform voltage compensation adjustment. When the voltages at the two input terminals are equal, the output voltage depends on the characteristics of the comparator. There may be a certain bias voltage, or the output may be in an uncertain state. At this time, it means that the real-time voltage on the first voltage signal line 102 running within the border area NA of the display panel 10 compared and contrasted by the comparison module 301 is consistent with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30.

[0049] In some alternative embodiments, please refer to Figure 5 , Figure 5 It is another planar structural schematic diagram of the display device provided by an embodiment of the present invention. In this embodiment, one end of the first connection line L1 is electrically connected to the first comparison end 3011 of the comparison module 301, and the connection node J between the other end of the first connection line L1 and the first voltage signal line 102 is located in the border area NA.

[0050] This embodiment explains that the layout method of the first connection line L1 electrically connected to the first voltage signal line 102 running in the border area NA of the display panel 10 can be that one end of the first connection line L1 is electrically connected to the first comparison end 3011 of the comparison module 301, and the other end of the first connection line L1 and the connection node J of the first voltage signal line 102 are located in the border area NA, that is, the other end of the first connection line L1 is directly electrically connected to the first voltage signal line 102 in the border area NA of the display panel 10. Since the first connection line L1 is set in this embodiment to electrically connect the first voltage signal line 102 routed in the border area NA of the display panel 10 to the first connection line L1, and a comparison module 301 and an adjustment module 302 are set in the power management integrated circuit 30, the comparison module 301 compares and contrasts the real-time voltage on the first voltage signal line 102 routed in the border area NA of the display panel 10 with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30 in real time. Therefore, the connection node J between the first connection line L1 and the first voltage signal line 102 is set in the border area NA, and the first connection line L1 is directly led out from the first voltage signal line 102 in the border area NA of the display panel 10, which can accurately feedback the real-time VGL1 signal that needs to be compared transmitted on the first voltage signal line 102 of the display panel 10, thereby ensuring that the adjustment module 302 makes more accurate feedback compensation, which can better ensure the display quality.

[0051] In some alternative embodiments, please refer to Figure 6 , Figure 6 It is another planar structural schematic diagram of the display device provided by an embodiment of the present invention. In this embodiment, one end of the first connecting line L1 is electrically connected to the first comparison end 3011 of the comparison module 301, and the connection node J between the other end of the first connecting line L1 and the first voltage signal line 102 is located on the input pin IN-pin of the display driver chip 20.

[0052] This embodiment explains that the layout of the first connection line L1 electrically connected to the first voltage signal line 102 running in the frame area NA of the display panel 10 can be that one end of the first connection line L1 is electrically connected to the first comparison end 3011 of the comparison module 301, and the connection node J between the other end of the first connection line L1 and the first voltage signal line 102 is located on the input pin IN-pin of the display driver chip 20, that is, an input pin IN-pin of the VGL1 signal is found on the display driver chip 20, and the real-time voltage transmitted on the first voltage signal line 102 is introduced into the first connection line L1 through the input pin IN-pin of the display driver chip 20, so as to realize real-time comparison and contrast of the real-time voltage on the first voltage signal line 102 running in the frame area NA of the display panel 10 with the preset voltage output by the first output end 30-out1 of the power management integrated circuit 30 through the comparison module 301, so that the adjustment module 302 can adjust the VGL1 voltage output by the power management integrated circuit 30 to ensure the display quality. Furthermore, the connection node J between the first connection line L1 and the first voltage signal line 102 is located on the input pin IN-pin of the display driver chip 20, so that the layout of the first connection line L1 does not occupy the frame space of the display panel 10, which is beneficial to reducing the frame of the display device 000 and improving the screen-to-body ratio.

[0053] In some alternative embodiments, please refer to Figure 7 , Figure 7 3 is another planar structural diagram of a display device provided in an embodiment of the present invention. In this embodiment, the power management integrated circuit 30 includes a high-frequency crystal oscillator 303 , and a frequency output terminal 3031 of the high-frequency crystal oscillator 303 is electrically connected to a first comparison terminal 3011 of the comparison module 301 .

[0054] This embodiment explains that since it is necessary to transmit the voltage value on the first voltage signal line 102 running in the frame area NA of the display panel 10 in real time and compare it in real time through the comparison module 301, a high-frequency crystal oscillator 303 can be set in the power management integrated circuit 30, and the first comparison terminal 3011 of the comparison module 301 responds to the voltage value on the first voltage signal line 102 according to the oscillation frequency given by the high-frequency crystal oscillator 303 itself. Specifically, the high-frequency crystal oscillator 303 can be an oscillator based on a quartz crystal, which realizes oscillation through the resonant frequency of the quartz crystal, and the vibration frequency of the high-frequency crystal oscillator 303 can be controlled within a fixed numerical range, which can generally reach a frequency of millions of times / second or even hundreds of millions of times / second. The frequency output terminal 3031 of the high-frequency crystal oscillator 303 is electrically connected to the first comparison terminal 3011 of the comparison module 301, and the first comparison terminal 3011 of the comparison module 301 is also electrically connected to the first voltage signal line 102 in the display panel 10 through the first connection line L1. Therefore, the high vibration frequency of the fixed value output by the frequency output terminal 3031 of the high-frequency crystal oscillator 303 can be used to achieve real-time monitoring of the voltage of VGL1 of each pixel circuit row scanned by the display panel 10 as much as possible, that is, the high vibration frequency of the fixed value output by the frequency output terminal 3031 of the high-frequency crystal oscillator 303 controls the feedback frequency of the first connection line L1 fed back to the first comparison terminal 3011 of the comparison module 301 for real-time monitoring. In actual implementation, the scanning signal may enter the porch area of ​​the display panel every few rows, and then the response begins to compare and adjust the real-time voltage value on the first voltage signal line 102 with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30. Optionally, in this embodiment, for the selection of a fixed value of a high vibration frequency output by the frequency output terminal 3031 of the high-frequency crystal oscillator 303, a frequency greater than or equal to the frequency at which the display panel enters the porch area can be selected to ensure that the voltage on the first voltage signal line 102 is compared and adjusted in each porch area as much as possible, or the voltage on the first voltage signal line 102 is more finely compared and adjusted when each pixel circuit row is working, so as to effectively improve the display horizontal stripe phenomenon.

[0055] In some optional embodiments, please refer to Figure 4-Figure 7 , Figure 8 and Fig. 9 , Figure 8 is another schematic diagram of a planar structure of a display device provided by an embodiment of the present invention, Fig. 9 yes Figure 8Schematic diagram of an electrical connection structure between a pixel circuit and a light-emitting element. In this embodiment, the display panel 10 includes a display area AA, and the display area AA includes a plurality of pixel circuits 103 and a light-emitting element 104; the pixel circuit 103 includes an electrically connected driving module 1031, a first reset module 1032, a data writing module 1033, a bias adjustment module 1034 and a light-emitting control module 1035;

[0056] A first end of the first reset module 1032 is electrically connected to the first reset signal line REF1, and a second end of the first reset module 1032 is electrically connected to the anode of the light emitting element 104; a first end of the data writing module 1033 and a first end of the bias regulating module 1034 are both electrically connected to the first end of the driving module 1031, a second end of the data writing module 1033 is electrically connected to the data line DATA, and a second end of the bias regulating module 1034 is electrically connected to the bias regulating signal line DVH;

[0057] The light control module 1035 includes a first light control module 10351 and a second light control module 10352, wherein a first end of the first light control module 10351 is electrically connected to a first power signal line PVDD, a second end of the first light control module 10351 is electrically connected to a first end of the driving module 1031, a first end of the second light control module 10352 is electrically connected to a second end of the driving module 1031, a second end of the second light control module 10352 is electrically connected to an anode of the light emitting element 104, and a cathode of the light emitting element 104 is electrically connected to a second power signal line PVEE;

[0058] The control ends of the first reset module 1032 and the bias adjustment module 1034 are electrically connected to the first scan signal line SPX, the control end of the data writing module 1033 is electrically connected to the second scan signal line SP, and the control end of the light emitting control module 1035 is electrically connected to the light emitting control signal line EM;

[0059] The enable signals VGL1 of the first scanning signal line SPX, the second scanning signal line SP, and the light emission control signal line EM are all low level signals.

[0060] The pixel circuit 103 further includes a threshold compensation module 1036 and a second reset module 1037;

[0061] A first end of the second reset module 1037 is electrically connected to the second reset signal line REF2, a second end of the second reset module 1037 is electrically connected to the control end of the driving module 1031, and a control end of the second reset module 1037 is electrically connected to the third scan signal line S1N;

[0062] A first end of the threshold compensation module 1036 is electrically connected to the control end of the driving module 1031, a second end of the threshold compensation module 1036 is electrically connected to the second end of the driving module 1031, and a control end of the threshold compensation module 1036 is electrically connected to the fourth scan signal line S2N;

[0063] The enable signals of the third scanning signal line S1N and the fourth scanning signal line S2N are both high level signals.

[0064] Optionally, the first voltage signal terminal 1011 of the gate driving circuit 101 receives the voltage on the first voltage signal line 102, and generates an enable signal VGL1 for the first scanning signal line SPX, the second scanning signal line SP, and the light-emitting control signal line EM through the gate driving circuit 101. The enable signal indicates a signal that can make the first end and the second end of the module conductive. If the transistor included in the module is a P-type transistor, the first scanning signal line SPX, the second scanning signal line SP, and the light-emitting control signal line EM are electrically connected to the control end of the module, respectively. The low-level VGL1 signal provided can make the module conductive, otherwise the module is in the cut-off state.

[0065] This embodiment explains the electrical connection relationship of the module structure that the pixel circuit 103 set in the display area AA of the display panel 000 may specifically include. In this embodiment, the driving transistor DT of the driving module 1031 is electrically connected to the data writing module 1033, the threshold compensation module 1036 and the bias adjustment module 1034, and the first electrode of the driving transistor DT is electrically connected to the data writing module 1033 and the bias adjustment module 1034 respectively. The driving transistor DT is used to generate a driving current, wherein the first electrode of the driving transistor DT can be understood as the source of the driving transistor DT, and the second electrode of the driving transistor DT can be understood as the drain of the driving transistor DT, or the first electrode of the driving transistor DT can be understood as the drain of the driving transistor DT, and the second electrode of the driving transistor DT can be understood as the source of the driving transistor DT, and this embodiment does not limit this. The second end of the data writing module 1033 is electrically connected to the data line DATA. The data writing module 1033 is turned on under the control of the second scanning signal provided by the second scanning signal SP, and the data voltage is transmitted to the second end of the data writing module 1033 through the data line DATA. The first end of the data writing module 1033 is electrically connected to the first electrode of the driving transistor DT. The data writing module 1033 is used to provide the data voltage value to the driving transistor DT. The threshold compensation module 1036 is connected between the gate of the driving transistor DT and the second electrode of the driving transistor DT. The threshold compensation module 1036 is turned on under the control of the fourth scanning signal provided by the fourth scanning signal line S2N. The threshold compensation module 1036 is used to detect and compensate for the deviation of the threshold voltage of the driving transistor DT, and provide the deviation of the compensated threshold voltage and the data signal provided by the data line DATA itself to the driving transistor DT to realize the threshold compensation of the driving transistor DT. The threshold compensation module 1036 set in this embodiment can improve the display unevenness caused by the difference in the threshold voltage of the driving transistor DT caused by the manufacturing process and the threshold voltage drift of the driving transistor DT caused by transistor aging. The second reset module 1037 is turned on under the control of the third scan signal provided by the third scan signal line S1N, and the second reset signal provided by the second reset signal line REF2 can reset the gate of the driving transistor DT and refresh the gate potential of the driving transistor DT in the previous frame.

[0066] When the light-emitting element 104 emits light, the light-emitting control signal provided by the light-emitting control signal line EM is turned on by the first light-emitting control module 10351 and the second light-emitting control module 10352, and a conductive path is formed among the first power signal line PVDD, the first light-emitting control module 10351, the driving transistor DT, the second light-emitting control module 10352, the light-emitting element 104, and the second power signal line PVEE, and the driving current is provided to the light-emitting element 104 to control the light-emitting element 104 to emit light.

[0067] Optional, such as Figure 8 and Fig.10 As shown, Fig.10 yes Figure 8 A schematic diagram of another electrical connection structure between the pixel circuit and the light-emitting element, wherein the driving module 1031 includes a driving transistor DT, the first reset module 1032 includes a first transistor M1, the data writing module 1033 includes a second transistor M2, the bias adjustment module 1034 includes a third transistor M3, the first light-emitting control module 10351 includes a fourth transistor M4, the second light-emitting control module 10352 includes a fifth transistor M5, the threshold compensation module 1036 includes a sixth transistor M6, and the second reset module 1037 includes a seventh transistor M7, wherein, further optionally, the second reset module 1037 and the threshold compensation module 1036 include metal oxide transistors, that is, the sixth transistor M6 and the seventh transistor M7 are metal oxide transistors, such as N-type metal oxide transistors. The driving module 1031, the first reset module 1032, the data writing module 1033, the bias adjustment module 1034, the first light-emitting control module 10351 and the second light-emitting control module 10352 respectively include low-temperature polysilicon transistors, that is, the driving transistor DT, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are all low-temperature polysilicon transistors, such as P-type low-temperature polysilicon transistors. In this embodiment, the sixth transistor M6 and the seventh transistor M7 connected to the control end of the driving module 1031, that is, the gate of the driving transistor DT, are N-type metal oxide transistors, and the remaining first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, and driving transistor DT are all P-type low-temperature polysilicon transistors. Since the metal oxide transistor has a low leakage current in the off state, the influence of the leakage current on the gate potential of the driving transistor DT can be reduced, thereby stabilizing the gate voltage of the driving transistor DT, improving the working stability of the driving transistor DT, and further ensuring the stability of the driving current, which is conducive to the display panel 10 of this embodiment to ensure the uniformity of the light emitting brightness of the light emitting element 104. In particular, when the display panel 10 realizes low-frequency driving display, the display time of a frame is long, and the time that the potential of the driving transistor DT needs to be maintained is also long. If the transistor connected to the gate of the driving transistor DT is a low-temperature polysilicon transistor, it is easy to have a large leakage current in the off state of the low-temperature polysilicon transistor, and the leakage current of the transistor connected to the gate of the driving transistor DT has a large influence on the potential of the gate of the driving transistor DT, thereby causing obvious flickering. Therefore, in this embodiment, the sixth transistor M6 and the seventh transistor M7 are set to be N-type metal oxide transistors, and the small off-state leakage current is utilized to maintain the gate potential of the driving transistor DT for a long time when the display panel 10 realizes low-frequency driving display, thereby improving the flickering phenomenon during low-frequency driving and enhancing the display effect.

[0068] Further optionally, the pixel circuit 103 also includes a storage capacitor C, one end of which is connected to the first power signal line PVDD, and the other end of which is connected to the gate of the driving transistor DT. The storage capacitor C is used to stabilize the potential of the gate of the driving transistor DT, which is beneficial for the driving transistor DT to remain turned on.

[0069] It is understandable that the working process of the pixel circuit using the LTPO screen technology is not described in detail in this embodiment, and it is not the main invention of the present disclosure. Therefore, the working timing of the OLED display panel in the related art can be specifically understood.

[0070] In some optional embodiments, please refer to Figure 4-Figure 10 and Fig.11 , Fig.11 : is a flowchart of a method for driving a display device provided in an embodiment of the present invention. The driving method provided in this embodiment is used to drive the display device 111 in any of the above embodiments. The driving method provided in this embodiment includes:

[0071] S10: within a frame display period of the display panel 10, the actual first voltage signal VGL1-FB transmitted on the first voltage signal line 102 is transmitted to the first comparison terminal 3011 of the comparison module 301 of the power management integrated circuit 30 through the first connection line L1;

[0072] S20: The second comparison terminal 3012 of the comparison module 301 receives the preset first voltage signal VGL1 -YS outputted by the first output terminal 30 - out1 of the power management integrated circuit 30;

[0073] S30: the comparison module 301 compares the actual first voltage signal VGL1 -FB with the preset first voltage signal VGL1 -YS to obtain an error value;

[0074] S40: the feedback terminal 3013 of the comparison module 301 feeds back the error value to the input terminal 302-in of the adjustment module 302;

[0075] S50 : adjusting through the adjusting module 302 , and the output terminal 302 -out of the adjusting module 302 transmits the adjusted compensated first voltage signal ΔVGL1 to the first output terminal 30 - out1 of the power management integrated circuit 30 .

[0076] The driving method provided in this embodiment is used to compensate for the voltage on the first voltage signal line 102 set in the frame area NA of the display panel 10. The first voltage signal line 102 is mainly used to introduce the low-level VGL1 signal output by the first output terminal 30-out1 of the power management integrated circuit 30 into the gate driving circuit 101 of the frame area NA through the input pin IN-pin and the output pin OUT-pin of the display driver chip 20, and the cascade characteristics of the gate driving circuit 101 generate the control signals required by the pixel circuit of the display panel 10, such as the EM signal required for light emission control, the SP signal required for data writing, and the SPX signal required for bias adjustment.

[0077] Since the first comparison terminal 3011 of the comparison module 301 in the power management integrated circuit 30 is electrically connected to the first voltage signal line 102 in the frame area NA of the display panel 10 through the first connection line L1, the real-time voltage on the first voltage signal line 102 in the frame area NA of the display panel 10 can be transmitted to the first comparison terminal 3011 of the comparison module 301 through the first connection line L1; for example, in a frame display cycle of the display panel 10, when the falling edge of the EM signal appears in the scanning and driving process of the display panel 10 to enter the porch area or when each pixel circuit is scanned and driven, the actual first voltage signal VGL1-FB transmitted on the first voltage signal line 102 is transmitted to the comparison module 301 through the first connection line L1. The first comparison terminal 3011 of the comparison module 301, and the second comparison terminal 3012 of the comparison module 301 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30, that is, the preset first voltage signal VGL1-YS output by the first output terminal 30-out1 of the power management integrated circuit 30 can be directly transmitted to the second comparison terminal 3012 of the comparison module 301 in the power management integrated circuit 30, and the comparison module 301 can compare the actual first voltage signal VGL1-FB on the first voltage signal line 102 routed in the border area NA of the display panel 10 with the preset first voltage signal VGL1-YS output by the first output terminal 30-out1 of the power management integrated circuit 30 in real time to obtain an error value. The feedback terminal 3013 of the comparison module 301 is electrically connected to the input terminal 302-in of the adjustment module 302, and the output terminal 302-out of the adjustment module 302 is electrically connected to the first output terminal 30-out1 of the power management integrated circuit 30. If the feedback result obtained by the feedback terminal 3013 of the comparison module 301, i.e., the error value, exceeds the preset range, the adjustment module 302 can adjust the control parameters inside the power management integrated circuit 30 according to the error voltage, and adjust the output voltage of the first output terminal 30-out1 of the power management integrated circuit 30. Finally, the output terminal 302-out of the adjustment module 302 transmits the adjusted compensation first voltage signal ΔVGL1 to the first output terminal 30-out1 of the power management integrated circuit 30. This embodiment provides a driving method, which can ensure that the VGL1 level of the EM signal falling edge entering the porch area at different times remains unchanged, and thus the coupling amount to the SPX signal is fixed, and the display brightness of different areas of the display panel 10 can also be unaffected, effectively improving the display problem of bright and dark horizontal stripes of the display device under low grayscale display, which is conducive to improving the display quality.

[0078] Optionally, in this embodiment, the comparison module 301 compares the actual first voltage signal VGL1-FB with the preset first voltage signal VGL1-YS to obtain an error value. The comparison module 301 can be a comparator structure. The comparator can be composed of a differential amplifier. The amplifier has two input terminals (a positive input terminal and a negative input terminal) and an output terminal. The two input terminals are the first comparison terminal 3011 and the second comparison terminal 3012, and the output terminal is the feedback terminal 3013. For example, the first comparison terminal 3011 is the negative input terminal, and the second comparison terminal 3012 is the positive input terminal. When the voltage of the positive input terminal is higher than that of the negative input terminal, the output voltage, that is, the error value, is a high level. When the voltage of the negative input terminal is higher than that of the positive input terminal, the output voltage, that is, the error value, is a low level. According to the feedback result of the feedback terminal 3013, the adjustment module 302 can perform voltage compensation adjustment. When the voltages at the two input terminals are equal, the output voltage depends on the characteristics of the comparator, and there may be a certain bias voltage, or the output is in an uncertain state. At this time, it means that the real-time voltage on the first voltage signal line 102 running within the border area NA of the display panel 10 compared and contrasted by the comparison module 301 is consistent with the preset voltage output by the first output terminal 30-out1 of the power management integrated circuit 30, and no adjustment or compensation is required.

[0079] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0080] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display device, characterized in that: It includes a display panel, a display driver chip and a power management integrated circuit; the display panel includes a frame area, and the frame area includes a gate drive circuit and a first voltage signal line; The first output terminal of the power management integrated circuit is electrically connected to the input pin of the display driver chip, the output pin of the display driver chip is electrically connected to one end of the first voltage signal line, and the other end of the first voltage signal line is electrically connected to the first voltage signal terminal of the gate drive circuit; The power management integrated circuit includes a comparison module and an adjustment module; the first comparison end of the comparison module is electrically connected to the first voltage signal line through a first connecting line, the second comparison end of the comparison module is electrically connected to the first output end of the power management integrated circuit, the feedback end of the comparison module is electrically connected to the input end of the adjustment module, and the output end of the adjustment module is electrically connected to the first output end of the power management integrated circuit.

2. The display device according to claim 1, characterized in that One end of the first connection line is electrically connected to the first comparison end of the comparison module, and a connection node between the other end of the first connection line and the first voltage signal line is located in the border area.

3. The display device according to claim 1, characterized in that One end of the first connection line is electrically connected to the first comparison end of the comparison module, and a connection node between the other end of the first connection line and the first voltage signal line is located on an input pin of the display driver chip.

4. The display device according to claim 1, characterized in that The power management integrated circuit comprises a high-frequency crystal oscillator, and a frequency output terminal of the high-frequency crystal oscillator is electrically connected to a first comparison terminal of the comparison module.

5. The display device according to claim 1, characterized in that The display panel includes a display area, and the display area includes a plurality of pixel circuits and light-emitting elements; the pixel circuit includes an electrically connected driving module, a first reset module, a data writing module, a bias adjustment module and a light-emitting control module; The first end of the first reset module is electrically connected to the first reset signal line, and the second end of the first reset module is electrically connected to the anode of the light-emitting element; the first end of the data writing module and the first end of the bias adjustment module are both electrically connected to the first end of the driving module, the second end of the data writing module is electrically connected to the data line, and the second end of the bias adjustment module is electrically connected to the bias adjustment signal line; The light control module comprises a first light control module and a second light control module, wherein a first end of the first light control module is electrically connected to a first power signal line, a second end of the first light control module is electrically connected to a first end of the driving module, a first end of the second light control module is electrically connected to a second end of the driving module, a second end of the second light control module is electrically connected to an anode of the light emitting element, and a cathode of the light emitting element is electrically connected to a second power signal line; The control ends of the first reset module and the bias adjustment module are electrically connected to the first scan signal line, the control end of the data writing module is electrically connected to the second scan signal line, and the control end of the light emitting control module is electrically connected to the light emitting control signal line; The enable signals of the first scanning signal line, the second scanning signal line, and the light emitting control signal line are all low level signals.

6. The display device according to claim 5, characterized in that: The first voltage signal terminal of the gate driving circuit receives the voltage on the first voltage signal line, and generates enable signals of the first scanning signal line, the second scanning signal line, and the light emitting control signal line through the gate driving circuit.

7. The display device according to claim 5, characterized in that: The pixel circuit also includes a threshold compensation module and a second reset module; The first end of the second reset module is electrically connected to the second reset signal line, the second end of the second reset module is electrically connected to the control end of the driving module, and the control end of the second reset module is electrically connected to the third scan signal line; The first end of the threshold compensation module is electrically connected to the control end of the driving module, the second end of the threshold compensation module is electrically connected to the second end of the driving module, and the control end of the threshold compensation module is electrically connected to the fourth scan signal line; The enable signals of the third scanning signal line and the fourth scanning signal line are both high level signals.

8. The display device according to claim 7, characterized in that: The second reset module and the threshold compensation module include metal oxide transistors.

9. The display device according to claim 7, characterized in that: The driving module, the first resetting module, the data writing module, the bias regulating module, and the light emitting control module respectively include low temperature polysilicon transistors.

10. A method for driving a display device, characterized in that: The driving method is used to drive the display device according to any one of claims 1 to 9; the driving method comprises: In a frame display cycle of the display panel, an actual first voltage signal transmitted on the first voltage signal line is transmitted to a first comparison terminal of the comparison module of the power management integrated circuit through the first connection line, a second comparison terminal of the comparison module receives a preset first voltage signal output by a first output terminal of the power management integrated circuit, and the comparison module compares the actual first voltage signal with the preset first voltage signal to obtain an error value; The feedback end of the comparison module feeds back the error value to the input end of the adjustment module and is electrically connected. The adjustment is performed through the adjustment module, and the output end of the adjustment module transmits the adjusted compensated first voltage signal to the first output end of the power management integrated circuit.

Images