Semiconductor device and manufacturing method thereof, and electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the method comprising: providing a semiconductor substrate, a shallow trench isolation structure formed in the semiconductor substrate, and a first etch stop layer formed on the semiconductor substrate between adjacent shallow trench isolation structures; etching back the first etch stop layer to obtain a second etch stop layer, the width of the second etch stop layer being smaller than the width of the first etch stop layer; ion implanting the semiconductor substrate using the second etch stop layer as a mask to form a source-drain region in the semiconductor substrate; removing the second etch stop layer; forming a gate electrode layer on the semiconductor substrate; forming a sidewall structure on the sidewall of the gate electrode layer, the top of the sidewall structure being flush with the top of the gate electrode layer. The present invention uses an etch stop layer to define the source-drain ion implantation region, and does not need to etch the sidewall structure to form a slanted shoulder structure with a sharper top. The sidewall with uniform width can increase the effective distance between the gate and the contact hole, and improve the leakage problem.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] At present, with the continuous reduction of process dimensions, the power supply voltage has not been able to decrease in proportion to the reduction of device channel length, junction depth, gate oxide thickness and the increase of substrate doping concentration, resulting in a significant increase in the channel lateral and longitudinal electric fields. The high electric field will accelerate the movement of carriers, so that the carriers become hot carriers with high energy. The carriers can directly enter the gate oxide layer through the tunneling effect, causing the threshold voltage and other parameters of the MOSFET transistor to drift or degrade, affecting the reliability of the device and ultimately causing the device to fail.

[0003] A more common method to solve the above HCI effect is to form a lightly doped drain (LDD), which is commonly known as source drain extension technology. LDD technology transforms the originally heavily doped n+ abrupt junction into a gradual junction. Taking NMOS as an example, by wrapping lightly doped n-type impurities on the outside of the drain region, an n+n / pw junction is formed, thereby easing the electric field strength, allowing the accelerated electrons to obtain relatively small kinetic energy in a single free path, thereby reducing the number of "hot carriers" and achieving the purpose of protecting the gate.

[0004] As the process nodes continue to shrink, the size of the device will also continue to shrink. When the device operating voltage is relatively large, the smaller the device size, the greater the electric field strength that the pn junction between the drain region and the channel region of the NMOS will withstand. Although LDD technology is used, more HCI will still be generated, and the reliability will deteriorate. After the semiconductor manufacturing process enters the nanoscale, a sidewall structure (spacer) is generally used in CMOS devices. The sidewall structure surrounds the gate, which can protect the polysilicon gate, define the source and drain extension of the semiconductor substrate and the source and drain ion implantation area, prevent self-aligned silicide from causing bridging, and prevent the source / drain area from being too close to the channel during high-intensity and high-dose injection, resulting in source / drain penetration.

[0005] Currently, a lightly doped drain region is usually formed first, and then the source and drain injection areas are defined by sidewalls to improve the hot carrier injection effect. However, the sidewall process window is limited by the shrinking process node, resulting in a smaller width of the effective lightly doped drain region. At the same time, the pointed shoulder structure formed after sidewall etching is prone to defects, increasing the risk of leakage between the gate and the contact hole, affecting device performance. Summary of the invention

[0006] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0007] In view of the existing problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0008] Providing a semiconductor substrate, wherein a shallow trench isolation structure is formed in the semiconductor substrate, and a first etch stop layer is formed on the semiconductor substrate between adjacent shallow trench isolation structures;

[0009] Etching back the first etch stop layer to obtain a second etch stop layer, wherein the width of the second etch stop layer is smaller than the width of the first etch stop layer;

[0010] Performing ion implantation on the semiconductor substrate using the second etch stop layer as a mask to form source and drain regions in the semiconductor substrate;

[0011] removing the second etch stop layer;

[0012] forming a gate electrode layer on the semiconductor substrate;

[0013] A spacer structure is formed on the sidewall of the gate electrode layer, and the top of the spacer structure is flush with the top of the gate electrode layer.

[0014] In one embodiment, forming a spacer structure on the sidewall of the gate electrode layer includes:

[0015] forming a first spacer layer on the sidewall of the gate electrode layer; and,

[0016] A second spacer layer is formed on the outer side of the first spacer layer.

[0017] In one embodiment, after forming the first spacer layer and before forming the second spacer layer, the method further includes:

[0018] Ion implantation is performed on the semiconductor substrate using the gate electrode layer and the first spacer layer as masks to form a lightly doped drain region in the semiconductor substrate.

[0019] In one embodiment, a material of the first spacer layer includes silicon oxide, and a material of the second spacer layer includes silicon nitride.

[0020] In one embodiment, the material of the first etch stop layer includes silicon nitride.

[0021] In one embodiment, etching back the first etch stop layer includes:

[0022] The first etch stop layer is etched back using a wet etching process.

[0023] In one embodiment, the etchant of the wet etching process includes a phosphoric acid solution.

[0024] In one embodiment, the thickness of the spacer structure is 100 angstroms to 800 angstroms.

[0025] Another aspect of an embodiment of the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by the method as described above.

[0026] Another aspect of an embodiment of the present invention provides an electronic device, wherein the electronic device includes the semiconductor device as described above.

[0027] According to the manufacturing method of the semiconductor device provided by the present invention, after forming the shallow trench isolation structure and before removing the shallow trench etch stop layer, the etch stop layer is etched back to define the source and drain ion implantation area; after completing the source and drain ion implantation, it is removed to form the gate and sidewall structure. Since the source and drain implantation has been completed, there is no need to etch the sidewall structure to form a shoulder structure with a sharp top. The sidewall with uniform width can increase the effective distance between the gate and the contact hole and improve the leakage problem; at the same time, the source and drain ion implantation area is defined by the shallow trench etch stop layer and is not limited by the process window of the sidewall structure, which can increase the effective lightly doped drain area width, improve the hot carrier injection effect, and improve the device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0029] In the attached figure:

[0030] Figures 1A to 1H A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing various steps according to a method for manufacturing a semiconductor device in the related art is shown;

[0031] Figure 2 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention;

[0032] FIG. 3A to FIG. 3H The cross-sectional view of a semiconductor device obtained by sequentially performing various steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0033] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0034] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0035] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0036] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0039] like Figures 1A to 1H As shown, in the related art, firstly, Figure 1A As shown, a semiconductor substrate 100 is provided, a shallow trench isolation structure 102 is formed in the semiconductor substrate, and an etch stop layer 101 is formed on the semiconductor substrate 100 between adjacent shallow trench isolation structures 102; then as shown in FIG. Figure 1B As shown, the etching stop layer 101 is removed; Figure 1C As shown, a gate electrode layer 103 is formed on a semiconductor substrate 100; Figure 1D As shown, ion implantation is performed on the semiconductor substrate 100 using the gate electrode layer 103 as a mask to form a lightly doped drain region 104; Figure 1E As shown, a spacer structure 105 is formed on the sidewall of the gate electrode layer 103; Figure 1F As shown, the sidewall structure 105 is etched to form a shoulder structure; Figure 1G As shown, source and drain ion implantation is performed on the semiconductor substrate 100 to form source and drain regions 106; finally, as shown in FIG. Figure 1H As shown, contact holes 107 contacting the source and drain regions 106 are formed.

[0040] In the above technical solution, after the lightly doped drain region 104 is formed, the source and drain injection regions are defined by the sidewall structure 105 to improve the hot carrier injection effect. However, the sidewall process window is limited by the shrinking process node, resulting in a smaller effective lightly doped drain region width. At the same time, the sharp shoulder structure formed after the sidewall etching is prone to defects, increasing the risk of leakage between the gate electrode layer 103 and the contact hole 107, affecting the device performance.

[0041] Therefore, in view of the existence of the above-mentioned technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, such as Figure 2 As shown, it mainly includes the following steps:

[0042] In step S201, a semiconductor substrate is provided, wherein a shallow trench isolation structure is formed in the semiconductor substrate, and a first etch stop layer is formed on the semiconductor substrate between adjacent shallow trench isolation structures;

[0043] In step S202, the first etch stop layer is etched back to obtain a second etch stop layer, wherein the width of the second etch stop layer is smaller than the width of the first etch stop layer;

[0044] In step S203, ion implantation is performed on the semiconductor substrate using the second etch stop layer as a mask to form source and drain regions in the semiconductor substrate;

[0045] In step S204, removing the second etch stop layer;

[0046] In step S205, a gate electrode layer is formed on the semiconductor substrate;

[0047] In step S206 , a spacer structure is formed on the sidewall of the gate electrode layer, and the top of the spacer structure is flush with the top of the gate electrode layer.

[0048] The manufacturing method of the semiconductor device provided by the embodiment of the present invention, after forming the shallow trench isolation structure and before removing the shallow trench etch stop layer, the etch stop layer is etched back to define the source and drain ion implantation area; after the source and drain ion implantation is completed, it is removed to form a gate and sidewall structure. Since the source and drain implantation has been completed, there is no need to etch the sidewall structure to form a shoulder structure with a sharp top. The sidewall with uniform width can increase the effective distance between the gate and the contact hole and improve the leakage problem; at the same time, the source and drain ion implantation area is defined by the shallow trench etch stop layer and is not limited by the process window of the sidewall structure, which can increase the effective lightly doped drain area width, improve the hot carrier injection effect, and improve the device reliability.

[0049] Embodiment 1

[0050] Below, reference Figure 2 and FIG. 3A to FIG. 3H A method for manufacturing a semiconductor device according to an embodiment of the present invention is described in detail, wherein: Figure 2 A flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 3A to FIG. 3H The cross-sectional view of a semiconductor device obtained by sequentially performing various steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0051] First, step S201 is performed to provide a semiconductor substrate. Figure 3AAs shown, the material of the semiconductor substrate 300 includes but is not limited to at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, or silicon on dielectric (SOI), stacked silicon on dielectric (SSOI), stacked silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI) and germanium on dielectric (GeOI). As an example, in this embodiment, the semiconductor substrate 300 is made of single crystal silicon material.

[0052] A shallow trench isolation structure 301 is formed in the semiconductor substrate 300 , and a first etch stop layer 302 is formed between adjacent shallow trench isolation structures 301 . The first etch stop layer 302 is used to form the shallow trench isolation structure 301 .

[0053] Exemplarily, in the process of forming the shallow trench isolation structure 301, a first etch stop layer 302 is first formed on the semiconductor substrate 300. The material of the first etch stop layer 302 includes silicon nitride; optionally, the first etch stop layer 302 may also include a silicon oxide layer and a silicon nitride layer formed sequentially from bottom to top. Among them, the silicon oxide layer can be obtained by a high-temperature oxidation method, and its thickness can be 100-200 angstroms. The silicon nitride layer can be formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD) method. As an example, the silicon nitride layer can be formed by low-pressure chemical vapor deposition at a temperature of about 750°C using ammonia and dichlorosilane.

[0054] Next, the first etch stop layer 302 and the semiconductor substrate 300 are etched in sequence to form a plurality of shallow trenches. The substrate may be etched by anisotropic dry etching methods such as plasma etching and reactive ion etching, or anisotropic wet etching methods such as KOH and TMAH may be used. Specifically, a photoresist layer having a pattern may be formed on the first etch stop layer 302, and dry etching may be performed using the photoresist layer as a mask to transfer the pattern to the first etch stop layer 302, and the semiconductor substrate 300 may be etched using the photoresist layer and the first etch stop layer 302 as masks to form shallow trenches.

[0055] Next, an isolation layer is deposited in the shallow trench, and the isolation layer fills the shallow trench and covers the first etch stop layer. In some embodiments, a high density plasma deposition process (HDP, High Density Plasma) can be used to deposit the isolation layer. The material of the isolation layer includes silicon oxide. In some embodiments, a pad oxide layer can also be deposited in the shallow trench in advance to improve the deposition effect of the isolation layer. The pad oxide layer can be formed by thermal oxidation, such as dry oxygen oxidation, water vapor oxidation, wet oxygen oxidation, etc., or other suitable deposition methods such as chemical vapor deposition processes. HARP oxide can be used to fill the trench to form a shallow trench isolation structure. For example, a filling HARP oxide layer is formed using sub-atmospheric pressure chemical vapor deposition.

[0056] Next, the isolation layer above the first etch stop layer 302 is removed to form a shallow trench isolation structure 301. Specifically, the isolation layer may be chemically mechanically polished to remove the isolation layer outside the shallow trench until the first etch stop layer 302 is exposed, thereby forming a shallow trench isolation structure 301 in the area where the first etch stop layer 302 is not formed.

[0057] Execute step 202, such as Figure 3B As shown, the first etch stop layer 302 is etched back to obtain a second etch stop layer 303 , and the width of the second etch stop layer 303 is smaller than the width of the first etch stop layer.

[0058] By etching back the first etch stop layer 302, a second etch stop layer 303 for defining the source and drain ion implantation region can be obtained. Exemplarily, a wet etching process can be used to etch back the first etch stop layer 302, and the wet process has a stable etching rate and a high degree of process control. The etchant used in the wet etching process includes but is not limited to a phosphoric acid solution, and the phosphoric acid solution has a high etching selectivity for silicon nitride.

[0059] Execute step 203, refer to Figure 3C , ion implantation is performed on the semiconductor substrate 300 using the second etch stop layer 303 as a mask to form source / drain regions 304 in the semiconductor substrate 300. The implanted ion types of the source / drain ion implantation include carbon, nitrogen, phosphorus, boron, arsenic, etc., and the doping concentration can be selected from the commonly used range in the field. After the ion implantation is performed, annealing treatment can also be performed to activate the ions implanted in the source / drain. The annealing treatment can be a spike annealing process, and the annealing temperature range used in the spike annealing process can be appropriately adjusted according to actual process requirements.

[0060] In the embodiment of the present invention, the etch stop layer of the shallow trench isolation structure is back-etched and used to define the source and drain ion implantation area, so that the source and drain ion implantation is not limited by the process window of the sidewall structure. The source and drain blocking area formed by the etch stop layer has an additional distance than the source and drain blocking area formed by the sloped shoulder sidewall process, which can increase the effective lightly doped drain area width, increase the degree of gradual change of the PN junction between the drain area and the channel area, and improve the reliability of hot carrier injection.

[0061] After forming the source and drain regions 304, step S204 is performed. Figure 3D As shown, the second etch stop layer is removed. Exemplarily, the second etch stop layer can be removed by a wet etching process, and the etchant used in the wet etching process includes but is not limited to a phosphoric acid solution.

[0062] Next, execute step S205, such as Figure 3E As shown, a gate electrode layer 305 is formed on the semiconductor substrate. The gate electrode layer 305 is formed between adjacent shallow trench isolation structures 301. The gate electrode layer 305 includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer, wherein the constituent material of the metal layer may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride layer includes a titanium nitride (TiN) layer; the conductive metal oxide layer includes an iridium oxide (IrO2) layer; and the metal silicide layer includes a titanium silicide (TiSi) layer. In this embodiment, the gate electrode layer 305 is a polysilicon layer.

[0063] Exemplarily, after forming the gate electrode layer 305, step S206 is performed to form a sidewall structure on the sidewall of the gate electrode layer, and the top of the sidewall structure is flush with the top of the gate electrode layer. The sidewall structure can be used to protect the gate electrode layer. The material of the sidewall structure can be a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The sidewall structure can be deposited by chemical vapor deposition, thermal oxidation or furnace atomic layer deposition, and the deposition thickness is 100 angstroms to 800 angstroms. Since the source and drain injection has been completed, there is no need to etch the sidewall structure to form a shoulder structure with a sharper top, and the sidewall structure can maintain a uniform width. The sidewall with uniform width can increase the effective distance between the gate and the contact hole, and improve the leakage problem.

[0064] In some embodiments, forming a spacer structure on the sidewall of the gate electrode layer includes: firstly Figure 3F As shown, a first spacer layer 306 is formed on the sidewall of the gate electrode layer 305, and then as shown in FIG. Figure 3G As shown, a second spacer layer 308 is formed outside the first spacer layer 306 .

[0065] The material of the first spacer layer 306 includes silicon oxide, and the material of the second spacer layer 308 includes silicon nitride. After the first spacer layer 306 and the second spacer layer 308 are deposited, the first spacer layer 306 and the second spacer layer 308 can be etched to remove the portion thereof located on the top of the gate electrode layer 305. The deposition method of the first spacer layer 306 and the second spacer layer 308 can adopt various suitable process technologies familiar to those skilled in the art, such as low pressure chemical vapor deposition (LPCVD) formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD), laser ablation deposition (LAD) and epitaxial growth. The etching method can be anisotropic dry etching, such as plasma dry etching or reactive ion etching.

[0066] After forming the first spacer 306 and before forming the second spacer 308, the semiconductor substrate 300 may be ion implanted using the gate electrode layer 305 and the first spacer 306 as a mask to form a lightly doped drain region 307 in the semiconductor substrate 300. The lightly doped drain region 307 may be used to suppress hot carrier effects. Since the second spacer 308 is not formed when the lightly doped drain region 307 is formed, the effective lightly doped drain region width may be increased.

[0067] Then, if Figure 3H As shown, contact holes 309 are formed on both sides of the sidewall structure. Specifically, an interlayer dielectric layer covering the gate electrode layer and the sidewall structure can be deposited, and the interlayer dielectric layer can be etched to form the contact hole 309, and a conductive material can be filled therein. Since the sidewall structure of the embodiment of the present invention does not need to be etched to form a sloping shoulder structure with a sharp top, the sidewall with uniform width can increase the effective distance between the gate electrode layer 305 and the contact hole 309, improve the leakage problem, and improve the device performance.

[0068] At this point, the process steps implemented in the manufacturing method of a semiconductor device according to an embodiment of the present invention have been completed. It can be understood that the semiconductor device manufacturing method of this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of this embodiment.

[0069] According to the manufacturing method of the semiconductor device provided by the embodiment of the present invention, after forming the shallow trench isolation structure and before removing the shallow trench etch stop layer, the etch stop layer is etched back to define the source and drain ion implantation area; after the source and drain ion implantation is completed, it is removed to form the gate and sidewall structure. Since the source and drain implantation has been completed, there is no need to etch the sidewall structure to form a shoulder structure with a sharp top. The sidewall with uniform width can increase the effective distance between the gate and the contact hole and improve the leakage problem; at the same time, the source and drain ion implantation area is defined by the shallow trench etch stop layer and is not limited by the process window of the sidewall structure, which can increase the effective lightly doped drain area width, improve the hot carrier injection effect, and improve the device reliability.

[0070] Embodiment 2

[0071] The present invention also provides a semiconductor device, which can be prepared by the method in the above-mentioned embodiment 1.

[0072] Below, reference Figure 3H The semiconductor device of the present invention is introduced and described in detail. It is worth mentioning that in order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment 1. For specific explanations and descriptions, reference can be made to the description in embodiment 1.

[0073] Specifically, Figure 3H As shown, the semiconductor device of the embodiment of the present invention includes a semiconductor substrate 300, in which a shallow trench isolation structure 301 is formed; a gate electrode layer 305 is formed on the semiconductor substrate between adjacent shallow trench isolation structures 301, and a sidewall structure is formed on the sidewall of the gate electrode layer, and the top of the sidewall structure is flush with the top of the gate electrode layer 305. Exemplarily, the sidewall structure includes a first sidewall layer 306 formed on the sidewall of the gate electrode layer 305 and a second sidewall layer 308 formed outside the first sidewall layer 306. The material of the first sidewall layer 306 includes silicon oxide, and the material of the second sidewall layer 308 includes silicon nitride.

[0074] The top of the spacer structure in the embodiment of the present invention is flush with the top of the gate electrode layer 305. Compared with the inclined shoulder structure with a sharper top, the spacer with uniform width can increase the effective distance between the gate and the contact hole, thereby improving the leakage problem.

[0075] Embodiment 3

[0076] Another embodiment of the present invention provides an electronic device, comprising the aforementioned semiconductor device, wherein the semiconductor device is manufactured according to the aforementioned method.

[0077] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

[0078] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Providing a semiconductor substrate, and forming a first etch stop layer on the semiconductor substrate; Sequentially etching the first etch stop layer and the semiconductor substrate to form a shallow trench in the semiconductor substrate; Depositing an isolation layer in the shallow trench, wherein the isolation layer fills the shallow trench and covers the first etch stop layer; removing the isolation layer above the first etch stop layer to form a shallow trench isolation structure in the semiconductor substrate, wherein the first etch stop layer is formed on the semiconductor substrate between adjacent shallow trench isolation structures; Etching the first etch stop layer to obtain a second etch stop layer; Performing ion implantation on the semiconductor substrate using the second etch stop layer as a mask to form source and drain regions in the semiconductor substrate; removing the second etch stop layer; forming a gate electrode layer on the semiconductor substrate; A spacer structure is formed on the sidewall of the gate electrode layer, and the top of the spacer structure is flush with the top of the gate electrode layer.

2. The manufacturing method according to claim 1, characterized in that The step of forming a sidewall structure on the sidewall of the gate electrode layer comprises: forming a first spacer layer on the sidewall of the gate electrode layer; and, A second spacer layer is formed on the outer side of the first spacer layer.

3. The manufacturing method according to claim 2, characterized in that: After forming the first spacer layer and before forming the second spacer layer, the method further includes: Ion implantation is performed on the semiconductor substrate using the gate electrode layer and the first spacer layer as masks to form a lightly doped drain region in the semiconductor substrate.

4. The manufacturing method according to claim 2 or 3, characterized in that: The material of the first spacer layer includes silicon oxide, and the material of the second spacer layer includes silicon nitride.

5. The manufacturing method according to claim 1, characterized in that: The material of the first etch stop layer includes silicon nitride.

6. The manufacturing method according to claim 1, characterized in that: The etching of the first etch stop layer comprises: The first etch stop layer is etched using a wet etching process.

7. The manufacturing method according to claim 6, characterized in that: The etchant of the wet etching process includes a phosphoric acid solution.

8. The manufacturing method according to claim 1, characterized in that: The thickness of the sidewall structure is 100 angstroms to 800 angstroms.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic apparatus includes the semiconductor device according to claim 9.

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