Preparation method of semiconductor structure, semiconductor structure, device and equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. The method comprises the steps of forming a first fin-shaped structure, a middle lamination layer and a second fin-shaped structure on a substrate; forming a first power rail structure; performing fin cutting processing on the first front source drain region to form a first gap; forming a first intermediate isolation layer based on the first gap; etching the first intermediate isolation layer in the first front source-drain region to form a second gap; forming a front metal electric connection layer based on the second gap; forming a first semiconductor structure; reversing the wafer and removing the substrate; forming a second power rail structure; performing fin cutting processing on the first back source-drain region and the second back source-drain region to form a third gap; forming a second intermediate isolation layer based on the third gap; etching the second intermediate isolation layer in the second back source-drain region to form a fourth gap; forming a back metal electric connection layer based on the fourth gap; and forming a second semiconductor structure.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] Currently, in order to provide voltage, a power rail can be embedded inside the semiconductor structure. However, how to improve the power supply method inside the semiconductor structure and optimize the lead-out method of the power rail are still issues that need to be urgently addressed. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus, so as to provide a new solution for leading out a power rail structure inside a semiconductor structure.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, wherein the semiconductor structure comprises a first semiconductor structure and a second semiconductor structure which are stacked, wherein the first semiconductor structure comprises a first front source-drain region and a second front source-drain region which are arranged opposite to each other, and the second semiconductor structure comprises a first back source-drain region and a second back source-drain region which are arranged opposite to each other; the method comprises: forming a pair of first fin structures, a pair of intermediate stacks, and a pair of second fin structures on a substrate in sequence; the intermediate stack comprises a first sacrificial layer close to the first fin structure, a second sacrificial layer close to the second fin structure, and a transition layer between the first sacrificial layer and the second sacrificial layer; depositing a metal material of a preset height in the first region to form a The first power rail structure is formed; the first region is located between the first sacrificial layers of a pair of intermediate stacks; a fin cutting process is performed in the first front source and drain region until the first fin structure and the first sacrificial layer in the first front source and drain region are removed to form a pair of first grooves and a pair of first gaps; the pair of first gaps are located between the pair of first fin structures and the transition layer; the first groove is used to form a front interlayer dielectric layer of the first semiconductor structure; a first insulating material is deposited in the pair of first gaps to form a first intermediate isolation layer; the first intermediate isolation layer located in the first front source and drain region is etched to form a pair of second gaps; a metal material is filled in the pair of second gaps to form a pair of front metal electrical connection layers; the first power rail structure is located in the pair of front The invention relates to a method for forming a first power rail structure in a semiconductor structure by depositing a metal material of a preset height in a second region between metal electrical connection layers; forming a first semiconductor structure based on a pair of first fin structures; flipping the wafer and removing the substrate; depositing a metal material of a preset height in a second region to form a second power rail structure; the second region is located between a second sacrificial layer of a pair of intermediate stacks; performing fin cutting in a first back source and drain region and a second back source and drain region until the second fin structure in the first back source and drain region, the second fin structure in the second back source and drain region and the second sacrificial layer are removed to form a pair of second grooves, a pair of third grooves and a pair of third gaps; the pair of third gaps are located between a pair of second fin structures and a transition layer; the second grooves and the third grooves are used to form a back interlayer dielectric layer of the second semiconductor structure; in a pair of third gaps, the second grooves and the third grooves are used to form a back interlayer dielectric layer of the second semiconductor structure; in a pair of third gaps, the second fin structure ... The invention relates to a semiconductor device for manufacturing a semiconductor device of the present invention, wherein the first insulating material is deposited in the gap to form a second intermediate isolation layer; the second intermediate isolation layer located in the second back source and drain region is etched to form a pair of fourth gaps; a metal material is filled in the pair of fourth gaps to form a pair of back metal electrical connection layers; the second power rail structure is located between the pair of back metal electrical connection layers; based on a pair of second fin structures, a second semiconductor structure is formed; wherein the first back source and drain metal of the second semiconductor structure is connected to the front metal electrical connection layer through the first metal through hole; the second back source and drain metal through hole of the second semiconductor structure is connected to the back metal electrical connection layer through the second metal through hole; the back back metal interconnection layer in the second semiconductor structure is electrically connected to the first back source and drain metal and the second back source and drain metal.

[0006] In some possible implementations, after forming the back metal electrical connection layer, the method further includes: depositing a first dielectric material on the back interlayer dielectric layer to form a first dielectric layer; photolithography the first dielectric layer and the back interlayer dielectric layer under the action of a photoresist mask to form a first back source / drain metal groove and a second back source / drain metal groove; the first back source / drain metal groove is located in the first back source / drain region, and the second back source / drain metal groove is located in the second back source / drain region; photolithography the back interlayer dielectric layer at the bottom of the first back source / drain metal groove under the action of a photoresist mask to form a first through hole; the first through hole Extending to the first surface of the front metal electrical connection layer; the first surface is the surface of the front metal electrical connection layer close to the second intermediate isolation layer; under the action of the photoresist mask, the back interlayer dielectric layer located at the bottom of the second back source and drain metal groove is photoetched to form a second through hole; the second through hole extends to the second surface of the back metal electrical connection layer; the second surface is the surface of the back metal electrical connection layer away from the first intermediate isolation layer; metal material is filled in the first through hole, the second through hole, the first back source and drain metal groove and the second back source and drain metal groove to form a first metal through hole, a second metal through hole, a first back source and drain metal and a second back source and drain metal.

[0007] In some possible embodiments, after forming the first power rail structure, the method further includes: depositing a second dielectric material between a pair of first fin structures and on the first power rail structure to form a first dielectric wall structure; the pair of first fin structures are symmetrically arranged on both sides of the first dielectric wall structure; after forming the second power rail structure, the method further includes: depositing a second dielectric material between a pair of second fin structures and on the second power rail structure to form a second dielectric wall structure; the pair of second fin structures are symmetrically arranged on both sides of the second dielectric wall structure.

[0008] In some possible embodiments, before depositing a metal material of a preset height in the first area to form a first power rail structure, the method further includes: depositing a second insulating material on a pair of first fin structures, a pair of intermediate stacks, a pair of second fin structures and a substrate to form a first shallow trench isolation structure; the first shallow trench isolation structure wraps the pair of first fin structures, the pair of intermediate stacks and the pair of second fin structures; etching a portion of the first shallow trench isolation structure until the first sacrificial layer in the pair of first fin structures and the pair of intermediate stacks is exposed; and depositing oxide on the surfaces of the pair of first fin structures and the first sacrificial layer to form a first oxide layer.

[0009] In some possible embodiments, before depositing a metal material of a preset height in the second region to form a second power rail structure, the method further includes: etching a portion of the first shallow trench isolation structure until a pair of second fin structures and a second sacrificial layer in a pair of intermediate stacks are exposed, and a shallow trench isolation layer is formed; the shallow trench isolation layer corresponds to the transition layer in the intermediate stack; and oxide is deposited on the surfaces of the pair of second fin structures and the second sacrificial layer to form a second oxide layer.

[0010] In some possible embodiments, a first semiconductor structure is formed based on a pair of first fin structures, including: based on the first fin structure, growing source and drain epitaxy in the second front source and drain region to form a front source and drain structure; depositing a third dielectric material on the front source and drain structure and in a pair of first grooves to form a front interlayer dielectric layer; photolithographically opening the front gate region of the first semiconductor structure, and depositing a metal material in the front gate region to form a front gate structure; performing gate cut-off processing on the front gate structure to form a front gate cut-off structure on both sides of the front gate structure; performing back-end processing on the front interlayer dielectric layer and the front gate structure to form a front back-end metal interconnect layer.

[0011] In some possible embodiments, a second semiconductor structure is formed based on a pair of second fin structures, including: depositing a third dielectric material in a pair of second grooves and a pair of third grooves to form a back interlayer dielectric layer; photolithographically opening a back gate region of the second semiconductor structure, and depositing a metal material in the back gate region to form a back gate structure; performing gate cut-off processing on the back gate structure to form a back gate cut-off structure on both sides of the back gate structure; and performing a back-end process on the first dielectric layer to form a back-end metal interconnection layer.

[0012] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by the method described in the above embodiment, and the semiconductor structure includes: a first semiconductor structure; the first semiconductor structure includes a first front source and drain region and a second front source and drain region arranged oppositely; the first semiconductor structure includes a pair of first fin structures; a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked; the second semiconductor structure includes a first back source and drain region and a second back source and drain region arranged oppositely; the second semiconductor structure includes a pair of second fin structures; a pair of transition layers; a pair of first fin structures, a pair of intermediate stacks and a pair of second fin structures are formed by the same process; a first power rail structure; the first power rail structure is located between the first sacrificial layers of a pair of intermediate stacks; the second power rail structure structure; the second power rail structure is located between a pair of second sacrificial layers of the middle stack; a pair of front metal electrical connection layers; a pair of front metal electrical connection layers are located between a pair of first fin structures and a transition layer in the first front source and drain region; the first power rail structure is located between a pair of front metal electrical connection layers; a pair of back metal electrical connection layers; a pair of back metal electrical connection layers are located between a pair of second fin structures and a transition layer in the second back source and drain region; the second power rail structure is located between a pair of back metal electrical connection layers; wherein the first back source and drain metal of the second semiconductor structure is connected to the front metal electrical connection layer through a first metal through hole; the second back source and drain metal through hole of the second semiconductor structure is connected to the back metal electrical connection layer through a second metal through hole; the back back metal interconnection layer in the second semiconductor structure is electrically connected to the first back source and drain metal and the second back source and drain metal.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the above embodiment.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, since the first power rail structure is located between a pair of front metal electrical connection layers, that is, the first power rail structure is connected to the front metal electrical connection layer, the front metal electrical connection layer is connected to the first back source and drain metal through the first metal through hole, and the first back source and drain metal is connected to the back back metal interconnection layer, so that the first power rail structure in the first semiconductor structure is electrically connected to the back back metal interconnection layer; since the second power rail structure is located between a pair of back metal electrical connection layers, that is, the second power rail structure is connected to the back metal electrical connection layer, the back metal electrical connection layer is connected to the second back source and drain metal through the second metal through hole, and the second back source and drain metal is connected to the back back metal interconnection layer, so that the second power rail structure in the second semiconductor structure is electrically connected to the back back metal interconnection layer; the electrical connection between the first power rail structure and the back back metal interconnection layer and the electrical connection between the second power rail structure and the back back metal interconnection layer provide a new solution for leading out a power rail structure (that is, the first power rail structure and the second power rail structure) inside the semiconductor structure.

[0016] Furthermore, the process flow of the embodiment of the present application is compatible with the standard process flow, and the above process flow can be applied to logic transistors (transistor logic) and static random-access memory (SRAM) only by modifying the photolithography plate according to actual needs.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0020] Figure 2 A design layout of a semiconductor structure in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of a semiconductor structure in an embodiment of the present application;

[0022] FIG. 4A to FIG. 4J is a schematic diagram of a semiconductor structure preparation process in an embodiment of the present application;

[0023] The above pictures:

[0024] 10. semiconductor structure; 11. first semiconductor structure; 111. first fin structure; 112. first power rail structure; 113. front metal electrical connection layer; 114. front spacer; 115. front gate dielectric layer; 116. front gate structure; 117. front gate cut-off structure; 118. front interlayer dielectric layer; 119. front source and drain metal; 1110. front back metal interconnection layer; 12. second semiconductor structure; 121. second fin structure; 122. second power rail structure; 123. back metal electrical connection layer; 127. back gate cut-off structure; 128. back interlayer dielectric layer; 1291. first back source and drain metal; 1292. second back source and drain metal; 1210. back back metal interconnection layer; 13. insulating layer; 14. carrier wafer; 21. substrate; 22. first stack; 23. second stack; 24. third stack; 25. hard mask; 26, intermediate stack; 261, first sacrificial layer; 262, transition layer; 263, second sacrificial layer; 271, first shallow trench isolation structure; 272, second shallow trench isolation structure; 273, third shallow trench isolation structure; 274, shallow trench isolation layer; 311, first oxide layer; 321, first dielectric wall structure; 322, second dielectric wall structure; 331, first photoresist layer; 332, second photoresist layer; 333, third photoresist layer; 341, first intermediate isolation layer; 342, second intermediate isolation layer; 41, first groove; 42, first gap; 43, second gap; 44, second groove; 45, third groove; 46, third gap; 47, first through hole; 48, second through hole; 51, front source and drain structure; 52, first dielectric layer; 53, first metal through hole; 54, second metal through hole; 55, first metal wire; 56, second metal wire. DETAILED DESCRIPTION

[0025] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0026] Traditional two-dimensional transistor structures face performance limitations and increased power consumption as device size continues to shrink. Stacked transistors can effectively increase device functionality and performance, and can be achieved without increasing device size. Stacked transistors refer to stacking multiple transistors together to form a three-dimensional structure to improve the performance and more functions of electronic devices.

[0027] Currently, in order to provide voltage, a power rail can be embedded inside the semiconductor structure. However, how to improve the power supply method inside the semiconductor structure and optimize the lead-out method of the power rail are still issues that need to be urgently addressed.

[0028] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a semiconductor structure, so as to provide a new solution for leading out a power rail structure inside the semiconductor structure.

[0029] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0030] In some embodiments, the semiconductor structure includes: a first semiconductor structure; the first semiconductor structure includes a first front source-drain region and a second front source-drain region that are oppositely arranged; the first semiconductor structure includes a pair of first fin structures; a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked; the second semiconductor structure includes a first back source-drain region and a second back source-drain region that are oppositely arranged; the second semiconductor structure includes a pair of second fin structures; a pair of intermediate stacks; the pair of first fin structures, the pair of intermediate stacks and the pair of second fin structures are formed by the same process; the intermediate stack includes a first sacrificial layer close to the first fin structure, a first sacrificial layer close to the second fin structure, and a second sacrificial layer close to the second fin structure. The second sacrificial layer of the structure and the transition layer located between the first sacrificial layer and the second sacrificial layer; a first power rail structure; the first power rail structure is located between the first sacrificial layer of a pair of intermediate stacks; a second power rail structure; the second power rail structure is located between the second sacrificial layer of a pair of intermediate stacks; a pair of front metal electrical connection layers; a pair of front metal electrical connection layers are located between a pair of first fin structures and the transition layer in the first front source and drain region; the first power rail structure is located between a pair of front metal electrical connection layers; a pair of back metal electrical connection layers; a pair of back metal electrical connection layers are located between a pair of second fin structures and the transition layer in the second back source and drain region; the second power rail structure is located between a pair of back metal electrical connection layers.

[0031] In some embodiments, the first back side source and drain metal of the second semiconductor structure is connected to the front side metal electrical connection layer through a first metal via; the second back side source and drain metal via of the second semiconductor structure is connected to the back side metal electrical connection layer through a second metal via; and the back side back-end metal interconnection layer in the second semiconductor structure is electrically connected to the first back side source and drain metal and the second back side source and drain metal.

[0032] In the embodiment of the present application, since the first metal through hole connects the first back source and drain metal and the front metal electrical connection layer, the front metal electrical connection layer is in contact with the first power rail structure, and the first back source and drain metal is connected to the back back-end metal interconnection layer, the first power rail structure is connected to the back back-end metal interconnection layer through the front metal electrical connection layer, the first metal through hole and the first back source and drain metal; correspondingly, since the second metal through hole connects the second back source and drain metal and the back metal electrical connection layer, the back metal electrical connection layer is in contact with the second power rail structure, and the second back source and drain metal is connected to the back back-end metal interconnection layer, the second power rail structure is connected to the back back-end metal interconnection layer through the back metal electrical connection layer, the second metal through hole and the second back source and drain metal.

[0033] In an embodiment of the present application, a pair of first fin structures, a pair of intermediate stacks and a pair of second fin structures are formed through the same process, so that the active area of ​​the first semiconductor structure and the active area of ​​the second semiconductor structure are self-aligned, and the self-alignment of the active area enables the first semiconductor structure and the second semiconductor structure to be self-aligned in a direction perpendicular to the active area.

[0034] In the embodiment of the present application, the active region is a collective name for the source region, the drain region and the channel region.

[0035] Combine the following Figure 2 The semiconductor structure shown illustrates the method for preparing the semiconductor structure provided in the embodiment of the present application.

[0036] Figure 1 : is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application, wherein the semiconductor structure includes a first semiconductor structure and a second semiconductor structure stacked together, wherein the first semiconductor structure includes a first front source-drain region and a second front source-drain region arranged oppositely, and the second semiconductor structure includes a first back source-drain region and a second back source-drain region arranged oppositely; see Figure 1 As shown, the method for preparing the semiconductor structure may include:

[0037] S101 , forming a pair of first fin structures, a pair of intermediate stacks, and a pair of second fin structures in sequence on a substrate.

[0038] The middle stack includes a first sacrificial layer close to the first fin structure, a second sacrificial layer close to the second fin structure, and a transition layer between the first sacrificial layer and the second sacrificial layer.

[0039] It can be understood that a first stack, a second stack and a third stack are sequentially stacked on the substrate. A pair of first fin structures, a pair of intermediate stacks and a pair of second fin structures are formed by etching the first stack, a pair of intermediate stacks are formed by etching the second stack, and a pair of second fin structures are formed by etching the third stack. The second stack is sequentially stacked from top to bottom: a first sacrificial layer, a transition layer and a second sacrificial layer; accordingly, after etching the second stack, a pair of intermediate stacks are also stacked from top to bottom: a first sacrificial layer, a transition layer and a second sacrificial layer; wherein the first sacrificial layer is in contact with the first fin structure, and the second sacrificial layer is in contact with the second fin structure.

[0040] In some embodiments, the first stack may be formed by alternately stacking a first semiconductor material layer and a second semiconductor material layer. For example, the first semiconductor material layer may be a silicon (Si) material layer, and the second semiconductor material layer may be a silicon germanium (SiGe) material layer. Similar to the first stack, the third stack may also be formed by alternately stacking a first semiconductor material layer and a second semiconductor material layer.

[0041] In some embodiments, the first sacrificial layer and the second sacrificial layer in the second stack may be formed of the same material, and the transition layer may be formed of a material different from that of the first sacrificial layer and the second sacrificial layer. For example, the first sacrificial layer and the second sacrificial layer may be formed of SiGe 1 material, and the transition layer may be formed of SiGe 2 material, wherein the Ge content in SiGe 1 is greater than the Ge content in SiGe 2. The material selected for the transition layer may be the same as the material selected for the second semiconductor material layer.

[0042] In some embodiments, the above S101 may include: depositing a mask material on the first stack to form a pair of hard masks arranged opposite to each other, the pair of hard masks being symmetrically arranged on both sides of the central axis of the first stack, and there being a gap between the pair of hard masks; under the masking action of the pair of hard masks, etching the first stack, the second stack and the third stack to form a pair of first fin structures, a pair of intermediate stacks and a pair of second fin structures.

[0043] It should be noted that the etching process mentioned in the embodiments of the present application may include but is not limited to any of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, and the embodiments of the present application do not specifically limit this.

[0044] In some possible embodiments, after S101 and before S102, the method may further include: depositing a second insulating material on a pair of first fin structures, a pair of intermediate stacks, a pair of second fin structures and the substrate to form a first shallow trench isolation structure; the first shallow trench isolation structure wraps the pair of first fin structures, the pair of intermediate stacks and the pair of second fin structures; etching a portion of the first shallow trench isolation structure until the first sacrificial layer in the pair of first fin structures and the pair of intermediate stacks is exposed; and depositing oxide on the surfaces of the pair of first fin structures and the first sacrificial layer to form a first oxide layer.

[0045] It can be understood that a first shallow trench isolation structure can be formed by depositing a second insulating material on a pair of hard masks, a pair of first fin structures, a pair of intermediate stacks, a pair of second fin structures and a substrate; after removing the pair of hard masks, a portion of the first shallow trench isolation structure is etched until the first fin structure and the first sacrificial layer are exposed; then, a layer of oxide is deposited on the upper surface of the etched first shallow trench isolation structure and the surface of the first fin structure and the first sacrificial layer to form a first oxide layer.

[0046] In the embodiment of the present application, the second insulating material forming the first shallow trench isolation structure may be any one of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc.

[0047] In some embodiments, after forming the first shallow trench isolation structure, the method may further include: performing a chemical-mechanical planarization (CMP) process on the first shallow trench isolation structure.

[0048] In an embodiment of the present application, chemical mechanical planarization is performed on the first shallow trench isolation structure, so that when the first shallow trench isolation structure is subsequently etched, the corresponding corrosion depths of the first shallow trench isolation structure in different areas are the same, thereby making the exposed fin structures (i.e., the first fin structure and the second fin structure) have the same height.

[0049] In the embodiment of the present application, the solvent used for etching the first shallow trench isolation structure may be: DHF solution or BOE solution. The solvent used in the etching process in the embodiment of the present application may be selected according to actual conditions and is not limited to the above DHF solution or BOE solution.

[0050] S102 , depositing a metal material with a preset height in a first region to form a first power rail structure.

[0051] The first region is located between the first sacrificial layers of a pair of intermediate stacked layers.

[0052] It can be understood that the first power rail structure is formed of a metal material and is located on the etched first shallow trench isolation structure and between a pair of first sacrificial layers.

[0053] In some embodiments, the above S102 may include: depositing metal material on the etched first shallow trench isolation structure until the height of the deposited metal material is the same as the height of a pair of first fin structures (or slightly higher / lower than the pair of first fin structures), and then removing a portion of the metal material by selective etching until the thickness of the retained metal material meets a preset height (i.e., the same as the height of the first sacrificial layer); removing the metal material located on the sides of the pair of first sacrificial layers by etching, and retaining the metal material located between the pair of first sacrificial layers to form a first power rail structure.

[0054] S103 , performing a fin cutting process in the first front source and drain region until the first fin-shaped structure and the first sacrificial layer in the first front source and drain region are removed to form a pair of first grooves and a pair of first gaps.

[0055] Wherein, a pair of first gaps are located between a pair of first fin-shaped structures and the transition layer; and the first groove is used to form a front interlayer dielectric layer of the first semiconductor structure.

[0056] It can be understood that removing the first fin structure located in the first front source and drain region can form a pair of first grooves; removing the pair of first sacrificial layers can form a pair of first gaps, and the pair of first gaps are located between the pair of first fin structures and the pair of transition layers.

[0057] In some embodiments, before the above S103, the above method may further include: depositing a second insulating material on the etched first shallow trench isolation structure and on a pair of first fin structures to form a second shallow trench isolation structure; the second shallow trench isolation structure wraps the pair of first fin structures and contacts the first shallow trench isolation structure; coating photoresist on the second shallow trench isolation structure to form a photoresist pattern; under the masking action of the photoresist, etching the first fin structure in the first front source and drain region to form a pair of first grooves; then, etching a pair of first sacrificial layers to form a pair of first gaps; finally, removing the second shallow trench isolation structure.

[0058] S104 , depositing a first insulating material in a pair of first gaps to form a first intermediate isolation layer.

[0059] It can be understood that a first insulating material is deposited on the etched first shallow trench isolation structure, and the deposition height is greater than the height of the first gap, so that the first gap is filled with the first insulating material; then, a portion of the first insulating material is removed by anisotropic etching, and only the first insulating material filled in the first gap is retained to form a pair of first intermediate isolation layers. The pair of first intermediate isolation layers are symmetrically arranged on both sides of the first power rail structure.

[0060] S105, etching the first intermediate isolation layer in the first front source and drain region to form a pair of second gaps.

[0061] It can be understood that a pair of first grooves formed after fin cutting in the first front source and drain area are used to fill the dielectric material to form a front interlayer dielectric layer; photoresist is coated on the front interlayer dielectric layer located in the first front source and drain area, and after the photolithography pattern is developed, the front interlayer dielectric layer can be photolithographically processed to form grooves, and the bottom of the grooves exposes the first intermediate isolation layer; the first intermediate isolation layer in the first front source and drain area is removed to form a pair of symmetrically arranged gaps (i.e., second gaps), and the pair of second gaps are symmetrically arranged on both sides of the first power rail.

[0062] In some embodiments, after forming the front interlayer dielectric layer, the front gate structure and the front gate cut-off structure of the first semiconductor structure, the above S105 may include: coating a photoresist on the front interlayer dielectric layer located in the first front source and drain region to form a photoresist board; under the masking action of the photoresist board, selectively etching the front interlayer dielectric layer, and stopping the etching to the upper surface of the first shallow trench isolation structure after etching until a portion of the first intermediate isolation layer is exposed and a pair of grooves are formed; then, selectively etching the first intermediate isolation layer in the above grooves until the first intermediate isolation layer in the first front source and drain region is removed to form a pair of second gaps.

[0063] S106, filling a pair of second gaps with metal material to form a pair of front metal electrical connection layers.

[0064] The first power rail structure is located between a pair of front metal electrical connection layers.

[0065] It is understandable that by filling the second gap with metal material, a pair of front metal electrical connection layers symmetrically arranged on both sides of the first power rail can be formed. Since the first power rail structure and the front metal electrical connection layer are both made of metal material, the first power rail structure and the front metal electrical connection layer can be electrically connected.

[0066] In some embodiments, the above S106 may include: filling a pair of second gaps and the above pair of grooves with metal material; removing the metal material in the above pair of grooves by isotropic etching, and only retaining the metal material in the second gaps to form a pair of symmetrically arranged front metal electrical connection layers. Finally, filling the above pair of grooves with dielectric material to re-form a complete front interlayer dielectric layer.

[0067] S107 , forming a first semiconductor structure based on a pair of first fin structures.

[0068] It can be understood that in addition to forming the first power rail structure, the first intermediate isolation layer and the front metal electrical connection layer in the first semiconductor structure mentioned in the above embodiment, in the process of preparing the first semiconductor structure, other structures in the first semiconductor structure can also be formed based on a pair of first fin structures, for example, a front source and drain structure, a front interlayer dielectric layer, a front gate structure, a front gate cut-off structure and a front back-end metal interconnection layer.

[0069] It should be noted that the implementation order of the above-mentioned process of S107 is not limited to be after the implementation order of the above-mentioned process of S106. The process order of S107 can be implemented before flipping the wafer according to actual design requirements.

[0070] In some possible embodiments, the above S107 may include: based on the first fin structure, growing source and drain epitaxy in the second front source and drain region to form a front source and drain structure; depositing a third dielectric material on the front source and drain structure and in a pair of first grooves to form a front interlayer dielectric layer; photolithographically opening the front gate region of the first semiconductor structure, and depositing a metal material in the front gate region to form a front gate structure; performing gate cut-off processing on the front gate structure to form a front gate cut-off structure on both sides of the front gate structure; performing back-end process processing on the front interlayer dielectric layer and the front gate structure to form a front back-end metal interconnection layer.

[0071] It can be understood that the front source and drain structure can be formed after fin cutting a pair of first fin structures in the first front source and drain region. Since the first fin structure in the first front source and drain region is removed, the front source and drain structure in the first semiconductor structure is formed in the second front source and drain region; the front interlayer dielectric layer can be prepared after forming the first intermediate isolation layer; the front gate structure can be prepared after forming the front source and drain structure; the front gate cut-off structure can be prepared after forming the front gate structure; and the front back-end metal interconnection layer can be prepared after forming the front gate cut-off structure.

[0072] In some embodiments, based on the first fin structure, growing source and drain epitaxy in the second front source and drain region to form the front source and drain structure may include: removing a portion of the first fin structure by etching to form a source and drain groove of the first semiconductor structure. In the source and drain groove of the first semiconductor structure, strained materials such as silicon germanium or silicon carbide are formed by selective epitaxial growth to fill the source and drain groove of the first semiconductor structure, and then a front source and drain structure is formed on the strained material by a heavy doping process.

[0073] It should be noted that, for ease of explanation, the front source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the front source structure and / or the front drain structure. In addition, the expressions such as the front source-drain region, the back source-drain region, the front source-drain metal, and the back source-drain metal mentioned in the embodiments of the present application, where "source and drain" are all abbreviations of "source and / or drain".

[0074] In some embodiments, the above-mentioned deposition of a third dielectric material on the front source and drain structure and in a pair of first grooves to form a front interlayer dielectric layer may include: depositing a third dielectric material (such as SiO2) on the front source and drain structure and in a pair of first grooves to form a front interlayer dielectric layer; the front interlayer dielectric layer may cover the first fin structure and wrap the front source and drain structure.

[0075] In some embodiments, before forming the front gate structure, the front gate region is filled with a front dummy gate structure, and a front spacer is deposited on the sidewall of the front dummy gate structure. Then, the above-mentioned photolithography opens the front gate region of the first semiconductor structure and deposits a metal material in the front gate region to form the front gate structure, which may include: removing the front dummy gate structure by etching to expose the front gate region of the first semiconductor structure, and depositing a metal material in the front gate region to form the front gate structure.

[0076] In some embodiments, the above-mentioned gate cut-off processing of the front gate structure to form a front gate cut-off structure on both sides of the front gate structure may include: coating a photoresist on the front gate structure and the front interlayer dielectric layer, and after the photoresist is developed, etching the front gate structure and the front interlayer dielectric layer according to the photolithography pattern to form a pair of first gate cut-off grooves; depositing an insulating material in the pair of first gate cut-off grooves to form a pair of front gate cut-off structures.

[0077] In some embodiments, the above-mentioned back-end process treatment on the front interlayer dielectric layer and the front gate structure to form a front back-end metal interconnection layer may include: performing interconnect line dielectric deposition, metal line formation, lead pad formation and other processes on the front interlayer dielectric layer and the front gate structure to form a front back-end metal interconnection layer of the first semiconductor structure.

[0078] In some embodiments, after forming the front gate cut-off structure, the method may further include: depositing a first dielectric material on the front interlayer dielectric layer and the front gate structure to form a second dielectric layer; etching the second dielectric layer and a portion of the front interlayer dielectric layer under the mask of the photoresist to form a front source-drain metal groove; the front source-drain metal groove is located above the front source-drain structure and contacts the front source-drain structure. Depositing a metal material in the front source-drain metal groove to form a front source-drain metal.

[0079] S108, flipping the wafer and removing the substrate.

[0080] It can be understood that after the first semiconductor structure is prepared, the first semiconductor structure is flipped over so that the substrate is placed upward, and then the substrate is removed until the surface of the first shallow trench isolation structure and the second fin structure away from the first fin structure is exposed.

[0081] In some possible implementations, before the above S108, the above method may further include: depositing an insulating material on the upper surface of the first semiconductor structure to form an insulating layer; and bonding the insulating layer to the carrier wafer.

[0082] In the embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped first semiconductor structure after inversion, thereby effectively preventing the first semiconductor structure from being broken by external force during the preparation of the second semiconductor structure.

[0083] In some possible embodiments, after S108 and before S109, the method may further include: etching a portion of the first shallow trench isolation structure until a pair of second fin structures and a second sacrificial layer in a pair of intermediate stacks are exposed, and a shallow trench isolation layer is formed; the shallow trench isolation layer corresponds to the transition layer in the intermediate stack; and depositing oxide on the surfaces of the pair of second fin structures and the second sacrificial layer to form a second oxide layer.

[0084] It can be understood that after flipping the wafer and removing the substrate, the etched first shallow trench isolation structure is exposed, and a portion of the first shallow trench isolation structure is removed until a pair of second fin structures and a pair of second sacrificial layers in a pair of intermediate stacks are exposed, and the first shallow trench isolation structure with a preset height is retained as a shallow trench isolation layer. The height of the shallow trench isolation layer can be consistent with the transition layer in the pair of intermediate stacks; then, a layer of oxide is deposited on the upper surface of the shallow trench isolation layer and the surfaces of the second fin structure and the second sacrificial layer to form a second oxide layer.

[0085] S109, depositing a metal material with a preset height in the second region to form a second power rail structure.

[0086] The second region is located between the second sacrificial layers of a pair of intermediate stacked layers.

[0087] It can be understood that the second power rail structure is formed of a metal material and is located on the shallow trench isolation layer and between a pair of second sacrificial layers.

[0088] In some embodiments, the above S109 may include: depositing metal material on the shallow trench isolation layer until the height of the deposited metal material is the same as the height of a pair of second fin structures (or slightly higher / lower than a pair of first fin structures), and then removing a portion of the metal material by selective etching until the thickness of the retained metal material meets a preset height (i.e., the same as the height of the second sacrificial layer); removing the metal material located on the sides of the pair of second sacrificial layers by etching, and retaining the metal material located between the pair of second sacrificial layers to form a second power rail structure.

[0089] S110, performing fin cutting processing in the first back side source and drain region and the second back side source and drain region until the second fin structure in the first back side source and drain region, the second fin structure in the second back side source and drain region and the second sacrificial layer are removed to form a pair of second grooves, a pair of third grooves and a pair of third gaps.

[0090] The pair of third gaps is located between the pair of second fin-shaped structures and the transition layer; the second groove and the third groove are used to form a back-side interlayer dielectric layer of the second semiconductor structure.

[0091] It can be understood that by removing the second fin structure located in the first back side source and drain region and the second fin structure located in the second back side source and drain region, a pair of second grooves and a pair of third grooves can be formed; by removing a pair of second sacrificial layers, a pair of third gaps can be formed, and the pair of third gaps are located between the pair of second fin structures and the pair of transition layers.

[0092] In some embodiments, before the above S110, the above method may further include: depositing a second insulating material on the shallow trench isolation layer and on a pair of second fin structures to form a third shallow trench isolation structure wrapping the second fin structure; coating photoresist on the third shallow trench isolation structure to form a photoresist pattern; under the masking action of the photoresist, etching the second fin structure in the first back side source and drain region and the second fin structure in the second back side source and drain region to form a pair of second grooves and a pair of third grooves; then, etching a pair of second sacrificial layers to form a pair of third gaps; finally, removing the third shallow trench isolation structure to expose the shallow trench isolation layer.

[0093] S111 , depositing a first insulating material in a pair of third gaps to form a second intermediate isolation layer.

[0094] It can be understood that the first insulating material is deposited on the shallow trench isolation layer, and the deposition height is greater than the height of the third gap, so that the third gap is filled with the first insulating material; then, a portion of the first insulating material is removed by anisotropic etching, and only the first insulating material filled in the third gap is retained to form a pair of second intermediate isolation layers. The pair of second intermediate isolation layers are symmetrically arranged on both sides of the second power rail structure.

[0095] S112, etching the second intermediate isolation layer in the second backside source / drain region to form a pair of fourth gaps.

[0096] It can be understood that a pair of second grooves formed after fin cutting in the first back source and drain region and a pair of third grooves formed after fin cutting in the second back source and drain region are used to fill the dielectric material to form a back interlayer dielectric layer; photoresist is coated on the back interlayer dielectric layer located in the second back source and drain region, and after the photolithography pattern is developed, the back interlayer dielectric layer can be photolithographically processed to form grooves, and the bottom of the grooves exposes the second intermediate isolation layer; the second intermediate isolation layer in the second back source and drain region is removed to form a pair of symmetrically arranged gaps (i.e., fourth gaps), and the pair of fourth gaps are symmetrically arranged on both sides of the second power rail.

[0097] In some embodiments, after forming the back interlayer dielectric layer, the back gate structure and the back gate cut-off structure of the second semiconductor structure, the above S112 may include: coating a photoresist on the back interlayer dielectric layer located in the second back source and drain region to form a photoresist; under the mask of the photoresist, selectively etching the back interlayer dielectric layer, and stopping the etching to the upper surface of the etched shallow trench isolation layer until a portion of the second intermediate isolation layer is exposed and a pair of grooves are formed; then, selectively etching the second intermediate isolation layer in the above grooves until the second intermediate isolation layer in the second back source and drain region is removed to form a pair of fourth gaps.

[0098] S113, filling a pair of fourth gaps with metal material to form a pair of back metal electrical connection layers.

[0099] The second power rail structure is located between a pair of back metal electrical connection layers.

[0100] It is understandable that by filling the fourth gap with metal material, a pair of back metal electrical connection layers symmetrically arranged on both sides of the second power rail can be formed. Since the second power rail structure and the back metal electrical connection layer are both made of metal material, the second power rail structure and the back metal electrical connection layer can be electrically connected.

[0101] In some embodiments, the above S113 may include: filling a pair of fourth gaps and the above pair of grooves with metal material; removing the metal material in the above pair of grooves by isotropic etching, and only retaining the metal material in the fourth gap to form a pair of symmetrically arranged back metal electrical connection layers. Finally, filling the above pair of grooves with dielectric material to re-form a complete back interlayer dielectric layer.

[0102] In some possible implementations, after S113, the method may further include: depositing a first dielectric material on the back interlayer dielectric layer to form a first dielectric layer; performing photolithography on the first dielectric layer and the back interlayer dielectric layer under the action of a photoresist mask to form a first back source / drain metal groove and a second back source / drain metal groove; the first back source / drain metal groove is located in the first back source / drain region, and the second back source / drain metal groove is located in the second back source / drain region; performing photolithography on the back interlayer dielectric layer at the bottom of the first back source / drain metal groove under the action of a photoresist mask to form a first through hole; the first through hole Extending to the first surface of the front metal electrical connection layer; the first surface is the surface of the front metal electrical connection layer close to the second intermediate isolation layer; under the action of the photoresist mask, the back interlayer dielectric layer located at the bottom of the second back source and drain metal groove is photoetched to form a second through hole; the second through hole extends to the second surface of the back metal electrical connection layer; the second surface is the surface of the back metal electrical connection layer away from the first intermediate isolation layer; metal material is filled in the first through hole, the second through hole, the first back source and drain metal groove and the second back source and drain metal groove to form a first metal through hole, a second metal through hole, a first back source and drain metal and a second back source and drain metal.

[0103] It can be understood that after forming the back metal electrical connection layer, a first dielectric layer can be formed on the back interlayer dielectric layer; then, a back source and drain metal groove of the second semiconductor structure is etched by photolithography; the back source and drain metal groove includes a first back source and drain metal groove located in the first back source and drain region and a second back source and drain metal groove located in the second back source and drain region; according to the design layout of the second semiconductor structure, photolithography is continued at the bottom of the back source and drain metal groove to etch a first through hole and a second through hole, the first through hole connects the first back source and drain metal groove and the front metal electrical connection layer, and the second through hole connects the second back source and drain metal groove and the back metal electrical connection layer. Through the same process, metal material is filled in the first through hole, the second through hole, the first back source and drain metal groove and the second back source and drain metal groove to form a first metal through hole, a second metal through hole, a first back source and drain metal and a second back source and drain metal.

[0104] In the embodiment of the present application, the first metal via connects the first back source and drain metal and the front metal electrical connection layer, and the front metal electrical connection layer is connected to the first power rail structure in the first semiconductor structure, so that the first power rail structure can be electrically connected to the first back source and drain metal. The second metal via connects the second back source and drain metal and the back metal electrical connection layer, and the back metal electrical connection layer is connected to the second power rail structure in the second semiconductor structure, so that the second power rail structure can be electrically connected to the second back source and drain metal.

[0105] S114 , forming a second semiconductor structure based on the pair of second fin structures.

[0106] Among them, the first back side source and drain metal of the second semiconductor structure is connected to the front side metal electrical connection layer through the first metal through hole; the second back side source and drain metal through hole of the second semiconductor structure is connected to the back side metal electrical connection layer through the second metal through hole; the back side back-end metal interconnection layer in the second semiconductor structure is electrically connected to the first back side source and drain metal and the second back side source and drain metal.

[0107] It can be understood that in addition to forming the second power rail structure, the second intermediate isolation layer and the back metal connection layer in the second semiconductor structure mentioned in the above embodiments, in the process of preparing the second semiconductor structure, other structures in the second semiconductor structure can also be formed based on a pair of second fin structures, such as a back interlayer dielectric layer, a back gate structure, a back gate cut-off structure and a back back metal interconnection layer.

[0108] It should be noted that the implementation order of the above-mentioned process of S114 is not limited to be after the implementation order of the above-mentioned process of S113, and the process order of S114 can be implemented after flipping the wafer according to actual design requirements.

[0109] In some possible implementations, the above S114 may include: depositing a third dielectric material in a pair of second grooves and a pair of third grooves to form a back interlayer dielectric layer; photolithographically opening a back gate region of the second semiconductor structure, and depositing a metal material in the back gate region to form a back gate structure; performing gate cut-off processing on the back gate structure to form a back gate cut-off structure on both sides of the back gate structure; and performing a back-end process on the first dielectric layer to form a back-end metal interconnection layer.

[0110] It can be understood that since the second fin structure in the first back source and drain region and the second fin structure in the second back source and drain region are removed, no back source and drain structure is formed in the second semiconductor structure; the back interlayer dielectric layer can be prepared after the second intermediate isolation layer is formed; the back gate structure can be prepared after the back source and drain structure is formed; the back gate cut-off structure can be prepared after the back gate structure is formed; and the back back-end metal interconnection layer can be prepared after the back gate cut-off structure is formed.

[0111] In an embodiment of the present application, the metal materials used to prepare the front gate structure and the back gate structure may include: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The materials of the front gate structure and the back gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0112] In some embodiments, the above-mentioned depositing a third dielectric material in a pair of second grooves and a pair of third grooves to form a back interlayer dielectric layer may include: depositing a third dielectric material (such as SiO2) in a pair of second grooves and a pair of third grooves to form a back interlayer dielectric layer; the back interlayer dielectric layer may cover the second fin structure.

[0113] In some embodiments, before forming the back gate structure, the back gate region is filled with a back dummy gate structure, and a back spacer is deposited on the sidewall of the back dummy gate structure. Then, the above-mentioned photolithography opens the back gate region of the second semiconductor structure and deposits a metal material in the back gate region to form the back gate structure, which may include: removing the back dummy gate structure by etching to expose the back gate region of the second semiconductor structure, and depositing a metal material in the back gate region to form the back gate structure.

[0114] It should be noted that the front gate structure and the back gate structure may be prepared using the same metal material or different metal materials, and this embodiment of the present application does not specifically limit this.

[0115] In some embodiments, the above-mentioned gate cut-off processing of the back gate structure to form a back gate cut-off structure on both sides of the back gate structure may include: coating a photoresist on the back gate structure and the back interlayer dielectric layer, and after the photoresist is developed, etching the back gate structure and the back interlayer dielectric layer according to the photolithography pattern to form a pair of second gate cut-off grooves; depositing an insulating material in the pair of second gate cut-off grooves to form a pair of back gate cut-off structures.

[0116] In some embodiments, the above-mentioned back-end process treatment on the first dielectric layer to form a back-end metal interconnection layer may include: performing processes such as interconnect line dielectric deposition, metal line formation, and lead pad formation on the first dielectric layer to form a back-end metal interconnection layer of the second semiconductor structure.

[0117] In some embodiments, in the back-end metal interconnect layer, metal wires can be led out above the first back-end source / drain metal and the second back-end source / drain metal to form a first metal wire contacting the first back-end source / drain metal and a second metal wire contacting the second back-end source / drain metal.

[0118] In some possible embodiments, after S102, the method may further include: depositing a second dielectric material between a pair of first fin structures and on the first power rail structure to form a first dielectric wall structure; a pair of first fin structures are symmetrically arranged on both sides of the first dielectric wall structure; after S109, the method may further include: depositing a second dielectric material between a pair of second fin structures and on the second power rail structure to form a second dielectric wall structure; a pair of second fin structures are symmetrically arranged on both sides of the second dielectric wall structure.

[0119] In some embodiments, the preparation method of the first semiconductor structure and the second semiconductor structure can reuse the preparation process of the fork transistor, that is, a first dielectric wall structure is set in the first semiconductor structure, and a second dielectric wall structure is set in the second semiconductor structure; in this way, the integration density of the semiconductor structure can be improved.

[0120] It can be understood that in the process of preparing the first semiconductor structure, after the first power rail structure is formed, the second dielectric material can be isotropically deposited on a pair of first fin structures and the first power rail structure, and the deposited second dielectric material wraps the first fin structure; then, by isotropically etching the second dielectric material, after the etching is completed, the second dielectric material of a preset height is retained between the pair of first fin structures, and the second dielectric material between the pair of first fin structures forms the above-mentioned first dielectric wall structure; the first dielectric wall structure divides the first semiconductor structure into two symmetrical parts. Correspondingly, in the process of preparing the second semiconductor structure, after the second power rail structure is formed, the second dielectric material can be isotropically deposited on a pair of second fin structures and the second power rail structure, and the deposited second dielectric material wraps the second fin structure; then, by isotropically etching the second dielectric material, after the etching is completed, the second dielectric material of a preset height is retained between the pair of second fin structures, and the second dielectric material between the pair of second fin structures forms the above-mentioned second dielectric wall structure; the second dielectric wall structure divides the second semiconductor structure into two symmetrical parts.

[0121] It should be noted that the height of the first dielectric wall structure can be designed according to actual needs, and when the first semiconductor structure is placed upward, in the horizontal direction, the height of the first dielectric wall structure is greater than the height of the uppermost Si layer in the first fin structure. Similarly, the height of the second dielectric wall structure can be designed according to actual needs, and when the second semiconductor structure is placed upward, in the horizontal direction, the height of the second dielectric wall structure is greater than the height of the uppermost Si layer in the second fin structure.

[0122] It should be noted that the first power rail structure and the second power rail structure can be connected to the back-end metal interconnection layer or to the front-end metal interconnection layer. The connection between the first power rail structure and the second power rail structure and the back-end metal interconnection layer mentioned in the above embodiment is only one example. When the first power rail structure and the second power rail structure are connected to the front-end metal interconnection layer, the preparation process of the first semiconductor structure can refer to the preparation method of the second semiconductor structure mentioned in the above embodiment. Correspondingly, the preparation of the second semiconductor structure can refer to the preparation method of the first semiconductor structure mentioned in the above embodiment.

[0123] Next, the semiconductor structure provided in the embodiment of the present application is described by taking the preparation process of the first semiconductor structure and the second semiconductor structure multiplexing fork transistor as an example. Figure 2 is the design layout of the semiconductor structure in the embodiment of the present application. Figure 2 (a) is a design layout of the first semiconductor structure in the semiconductor structure. Figure 2 (b) is a design layout of a second semiconductor structure in the semiconductor structure. Figure 3 This is a schematic diagram of a semiconductor structure in an embodiment of the present application. Figure 3 (a) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the first source / drain region (i.e., DD' direction); (b) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the second source / drain region (i.e., BB' direction); (c) is a cross-sectional view of the semiconductor structure taken along the extension direction of the first / second fin structure (i.e., EE' direction) between a pair of first / second fin structures.

[0124] It should be noted that the above-mentioned first source and drain region is the abbreviation of the first front source and drain region and the first back source and drain region, and correspondingly, the second source and drain region is the abbreviation of the second front source and drain region and the second back source and drain region.

[0125] See also Figure 3As shown, the semiconductor structure 10 includes: a first semiconductor structure 11 and a second semiconductor structure 12, wherein the first semiconductor structure 11 includes a first front source-drain region and a second front source-drain region that are oppositely arranged; the first semiconductor structure 11 also includes a pair of first fin structures 111; the second semiconductor structure 12 includes a first back source-drain region and a second back source-drain region that are oppositely arranged; the second semiconductor structure 12 also includes a pair of second fin structures 121; the first semiconductor structure 11 and the second semiconductor structure 12 are stacked. The semiconductor structure 10 also includes: a pair of transition layers 262; the pair of first fin structures 111, the pair of transition layers 262 and the pair of second fin structures 121 are formed by the same process. The semiconductor structure 10 also includes: a first power rail structure 112; the first power rail structure 112 is located between the first sacrificial layers 261 of a pair of intermediate stacks 26; a second power rail structure 122; the second power rail structure 122 is located between the second sacrificial layers 263 of a pair of intermediate stacks 26. The semiconductor structure 10 also includes: a pair of front metal connection layers 113; a pair of front metal connection layers 113 are located between a pair of first fin structures 111 and the transition layer 262 in the first front source and drain regions; a first power rail structure 112 is located between a pair of front metal connection layers 113; a pair of back metal connection layers 123; a pair of back metal connection layers 123 are located between a pair of second fin structures 121 and the transition layer 262 in the second back source and drain regions; and a second power rail structure 122 is located between a pair of back metal connection layers 123.

[0126] In combination with the above preparation method, Figure 3 The preparation process of the semiconductor structure 10 is described below. Figure 3 The semiconductor structure 10 shown may be FIG. 4A to FIG. 4J The process shown is prepared FIG. 4A to FIG. 4J Schematic diagram of the preparation process of the semiconductor structure in the embodiment of the present application.

[0127] In one example, taking the preparation process of the first semiconductor structure 11 and the second semiconductor structure 12 multiplexing the fork transistor as an example, the preparation process of the semiconductor structure 10 may include the following steps:

[0128] Step 1: Provide a substrate 21, on which a first stack 22, a second stack 23 and a third stack 24 are sequentially stacked (see Figure 4A (a) in the figure.

[0129] The substrate 21 is a Si substrate, the first stack 22 is formed by alternately depositing Si layers and SiGe 2 layers, the third stack 24 is formed by alternately depositing Si layers and SiGe 2 layers, and the second stack 23 is a SiGe 1 layer, a Si layer, and a SiGe 1 layer stacked in sequence.

[0130] Step 2: Deposit a mask material on the third stack 24 to form a pair of hard masks 25 (see Figure 4A (b) in the figure.

[0131] Step 3: Under the masking action of a pair of hard masks 25, the third stack 24, the second stack 23 and the first stack 22 are etched, and the etching stops at the substrate 21 to form the first fin structure 111, the second fin structure 121 and the intermediate stack 26 (see Figure 4A (c) in the figure.

[0132] The intermediate stack 26 includes a first sacrificial layer 261 close to the first fin structure 111 , a second sacrificial layer 263 close to the second fin structure 121 , and a transition layer 262 between the first sacrificial layer 261 and the second sacrificial layer 263 .

[0133] Step 4: Deposit a second insulating material on the first fin structure 111, the second fin structure 121, the intermediate stack 26 and the substrate 21 to form a first shallow trench isolation structure 271 (see Figure 4A (d) in the figure.

[0134] Step 5: Remove the pair of hard masks 25 (see Figure 4A (e) in the figure.

[0135] Step 6: Remove a portion of the first shallow trench isolation structure 271 by etching until the first fin structure 111 and the first sacrificial layer 261 are exposed (see Figure 4A (f) in the figure.

[0136] Step 7: Deposit oxide on the substrate 21, the first fin structure 111 and the first sacrificial layer 261 to form a first oxide layer 311 (see Figure 4A (g) in the figure.

[0137] Step 8: Deposit a metal material on the first shallow trench isolation structure 271 and between the pair of first fin structures 111. The height of the deposited metal material in the horizontal direction may be consistent with the height of the first fin structure 111 (see Figure 4A (h) in the figure.

[0138] Step 9: Remove a portion of the metal material deposited in the eighth step by selective etching to form a metal material layer located above the first shallow trench isolation structure 271. In the horizontal direction, the height of the metal material layer can be greater than the height of the first sacrificial layer 261 and less than the height of the Si layer at the bottom of the first fin structure 111 (see Figure 4A (i) in the figure.

[0139] Step 10: Depositing oxide on the metal material layer to form an oxide layer covering the metal material layer (see Figure 4B (a) in the figure.

[0140] Step 11: isotropically deposit a second dielectric material on the metal material layer and between the pair of first fin structures 111, and the deposited second dielectric material wraps the first fin structure 111 (see Figure 4B (b) in the figure.

[0141] Step 12: isotropically etch the second dielectric material deposited in step 11, by strictly controlling the time of depositing the second dielectric material in step 11 and the etching rate and time in step 12, so that a portion of the second dielectric material is left between the first fin structures 111, forming a first dielectric wall structure 321 (see Figure 4B (c) in the figure.

[0142] It should be noted that, in the twelfth step, the above process can also be implemented by photolithography. For example, under the action of the photoresist mask, the second dielectric material on both sides is first etched to retain the second dielectric material located between the first fin structures 111. After the photolithography is completed, the photoresist is removed and the second dielectric material located between the first fin structures 111 is further etched until the first dielectric wall structure 321 is formed.

[0143] Step 13: Remove the exposed first oxide layer 311 and the oxide layer formed in step 10 (see Figure 4B (d) in the figure.

[0144] Step 14: Deposit a mask material to form a hard mask. Under the action of the hard mask, etch a portion of the metal material layer formed in step 9 to retain the metal material between the pair of first fin structures 111 to form a first power rail structure 112 (see Figure 4B (e) in the figure.

[0145] Step 15: Deposit a second insulating material on the first shallow trench isolation structure 271 and the first fin structure 111 to form a second shallow trench isolation structure 272. The second shallow trench isolation structure 272 wraps the first fin structure 111 (see Figure 4B (f) in the figure.

[0146] Step 16: Coat photoresist on the second shallow trench isolation structure 272 to form a first photoresist layer 331 (see Figure 4C (a) in the figure.

[0147] Step 17: Under the masking effect of the first photoresist layer 331, the first fin structure 111 in the first front source and drain region is etched to form a pair of first grooves 41; the first sacrificial layer 261 is etched to form a first gap 42 (see Figure 4C(b) in the figure.

[0148] Step 18: Remove the first photoresist layer 331 (see Figure 4C (c) in the figure.

[0149] Step 19: Fill the first groove 41 and the first gap 42 with a second insulating material to re-form a complete second shallow trench isolation structure 272 (see Figure 4C (d) in the figure.

[0150] Step 20: Etch the second shallow trench isolation structure 272 until the first power rail structure 112 is exposed (see Figure 4C (e) in the figure.

[0151] Step 21: According to the standard process for manufacturing transistors, a front source-drain structure 51 is formed in the second front source-drain region (see Figure 4D (a) in the figure.

[0152] Step 22: Fill the first gap 42 with a first insulating material to form a first intermediate isolation layer 341 (see Figure 4D (b) in the figure.

[0153] Step 23: According to the standard process for preparing transistors, a front spacer 114, a front gate dielectric layer 115 and a front gate structure 116 are formed (see Figure 4E (a) in the figure.

[0154] Step 24: According to the design layout of the first semiconductor structure, a front gate cut-off structure 117 is formed (see Figure 4E (b) in the figure.

[0155] It should be noted that forming the front gate cut-off structure 117 is only one example of the method for preparing a semiconductor structure. According to actual needs, the front gate cut-off structure 117 may not be formed in the first semiconductor structure, and the embodiment of the present application does not make any specific limitation on this.

[0156] Step 25: Coat photoresist on the front interlayer dielectric layer 118 in the first front source / drain region to form a second photoresist layer 332 (see Figure 4F (a) in the figure.

[0157] Step 26: Under the masking effect of the second photoresist layer 332, a portion of the front interlayer dielectric layer 118 is selectively etched to form a pair of symmetrically arranged grooves and expose the first intermediate isolation layer 341 (see Figure 4F (b) in the figure.

[0158] Step 27: Based on the exposed first intermediate isolation layer 341, the first intermediate isolation layer 341 located in the first front source and drain region is removed to form a pair of second gaps 43 (see Figure 4F (c) in the figure.

[0159] Step 28: Remove the oxide layer on the surface of the first power rail structure 112 that contacts the second gap 43 (see Figure 4F (d) in the figure.

[0160] Step 29: Fill the pair of grooves and the pair of second gaps 43 formed in step 26 with metal material (see Figure 4F (e) in the figure.

[0161] Step 30: Remove the metal material on both sides of the front interlayer dielectric layer 118 to form a pair of front metal electrical connection layers 113 and a pair of grooves (see Figure 4F (f) in the figure.

[0162] Step 31: Remove the second photoresist layer 332 (see Figure 4F (g) in the figure.

[0163] Step 32: Fill the groove formed in step 30 with dielectric material to re-form a complete front interlayer dielectric layer 118 (see Figure 4F (h) in the figure.

[0164] Step 33: According to the standard process for manufacturing transistors, the front source and drain metal 119 and the front back-end metal interconnection layer 1110 in the first semiconductor structure 11 are formed (see Figure 4G (a) in the figure.

[0165] Step 34: Deposit an insulating layer 13 on the surface of the front back-end metal interconnect layer 1110, and then bond the insulating layer 13 to the carrier wafer 14. Flip the first semiconductor structure 11 and remove the substrate 21, so that the surface of the second fin structure 121 away from the first fin structure 111 is exposed (see Figure 4G (b) in the figure.

[0166] Step 35: According to the above process of preparing the first power rail structure 112 and the first dielectric wall structure 321 in the first semiconductor structure 11, prepare the second power rail structure 122, the second dielectric wall structure 322 and the third shallow trench isolation structure 273 in the second semiconductor structure 12 (see Figure 4G (c) in the figure.

[0167] Step 36: Coat photoresist on the third shallow trench isolation structure 273 located in the first back source and drain region and the second back source and drain region to form a third photoresist layer 333 (see Figure 4H (a) in the figure.

[0168] Step 37: Under the masking effect of the third photoresist layer 333, the second fin structure 121 in the first back source and drain region and the second fin structure 121 in the second back source and drain region are removed to form a pair of second grooves 44 and a pair of third grooves 45; the second sacrificial layer 263 is removed to form a pair of third gaps 46 (see Figure 4H (b) in the figure.

[0169] Step 38: Remove the third photoresist layer 333, fill the second insulating material in the second groove 44, the third groove 45 and the third gap 46, re-form a complete third shallow trench isolation structure 273, etch the third shallow trench isolation structure 273 until the second power rail structure 122 is exposed, and form a shallow trench isolation layer 274 (see Figure 4H (c) in the figure.

[0170] Step 39: According to the above-mentioned process of preparing the first intermediate isolation layer 341, the front metal connection layer 113, and the front gate cut-off structure 117 in the first semiconductor structure 11, the second intermediate isolation layer 342, the back metal connection layer 123 and the back gate cut-off structure 127 in the second semiconductor structure 12 are formed, and the back interlayer dielectric layer 128 is formed (see Fig. 4I (a) in the figure.

[0171] It should be noted that forming the back gate cut-off structure 127 is only one example of the method for preparing a semiconductor structure. According to actual needs, the back gate cut-off structure 127 may not be formed in the second semiconductor structure, and the embodiments of the present application do not make any specific limitations on this.

[0172] Step 40: Deposit a first dielectric material on the back interlayer dielectric layer 128 to form a first dielectric layer 52 (see Fig. 4I (b) in the figure.

[0173] Step 41: Coat a photoresist (not shown) on the first dielectric layer 52, and under the masking effect of the photoresist layer, etch a portion of the first dielectric layer 52 and the back interlayer dielectric layer 128 located in the first back source and drain region and the second back source and drain region to form a first back source and drain metal groove and a second back source and drain metal groove (see Fig. 4I (c) in the figure.

[0174] Step 42: Coat a photoresist (not shown in the figure), and under the masking effect of the photoresist layer, perform photolithography on the back interlayer dielectric layer 128 located at the bottom of the first back source and drain metal groove to form a first through hole 47; perform photolithography on the back interlayer dielectric layer 128 located at the bottom of the second back source and drain metal groove to form a second through hole 48 (see Figure 4J (a) in the figure.

[0175] Step 43: Fill the first back source and drain metal groove, the second back source and drain metal groove, the first through hole 47 and the second through hole 48 with metal material to form the first back source and drain metal 1291, the second back source and drain metal 1292, the first metal through hole 53 and the second metal through hole 54 (see Figure 4J (b) in the figure.

[0176] Step 44: According to the standard process for preparing transistors, a back-end metal interconnection layer 1210 is formed in the second semiconductor structure 12, wherein the first metal line 55 in the back-end metal interconnection layer 1210 is connected to the first back-end source-drain metal 1291, and the second metal line 56 in the back-end metal interconnection layer 1210 is connected to the second back-end source-drain metal 1292 (see Figure 4J (c) in the figure.

[0177] At this point, the semiconductor structure 10 is completed by using the process of multiplexing the fork transistor.

[0178] It should be noted that the first power rail structure and the second power rail structure are electrically connected to the back-end metal interconnection layer through the front metal electrical connection layer, the back metal electrical connection layer, the source and drain metal (i.e., the first back source and drain metal and the second back source and drain metal), the metal through-hole (the first metal through-hole and the second metal through-hole), and the metal wire (i.e., the first metal wire and the second metal wire). The embodiment of the present application does not specifically limit the position, size and number of the source and drain metal, the metal through-hole and the metal wire, and can be designed according to actual needs to meet the interconnection requirements and basic design rules.

[0179] In the embodiment of the present application, since the first power rail structure is located between a pair of front metal electrical connection layers, that is, the first power rail structure is connected to the front metal electrical connection layer, the front metal electrical connection layer is connected to the first back source and drain metal through the first metal through hole, and the first back source and drain metal is connected to the back back metal interconnection layer, so that the first power rail structure in the first semiconductor structure is electrically connected to the back back metal interconnection layer; since the second power rail structure is located between a pair of back metal electrical connection layers, that is, the second power rail structure is connected to the back metal electrical connection layer, the back metal electrical connection layer is connected to the second back source and drain metal through the second metal through hole, and the second back source and drain metal is connected to the back back metal interconnection layer, so that the second power rail structure in the second semiconductor structure is electrically connected to the back back metal interconnection layer; the electrical connection between the first power rail structure and the back back metal interconnection layer and the electrical connection between the second power rail structure and the back back metal interconnection layer provide a new type of power rail structure (that is, the first power rail structure and the second power rail structure) lead-out solution inside the semiconductor structure.

[0180] Furthermore, the process flow of the embodiment of the present application is compatible with the standard process flow, and the above process flow can be applied to logic transistors (transistor logic) and static random-access memory (SRAM) only by modifying the photolithography plate according to actual needs.

[0181] Furthermore, the semiconductor structure provided in the embodiment of the present application can be detected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the semiconductor structure provided in the embodiment of the present application can be detected by TEM slicing, such as the first metal via, the second metal via, the connection relationship between the first power rail structure and the back-end metal interconnection layer, the connection relationship between the second power rail structure and the back-end metal interconnection layer, etc.

[0182] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 3 The semiconductor structure shown will not be described in detail here.

[0183] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 3 , I will not go into details here.

[0184] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0185] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, It is characterized in that The semiconductor structure comprises a first semiconductor structure and a second semiconductor structure which are stacked, wherein the first semiconductor structure comprises a first front source-drain region and a second front source-drain region which are oppositely arranged, and the second semiconductor structure comprises a first back source-drain region and a second back source-drain region which are oppositely arranged; The method comprises: A pair of first fin structures, a pair of intermediate stacks and a pair of second fin structures are sequentially formed on the substrate; the intermediate stacks include a first sacrificial layer close to the first fin structure, a second sacrificial layer close to the second fin structure and a transition layer between the first sacrificial layer and the second sacrificial layer; Depositing a metal material of a preset height in a first region to form a first power rail structure; the first region is located between the first sacrificial layers of the pair of intermediate stacks; Performing fin cutting processing in the first front source and drain region until the first fin-shaped structure and the first sacrificial layer in the first front source and drain region are removed to form a pair of first grooves and a pair of first gaps; the pair of first gaps are located between the pair of first fin structures and the transition layer; the first groove is used to form a front interlayer dielectric layer of the first semiconductor structure; depositing a first insulating material in the pair of first gaps to form a first intermediate isolation layer; Etching the first intermediate isolation layer in the first front source / drain region to form a pair of second gaps; Filling the pair of second gaps with metal material to form a pair of front metal electrical connection layers; the first power rail structure is located between the pair of front metal electrical connection layers; Based on the pair of first fin structures, forming the first semiconductor structure; flipping the wafer and removing the substrate; Depositing a metal material of a preset height in a second region to form a second power rail structure; the second region is located between the second sacrificial layers of the pair of intermediate stacks; Performing fin cutting processing in the first back source and drain region and the second back source and drain region until the second fin structure in the first back source and drain region, the second fin structure in the second back source and drain region, and the second sacrificial layer are removed to form a pair of second grooves, a pair of third grooves, and a pair of third gaps; the pair of third gaps are located between the pair of second fin structures and the transition layer; the second groove and the third groove are used to form a back interlayer dielectric layer of the second semiconductor structure; depositing a first insulating material in the pair of third gaps to form a second intermediate isolation layer; Etching the second intermediate isolation layer in the second back source and drain region to form a pair of fourth gaps; Filling the pair of fourth gaps with metal material to form a pair of back metal electrical connection layers; the second power rail structure is located between the pair of back metal electrical connection layers; Based on the pair of second fin structures, forming the second semiconductor structure; Among them, the first back side source and drain metal of the second semiconductor structure is connected to the front side metal electrical connection layer through a first metal via; the second back side source and drain metal via of the second semiconductor structure is connected to the back side metal electrical connection layer through a second metal via; and the back side back-end metal interconnection layer in the second semiconductor structure is electrically connected to the first back side source and drain metal and the second back side source and drain metal.

2. The method according to claim 1, It is characterized in that After forming the back metal connection layer, the method further comprises: Depositing a first dielectric material on the back interlayer dielectric layer to form a first dielectric layer; Under the action of a photoresist mask, photolithography is performed on the first dielectric layer and the back interlayer dielectric layer to form a first back source / drain metal groove and a second back source / drain metal groove; the first back source / drain metal groove is located in the first back source / drain region, and the second back source / drain metal groove is located in the second back source / drain region; Under the action of the photoresist mask, the back-side interlayer dielectric layer located at the bottom of the first back-side source-drain metal groove is photoetched to form a first through hole; the first through hole extends to the first surface of the front-side metal electrical connection layer; the first surface is the surface of the front-side metal electrical connection layer close to the second intermediate isolation layer; Under the action of the photoresist mask, the back interlayer dielectric layer located at the bottom of the second back source and drain metal groove is photoetched to form a second through hole; the second through hole extends to the second surface of the back metal electrical connection layer; the second surface is the surface of the back metal electrical connection layer away from the first intermediate isolation layer; Metal material is filled in the first through hole, the second through hole, the first back side source and drain metal groove, and the second back side source and drain metal groove to form a first metal through hole, a second metal through hole, the first back side source and drain metal, and the second back side source and drain metal.

3. The method according to claim 1, It is characterized in that After forming the first power rail structure, the method further includes: depositing a second dielectric material between the pair of first fin structures and on the first power rail structure to form a first dielectric wall structure; the pair of first fin structures are symmetrically arranged on both sides of the first dielectric wall structure; After forming the second power rail structure, the method further includes: depositing the second dielectric material between the pair of second fin structures and on the second power rail structure to form a second dielectric wall structure; the pair of second fin structures are symmetrically arranged on both sides of the second dielectric wall structure.

4. The method according to claim 1, It is characterized in that Before depositing a metal material of a preset height in the first region to form a first power rail structure, the method further includes: Depositing a second insulating material on the pair of first fin structures, the pair of intermediate stacks, the pair of second fin structures and the substrate to form a first shallow trench isolation structure; the first shallow trench isolation structure encapsulates the pair of first fin structures, the pair of intermediate stacks and the pair of second fin structures; Etching a portion of the first shallow trench isolation structure until the pair of first fin structures and the first sacrificial layer in the pair of middle stacks are exposed; Oxide is deposited on surfaces of the pair of first fin structures and the first sacrificial layer to form a first oxide layer.

5. The method according to claim 4, It is characterized in that Before depositing a metal material of a preset height in the second region to form a second power rail structure, the method further includes: Etching a portion of the first shallow trench isolation structure until the pair of second fin structures and the second sacrificial layer in the pair of intermediate stacks are exposed, and forming a shallow trench isolation layer; the shallow trench isolation layer corresponds to the transition layer in the intermediate stack; Oxide is deposited on surfaces of the pair of second fin structures and the second sacrificial layer to form a second oxide layer.

6. The method according to claim 1, It is characterized in that The forming of the first semiconductor structure based on the pair of first fin structures includes: Based on the first fin structure, growing source and drain epitaxy in the second front source and drain region to form a front source and drain structure; Depositing a third dielectric material on the front source-drain structure and in the pair of first grooves to form the front interlayer dielectric layer; Photolithographically opening a front gate region of the first semiconductor structure, and depositing a metal material in the front gate region to form a front gate structure; Performing a gate cut-off process on the front gate structure to form a front gate cut-off structure on both sides of the front gate structure; A back-end process is performed on the front interlayer dielectric layer and the front gate structure to form a front back-end metal interconnection layer.

7. The method according to claim 2, It is characterized in that The forming of the second semiconductor structure based on the pair of second fin structures comprises: Depositing a third dielectric material in the pair of second grooves and the pair of third grooves to form the back-side interlayer dielectric layer; Photolithographically opening a back gate region of the second semiconductor structure, and depositing a metal material in the back gate region to form a back gate structure; Performing a gate cut-off process on the back gate structure to form a back gate cut-off structure on both sides of the back gate structure; A back-end process is performed on the first dielectric layer to form a back-end metal interconnection layer.

8. A semiconductor structure, It is characterized in that Prepared by the method according to any one of claims 1 to 7, the semiconductor structure comprises: A first semiconductor structure; the first semiconductor structure comprises a first front source-drain region and a second front source-drain region which are arranged opposite to each other; the first semiconductor structure comprises a pair of first fin structures; a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked; the second semiconductor structure comprises a first back source and drain region and a second back source and drain region which are arranged opposite to each other; the second semiconductor structure comprises a pair of second fin structures; A pair of transition layers; the pair of first fin structures, the pair of intermediate stacks and the pair of second fin structures are formed by the same process; a first power rail structure; the first power rail structure is located between the first sacrificial layers of the pair of intermediate stacks; a second power rail structure; the second power rail structure is located between the second sacrificial layers of the pair of intermediate stacks; A pair of front metal electrical connection layers; the pair of front metal electrical connection layers are located between the pair of first fin structures and the transition layer in the first front source and drain region; the first power rail structure is located between the pair of front metal electrical connection layers; a pair of back metal electrical connection layers; the pair of back metal electrical connection layers are located between the pair of second fin structures and the transition layer in the second back source and drain region; the second power rail structure is located between the pair of back metal electrical connection layers; Among them, the first back side source and drain metal of the second semiconductor structure is connected to the front side metal electrical connection layer through a first metal via; the second back side source and drain metal via of the second semiconductor structure is connected to the back side metal electrical connection layer through a second metal via; and the back side back-end metal interconnection layer in the second semiconductor structure is electrically connected to the first back side source and drain metal and the second back side source and drain metal.

9. A semiconductor device, It is characterized in that include: The semiconductor structure as claimed in claim 8.

10. An electronic device, It is characterized in that include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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