Power submodule and power module having the same

Abstract

The present invention provides a power submodule and a power module having the same, the power submodule comprising: an upper half-bridge unit, comprising an upper substrate, a plurality of upper MOSFET chips in parallel, an upper series diode and a plurality of upper diode chips in parallel, the number of upper MOSFET chips being an even number, and two upper MOSFET chips being an upper MOSFET chipset, and an upper series diode being arranged between the two upper MOSFET chipsets; a lower half-bridge unit, comprising a lower substrate, a plurality of lower MOSFET chips in parallel, a lower series diode and a plurality of lower diode chips in parallel, the number of lower MOSFET chips being an even number, and two lower MOSFET chips being a lower MOSFET chipset, and a lower series diode being arranged between the two lower MOSFET chipsets. Through the technical solution provided by the present application, the problem that the parasitic inductance of the power module in the related art is large and the application of silicon carbide devices in the high voltage field is limited can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and in particular to a power submodule and a power module having the same. Background Art

[0002] The fully controlled device power field effect transistor (MOSFET) is a semiconductor device. It is a voltage-controlled device that uses gate voltage to control the flow of current. MOSFET is a field effect transistor with a metal-oxide-semiconductor (MOS) structure and is widely used in various electronic circuits, especially in the field of power electronics. The fully controlled device power field effect transistor (MOSFET) is considered to be an ideal switching device due to its advantages such as high input impedance, fast switching rate and low driving requirements. However, the power handling capacity of traditional silicon-based power MOSFET devices in the high voltage field is limited by the internal resistance of the chip. How to reduce the chip on-resistance and increase the chip breakdown voltage is the research focus of the next generation of power MOSFET devices.

[0003] In the relevant technology, wide bandgap semiconductor materials represented by silicon carbide materials are considered to be ideal materials for the next generation of high-voltage power devices due to their excellent material properties: wide bandgap width, high critical breakdown field strength, and high saturated carrier mobility. Among all silicon carbide devices, silicon carbide MOSFET has the advantages of low on-resistance, fast switching speed, and high withstand voltage, and has gradually replaced silicon-based MOSFET and IGBT devices. Due to the low current level of a single chip, multiple chips are generally packaged in parallel to form a high-efficiency module in high-current applications. At present, the packaging of silicon carbide power modules still uses the packaging of traditional silicon-based power modules. The parasitic inductance of the power module is large, and the switching speed of silicon carbide is fast. The large parasitic inductance produces a large voltage overshoot during the switching transient, which seriously limits the application of silicon carbide devices in the high-voltage field and cannot give full play to the advantage of silicon carbide's high withstand voltage.

[0004] Therefore, in the related art, there is a problem that the parasitic inductance of the power module is large, which limits the application of silicon carbide devices in the high voltage field. Summary of the invention

[0005] The present invention provides a power submodule and a power module having the same, so as to solve the problem that the parasitic inductance of the power module in the related art is large, which limits the application of silicon carbide devices in the high voltage field.

[0006] According to one aspect of the present invention, a power sub-module is provided, the power sub-module comprising: an upper half-bridge unit, comprising an upper substrate, a plurality of upper MOSFET chips connected in parallel, an upper series diode and a plurality of upper diode chips connected in parallel, the number of the upper MOSFET chips is an even number, and two upper MOSFET chips form an upper MOSFET chip group, an upper series diode is arranged between the two upper MOSFET chip groups, the drain of the upper MOSFET chip is connected to the first upper drain conductive layer of the upper substrate, the power source of the upper MOSFET chip is connected to the anode of the upper diode chip, the cathode of the upper series diode is connected to the first upper drain conductive layer, the anode of the upper series diode is connected to the second upper drain conductive layer of the upper substrate, the cathode of the upper diode chip is connected to the second upper drain conductive layer, the anode of the upper diode chip is connected to the upper power source conductive layer of the upper substrate, The lower half-bridge unit comprises a lower substrate, a plurality of lower MOSFET chips connected in parallel, a lower series diode and a plurality of lower diode chips connected in parallel, the number of the lower MOSFET chips is an even number, and two lower MOSFET chips form a lower MOSFET chipset, a lower series diode is arranged between the two lower MOSFET chipsets, the drain of the lower MOSFET chip is connected to the first lower drain conductive layer of the lower substrate, the power source of the lower MOSFET chip is connected to the anode of the lower diode chip, the cathode of the lower series diode is connected to the first lower drain conductive layer, the anode of the lower series diode is connected to the second lower drain conductive layer of the lower substrate, the cathode of the lower diode chip is connected to the second lower drain conductive layer, the anode of the lower diode chip is connected to the lower power source conductive layer of the lower substrate, and the upper power source conductive layer is connected to the second lower drain conductive layer.

[0007] Furthermore, the upper half-bridge unit also includes an upper drain power terminal, which is connected to the second upper drain conductive layer; the lower half-bridge unit also includes a first lower output power terminal, a second lower output power terminal and a lower power source power terminal, the lower power source power terminal is connected to the lower power source conductive layer, and the first lower output power terminal and the second lower output power terminal are respectively connected to the second lower drain conductive layer.

[0008] Further, the upper drain power terminal, the first lower output power terminal, the second lower output power terminal and the lower power source power terminal are all low-thread power terminals.

[0009] Furthermore, two upper power source conductive layers are arranged on the upper substrate, and the two upper power source conductive layers are respectively arranged on both sides of the upper drain power terminal; the second lower drain conductive layer includes a first section, a second section and a third section, the first section and the third section are respectively connected to the two ends of the second section, the first section and the third section are located on the same side of the second section, a plurality of lower diode chips are arranged on the second section at intervals along the extension direction of the second section, the second lower output power terminal is arranged on the first section, and the first lower output power terminal is arranged on the third section; the first section is connected to one of the upper power source conductive layers, and the third section is connected to the other upper power source conductive layer.

[0010] Furthermore, the second upper drain conductive layer includes a fourth segment and a fifth segment which are perpendicular to each other, one end of the fifth segment is connected to the middle of the fourth segment, a plurality of upper diode chips are arranged on the fourth segment at intervals along the length direction of the fourth segment, and the upper drain power terminal is arranged on the fifth segment.

[0011] Furthermore, the first section is connected to one of the upper power source conductive layers through a first bridge arm connecting bonding wire, and the third section is connected to another upper power source conductive layer through a second bridge arm connecting bonding wire.

[0012] Further, the gate of the upper MOSFET chip is connected to the first upper gate conductive layer of the upper substrate, the driving source of the upper MOSFET chip is connected to the upper driving source conductive layer of the upper substrate, the upper half-bridge unit also includes an upper driving resistor, a first upper gate signal terminal, a first upper driving source signal terminal, a second upper driving source signal terminal and a second upper gate signal terminal, the first upper gate conductive layer is connected to the upper driving resistor, the upper driving resistor is connected to the second upper gate conductive layer of the upper substrate, the first upper gate signal terminal and the second upper gate signal terminal are respectively connected to the second upper gate conductive layer, the first upper driving source signal terminal and the second upper driving source signal terminal are respectively connected to the upper driving source conductive layer The lower half-bridge unit further comprises a lower driving resistor, a first lower driving source signal terminal, a first lower gate signal terminal, a second lower driving source signal terminal and a second lower gate signal terminal. The first lower gate conductive layer is connected to the lower driving resistor, the lower driving resistor is connected to the second lower gate conductive layer of the lower substrate, the first lower gate signal terminal and the second lower gate signal terminal are respectively connected to the second lower gate conductive layer, and the first lower driving source signal terminal and the second lower driving source signal terminal are respectively connected to the lower driving source conductive layer.

[0013] Further, the first upper drain conductive layer is located on a side of the second upper drain conductive layer away from the upper power source conductive layer, a plurality of upper MOSFET chips are arranged at intervals along the length direction of the first upper drain conductive layer, the upper half-bridge unit includes a plurality of upper driving resistors, a plurality of first upper gate conductive layers are arranged on the upper substrate, the plurality of first upper gate conductive layers are arranged in a one-to-one correspondence with the plurality of upper MOSFET chips, the plurality of upper driving resistors are arranged in a one-to-one correspondence with the plurality of first upper gate conductive layers, the plurality of first upper gate conductive layers are all located on a side of the first upper drain conductive layer away from the second upper drain conductive layer, the second upper gate conductive layer is located on a side of the first upper gate conductive layer away from the first upper drain conductive layer, and the upper driving source conductive layer is located on the second upper gate conductive layer. The first lower drain conductive layer is located on a side of the second lower drain conductive layer away from the lower power source conductive layer, the lower half-bridge unit includes multiple lower driving resistors, multiple first lower gate conductive layers are arranged on the lower substrate, the multiple first lower gate conductive layers are arranged in a one-to-one correspondence with the multiple lower MOSFET chips, the multiple lower driving resistors are arranged in a one-to-one correspondence with the multiple first lower gate conductive layers, the multiple first lower gate conductive layers are all located on a side of the first lower drain conductive layer away from the second lower drain conductive layer, the second lower gate conductive layer is located on a side of the first lower gate conductive layer away from the first lower drain conductive layer, and the lower driving source conductive layer is located on a side of the second lower gate conductive layer away from the first lower gate conductive layer.

[0014] Furthermore, the first upper drain conductive layer, the second upper gate conductive layer and the upper driving source conductive layer are all long strip structures; the first lower drain conductive layer, the second lower gate conductive layer and the lower driving source conductive layer are all long strip structures.

[0015] Further, the drain of the upper MOSFET chip is sintered and connected to the first upper drain conductive layer through solder, the power source of the upper MOSFET chip is connected to the anode of the upper diode chip through the first upper MOSFET power source bonding wire, the gate of the upper MOSFET chip is connected to the first upper gate conductive layer through the upper MOSFET gate bonding wire, the driving source of the upper MOSFET chip is connected to the upper driving source conductive layer through the upper MOSFET driving source bonding wire, the cathode of the upper series diode is sintered and connected to the first upper drain conductive layer through solder, the anode of the upper series diode is connected to the second upper drain conductive layer through the upper series diode anode bonding wire, the cathode of the upper diode chip is sintered and connected to the second upper drain conductive layer through solder, and the anode of the upper diode chip is connected to the upper power source conductive layer through the second upper MOSFET power source bonding wire; the lower MOSFET The drain of the chip is sintered and connected to the first lower drain conductive layer through solder, the power source of the lower MOSFET chip is connected to the anode of the lower diode chip through the first lower MOSFET power source bonding wire, the gate of the lower MOSFET chip is connected to the first lower gate conductive layer through the lower MOSFET gate bonding wire, the driving source of the lower MOSFET chip is connected to the lower driving source conductive layer through the lower MOSFET driving source bonding wire, the cathode of the lower series diode is sintered and connected to the first lower drain conductive layer through solder, the anode of the lower series diode is connected to the second lower drain conductive layer through the lower series diode anode bonding wire, the cathode of the lower diode chip is sintered and connected to the second lower drain conductive layer through solder, the anode of the lower diode chip is connected to the lower power source conductive layer through the second lower MOSFET power source bonding wire, and the upper power source conductive layer is connected to the second lower drain conductive layer.

[0016] Furthermore, the upper half-bridge unit includes four upper MOSFET chips connected in parallel, one upper series diode and three upper diode chips connected in parallel; the lower half-bridge unit includes four lower MOSFET chips connected in parallel, one lower series diode and three lower diode chips connected in parallel.

[0017] Furthermore, both the upper substrate and the lower substrate are ceramic substrates.

[0018] According to another aspect of the present invention, a power module is provided, the power module comprising: a substrate; a power sub-module arranged on the substrate, the power sub-module being the power sub-module provided above.

[0019] Furthermore, the power module includes a plurality of power sub-modules.

[0020] Furthermore, a plurality of power sub-modules are arranged at intervals in the length direction of the substrate, and an upper half-bridge unit and a lower half-bridge unit of each power sub-module are arranged at intervals in the width direction of the substrate.

[0021] Furthermore, the currents of two adjacent power sub-modules flow in opposite directions.

[0022] Furthermore, the lower surface of the upper substrate of the power sub-module is connected to the substrate by solder sintering, and the lower surface of the lower substrate of the power sub-module is connected to the substrate by solder sintering.

[0023] The technical solution of the present invention is applied, and the power sub-module includes an upper half-bridge unit and a lower half-bridge unit, wherein the upper half-bridge unit includes an upper substrate, a plurality of upper MOSFET chips connected in parallel, an upper series diode, and a plurality of upper diode chips connected in parallel, wherein the number of upper MOSFET chips is an even number, and two upper MOSFET chips form an upper MOSFET chipset, and an upper series diode is arranged between the two upper MOSFET chipsets. The lower half-bridge unit includes a lower substrate, a plurality of lower MOSFET chips connected in parallel, a lower series diode, and a plurality of lower diode chips connected in parallel, wherein the number of lower MOSFET chips is an even number, and two lower MOSFET chips form a lower MOSFET chipset, and a lower series diode is arranged between the two lower MOSFET chipsets. With the above structure, the upper series diode can group the plurality of upper MOSFET chips connected in parallel, and the lower series diode can group the plurality of lower MOSFET chips connected in parallel, thereby eliminating the current coupling effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0025] Figure 1 A schematic diagram of the structure of a power module provided according to an embodiment of the present invention is shown;

[0026] Figure 2 A schematic diagram of the structure of a power submodule provided in an embodiment of the present invention is shown;

[0027] Figure 3 A schematic diagram showing the structure of an upper half-bridge unit of a power sub-module provided according to an embodiment of the present invention is shown;

[0028] Figure 4 A schematic diagram of the structure of a lower half-bridge unit of a power sub-module provided according to an embodiment of the present invention is shown;

[0029] Figure 5 A schematic diagram showing the principle of a double pulse test circuit for a lower half-bridge unit of a power sub-module provided in an embodiment of the present invention is shown;

[0030] Figure 6 A circuit topology diagram of a power module provided according to an embodiment of the present invention is shown;

[0031] Figure 7 shows a current direction diagram of a power module provided according to an embodiment of the present invention;

[0032] Figure 8 A schematic diagram showing the structure of a power submodule from another perspective according to an embodiment of the present invention is shown;

[0033] Fig. 9 A schematic structural diagram of an upper half-bridge unit of a power sub-module provided in an embodiment of the present invention from another perspective is shown;

[0034] Fig.10 A schematic structural diagram from another perspective of a lower half-bridge unit of a power sub-module provided according to an embodiment of the present invention is shown.

[0035] The above drawings include the following reference numerals:

[0036] 1. First submodule; 2. Second submodule; 3. Third submodule; 4. Fourth submodule; 5. Substrate; 6. Lower half-bridge unit; 7. Upper half-bridge unit; 8. Upper MOSFET gate bonding wire; 9. Upper MOSFET driver source bonding wire;

[0037] 10. Upper series diode; 11. Upper MOSFET chip; 12. First upper MOSFET power source bonding wire; 13. Upper diode chip; 14. Second upper MOSFET power source bonding wire; 15. Upper power source conductive layer; 16. Upper drain power terminal; 17. Upper series diode anode bonding wire; 18. Second upper drain conductive layer; 181. Fourth segment; 182. Fifth segment; 19. First upper drain conductive layer;

[0038] 20. upper driving resistor; 21. upper substrate; 22. second upper gate conductive layer; 23. upper driving source conductive layer; 24. first upper gate signal terminal; 25. first upper driving source signal terminal; 26. second upper driving source signal terminal; 27. second upper gate signal terminal; 28. first lower output power terminal; 29. ​​second lower MOSFET power source bonding wire;

[0039] 30. first lower MOSFET power source bonding wire; 31. lower series diode anode bonding wire; 32. lower series diode; 33. second lower gate conductive layer; 34. lower drive source conductive layer; 35. first lower drive source signal terminal; 36. first lower gate signal terminal; 37. second lower drive source signal terminal; 38. second lower gate signal terminal; 39. lower MOSFET gate bonding wire;

[0040] 40. Lower MOSFET driving source bonding wire; 41. Lower driving resistor; 42. Lower MOSFET chip; 43. First lower drain conductive layer; 44. Lower diode chip; 45. Second lower drain conductive layer; 451. First section; 452. Second section; 453. Third section; 46. Lower substrate; 47. Second lower output power terminal; 48. Lower power source power terminal; 49. Lower power source conductive layer;

[0041] 50. First upper gate conductive layer; 51. First lower gate conductive layer; 53. First bridge arm connected to bonding wires; 54. Second bridge arm connected to bonding wires. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] like Figures 1 to 10As shown, an embodiment of the present invention provides a power sub-module, which includes an upper half-bridge unit 7 and a lower half-bridge unit 6. The upper half-bridge unit 7 includes an upper substrate 21, a plurality of upper MOSFET chips 11 connected in parallel, an upper series diode 10, and a plurality of upper diode chips 13 connected in parallel. The number of upper MOSFET chips 11 is an even number, and two upper MOSFET chips 11 form an upper MOSFET chip group. An upper series diode 10 is arranged between the two upper MOSFET chip groups. The drain of the upper MOSFET chip 11 is connected to the first upper drain conductive layer 19 of the upper substrate 21, the power source of the upper MOSFET chip 11 is connected to the anode of the upper diode chip 13, the cathode of the upper series diode 10 is connected to the first upper drain conductive layer 19, the anode of the upper series diode 10 is connected to the second upper drain conductive layer 18 of the upper substrate 21, the cathode of the upper diode chip 13 is connected to the second upper drain conductive layer 18, and the anode of the upper diode chip 13 is connected to the upper power source conductive layer 15 of the upper substrate 21. The lower half-bridge unit 6 includes a lower substrate 46, a plurality of lower MOSFET chips 42 connected in parallel, a lower series diode 32 and a plurality of lower diode chips 44 connected in parallel, the number of the lower MOSFET chips 42 is an even number, and two lower MOSFET chips 42 form a lower MOSFET chip group, a lower series diode 32 is arranged between the two lower MOSFET chip groups, the drain of the lower MOSFET chip 42 is connected to the first lower drain conductive layer 43 of the lower substrate 46, the power source of the lower MOSFET chip 42 is connected to the anode of the lower diode chip 44, the cathode of the lower series diode 32 is connected to the first lower drain conductive layer 43, the anode of the lower series diode 32 is connected to the second lower drain conductive layer 45 of the lower substrate 46, the cathode of the lower diode chip 44 is connected to the second lower drain conductive layer 45, the anode of the lower diode chip 44 is connected to the lower power source conductive layer 49 of the lower substrate 46, and the upper power source conductive layer 15 is connected to the second lower drain conductive layer 45.

[0044] The power submodule provided in this embodiment is applied, and the upper half-bridge unit 7 includes an upper substrate 21, a plurality of upper MOSFET chips 11 connected in parallel, an upper series diode 10, and a plurality of upper diode chips 13 connected in parallel. The number of upper MOSFET chips 11 is an even number, and two upper MOSFET chips 11 form an upper MOSFET chip group, and an upper series diode 10 is arranged between the two upper MOSFET chip groups. The lower half-bridge unit 6 includes a lower substrate 46, a plurality of lower MOSFET chips 42 connected in parallel, a lower series diode 32, and a plurality of lower diode chips 44 connected in parallel. The number of lower MOSFET chips 42 is an even number, and two lower MOSFET chips 42 form a lower MOSFET chip group, and a lower series diode 32 is arranged between the two lower MOSFET chip groups. With the above structure, the upper series diode 10 can group the plurality of upper MOSFET chips 11 connected in parallel, and the lower series diode 32 can group the plurality of lower MOSFET chips 42 connected in parallel, thereby eliminating the current coupling effect and achieving a better current sharing effect.

[0045] Furthermore, when the upper MOSFET chip 11 is turned off, the upper diode chip 13 is turned on for current freewheeling. When the lower MOSFET chip 42 is turned off, the lower diode chip 44 is turned on for current freewheeling.

[0046] In order to explain how the power submodule provided in this embodiment eliminates the current coupling effect, the following can be combined with Figure 5 And the following content to understand:

[0047] Figure 5 The schematic diagram of the double pulse test circuit principle of the lower half-bridge unit provided by the embodiment of the present invention is shown in FIG. Figure 5 , V DC It is a DC voltage source used to power the power circuit of the power module. bus L is the busbar capacitor, used to maintain DC voltage stability. load is the load inductance, V D Q1~Q4 are the lower MOSFET chips 42 in the lower half-bridge unit, L is the three upper diode chips 13 in parallel in the upper half-bridge unit, and is used for freewheeling when the four lower MOSFET chips 42 in parallel in the lower half-bridge unit are turned off. s is the source side stray inductance of the lower MOSFET chip 42, L g is the gate stray inductance of the lower MOSFET chip 42, L as is the driver source stray inductance of the lower MOSFET chip 42, L d is the stray inductance between the drain-side branches of the lower MOSFET chip 42, L b is the stray inductance between the power source side branches of the lower MOSFET chip 42, La is the stray inductance between the gate-side branches of the lower MOSFET chip 42, L c The stray inductance between the source side branches of the lower MOSFET chip 42 is driven, i d is the current flowing through the load inductor, i d1 is the current flowing through Q1, i d2 is the current flowing through Q2, i d3 is the current flowing through Q3, i d4 is the current flowing through Q4. V driver It is the gate drive power supply, used to power the drive circuit, R g is the gate drive resistor. O is the power source current confluence point, which is also the power source potential reference point when analyzing the current coupling effect. O1 is the power source current potential reference point of Q1, O2 is the power source current potential reference point of Q2, O3 is the power source current potential reference point of Q3, O4 is the power source current potential reference point of Q4, L1 is the parasitic inductance between the load inductor and the positive pole of the DC voltage source, L2 is the parasitic inductance between the power source current potential reference point O and the negative pole of the DC voltage source, ASO is the driving source current confluence point, which is also the driving source potential reference point, and L3 is the parasitic inductance between the driving source potential reference point ASO and the negative pole of the DC voltage source. i g is the total current of the parallel chips in the drive circuit, i g1 ~i g4 is the driving current of Q1~Q4, and S1~S4 are the power sources of Q1~Q4.

[0048] The principle of how the power module eliminates the influence of current coupling effect is deduced and proved below.

[0049] The drain current of the lower MOSFET chip 42 can be expressed as i d It can be expressed as follows:

[0050]

[0051] Among them, g fs is the transconductance of the lower MOSFET chip 42, V gs1 is the gate-source voltage difference of Q1, V gs2 is the gate-source voltage difference of Q2, V gs3 is the gate-source voltage difference of Q3, V gs4 is the gate-source voltage difference of Q4, V th is the threshold voltage. g is the total current of the parallel chips in the drive circuit, L g2 is the parasitic gate inductance of Q2, L g3 is the parasitic gate inductance of Q3, i g1 ~i g4is the gate current of Q1~Q4. V gs In the drive circuit, it can be expressed as follows:

[0052]

[0053] Since the lower MOSFET chip 42 is a voltage-controlled device, the required driving current is only a few hundred milliamperes, and the drain current of a single lower MOSFET chip 42 is tens of amperes, so the current of the driving circuit is much smaller than the current of the power circuit, and the effect of the driving current on the gate inductance on V gs The impact of V gs It can be simplified to the following expression:

[0054]

[0055] The unbalanced current of the parallel MOSFET chip 42 can be expressed by the following expression:

[0056]

[0057] Among them, △i d12 is the dynamic unbalanced current of Q1 and Q2, △i d13 is the dynamic unbalanced current between Q1 and Q3, △i d14 is the dynamic unbalanced current between Q1 and Q4, △i d23 is the dynamic unbalanced current of Q2 and Q3, △i d34 is the dynamic unbalanced current of Q3 and Q4, g fs For transconductance.

[0058] From the above formula, we can see that the unbalanced current of the parallel lower MOSFET chip 42 is mainly due to the stray inductance L between the branches on the power source side of the lower MOSFET chip 42. b However, the stray inductance L between the branches on the power source side is b Only one chip's current flows through it, without coupling the current of other chips. Therefore, this design can eliminate the influence of current coupling effect on parallel current sharing.

[0059] It should be noted that, in the above formula, dt refers to the differential with respect to time.

[0060] It should be noted that MOSFET is the abbreviation of "Metal-Oxide-Semiconductor Field-EffectTransistor", which means "Metal-Oxide-Semiconductor Field-Effect Transistor" in Chinese. It is a common semiconductor device widely used in electronic circuits, especially in analog and digital circuit design.

[0061] In this embodiment, the upper MOSFET chip 11 and the lower MOSFET chip 42 are both silicon carbide MOSFETs, the upper diode chip 13 and the lower diode chip 44 are both SiC SBDs, and the upper series diode 10 and the lower series diode 32 are both Schottky diodes.

[0062] It should be noted that SiC SBD is the abbreviation of "Silicon Carbide Schottky Barrier Diodes", which means silicon carbide Schottky barrier diode in Chinese.

[0063] like Figure 3 As shown, the upper half-bridge unit 7 also includes an upper drain power terminal 16, which is sintered and connected to the second upper drain conductive layer 18, and the lower half-bridge unit 6 also includes a first lower output power terminal 28, a second lower output power terminal 47 and a lower power source power terminal 48, and the lower power source power terminal 48 is sintered and connected to the lower power source conductive layer 49, and the first lower output power terminal 28 and the second lower output power terminal 47 are sintered and connected to the second lower drain conductive layer 45, respectively, so as to facilitate the use of power terminals to realize the connection between the power module and other components.

[0064] In this embodiment, the upper drain power terminal 16, the first lower output power terminal 28, the second lower output power terminal 47 and the lower power source power terminal 48 are all low-thread power terminals, which can effectively reduce the parasitic inductance of the power terminal and reduce the switching transient voltage overshoot of the power module.

[0065] Among them, the low-thread power terminal is a copper pillar terminal with a relatively low height, and the top of the copper pillar terminal has a thread connected to the capacitor busbar.

[0066] It should be noted that the low-thread power terminal refers to a power terminal whose height dimension is between 14 mm and 16 mm. Specifically, the height dimension of the low-thread power terminal can be 14 mm, 15 mm, 16 mm, and any other value between 14 mm and 16 mm.

[0067] In this embodiment, the height dimension of the low screw power terminal is 15.6 mm.

[0068] In the related art, the height of the same type of power terminal is 40 mm.

[0069] It should be noted that the power sub-module is connected to the capacitor busbar, which has DC+, DC- and AC terminals. The upper drain power terminal 16 is connected to DC+, the first lower output power terminal 28 and the second lower output power terminal 47 are simultaneously connected to AC, and the lower power source power terminal 48 is connected to DC-.

[0070] like Figure 3As shown, two upper power source conductive layers 15 are disposed on the upper substrate 21, and the two upper power source conductive layers 15 are respectively disposed on both sides of the upper drain power terminal 16. With the above structure, the two upper power source conductive layers 15 are respectively disposed on both sides of the upper drain power terminal 16, so that the layout of the upper half-bridge unit 7 is more compact, and it is convenient to place more components in the same area.

[0071] like Figure 4 As shown, the second lower drain conductive layer 45 includes a first section 451, a second section 452 and a third section 453. The first section 451 and the third section 453 are respectively connected to the two ends of the second section 452. The first section 451 and the third section 453 are located on the same side of the second section 452. A plurality of lower diode chips 44 are arranged on the second section 452 at intervals along the extension direction of the second section 452. The second lower output power terminal 47 is arranged on the first section 451, and the first lower output power terminal 28 is arranged on the third section 453. The first section 451 is connected to one of the upper power source conductive layers 15, and the third section 453 is connected to the other upper power source conductive layer 15. With the above structure, the second section 452 is used to facilitate the placement of a plurality of lower diode chips 44, the first section 451 is used to facilitate the placement of the second lower output power terminal 47, and the third section 453 is used to facilitate the placement of the first lower output power terminal 28, so that the layout of the lower half-bridge unit 6 is more compact, and it is convenient to place more components in the same area.

[0072] like Figure 3 As shown, the second upper drain conductive layer 18 includes a fourth segment 181 and a fifth segment 182 which are perpendicular to each other, one end of the fifth segment 182 is connected to the middle of the fourth segment 181, a plurality of upper diode chips 13 are arranged on the fourth segment 181 at intervals along the length direction of the fourth segment 181, and the upper drain power terminal 16 is arranged on the fifth segment 182. With the above structure, the fourth segment 181 is used to place a plurality of upper diode chips 13, the upper drain power terminal 16 is arranged on the fifth segment 182, and the two upper power source conductive layers 15 are respectively arranged on both sides of the upper drain power terminal 16, which can further improve the compactness of the layout of the upper half-bridge unit 7.

[0073] In this embodiment, the second upper drain conductive layer 18 includes a fourth segment 181 and a fifth segment 182 which are perpendicular to each other to form a T-shaped structure, and the second lower drain conductive layer 45 includes a first segment 451, a second segment 452 and a third segment 453 to form a concave structure. Specifically, the protruding portion of the T-shaped structure corresponds to the concave position of the concave structure.

[0074] like Figure 2As shown, in this embodiment, the first section 451 is connected to one of the upper power source conductive layers 15 through the first bridge arm connecting bonding wire 53, and the third section 453 is connected to the other upper power source conductive layer 15 through the second bridge arm connecting bonding wire 54. The connection between the second lower drain conductive layer 45 and the upper power source conductive layer 15 is achieved by using the first bridge arm connecting bonding wire 53 and the second bridge arm connecting bonding wire 54, which has the advantages of simple connection structure and low cost.

[0075] like Figure 3 and Figure 4 As shown, the gate of the upper MOSFET chip 11 is connected to the first upper gate conductive layer 50 of the upper substrate 21, the driving source of the upper MOSFET chip 11 is connected to the upper driving source conductive layer 23 of the upper substrate 21, the upper half-bridge unit 7 also includes an upper driving resistor 20, a first upper gate signal terminal 24, a first upper driving source signal terminal 25, a second upper driving source signal terminal 26 and a second upper gate signal terminal 27, the first upper gate conductive layer 50 is connected to the upper driving resistor 20, the upper driving resistor 20 is connected to the second upper gate conductive layer 22 of the upper substrate 21, the first upper gate signal terminal 24 and the second upper gate signal terminal 27 are sintered and connected to the second upper gate conductive layer 22, and the first upper driving source signal terminal 25 and the second upper driving source signal terminal 26 are sintered and connected to the upper driving source conductive layer 23, respectively. The gate of the lower MOSFET chip 42 is connected to the first lower gate conductive layer 51 of the lower substrate 46, the driving source of the lower MOSFET chip 42 is connected to the lower driving source conductive layer 34 of the lower substrate 46, the lower half-bridge unit 6 also includes a lower driving resistor 41, a first lower driving source signal terminal 35, a first lower gate signal terminal 36, a second lower driving source signal terminal 37 and a second lower gate signal terminal 38, the first lower gate conductive layer 51 is connected to the lower driving resistor 41, the lower driving resistor 41 is connected to the second lower gate conductive layer 33 of the lower substrate 46, the first lower gate signal terminal 36 and the second lower gate signal terminal 38 are respectively connected to the second lower gate conductive layer 33, and the first lower driving source signal terminal 35 and the second lower driving source signal terminal 37 are respectively connected to the lower driving source conductive layer 34. The above terminals are used to facilitate the connection of the power module with other components.

[0076] like Figure 3As shown, the first upper drain conductive layer 19 is located on the side of the second upper drain conductive layer 18 away from the upper power source conductive layer 15, and the plurality of upper MOSFET chips 11 are arranged at intervals along the length direction of the first upper drain conductive layer 19. The upper half-bridge unit 7 includes a plurality of upper driving resistors 20, and a plurality of first upper gate conductive layers 50 are arranged on the upper substrate 21. The plurality of first upper gate conductive layers 50 are arranged one-to-one with the plurality of upper MOSFET chips 11, and the plurality of upper driving resistors 20 are arranged one-to-one with the plurality of first upper gate conductive layers 50. The plurality of first upper gate conductive layers 50 are all located on the side of the first upper drain conductive layer 19 away from the second upper drain conductive layer 18, and the second upper gate conductive layer 22 is located on the side of the first upper gate conductive layer 50 away from the first upper drain conductive layer 19, and the upper driving source conductive layer 23 is located on the side of the second upper gate conductive layer 22 away from the first upper gate conductive layer 50. With the above structure, the upper surface of the upper substrate 21 can be fully utilized, the arrangement of the various conductive layers on the upper substrate 21 is compact, and the layout of the upper half-bridge unit 7 is reasonable.

[0077] Specifically, the interval between the second upper drain conductive layer 18 and the first upper drain conductive layer 19 is a first interval, and the interval between the second upper drain conductive layer 18 and the upper power source conductive layer 15 is a second interval, and the first interval is smaller than the second interval.

[0078] like Figure 4 As shown, the first lower drain conductive layer 43 is located on the side of the second lower drain conductive layer 45 away from the lower power source conductive layer 49, the lower half-bridge unit 6 includes a plurality of lower driving resistors 41, a plurality of first lower gate conductive layers 51 are arranged on the lower substrate 46, the plurality of first lower gate conductive layers 51 are arranged one-to-one with the plurality of lower MOSFET chips 42, the plurality of lower driving resistors 41 are arranged one-to-one with the plurality of first lower gate conductive layers 51, the plurality of first lower gate conductive layers 51 are all located on the side of the first lower drain conductive layer 43 away from the second lower drain conductive layer 45, the second lower gate conductive layer 33 is located on the side of the first lower gate conductive layer 51 away from the first lower drain conductive layer 43, and the lower driving source conductive layer 34 is located on the side of the second lower gate conductive layer 33 away from the first lower gate conductive layer 51. With the above structure, the upper surface of the lower substrate 46 can be fully utilized, the arrangement of the various conductive layers on the lower substrate 46 is compact, and the layout of the lower half-bridge unit 6 is reasonable.

[0079] Specifically, the interval between the first lower drain conductive layer 43 and the second lower drain conductive layer 45 is the third interval, the interval between the second lower drain conductive layer 45 and the lower power source conductive layer 49 is the fourth interval, and the third interval is smaller than the fourth interval.

[0080] like Figure 3 and Figure 4As shown, the first upper drain conductive layer 19, the second upper gate conductive layer 22 and the upper driving source conductive layer 23 are all long strip structures. In the length direction of the first upper drain conductive layer 19, the second upper gate conductive layer 22 and the upper driving source conductive layer 23, the upper surface of the upper substrate 21 can be fully utilized. The first lower drain conductive layer 43, the second lower gate conductive layer 33 and the lower driving source conductive layer 34 are all long strip structures. In the length direction of the first lower drain conductive layer 43, the second lower gate conductive layer 33 and the lower driving source conductive layer 34, the upper surface of the lower substrate 46 can be fully utilized.

[0081] It should be noted that when the upper half-bridge unit 7 and the lower half-bridge unit 6 are assembled together, the arrangement direction of the upper half-bridge unit 7 and the lower half-bridge unit 6 is the first direction, the extension direction of the first upper drain conductive layer 19, the second upper gate conductive layer 22 and the upper driving source conductive layer 23 is the second direction, the extension direction of the first lower drain conductive layer 43, the second lower gate conductive layer 33 and the lower driving source conductive layer 34 is also the second direction, and the first direction is perpendicular to the second direction.

[0082] The extending direction (length direction) of the fourth section 181 is also the second direction. The extending direction (length direction) of the second section 452 is also the second direction.

[0083] like Figures 2 to 4As shown, the drain of the upper MOSFET chip 11 is sintered and connected to the first upper drain conductive layer 19 through solder, the power source of the upper MOSFET chip 11 is connected to the anode of the upper diode chip 13 through the first upper MOSFET power source bonding wire 12, the gate of the upper MOSFET chip 11 is connected to the first upper gate conductive layer 50 through the upper MOSFET gate bonding wire 8, the driving source of the upper MOSFET chip 11 is connected to the upper driving source conductive layer 23 through the upper MOSFET driving source bonding wire 9, the cathode of the upper series diode 10 is sintered and connected to the first upper drain conductive layer 19 through solder, the anode of the upper series diode 10 is connected to the second upper drain conductive layer 18 through the upper series diode anode bonding wire 17, the cathode of the upper diode chip 13 is sintered and connected to the second upper drain conductive layer 18 through solder, and the anode of the upper diode chip 13 is connected to the upper power source conductive layer 15 through the second upper MOSFET power source bonding wire 14. The drain of the lower MOSFET chip 42 is sintered and connected to the first lower drain conductive layer 43 through solder, the power source of the lower MOSFET chip 42 is connected to the anode of the lower diode chip 44 through the first lower MOSFET power source bonding wire 30, the gate of the lower MOSFET chip 42 is connected to the first lower gate conductive layer 51 through the lower MOSFET gate bonding wire 39, the driving source of the lower MOSFET chip 42 is connected to the lower driving source conductive layer 34 through the lower MOSFET driving source bonding wire 40, the cathode of the lower series diode 32 is sintered and connected to the first lower drain conductive layer 43 through solder, the anode of the lower series diode 32 is connected to the second lower drain conductive layer 45 through the anode bonding wire 31, the cathode of the lower diode chip 44 is sintered and connected to the second lower drain conductive layer 45 through solder, the anode of the lower diode chip 44 is connected to the lower power source conductive layer 49 through the second lower MOSFET power source bonding wire 29, and the upper power source conductive layer 15 is connected to the second lower drain conductive layer 45.

[0084] Specifically, the upper MOSFET chip 11, the upper series diode 10 and the upper diode chip 13 are directly sintered on the conductive layer of the upper substrate 21: the drain of the upper MOSFET chip 11 is sintered and connected to the first upper drain conductive layer 19 through solder, the cathode of the upper series diode 10 is sintered and connected to the first upper drain conductive layer 19 through solder, and the cathode of the upper diode chip 13 is sintered and connected to the second upper drain conductive layer 18 through solder. The lower MOSFET chip 42, the lower series diode 32 and the lower diode chip 44 are directly sintered on the lower substrate 46: the drain of the lower MOSFET chip 42 is sintered and connected to the first lower drain conductive layer 43 through solder, the cathode of the lower series diode 32 is sintered and connected to the first lower drain conductive layer 43 through solder, and the cathode of the lower diode chip 44 is sintered and connected to the second lower drain conductive layer 45 through solder.

[0085] The MOSFET chip, the series diode and the diode chip are fixed by sintering connection, which has the advantages of firm connection and convenient heat conduction and heat dissipation by the conductive layer. The MOSFET chip, the series diode and the diode chip are connected to other components by bonding wire connection, which has the advantages of simple connection structure and low cost.

[0086] In this embodiment, the upper half-bridge unit 7 includes four upper MOSFET chips 11 connected in parallel, one upper series diode 10, and three upper diode chips 13 connected in parallel. The lower half-bridge unit 6 includes four lower MOSFET chips 42 connected in parallel, one lower series diode 32, and three lower diode chips 44 connected in parallel. The above arrangement eliminates the current coupling effect. For the specific principle, please refer to the double pulse test circuit principle of the lower half-bridge unit above.

[0087] In order to facilitate understanding of the power submodule provided in this embodiment, Figure 6 To explain, Figure 6 It is a circuit topology diagram of a power module, in which the upper drain power terminal 16 is electrically connected to the anode of the upper series diode 10, the cathode of the upper series diode 10 is electrically connected to the drain of the upper MOSFET chip 11, the power source of the upper MOSFET chip 11 is electrically connected to the anode of the upper diode chip 13 through the first upper MOSFET power source bonding wire 12, the anode of the upper diode chip 13 is electrically connected to the first lower output power terminal 28 and the second lower output power terminal 47 through the second upper MOSFET power source bonding wire 14, and the cathode of the upper diode chip 13 is electrically connected to the upper drain power terminal 16 and the anode of the upper series diode 10 at the same time. The anode of the lower series diode 32 is electrically connected to the first lower output power terminal 28 and the second lower output power terminal 47, the cathode of the lower series diode 32 is electrically connected to the drain of the lower MOSFET chip 42, the power source of the lower MOSFET chip 42 is electrically connected to the anode of the lower diode chip 44 through the first lower MOSFET power source bonding wire 30, the anode of the lower diode chip 44 is electrically connected to the lower power source power terminal 48 through the second lower MOSFET power source bonding wire 29, and the cathode of the lower diode chip 44 is electrically connected to the anode of the lower series diode 32, the first lower output power terminal 28, and the second lower output power terminal 47 at the same time.

[0088] Specifically, the upper substrate 21 and the lower substrate 46 are both ceramic substrates. Ceramic substrates help improve the efficiency, stability and safety of power electronic systems through their unique thermal, mechanical and electrical properties.

[0089] Ceramic substrates have high thermal conductivity, large heat capacity and strong heat diffusion function, which can effectively conduct the heat generated by the chip in the power module to the outside, achieving good heat dissipation effect. Ceramic substrates have strong electrical insulation capabilities, protecting users from the impact of the electrical system while ensuring electrical safety inside the module. Ceramic substrates have a low thermal expansion coefficient, which helps to maintain mechanical stability and is suitable for some demanding applications.

[0090] It should be noted that the conductive layer in this embodiment is copper clad.

[0091] like Figure 1 As shown, another embodiment of the present invention provides a power module, which includes a substrate 5 and a power sub-module, the power sub-module is arranged on the substrate 5, and the power sub-module is the power sub-module provided above. Therefore, the power module can also use the upper series diode 10 to group multiple parallel upper MOSFET chips 11, and use the lower series diode 32 to group multiple parallel lower MOSFET chips 42, thereby eliminating the current coupling effect.

[0092] In this embodiment, the power module includes a plurality of power submodules. By setting a plurality of power submodules, different power requirements can be met. Specifically, the plurality of power submodules include a first submodule 1, a second submodule 2, a third submodule 3, and a fourth submodule 4.

[0093] In this embodiment, a plurality of power sub-modules are arranged at intervals in the length direction of the substrate 5, and the upper half-bridge unit 7 and the lower half-bridge unit 6 of each power sub-module are arranged at intervals in the width direction of the substrate 5. In this way, the area of ​​the substrate 5 can be fully utilized to improve the integration of the power module.

[0094] like Figure 7 As shown, in this embodiment, the currents of two adjacent power sub-modules flow in opposite directions, and the mutual inductance of the two adjacent power sub-modules is negative, which can reduce the parasitic inductance.

[0095] Specifically, the lower surface of the upper substrate 21 of the power sub-module is connected to the substrate 5 by solder sintering, and the lower surface of the lower substrate 46 of the power sub-module is connected to the substrate 5 by solder sintering, so as to realize the connection between the upper substrate 21 and the lower substrate 46 and the substrate 5 respectively. The substrate 5 can be used to conduct heat and dissipate heat for the power sub-module.

[0096] In this embodiment, the power module is a silicon carbide power module.

[0097] It should be noted that in the relevant technology, there is no commercial 6.5kV silicon carbide half-bridge module. In addition, in order to improve the yield rate of the chip, the active area of ​​the silicon carbide chip is small, which makes the current level of a single chip small. The current level of a commercial high-voltage 6.5kV silicon carbide single chip is only 25A. In order to improve the current level of silicon carbide device applications, multiple chips need to be connected in parallel. When multiple chips are connected in parallel, they are affected by device parameters and packaging parameters. There is an imbalance in current distribution between parallel chips, which makes the temperature distribution of parallel chips uneven. In severe cases, chips with excessive current distribution will experience thermal runaway, which seriously threatens the overall reliability of the power module.

[0098] In order to achieve the requirements of high-voltage, high-current, low parasitic inductance power modules, the power module of the present invention meets the requirements of high-voltage insulation packaging while reducing parasitic parameters and module losses. Four parallel units are used to eliminate the influence of current coupling effect on the current distribution of parallel chips, and achieve current sharing of multiple chips in parallel. This power module is the world's first 6.5kV / 250A high-voltage, high-current power module, filling the gap in high-voltage, high-current power module packaging design.

[0099] The device provided by the embodiment has the following beneficial effects:

[0100] (1) There is currently no 6.5kV / 250A power module. The power module provided in this embodiment is divided into an upper half-bridge and a lower half-bridge. Each half-bridge uses 16 silicon carbide MOSFET chips. The current level is 320A at 25°C and the current level is 256A at 100°C. The power module is divided into four power sub-modules connected in parallel. Each power sub-module consists of 8 silicon carbide MOSFET chips, 6 silicon carbide Schottky diodes, and 2 series diodes. The upper half-bridge unit and the lower half-bridge unit of the power sub-module are each composed of 4 silicon carbide MOSFETs in parallel, eliminating the current coupling effect;

[0101] (2) The application of low-thread power terminals can effectively reduce the parasitic inductance of the power terminals and reduce the switching transient voltage overshoot of the power module;

[0102] (3) The current flows in opposite directions between adjacent power sub-modules in the four parallel power sub-modules, and the negative mutual inductance can reduce the parasitic inductance.

[0103] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0104] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0105] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0106] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0107] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0108] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A power sub-module, characterized in that: The power submodule comprises: An upper half-bridge unit (7) comprises an upper substrate (21), a plurality of upper MOSFET chips (11) connected in parallel, an upper series diode (10), and a plurality of upper diode chips (13) connected in parallel, wherein the number of the upper MOSFET chips (11) is an even number, and two of the upper MOSFET chips (11) form an upper MOSFET chip group, an upper series diode (10) is arranged between the two upper MOSFET chip groups, and the drain of the upper MOSFET chip (11) is connected to a first upper drain conductive layer ( 19), the power source electrode of the upper MOSFET chip (11) is connected to the anode of the upper diode chip (13), the cathode of the upper series diode (10) is connected to the first upper drain conductive layer (19), the anode of the upper series diode (10) is connected to the second upper drain conductive layer (18) of the upper substrate (21), the cathode of the upper diode chip (13) is connected to the second upper drain conductive layer (18), and the anode of the upper diode chip (13) is connected to the upper power source conductive layer (15) of the upper substrate (21); A lower half-bridge unit (6) comprises a lower substrate (46), a plurality of lower MOSFET chips (42) connected in parallel, a lower series diode (32) and a plurality of lower diode chips (44) connected in parallel, wherein the number of the lower MOSFET chips (42) is an even number, and two of the lower MOSFET chips (42) form a lower MOSFET chip group, a lower series diode (32) is arranged between the two lower MOSFET chip groups, the drain of the lower MOSFET chip (42) is connected to a first lower drain conductive layer (43) of the lower substrate (46), and the lower MOSFET chip (44) is connected to a first lower drain conductive layer (43) of the lower substrate (46). The power source electrode of the chip (42) is connected to the anode of the lower diode chip (44), the cathode of the lower series diode (32) is connected to the first lower drain conductive layer (43), the anode of the lower series diode (32) is connected to the second lower drain conductive layer (45) of the lower substrate (46), the cathode of the lower diode chip (44) is connected to the second lower drain conductive layer (45), the anode of the lower diode chip (44) is connected to the lower power source conductive layer (49) of the lower substrate (46), and the upper power source conductive layer (15) is connected to the second lower drain conductive layer (45); The upper half-bridge unit (7) further comprises an upper drain power terminal (16), wherein the upper drain power terminal (16) is connected to the second upper drain conductive layer (18); The lower half-bridge unit (6) further comprises a first lower output power terminal (28), a second lower output power terminal (47) and a lower power source power terminal (48), wherein the lower power source power terminal (48) is connected to the lower power source conductive layer (49), and the first lower output power terminal (28) and the second lower output power terminal (47) are respectively connected to the second lower drain conductive layer (45).

2. The power submodule according to claim 1, characterized in that: The upper drain power terminal (16), the first lower output power terminal (28), the second lower output power terminal (47) and the lower power source power terminal (48) are all low-thread power terminals.

3. The power submodule according to claim 1, characterized in that: Two upper power source conductive layers (15) are arranged on the upper substrate (21), and the two upper power source conductive layers (15) are respectively arranged on both sides of the upper drain power terminal (16); The second lower drain conductive layer (45) comprises a first section (451), a second section (452) and a third section (453); the first section (451) and the third section (453) are respectively connected to two ends of the second section (452); the first section (451) and the third section (453) are located on the same side of the second section (452); a plurality of lower diode chips (44) are arranged on the second section (452) at intervals along an extension direction of the second section (452); the second lower output power terminal (47) is arranged on the first section (451); and the first lower output power terminal (28) is arranged on the third section (453); The first section (451) is connected to one of the upper power source conductive layers (15), and the third section (453) is connected to another of the upper power source conductive layers (15).

4. The power submodule according to claim 1, characterized in that: The second upper drain conductive layer (18) comprises a fourth segment (181) and a fifth segment (182) which are perpendicular to each other, one end of the fifth segment (182) is connected to the middle of the fourth segment (181), a plurality of upper diode chips (13) are arranged on the fourth segment (181) at intervals along the length direction of the fourth segment (181), and the upper drain power terminal (16) is arranged on the fifth segment (182).

5. The power submodule according to claim 3, characterized in that: The first section (451) is connected to one of the upper power source conductive layers (15) via a first bridge arm connecting bonding wire (53), and the third section (453) is connected to another of the upper power source conductive layers (15) via a second bridge arm connecting bonding wire (54).

6. The power submodule according to any one of claims 1 to 5, characterized in that: The gate of the upper MOSFET chip (11) is connected to the first upper gate conductive layer (50) of the upper substrate (21); the driving source of the upper MOSFET chip (11) is connected to the upper driving source conductive layer (23) of the upper substrate (21); the upper half-bridge unit (7) further comprises an upper driving resistor (20), a first upper gate signal terminal (24), a first upper driving source signal terminal (25), a second upper driving source signal terminal (26) and a second upper gate signal terminal (27); the first upper gate conductive layer (50) is connected to the upper driving resistor (20); the upper driving resistor (20) is connected to the second upper gate conductive layer (22) of the upper substrate (21); the first upper gate signal terminal (24) and the second upper gate signal terminal (27) are respectively connected to the second upper gate conductive layer (22); the first upper driving source signal terminal (25) and the second upper driving source signal terminal (26) are respectively connected to the upper driving source conductive layer (23); The gate of the lower MOSFET chip (42) is connected to the first lower gate conductive layer (51) of the lower substrate (46); the driving source of the lower MOSFET chip (42) is connected to the lower driving source conductive layer (34) of the lower substrate (46); the lower half-bridge unit (6) further comprises a lower driving resistor (41), a first lower driving source signal terminal (35), a first lower gate signal terminal (36), a second lower driving source signal terminal (37) and a second lower gate signal terminal (38); the first lower gate conductive layer (51) is connected to the lower driving resistor (41); the lower driving resistor (41) is connected to the second lower gate conductive layer (33) of the lower substrate (46); the first lower gate signal terminal (36) and the second lower gate signal terminal (38) are respectively connected to the second lower gate conductive layer (33); and the first lower driving source signal terminal (35) and the second lower driving source signal terminal (37) are respectively connected to the lower driving source conductive layer (34).

7. The power submodule according to claim 6, characterized in that: The first upper drain conductive layer (19) is located on a side of the second upper drain conductive layer (18) away from the upper power source conductive layer (15); a plurality of upper MOSFET chips (11) are arranged at intervals along the length direction of the first upper drain conductive layer (19); the upper half-bridge unit (7) comprises a plurality of upper drive resistors (20); a plurality of first upper gate conductive layers (50) are arranged on the upper substrate (21); the plurality of first upper gate conductive layers (50) are arranged in one-to-one correspondence with the plurality of upper MOSFET chips (11); The plurality of upper driving resistors (20) are arranged in one-to-one correspondence with the plurality of first upper gate conductive layers (50); the plurality of first upper gate conductive layers (50) are all located on a side of the first upper drain conductive layer (19) away from the second upper drain conductive layer (18); the second upper gate conductive layer (22) is located on a side of the first upper gate conductive layer (50) away from the first upper drain conductive layer (19); and the upper driving source conductive layer (23) is located on a side of the second upper gate conductive layer (22) away from the first upper gate conductive layer (50); The first lower drain conductive layer (43) is located on a side of the second lower drain conductive layer (45) away from the lower power source conductive layer (49); the lower half-bridge unit (6) comprises a plurality of the lower drive resistors (41); a plurality of the first lower gate conductive layers (51) are arranged on the lower substrate (46); the plurality of the first lower gate conductive layers (51) are arranged in a one-to-one correspondence with the plurality of the lower MOSFET chips (42); the plurality of the lower drive resistors (41) are arranged in a one-to-one correspondence with the plurality of the first lower gate conductive layers (51); the plurality of the first lower gate conductive layers (51) are all located on a side of the first lower drain conductive layer (43) away from the second lower drain conductive layer (45); the second lower gate conductive layer (33) is located on a side of the first lower gate conductive layer (51) away from the first lower drain conductive layer (43); and the lower drive source conductive layer (34) is located on a side of the second lower gate conductive layer (33) away from the first lower gate conductive layer (51).

8. The power submodule according to claim 6, characterized in that: The first upper drain conductive layer (19), the second upper gate conductive layer (22) and the upper driving source conductive layer (23) are all long strip structures; The first lower drain conductive layer (43), the second lower gate conductive layer (33) and the lower driving source conductive layer (34) are all long strip structures.

9. The power submodule according to claim 6, characterized in that: The drain electrode of the upper MOSFET chip (11) is sintered and connected to the first upper drain conductive layer (19) via solder, the power source electrode of the upper MOSFET chip (11) is connected to the anode of the upper diode chip (13) via a first upper MOSFET power source bonding wire (12), the gate electrode of the upper MOSFET chip (11) is connected to the first upper gate conductive layer (50) via an upper MOSFET gate bonding wire (8), and the driving source electrode of the upper MOSFET chip (11) is connected to the anode electrode of the upper diode chip (13) via an upper MOSFET driving source bonding wire (9). The upper driving source conductive layer (23) is connected, the cathode of the upper series diode (10) is sintered and connected to the first upper drain conductive layer (19) through solder, the anode of the upper series diode (10) is connected to the second upper drain conductive layer (18) through an upper series diode anode bonding wire (17), the cathode of the upper diode chip (13) is sintered and connected to the second upper drain conductive layer (18) through solder, and the anode of the upper diode chip (13) is connected to the upper power source conductive layer (15) through a second upper MOSFET power source bonding wire (14); The drain of the lower MOSFET chip (42) is sintered and connected to the first lower drain conductive layer (43) via solder, the power source of the lower MOSFET chip (42) is connected to the anode of the lower diode chip (44) via a first lower MOSFET power source bonding wire (30), the gate of the lower MOSFET chip (42) is connected to the first lower gate conductive layer (51) via a lower MOSFET gate bonding wire (39), the drive source of the lower MOSFET chip (42) is connected to the lower drive source conductive layer (34) via a lower MOSFET drive source bonding wire (40), and the The cathode of the lower series diode (32) is sintered and connected to the first lower drain conductive layer (43) through solder, the anode of the lower series diode (32) is connected to the second lower drain conductive layer (45) through the lower series diode (32) anode bonding wire (31), the cathode of the lower diode chip (44) is sintered and connected to the second lower drain conductive layer (45) through solder, the anode of the lower diode chip (44) is connected to the lower power source conductive layer (49) through the second lower MOSFET power source bonding wire (29), and the upper power source conductive layer (15) is connected to the second lower drain conductive layer (45).

10. The power submodule according to any one of claims 1 to 5, characterized in that: The upper half-bridge unit (7) comprises four upper MOSFET chips (11) connected in parallel, one upper series diode (10) and three upper diode chips (13) connected in parallel; The lower half-bridge unit (6) comprises four lower MOSFET chips (42) connected in parallel, one lower series diode (32) and three lower diode chips (44) connected in parallel.

11. The power submodule according to any one of claims 1 to 5, characterized in that: The upper substrate (21) and the lower substrate (46) are both ceramic substrates.

12. A power module, characterized in that: The power module comprises: base(5); A power sub-module is arranged on the substrate (5), and the power sub-module is the power sub-module according to any one of claims 1 to 11.

13. The power module according to claim 12, characterized in that: The power module includes a plurality of power sub-modules.

14. The power module according to claim 13, characterized in that: The plurality of power sub-modules are arranged at intervals in the length direction of the substrate (5), and the upper half-bridge unit (7) and the lower half-bridge unit (6) of each power sub-module are arranged at intervals in the width direction of the substrate (5).

15. The power module according to claim 14, characterized in that: The currents of two adjacent power sub-modules flow in opposite directions.

16. The power module according to claim 12, characterized in that: The lower surface of the upper substrate (21) of the power sub-module is connected to the substrate (5) by solder sintering, and the lower surface of the lower substrate (46) of the power sub-module is connected to the substrate (5) by solder sintering.

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