Semiconductor structure with deep trench insulation and shallow trench insulation and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure with deep trench insulation and shallow trench insulation and a manufacturing method thereof, the semiconductor structure with deep trench insulation and shallow trench insulation comprises a substrate, the substrate is divided into a high-voltage transistor region and a low-voltage transistor region, a deep trench is arranged in the high-voltage transistor region, and a shallow trench is arranged in the low-voltage transistor region. Wherein the deep trench comprises a first trench and a second trench, the first trench comprises a first bottom, the second trench extends from the first bottom to the bottom of the substrate, a first shallow trench and a second shallow trench are arranged in the low-voltage transistor region, the length of the first shallow trench is equal to that of the second trench, and the length of the second shallow trench is equal to that of the first shallow trench. The first trench, the second trench, the first shallow trench and the second shallow trench are respectively filled with an insulating layer.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a deep trench insulation of a high voltage transistor region and a shallow trench insulation of a low voltage transistor region, and a semiconductor structure with deep trench insulation and shallow trench insulation manufactured by the above manufacturing method. Background Art

[0002] With the current semiconductor technology level, the industry has been able to integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and components on a single chip, thereby reducing costs and improving operating performance. Among them, high-voltage components such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and lateral-diffusion metal-oxide-semiconductor (LDMOS) are more commonly used because of their better switching efficiency. As known to those familiar with the art, the aforementioned high-voltage components are often required to withstand a higher breakdown voltage and operate at a lower resistance.

[0003] In addition, as the size of components continues to shrink, the development of existing planar field effect transistor components has faced the limit of manufacturing process. In order to overcome the limitation of manufacturing process, it has become the current mainstream development trend to replace planar transistor components with non-planar field effect transistor components, such as fin field effect transistor (Fin FET) components. Since the three-dimensional structure of the fin field effect transistor component can increase the contact area between the gate and the fin structure, the gate can further increase the control of the carrier channel region, thereby reducing the drain induced barrier lowering (DIBL) effect faced by small-sized components and suppressing the short channel effect (SCE). Furthermore, since the fin field effect transistor component has a wider channel width at the same gate length, it can obtain double the drain drive current. Even more, the threshold voltage of the transistor component can be regulated by adjusting the work function of the gate.

[0004] However, as the size of components continues to shrink, there are still many challenges in integrating the existing high-voltage components with the fin structure. Therefore, how to improve the existing high-voltage component and low-voltage component architecture is an important issue today. Summary of the invention

[0005] In view of this, the present invention provides a method for manufacturing a deep trench insulation of a high voltage transistor region and a shallow trench insulation of a low voltage transistor region to provide a deep trench insulation with sufficient depth for the high voltage transistor region.

[0006] According to a preferred embodiment of the present invention, a semiconductor structure with deep trench insulation and shallow trench insulation includes a substrate including a high-voltage transistor region and a low-voltage transistor region, a pad silicon oxide and a pad silicon nitride covering the high-voltage transistor region and the low-voltage transistor region, a deep trench arranged in the pad silicon nitride, pad silicon oxide and substrate in the high-voltage transistor region, wherein the deep trench includes a first trench and a second trench, wherein the first trench includes a first bottom, and the second trench extends from the first bottom to the bottom of the substrate, a first shallow trench and a second shallow trench are arranged in the pad silicon nitride, pad silicon oxide and substrate in the low-voltage transistor region, the first shallow trench and the second shallow trench define a fin structure on the substrate, wherein the length of the first shallow trench is the same as the length of the second trench, and an insulating layer fills the first trench, the second trench, the first shallow trench and the second shallow trench respectively.

[0007] According to another preferred embodiment of the present invention, a method for manufacturing a deep trench insulation integrating a high-voltage transistor region and a shallow trench insulation integrating a low-voltage transistor region comprises first providing a substrate, the substrate comprising a high-voltage transistor region and a low-voltage transistor region, a pad silicon nitride and a pad silicon oxide covering the high-voltage transistor region and the low-voltage transistor region, then etching the pad silicon nitride, the pad silicon oxide and the substrate of the high-voltage transistor region to form a first trench in the pad silicon nitride, the pad silicon oxide and the substrate, then forming a patterned mask covering the high-voltage transistor region and the low-voltage transistor region, wherein the patterned mask is filled in the first trench, A predetermined position of a second trench is defined on a patterned mask in the high-voltage transistor region, and a predetermined position of a first shallow trench and a predetermined position of a second shallow trench are defined on the patterned mask in the low-voltage transistor region. Then, using the patterned mask as a mask, the substrate is etched to extend a second trench from a first bottom of the first trench, and a first shallow trench and a second shallow trench are formed in the low-voltage transistor region. After forming the second trench, the first shallow trench, and the second shallow trench, the patterned mask is removed, and finally an insulating layer is formed to fill the first trench, the second trench, the first shallow trench, and the second shallow trench.

[0008] In order to make the above-mentioned objectives, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments and the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and explanation, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 6 A schematic diagram of a method for manufacturing a deep trench insulation of a high voltage transistor region and a shallow trench insulation of a low voltage transistor region according to a preferred embodiment of the present invention;

[0010] Figure 7 A schematic diagram of a semiconductor structure having a high voltage transistor and a low voltage transistor according to a preferred embodiment of the present invention is shown;

[0011] Figure 8 A schematic diagram of a variation of a deep trench according to a preferred embodiment of the present invention;

[0012] Fig. 9 A schematic diagram of a variation of a deep trench according to another preferred embodiment of the present invention;

[0013] Fig.10 It is an enlarged schematic diagram of a deep trench isolation according to a preferred embodiment of the present invention.

[0014] Explanation of symbols

[0015] 10: Base

[0016] 12: Silicon oxide pad

[0017] 14: Silicon nitride pad

[0018] 16: Patterned Mask

[0019] 18: First groove

[0020] 18a: Bottom

[0021] 18b: First side wall

[0022] 20: First groove

[0023] 20a: Bottom

[0024] 22: Patterned Mask

[0025] 22': Mask

[0026] 22a: Predetermined position of the second groove

[0027] 22b: Predetermined position of the first shallow trench

[0028] 22c: Predetermined position of the second shallow trench

[0029] 24: Second groove

[0030] 24a: Bottom

[0031] 24b: Second side wall

[0032] 26: Second groove

[0033] 28: Second groove

[0034] 30: Fin structure

[0035] 32: Second groove

[0036] 34: Insulation layer

[0037] 100:Semiconductor structure with deep trench insulation and shallow trench insulation

[0038] A: First Angle

[0039] B: Second angle

[0040] D1: Deep Groove

[0041] D2: Deep Groove

[0042] DI1: Deep Trench Insulation

[0043] DI2: Deep Trench Insulation

[0044] H: High voltage transistor area

[0045] L: Low voltage transistor area

[0046] L1: Length

[0047] L2: Length

[0048] L3: Length

[0049] L4: Length

[0050] L5: Length

[0051] S1: First shallow trench

[0052] S2: Second shallow trench

[0053] SI1: Shallow Trench Insulation

[0054] SI2: Shallow Trench Insulation

[0055] T1: High voltage transistor

[0056] T2: Fin transistor DETAILED DESCRIPTION

[0057] Figures 1 to 6A method for manufacturing a deep trench insulation of a high voltage transistor region and a shallow trench insulation of a low voltage transistor region is illustrated according to a preferred embodiment of the present invention.

[0058] like Figure 1 As shown, a substrate 10 is first provided, the substrate 10 includes a high-voltage transistor region H and a low-voltage transistor region L, a pad silicon oxide 12 and a pad silicon nitride 14 cover the high-voltage transistor region H and the low-voltage transistor region L, the pad silicon oxide 12 is located between the pad silicon nitride 14 and the substrate 10, and then, a patterned mask 16 is formed, the patterned mask 16 completely covers the low-voltage transistor region L and exposes part of the high-voltage transistor region H, and the patterned mask 16 is preferably a photoresist.

[0059] like Figure 2 As shown, using the patterned mask 16 as a mask, the pad silicon nitride 14, the pad silicon oxide 12 and the substrate 10 of the high-voltage transistor region H are etched to form at least one first trench 18 in the pad silicon nitride 14, the pad silicon oxide 12 and the substrate 10. The first trench 18 is located in the high-voltage transistor region H. In this embodiment, the formation of two first trenches 18 / 20 is taken as an example, but not limited to this. The widths of the openings of the two first trenches 18 / 20 can be the same or different, and then the patterned mask 16 is removed.

[0060] like Figure 3 As shown, a mask 22' is formed to cover the high voltage transistor region H and the low voltage transistor region L, wherein the mask 22' fills the first trench 18 / 20. Figure 4 As shown, a patterned mask 22' is formed to form a patterned mask 22. The patterned mask 22 in the high-voltage transistor region H defines a second trench predetermined position 22a, and a first shallow trench predetermined position 22b and a second shallow trench predetermined position 22c are defined on the patterned mask 22 in the low-voltage transistor region L. The second trench predetermined position 22a is located at the bottom 18a of the first trench 18 and the bottom 20a of the first trench 20, that is, part of the bottom 18a of the first trench 18, the bottom 20a of the first trench 20 and the silicon nitride pad 14 in the low-voltage transistor region H are exposed by the patterned mask 22.

[0061] like Figure 5As shown, with the patterned mask 22 as a mask, the substrate 10 is etched to extend a second trench 24 from the bottom 18a of the first trench 18, and to extend a second trench 26 and a second trench 28 from the bottom 20a of the first trench 20, and to form a first shallow trench S1 and a second shallow trench S2 in the pad silicon nitride 14, the pad silicon oxide 12 and the substrate 10 in the low-voltage transistor region L, and the substrate 10 between the first shallow trench S1 and the second shallow trench S2 is defined as a fin structure 30, and then the patterned mask 22 is removed, at which time the first trench 18 and the second trench 24 together form a deep trench D1, and the first trench 20, the second trench 26 and the second trench 28 together form a deep trench D2. Since the second groove 24 / 26 / 28, the first shallow groove S1 and the second shallow groove S2 are made using the same etching step, the length L1 of the second groove 24, the length L2 of the second groove 26, the length L3 of the second groove 28, the length L4 of the first shallow groove S1 and the length L5 of the second shallow groove S2 are all the same, the length L1 of the second groove 24 is defined as the distance from the opening to the bottom of the second groove 24, the length L2 of the second groove 26 is defined as the distance from the opening to the bottom of the second groove 26, the length L3 of the second groove 28 is defined as the distance from the opening to the bottom of the second groove 28, the length L4 of the first shallow groove S1 is defined as the distance from the opening to the bottom of the first shallow groove S1, and the length L5 of the second shallow groove S2 is defined as the distance from the opening to the bottom of the second shallow groove S2.

[0062] In addition Figure 5 In the embodiment, the profile of the first shallow trench S1 is the same as the profile of the second shallow trench S2, the width of the opening of the first shallow trench S1 is the same as the width of the opening of each second trench 24 / 26 / 28, and the profile of each second trench 24 / 26 / 28 is the same. However, the width of the opening of each second trench 24 / 26 / 28, the number of the second trenches 24 / 26 / 28, the number of the first shallow trenches S1, and the number of the second shallow trenches S2 can be adjusted as needed, as long as the pattern on the patterned mask 22 is modified. For example, Figure 8 As shown, the bottom 1 of the first trench 20 may have three second trenches 26 / 28 / 32 at the same time, and the width of the opening of each second trench 26 / 28 / 32 is smaller than the width of the opening of the second trench 24, and the width of the opening of the second trench 24 is greater than the width of the opening of the first shallow trench S1. Fig. 9 As shown, the width of the opening of the second trench 24 is smaller than the width of the opening of the first shallow trench S1 , and the width of the opening of the second trench 26 is smaller than the width of the opening of the second trench 28 .

[0063] like Figure 6 As shown, continued Figure 5The manufacturing process is to form an insulating layer 34 to fill the first trench 18 / 20, the second trench 24 / 26 / 28, the first shallow trench S1 and the second shallow trench S2, and the upper surface of the insulating layer 34 is aligned with the upper surface of the pad silicon nitride 14. So far, the semiconductor structure 100 with deep trench insulation and shallow trench insulation of the present invention has been completed. The first trench 18, the second trench 24 and the insulating layer 24 in the first trench 18 and the second trench 24 constitute a deep trench insulation DI1, the first trench 20, the second trench 26, the second trench 28 and the insulating layer 34 in the first trench 20, the second trench 26 and the second trench 28 constitute a deep trench insulation DI2, the first shallow trench S1 and the insulating layer 34 in the first shallow trench S1 constitute a shallow trench insulation SI1, and the second shallow trench S2 and the insulating layer 34 in the second shallow trench S2 constitute a shallow trench insulation SI2.

[0064] The semiconductor structure 100 with deep trench insulation and shallow trench insulation of the present invention can be used to manufacture high-voltage transistors and fin-shaped transistors in the future. Figure 7 As shown, the pad silicon nitride 14, the pad silicon oxide 12 and a portion of the insulating layer 34 are removed, so that the fin structure 30 in the low voltage transistor region L protrudes from the surface of the insulating layer 34 and the insulating layer 34 in the high voltage transistor region H is aligned with the upper surface of the substrate 10. Then, a high voltage transistor T1 is formed on the substrate 10 between the deep trench insulation DI1 and the deep trench insulation DI2, and a fin transistor T2 is formed on the fin structure 30.

[0065] Figure 6 A semiconductor structure with deep trench insulation and shallow trench insulation is shown according to a preferred embodiment of the present invention. Figure 5 and Figure 6The semiconductor structure 100 with deep trench insulation and shallow trench insulation includes a substrate 10, the substrate 10 includes a high voltage transistor region H and a low voltage transistor region L, a pad silicon oxide 12 and a pad silicon nitride 14 cover the substrate 10 of the high voltage transistor region H and the low voltage transistor region L, a deep trench D1 is set in the pad silicon nitride 14, the pad silicon oxide 12 and the substrate 10 in the high voltage transistor region H, wherein the deep trench D1 includes a first trench 18 and a second trench 24, wherein the first trench 18 includes a bottom 18a, the second trench 24 includes a bottom 18b, and the second trench 24 includes a bottom 18c. The two trenches 24 extend from the bottom 18a to the bottom of the substrate 10. A first shallow trench S1 and a second shallow trench S2 are disposed in the pad silicon nitride 14, the pad silicon oxide 12 and the substrate 10 of the low voltage transistor region L. The first shallow trench S1 and the second shallow trench S2 define a fin structure 30 on the substrate 10, wherein the length L4 of the first shallow trench S1 and the length L1 of the second trench 24 are the same, and an insulating layer 34 is filled in the first trench 17, the second trench 24, the first shallow trench S1 and the second shallow trench S2 respectively. In addition, the deep trench may also have two second trenches, such as the deep trench D2 including the second trench 26 and the second trench 28, the second trench 26 and the second trench 28 both extend from the bottom 20a to the bottom of the substrate 10, the second trench 28 is located on one side of the second trench 26, and the insulating layer 34 fills the second trench 26 and the second trench 28.

[0066] Furthermore, the profile of the second trench 24 may be the same as or different from the profile of the first shallow trench S1 , and the profile of the second trench 24 may be the same as or different from the profile of the second trench 26 / 28 .

[0067] Fig.10 FIG. 1 is an enlarged schematic diagram of a deep trench isolation according to a preferred embodiment of the present invention, wherein components having the same function and position will use the same reference numerals. Fig.10 As shown, the first trench 18 in the deep trench insulation DI1 of the present invention includes a first side wall 18b and a bottom 18a, the inner surface of the first side wall 18b contacts the insulating layer 34, the second trench 24 also includes a bottom 24a and a second side wall 24b, the inner surface of the second side wall 24b contacts the insulating layer 34, a first angle A is provided between the inner surface of the first side wall 18b and the bottom 18a, a second angle B is provided between the inner surface of the second side wall 24b and the bottom 24a, the first angle A is less than 100 degrees, the second angle B is less than 95 degrees, the degree of the first angle A is different from the degree of the second angle B, and the first angle A is preferably greater than the second angle B.

[0068] The deep trench in the high-voltage transistor region of the present invention is composed of a first trench and a second trench, that is, the length of the deep trench is divided into two etching processes to ensure that the deep trench meets the designed depth. In addition, the second trench and the shallow trench located in the low-voltage transistor region are manufactured using the same etching process, so there is no need to add additional manufacturing process steps.

[0069] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor structure having deep trench insulation and shallow trench insulation, comprising: A substrate including a high voltage transistor region and a low voltage transistor region; Pad silicon oxide and pad silicon nitride, covering the high voltage transistor region and the low voltage transistor region; A deep trench is disposed in the pad silicon nitride, the pad silicon oxide and the substrate in the high voltage transistor region, wherein the deep trench comprises: a first trench, wherein the first trench comprises a first bottom; as well as A second trench, wherein the second trench extends from the first bottom to the bottom of the substrate; a first shallow trench and a second shallow trench, disposed in the pad silicon nitride, the pad silicon oxide and the substrate in the low voltage transistor region, the first shallow trench and the second shallow trench defining a fin structure on the substrate, wherein the length of the first shallow trench is the same as the length of the second trench; as well as The insulating layer fills the first trench, the second trench, the first shallow trench and the second shallow trench respectively.

2. A semiconductor structure with deep trench insulation and shallow trench insulation as described in claim 1, wherein the length of the first shallow trench is the distance from the opening of the first shallow trench to the bottom of the first shallow trench, and the length of the second trench is the distance from the opening of the second trench to the bottom of the second trench. 3 . The semiconductor structure with deep trench insulation and shallow trench insulation as claimed in claim 1 , wherein a width of an opening of the first shallow trench is the same as a width of an opening of the second trench. 4 . The semiconductor structure with deep trench insulation and shallow trench insulation as claimed in claim 1 , wherein a width of an opening of the first shallow trench is different from a width of an opening of the second trench. 5 . The semiconductor structure with deep trench isolation and shallow trench isolation as claimed in claim 1 , wherein a profile of the first shallow trench is the same as a profile of the second shallow trench.

6. A semiconductor structure with deep trench insulation and shallow trench insulation as described in claim 1, wherein the first trench further includes a first sidewall, the inner surface of the first sidewall contacts the insulating layer, the second trench further includes a second bottom and a second sidewall, the inner surface of the second sidewall contacts the insulating layer, a first angle is formed between the inner surface of the first sidewall and the first bottom, a second angle is formed between the inner surface of the second sidewall and the second bottom, the first angle is less than 100 degrees, and the second angle is less than 95 degrees. 7 . The semiconductor structure with deep trench isolation and shallow trench isolation as claimed in claim 6 , wherein the degree of the first angle is different from the degree of the second angle.

8. The semiconductor structure with deep trench insulation and shallow trench insulation as described in claim 1, wherein the deep trench further includes a third trench extending from the first bottom to the bottom of the substrate, the insulating layer fills the third trench, and the third trench is located on one side of the second trench. 9 . The semiconductor structure with deep trench isolation and shallow trench isolation as claimed in claim 8 , wherein a profile of the third trench is the same as a profile of the second trench. 10 . The semiconductor structure with deep trench isolation and shallow trench isolation as claimed in claim 8 , wherein a profile of the third trench is different from a profile of the second trench.

11. A method for manufacturing a deep trench insulation of a high voltage transistor region and a shallow trench insulation of a low voltage transistor region, comprising: Providing a substrate, the substrate comprising a high-voltage transistor region and a low-voltage transistor region, wherein pad silicon nitride and pad silicon oxide cover the high-voltage transistor region and the low-voltage transistor region; etching the pad silicon nitride, the pad silicon oxide, and the substrate of the high voltage transistor region to form a first trench in the pad silicon nitride, the pad silicon oxide, and the substrate; Forming a patterned mask to cover the high voltage transistor region and the low voltage transistor region, wherein the patterned mask fills the first trench, the patterned mask in the high voltage transistor region defines a predetermined position of the second trench, and the patterned mask in the low voltage transistor region defines a predetermined position of the first shallow trench and a predetermined position of the second shallow trench; Using the patterned mask as a mask, etching the substrate to extend a second trench from a first bottom of the first trench, and forming a first shallow trench and a second shallow trench in the low voltage transistor region; removing the patterned mask after forming the second trench, the first shallow trench, and the second shallow trench; as well as An insulating layer is formed to fill the first trench, the second trench, the first shallow trench and the second shallow trench.

12. A method for manufacturing deep trench insulation integrating a high-voltage transistor region and shallow trench insulation integrating a low-voltage transistor region as described in claim 11, wherein the length of the first shallow trench is the distance from the opening of the first shallow trench to the bottom of the first shallow trench, the length of the second trench is the distance from the opening of the second trench to the bottom of the second trench, and the length of the first shallow trench is the same as the length of the second trench. 13 . The method for manufacturing the integrated deep trench insulation of the high voltage transistor region and the shallow trench insulation of the low voltage transistor region as claimed in claim 11 , wherein the width of the opening of the first shallow trench is the same as the width of the opening of the second trench. 14 . The method for manufacturing the integrated deep trench insulation of the high voltage transistor region and the shallow trench insulation of the low voltage transistor region as claimed in claim 11 , wherein the width of the opening of the first shallow trench is different from the width of the opening of the second trench.

15. A method for manufacturing deep trench insulation integrating a high-voltage transistor region and shallow trench insulation integrating a low-voltage transistor region as described in claim 11, wherein the first trench further comprises a first sidewall, an inner surface of the first sidewall contacts the insulating layer, the second trench further comprises a second bottom and a second sidewall, an inner surface of the second sidewall contacts the insulating layer, a first angle is formed between the inner surface of the first sidewall and the first bottom, a second angle is formed between the inner surface of the second sidewall and the second bottom, the first angle is less than 100 degrees, and the second angle is less than 95 degrees. 16 . The method for manufacturing the integrated deep trench insulation of the high voltage transistor region and the shallow trench insulation of the low voltage transistor region as claimed in claim 15 , wherein the degree of the first angle is different from the degree of the second angle.

17. The method for manufacturing the deep trench insulation of the integrated high-voltage transistor region and the shallow trench insulation of the low-voltage transistor region as described in claim 11 further comprises using the patterned mask as a mask to etch the substrate to form a third trench extending from the first bottom, the insulating layer filling the third trench, and the third trench being located on one side of the second trench. 18 . The method for manufacturing the integrated deep trench insulation of the high voltage transistor region and the shallow trench insulation of the low voltage transistor region as claimed in claim 11 , wherein the profile of the third trench is the same as the profile of the second trench. 19 . The method for manufacturing a deep trench insulation of a high voltage transistor region and a shallow trench insulation of a low voltage transistor region as claimed in claim 11 , wherein a profile of the third trench is different from a profile of the second trench. 20 . The method for manufacturing the integrated deep trench insulation of the high voltage transistor region and the shallow trench insulation of the low voltage transistor region as claimed in claim 11 , wherein the first shallow trench and the second shallow trench define a fin structure on the substrate.

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