Integrated circuit structure with backside contact exposure uniformity

Abstract

Integrated circuit structures with backside contact reveal uniformity and methods of making integrated circuit structures with backside contact reveal uniformity are described. In an example, an integrated circuit structure includes an integrated circuit structure including a plurality of horizontally stacked nanowires or fins. A gate stack is over the plurality of horizontally stacked nanowires or fins. An epitaxial source or drain structure is located at one end of the plurality of horizontally stacked nanowires or fins. A conductive source or drain contact is vertically below and in contact with the bottom of the epitaxial source or drain structure. And the conductive source electrode or the drain electrode contact part is positioned in the cavity in the isolation layer. The isolation layer extends laterally under the gate stack.

Description

Technical Field

[0001] Embodiments of the present disclosure are in the field of advanced integrated circuit structure fabrication, and in particular, integrated circuit structures with backside contact exposure uniformity and methods of fabricating integrated circuit structures with backside contact exposure uniformity. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the continued growth of the semiconductor industry. Scaling to smaller and smaller features enables the density of functional units to be increased on the limited footprint of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be incorporated on a chip, which helps to manufacture products with increased capacity. However, the pursuit of greater and greater capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly important.

[0003] Variability in conventional and currently known manufacturing processes may limit the possibility of further scaling to the 10 nm node or sub-10 nm node range. Therefore, manufacturing the functional components required for future technology nodes may require the introduction of new methods in current manufacturing processes or the integration of new technologies or replacement of current manufacturing processes.

[0004] In the manufacture of integrated circuit devices, multi-gate transistors (e.g., tri-gate transistors) have become more popular as device dimensions continue to shrink. Tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred because of their lower cost and compatibility with existing high-volume bulk silicon substrate infrastructure.

[0005] However, scaling multi-gate transistors is not without consequences. As the size of these fundamental building blocks of microelectronic circuitry decreases, and as the absolute number of fundamental building blocks fabricated in a given area increases, limitations on the semiconductor processes used to fabricate these building blocks have become inevitable. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are shown according to embodiments of the present disclosure.

[0007] Figure 2-Figure 3 Cross-sectional views and corresponding backside (BS) plan views representing various operations in a method of fabricating an integrated circuit structure with backside exposure for eventual backside gate contact or source or drain contact formation, in accordance with an embodiment of the present disclosure.

[0008] Figure 4-Figure 7Angled bottom cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having backside reveal uniformity for final backside gate contact or source or drain contact formation are illustrated.

[0009] Figure 8 and Fig.9A Depicted are cross-sectional views and corresponding back-side (BS) plan views representing various operations in a method of fabricating an integrated circuit structure having a directionally widened backside gate contact or source or drain contact, in accordance with an embodiment of the present disclosure.

[0010] Fig. 9B Cross-sectional views and corresponding back-side (BS) plan views illustrate operations in a method of fabricating an integrated circuit structure having a directionally widened backside source or drain contact in accordance with an embodiment of the present disclosure.

[0011] Fig. 10A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0012] Fig. 10B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0013] Fig.11A A plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0014] Fig. 11B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0015] Figure 12A-12J Cross-sectional views are illustrated of various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0016] Fig.13 A computing device according to one embodiment of the present disclosure is shown.

[0017] Fig.14 An interposer including one or more embodiments of the present disclosure is shown.

[0018] Fig.15 is an isometric view of a mobile computing platform employing an IC manufactured according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

[0019] Fig.16 A cross-sectional view of a flip-chip mounted die is shown in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Integrated circuit structures with uniform backside contact exposure and methods for manufacturing integrated circuit structures with uniform backside contact exposure are described. In the following description, many specific details are set forth, such as specific integration and material systems, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features (such as integrated circuit design layouts) are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0021] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "used as an example, instance or illustration". Any embodiment described herein as exemplary is not necessarily to be construed as being preferred or advantageous over other embodiments. In addition, there is no intention to be bound by any express or implied theory presented in the prior art field, background technology, summary of the invention or the following detailed description.

[0022] This specification includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0023] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0024] "Comprising". This term is open ended. As used in the appended claims, this term does not exclude additional structures or operations.

[0025] "Configured to." Various units or components may be described or claimed as being "configured to" perform one or more tasks. In such a context, "configured to" is used to imply structure by indicating that the unit or component includes structure to perform those one or more tasks during operation. Thus, even when the specified unit or component is not currently operating (e.g., not turned on or active), the unit or component can be said to be configured to perform a task. Reciting a unit or circuit or component as "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, sixth paragraph, with respect to that unit or component.

[0026] "First," "second," etc. As used herein, these terms serve as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0027] "Coupled" - The following description refers to elements, nodes or features that are "coupled" together. As used herein, unless expressly specified otherwise, "coupled" means that one element or node or feature is directly or indirectly joined to (or directly or indirectly communicates with) another element or node or feature (and not necessarily mechanically).

[0028] In addition, certain terms may also be used in the following description for reference purposes only, and therefore are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation or position, or both, of portions of a component within a consistent but arbitrary reference system, which may be clearly understood by reference to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0029] "Inhibit" - As used herein, "inhibit" is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, motion, or condition, it may completely prevent a result, consequence, or future state. Additionally, "inhibit" may also refer to reducing or mitigating a result, property, or effect that might otherwise occur. Thus, when a component, element, or feature is said to inhibit a result or state, it need not completely prevent or eliminate that result or state.

[0030] Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses all processes up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0031] Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0032] The embodiments described below may be applicable to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, although FEOL process scenarios may be used to illustrate exemplary process schemes, such methods may also be applicable to BEOL processes. Similarly, although BEOL process scenarios may be used to illustrate exemplary process schemes, such methods may also be applicable to FEOL processes.

[0033] One or more embodiments are directed to selective dielectric etching to improve backside contact exposure uniformity and prevent front-to-backside shorting. One or more embodiments described herein are directed to backside exposed integrated circuit structures including nanowire stacks. It should be understood that references to nanowires herein may indicate nanowires or nanoribbons or nanosheets or forked sheets unless otherwise indicated. One or more embodiments described herein are directed to backside exposed integrated circuit structures including fins.

[0034] To provide context, as poly pitch and cell height scale, the etches that define features such as nominal trench depth (NTD), metal gate cut (MGC), and fin trim isolation (FTI) become more difficult to control. If these etches exceed the depth of the shallow trench isolation (STI), these features will be revealed during the backside reveal process. Revealing these features may reduce the uniformity of the reveal polish, and any voids in the fill of these revealed features may create front-to-backside shorts. Filling these features after selectively etching back with a material that can be polished simultaneously with the STI solves both of these problems.

[0035] To provide background, features such as nominal trench depth (NTD), metal gate cut (MGC), and fin trim isolation (FTI) are etched and typically filled with a dielectric different from that of shallow trench isolation (STI). In accordance with one or more embodiments of the present disclosure, where the etch to define these features has extended below the STI, the following sequence: (1) etch back of the dielectric material that is selective to the STI dielectric, and (2) fill with a material that can be polished simultaneously with the STI dielectric, can be used to improve the uniformity of the reveal polish and avoid front-to-backside shorting. An example of this technique is etch back of ALD SiN that is selective to the STI oxide, followed by fill with ALD oxide.

[0036] To provide further context, as semiconductor scaling continues, low resistance power delivery solutions are needed to fit interconnects into increasingly compact spaces. Backside power delivery, a scheme where the power delivery interconnect network connects directly to the transistors from the backside of the wafer rather than sharing space with frontside wiring, is a possible solution for future semiconductor technology generations.

[0037] Traditionally, power is delivered from the front side interconnect. At the standard cell level, power can be delivered just on the top of the transistor or from the top or bottom cell boundary. The power delivered from the top or bottom cell boundary achieves a relatively short standard cell height and a slightly higher power network resistance. However, the front side power network shares the interconnect stack with the signal wiring, and reduces the signal wiring path. In addition, for high-performance design, the top or bottom cell boundary power metal wire must be wide enough to reduce the power network resistance and improve performance. This usually causes the cell height to increase. According to one or more embodiments of the present disclosure, power can be delivered from the back side of the wafer or substrate to solve area and performance problems. At the cell level, the wider metal 0 power at the top and bottom cell boundaries may no longer be needed, and therefore, the cell height can be reduced. In addition, the power network resistance can be significantly reduced, thereby bringing performance improvements. At the block and chip level, due to the removed power wiring, the front side signal wiring path is increased, and due to very wide wires, large vias and reduced interconnect layers, the power network resistance is significantly reduced.

[0038] In earlier technologies, the power delivery network from bumps to transistors required a large amount of block resources. Such resource usage on the metal stack has in some process nodes lent itself to standard cell architectures with layout versioning or cell placement restrictions at the block level. In an embodiment, eliminating the power delivery network from the front-side metal stack allows for free translational cell placement in a block without power delivery complexity and placement-related delay timing variations.

[0039] As an illustrative comparison, Figure 1 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are shown according to embodiments of the present disclosure.

[0040] refer to Figure 1 , an interconnect stack 100 with front-side power delivery includes a transistor 102 and a signal and power delivery metallization 104. The transistor 102 includes a bulk substrate 106, a semiconductor fin 108, a terminal 110, and a device contact 112. The signal and power delivery metallization 104 includes a conductive via 114, a conductive line 116, and a metal bump 118.

[0041] Reference again Figure 1 , an interconnect stack 150 with backside power delivery includes a transistor 152, a frontside signal metallization 154A, and a power delivery metallization 154B. The transistor 152 includes a semiconductor nanowire or nanoribbon 158, a terminal 160 and a device contact 162, and a boundary deep via 163. The frontside signal metallization 154A includes a conductive via 164A, a conductive line 166A, and a metal bump 168A. The power delivery metallization 154B includes a conductive via 164B, a conductive line 166B, and a metal bump 168B. It should be understood that the backside power method can also be implemented for a structure including a semiconductor fin.

[0042] To provide further background, a fundamental component of a backside power delivery network is an electrically functional feature that interfaces a source or drain contact of a transistor with the backside interconnect network. Therefore, designs and methods for fabricating interface features that are compatible with existing library cell design conventions and transistor contact process flows are needed.

[0043] Since backside power delivery has not yet been introduced in high volume manufacturing, no solution is currently being adopted in high volume manufacturing. Approaches may ultimately include deep trench contacts (TCNs), direct source-drain contacts from the backside, or replacing gate contact paths with backside power contacts. Depending on the proposed solution, the solution may suffer from high resistance contacts that negate the inherent value of backside power delivery co-optimization with front-end transistor processing, resulting in defects and performance risks and tradeoffs.

[0044] According to an embodiment of the present disclosure, a selective dielectric etch is performed to improve backside exposure uniformity and prevent front-to-backside shorting. The etch defines a nominal trench depth (NTD) on the front side that lands below the bottom of the STI, so that the spacer-filled NTD is exposed on the back side in a via without a backside contact. After the Si sub-fin is removed using etching, the NTD is etched back using a selective dielectric etch (SiN selective to SiOx) and the isolation nitride that has surrounded the sub-fin is removed. A fillable oxide is then deposited and polished back to reveal the backside contact footprint.

[0045] As an exemplary treatment scheme, Figure 2-Figure 3 Cross-sectional views and corresponding backside (BS) plan views representing various operations in a method of fabricating an integrated circuit structure with backside exposure for eventual backside gate contact or source or drain contact formation, in accordance with an embodiment of the present disclosure. Figure 4-Figure 7 Angled bottom cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having backside exposure uniformity for final backside gate contact or source or drain contact formation are shown. It should be understood that the described and illustrated embodiments may also be applicable to fin structures in place of stacks of nanowires or nanoribbons or nanosheets.

[0046] about Figure 2 and Figure 3 , the structures are shown as being performed on the original backside of the device wafer, but the figures are oriented with the original frontside of the wafer facing upward. In addition, Figure 2 The focus is on the gate contact formation position, while Figure 3 The focus is on the source or drain contact formation position. Figure 2 and Figure 3 Respectively, the gate structure and the source or drain structure are represented after the front side processing is completed, the device wafer is bonded to a carrier, is flipped over and then the back side is exposed.

[0047] refer to Figure 2 , in the gate region, the starting structure 200 includes a plurality of horizontally stacked nanowires (or nanoribbons or nanosheets, or alternatively, fins) 202, such as silicon nanowires located on silicon sub-fins, located on top of a sub-fin 204. A gate stack 206 (e.g., a stack including a metal gate electrode and a high-k gate dielectric layer) is located on and around the plurality of horizontally stacked nanowires 202. Dielectric sidewall spacers 208 (e.g., silicon nitride or carbon-doped silicon nitride spacers) are along the sides of the gate stack 206. A shallow trench isolation structure 210 (e.g., a silicon oxide isolation structure) is adjacent to the sub-fin 204. As can be seen from a backside (BS) plan view, a dielectric placeholder 212 (e.g., a silicon nitride placeholder) may be formed at a source or drain location (e.g., in combination with a gate electrode). Figure 3 described).

[0048] refer to Figure 3 , in the source or drain region, the starting structure 200 includes an epitaxial source or drain structure 214 (e.g., an epitaxial silicon or silicon germanium source or drain structure) located on and around a portion of the plurality of horizontally stacked nanowires 202 located outside the gate electrode (channel) region. In another embodiment (not shown), a portion of the plurality of horizontally stacked nanowires 202 is removed from the source or drain location, and the epitaxial source or drain structure 214 is located at one end of the horizontally stacked nanowires 202.

[0049] about Figure 4-Figure 7 , the structures are shown as being performed on the original backside of the device wafer, with the figures oriented with the original frontside of the wafer facing downward.

[0050] refer to Figure 4 , structure 400 includes a front side protection layer 402 and a front side structure 404, wherein the latter may represent a plurality of front side metallization layers. The device layer may include a gate structure 406 and a trench contact structure 408. Protruding features visible from the back side after planarization of the bulk substrate may include: a shallow trench isolation (STI) structure 410 (e.g., a silicon oxide or silicon dioxide structure), a sub-fin structure 412 (e.g., a silicon sub-fin structure), a gate spacer extension 414 (e.g., a silicon nitride gate spacer extension), an STI liner material 416 (e.g., a silicon nitride STI liner material), and a source or drain contact placeholder structure 418 for eventual replacement with a back side contact material. Although not visible from this angle, it should be understood that the gate structure 406 may have a corresponding plurality of underlying horizontally stacked nanowires (or nanoribbons or nanosheets, etc.) or fins.

[0051] refer to Figure 5 , the sub-fin structure 412 is removed using a silicon etch to form a trench 420. At this stage, a P-type epitaxial source or drain structure 422 and an N-type epitaxial source or drain structure 424 that are not targeted for backside contacts (i.e., not associated with source or drain contact placeholder structures) may be revealed.

[0052] refer to Figure 6 , a silicon nitride etch is used to recess the gate spacer extension 414 and the STI liner material 416 , the latter recessing forming a trench 426 .

[0053] refer to Figure 7, trenches 420 and 426 are filled with the same or substantially the same material as shallow trench isolation (STI) structure 410, for example, with silicon oxide or silicon dioxide, and the structure is planarized. The result includes a backside dielectric layer 428 (a combination of the shallow trench isolation (STI) structure 410 and the filling material of trenches 420 and 426), in which the source or drain contact placeholder structure 418 is exposed. Subsequent processing may include removing one or more of the contact placeholder structures 418 and backfilling with a conductive contact material (e.g., tungsten or cobalt) to form a conductive source or drain contact. In one embodiment, prior to backfilling, the opening formed after removing the source or drain contact placeholder structure 418 may be widened, an example of which is described below in conjunction with Fig.9A and Fig. 9B In addition, it should be understood that the contact portion may be formed below the gate electrode location (and it may also be widened), examples of which are described below in conjunction with Figure 8 Described.

[0054] With regard to the detectability of implementation of the embodiments described herein, a cross section may show features of a dielectric material that are recessed and filled with different dielectrics. The dielectric that fills these recessed features may have a seam opening in the direction of the exposed backside surface, indicating filling from the backside. APT or similar techniques may show the type of etchant (e.g., F, Br, etc.) embedded in the surrounding material. It should be understood that although the above figures show transistors based on a full surround gate, the embodiments may be applied to channels of any shape or material (fins, nanowires, nanobelts, nanocombs / fork-type sheets, etc.). It should be understood that although the figures show a single-layer transistor, the embodiments may be applied to a multi-layer transistor architecture. It should be understood that although the figures show widening of the structure located on the back side of the device, the embodiments may be applied to any other feature located anywhere on the wafer (e.g., a front-side via landing area).

[0055] In another aspect, one or more embodiments are directed to angled etching for wider via landing areas. One or more embodiments described herein are directed to integrated circuit structures fabricated using dimension-modifying etching for backside gate or source or drain contact widening. It should be understood that references to nanowires herein may refer to nanowires or nanoribbons unless otherwise indicated.

[0056] To provide context, previous approaches for backside connections to transistor gates use the original substrate (e.g., sub-fins) as a placeholder for the final first-layer backside metal (BM0) to gate vias (i.e., BVGs). This area is significantly narrower than the active gate area in the device and can limit the BVG / gate overlap, thereby limiting design and lithography overlap requirements. Additionally, backside contacts to epitaxial source / drain can also benefit from larger contacts to lower Rext.

[0057] The current state of the art backside power contact process flow allows self-aligned contacts to source / drain on the backside of the wafer, but may benefit from a larger space in which to form low resistance contacts to the epitaxial source / drain. It should be understood that a closely pitched backside connection may be required.

[0058] According to one or more embodiments of the present disclosure, a method is described by which a via landing area can be widened using an angled directional etch. As an example, a backside contact to a transistor (gate or source / drain) is formed, wherein sacrificial material is removed and the subsequent hole is widened using an angled directional etch. It should be understood that the embodiments described herein can be implemented to allow the hole to be widened to exceed any boundary material. In some embodiments, the widening is performed in only one direction.

[0059] In combination with Figure 4-Figure 7 Following the described uniform backside exposure process, the openings made for backside contact formation can be widened to be larger than the backside exposed features. As an exemplary processing scheme, Figure 8 and Fig.9A Cross-sectional views and corresponding back-side (BS) plan views representing various operations in a method of fabricating an integrated circuit structure with a directionally widened backside gate contact or source or drain contact in accordance with an embodiment of the present disclosure are shown. It should be understood that the described and illustrated embodiments may also be applicable to fin structures in place of a stack of nanowires or nanoribbons or nanosheets.

[0060] about Figure 8 and Fig.9A , the structures are shown as being performed on the original backside of the device wafer, but all figures are oriented with the original frontside of the wafer facing upward. Figure 8 The focus is on gate contact manufacturing, while Fig.9A The focus is on the source or drain contact manufacturing. Figure 8 and Fig.9A They respectively represent the gate structure and the source or drain structure after directional etching.

[0061] refer to Figure 8, using an angled directional etch, the cavity is widened in the direction along arrow 820 to form cavity 816A. Widening the cavity to form cavity 816A can increase the contact area of ​​the gate stack in one dimension (parallel to the source or drain structure, i.e., along the direction of arrow 820) without the risk of ultimately shorting in another direction (towards the source or drain region, i.e., along the direction orthogonal to arrow 820). In one embodiment, as depicted, the remainder of the initial cavity exists in the back side of the gate stack 806 as a stepped feature. It should be understood that subsequent processing may include forming a backside conductive gate contact structure in cavity 816A.

[0062] refer to Fig.9A , the cavity is widened in the direction along arrow 922 using an angled directional etch to form cavity 918A. Widening the cavity to form cavity 918A can increase the contact area of ​​the gate stack in one dimension (parallel to the source or drain structure, i.e., along the direction of arrow 922) without the risk of ultimately shorting in another direction (towards the source or drain region, i.e., along the direction orthogonal to arrow 922). It should be understood that subsequent processing can include forming a back-side conductive source or drain contact structure in cavity 918A.

[0063] It should be understood that the widening of the cavity may be performed in only a single direction. As an exemplary processing scheme, Fig. 9B A cross-sectional view and corresponding backside (BS) plan view of operations in a method of manufacturing an integrated circuit structure with a directionally widened backside source or drain contact according to an embodiment of the present disclosure are shown. It should be understood that the described and illustrated embodiments may also be applicable to fin structures in place of a stack of nanowires or nanoribbons or nanosheets. Fig. 9B Indicates that different from Fig.9A The source or drain structure after the directional etching in the directional etching.

[0064] refer to Fig. 9B , the cavity is widened in the direction along arrow 958 using an angled directional etch to form cavity 956. Widening the cavity to form cavity 956 can increase the contact area of ​​the source or drain structure in only one direction in one dimension (parallel to the source or drain structure, i.e., along the direction of arrow 958) without the risk of ultimately shorting in the other direction (towards the source or drain region, i.e., along the direction orthogonal to arrow 958). It should be understood that subsequent processing can include forming a back-side conductive source or drain contact structure in cavity 956.

[0065] It should be understood that Figure 8 , Fig.9A and Fig. 9B The widening of the contact openings in the process can be distinguished from isotropic etching, in which the openings are widened in all lateral directions. Such isotropic widening can surround the boundary material and increase the risk of shorting with adjacent structures. Regarding the detectability of the embodiments described herein, the cross section can show the area widened beyond the boundary material without etching around those boundary materials. APT or similar techniques can show the type of etchant (e.g., F, Br, etc.) embedded in the surrounding material. It should be understood that although the above figures show transistors based on a fully surrounding gate, the embodiments can be applied to channels of any shape or material (fins, nanowires, nanobelts, nanocombs / fork-shaped sheets, etc.). It should be understood that although the figures show a single-layer transistor, the embodiments can be applied to a multi-layer transistor architecture. It should be understood that although the figures show the widening of the structure located on the back side of the device, the embodiments can be applied to any other feature located anywhere on the wafer (e.g., a front-side via landing area).

[0066] In another aspect, it should be understood that the backside contact exposure uniformity method can be implemented using the front side architecture. In one example, the backside contact exposure uniformity method can be implemented using the contact over active gate (COAG) structure and process. It should also be understood that the COAG feature below can be applicable to the concepts of the backside gate contact (contact under active gate or CUAG) and source / drain contact described above. One or more embodiments of the present disclosure are directed to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed above the active portion of the gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure are directed to a method for manufacturing a semiconductor structure or device having one or more gate contact structures formed on the active portion of the gate electrode of the semiconductor structure or device. The method described herein can be used to reduce the standard cell area by enabling the gate contact to be formed above the active gate region. According to one or more embodiments, a tapered gate and a trench contact are implemented to achieve COAG manufacturing. Embodiments can be implemented to achieve patterning of tight spacing.

[0067] To provide further context for the importance of the COAG process scheme, in technologies where space and layout constraints are relaxed compared to current generations, a contact to a gate structure may be made by making contact with a portion of a gate electrode disposed over an isolation region. As an example, Fig. 10A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0068] refer to Fig. 10A , semiconductor structure or device 1000A includes a diffusion or active region 1004 disposed in substrate 1002 and within isolation region 1006. One or more gate lines (also referred to as poly lines) (e.g., gate lines 1008A, 1008B, and 1008C) are disposed over diffusion or active region 1004 and over a portion of isolation region 1006. Source or drain contacts (also referred to as trench contacts) (e.g., contacts 1010A and 1010B) are disposed over source and drain regions of semiconductor structure or device 1000A. Trench contact vias 1012A and 1012B provide contact to trench contacts 1010A and 1010B, respectively. A separate gate contact 1014 and an overlying gate contact via 1016 provide contact to gate line 1008B. In contrast to the source or drain trench contacts 1010A or 1010B, from a plan view perspective, the gate contact 1014 is disposed over the isolation region 1006 but not over the diffusion or active region 1004. In addition, neither the gate contact 1014 nor the gate contact via 1016 is disposed between the source or drain trench contacts 1010A and 1010B.

[0069] Fig. 10B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown. Fig. 10B , semiconductor structure or device 1000B (e.g., Fig. 10A 100A) includes a non-planar diffusion or active region 1004B (e.g., a fin structure) formed by a substrate 1002 and located within an isolation region 1006. A gate line 1008B is disposed over the non-planar diffusion or active region 1004B and over a portion of the isolation region 1006. As shown, the gate line 1008B includes a gate electrode 1050 and a gate dielectric layer 1052, as well as a dielectric cap layer 1054. It can also be seen from this perspective that the gate contact 1014 and the overlying gate contact via 1016, as well as the overlying metal interconnect 1060, are all disposed in an interlayer dielectric stack or layer 1070. From Fig. 10B It can also be seen from the perspective of FIG. 1 that the gate contact 1014 is disposed over the isolation region 1006 , but is not disposed over the non-planar diffusion or active region 1004B.

[0070] Reference again Fig. 10A and Fig. 10B, the arrangement of semiconductor structures or devices 1000A and 1000B respectively places the gate contact above the isolation region. Such an arrangement wastes layout space. However, placing the gate contact above the active area would require an extremely tight registration budget, or the gate size would have to be increased to provide sufficient space to place the gate contact. In addition, historically, contact with the gate above the diffusion region has been avoided due to the risk of drilling through other gate materials (e.g., polysilicon) and contacting the underlying active area. One or more embodiments described herein solve the above-mentioned problems by providing a feasible method and resulting structure for manufacturing a contact structure that contacts a portion of the gate electrode formed above the diffusion or active region.

[0071] As an example, Fig.11A FIG. 1 is a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure. Fig.11A , semiconductor structure or device 1100A includes a diffusion or active region 1104 disposed in a substrate 1102 and within an isolation region 1106. One or more gate lines (e.g., gate lines 1108A, 1108B, and 1108C) are disposed over the diffusion or active region 1104 and over a portion of the isolation region 1106. Source or drain trench contacts (e.g., trench contacts 1110A and 1110B) are disposed over the source and drain regions of the semiconductor structure or device 1100A. Trench contact vias 1112A and 1112B provide contact to trench contacts 1110A and 1110B, respectively. Gate contact via 1116 (which does not have an intervening separate gate contact layer) provides contact to gate line 1108B. Fig. 10A In contrast, from a plan view perspective, gate contact 1116 is disposed over diffusion or active region 1104 and between source or drain contacts 1110A and 1110B.

[0072] Fig. 11B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure is shown. Fig. 11B , semiconductor structure or device 1100B (e.g., Fig.11AThe non-planar version of the device 1100A in FIG. 1 includes a non-planar diffusion or active region 1104B (e.g., a fin structure) formed by a substrate 1102 and located within an isolation region 1106. A gate line 1108B is disposed over the non-planar diffusion or active region 1104B and over a portion of the isolation region 1106. As shown, the gate line 1108B includes a gate electrode 1150 and a gate dielectric layer 1152, as well as a dielectric cap layer 1154. From this perspective, it can also be seen that the gate contact via 1116 is disposed in an interlayer dielectric stack or layer 1170 along with the overlying metal interconnect 1160. In addition, from FIG. Fig. 11B As seen from the perspective of FIG. 1 , the gate contact via 1116 is disposed above the non-planar diffusion or active region 1104B.

[0073] Therefore, refer again Fig.11A and Fig. 11B In an embodiment, the trench contact vias 1112A, 1112B and the gate contact via 1116 are formed in the same layer and are substantially coplanar. Fig. 10A and Fig. 10B In contrast, the contact to the gate line will additionally include an additional gate contact layer, which may, for example, extend perpendicularly to the corresponding gate line. Fig.11A and Fig. 11B In the described (multiple) structures, the manufacture of structures 1100A and 1100B respectively enables the contact to be placed directly on the active gate portion from the metal interconnect layer without shorting to the adjacent source drain region. In an embodiment, such an arrangement provides a large area reduction of the circuit layout by eliminating the need to extend the transistor gate on the isolation to form a reliable contact. As used throughout the text, in an embodiment, a reference to the active portion of the gate refers to the portion of the gate line or structure disposed above the active or diffusion region of the underlying substrate (from a plan view perspective). In an embodiment, a reference to the passive portion of the gate refers to the portion of the gate line or structure disposed above the isolation region of the underlying substrate (from a plan view perspective).

[0074] In an embodiment, the semiconductor structure or device 1100 is a non-planar device, such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 1108A and 1108B surrounds at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is made into a discrete three-dimensional body (e.g., in a full surround gate device). In one such embodiment, the gate electrode stacks of gate lines 1108A and 1108B each completely surround the channel region.

[0075] Generally, one or more embodiments are directed to methods for placing gate contact vias directly on the gate of an active transistor and structures formed thereby. Such methods can eliminate the need to extend gate lines on isolation for contact purposes. Such methods can also eliminate the need for a separate gate contact (GCN) layer for conducting signals from a gate line or structure. In an embodiment, the elimination of the above features is achieved by recessing the contact metal in the trench contact (TCN) and introducing additional dielectric material (e.g., a trench insulation layer (TILA)) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer having etching characteristics different from the gate dielectric material cap layer used for trench contact alignment in a gate aligned contact process (GAP) processing scheme (e.g., using a gate insulation layer (GILA)).

[0076] As an exemplary manufacturing scheme, the starting structure includes one or more gate stack structures disposed on a substrate. The gate stack structure may include a gate dielectric layer and a gate electrode. A trench contact, such as a contact to a diffusion region of the substrate or to an epitaxial region formed in the substrate, is spaced apart from the gate stack structure by a dielectric spacer. An insulating cap layer may be disposed on the gate stack structure (e.g., GILA). In one embodiment, a contact blocking region or "contact plug" that may be made of an interlayer dielectric material is included in the region where contact formation is to be blocked.

[0077] In an embodiment, the contact pattern is substantially perfectly aligned with the existing gate pattern while eliminating the use of lithography operations with extremely tight registration budgets. In one such embodiment, the method enables the use of essentially highly selective wet etching (or anisotropic dry etching processes, some of which are non-plasma, gas phase isotropic etching (e.g., relative to classical dry or plasma etching)) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, as used in other methods, the method enables the elimination of the need for other critical lithography operations for generating the contact pattern. This method also allows perfect or near-perfect self-alignment with a large margin for edge placement errors. In an embodiment, the trench contact grid is not patterned separately, but is formed between polycrystalline (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0078] In addition, the gate stack structure can be manufactured by replacing the gate process. In such a scheme, the dummy gate material (e.g., polysilicon or silicon nitride column material) can be removed and replaced by a permanent gate electrode material. In one such embodiment, in contrast to the earlier processing, a permanent gate dielectric layer is also formed in the process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including aqueous phosphoric acid.

[0079] In an embodiment, one or more methods described herein substantially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in a particular such embodiment, an anneal of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius, such as after forming the gate dielectric layer. The annealing is performed before forming the permanent contact.

[0080] Next, the trench contact may be recessed to provide a recessed trench contact having a height lower than the top surface of the adjacent spacer. An insulating capping layer is then formed on the recessed trench contact (e.g., TILA). According to an embodiment of the present disclosure, the insulating capping layer on the recessed trench contact is composed of a material having different etching characteristics than the insulating capping layer on the gate stack structure.

[0081] The trench contact can be recessed by a process that is selective to the materials of the spacer and the gate insulating cap layer. For example, in one embodiment, the trench contact is recessed by an etching process (e.g., a wet etching process or a dry etching process). The trench contact insulating cap layer can be formed by a process suitable for providing a conformal and sealed layer above the exposed portion of the trench contact. For example, in one embodiment, the trench contact insulating cap layer is formed as a conformal layer located above the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized by chemical mechanical polishing (CMP) to provide a trench contact insulating cap layer only above the recessed trench contact.

[0082] Regarding material combinations suitable for the gate or trench contact insulating capping layer, in one embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon oxide, and the other material is composed of silicon nitride. In another embodiment, one material of the pair of gate and trench contact insulating capping materials is composed of silicon oxide, and the other material is composed of carbon-doped silicon nitride. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon oxide, and the other material is composed of silicon carbide. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon nitride, and the other material is composed of carbon-doped silicon nitride. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon nitride, and the other material is composed of silicon carbide. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of silicon nitride, and the other material is composed of silicon carbide. In another embodiment, one material of a pair of gate and trench contact insulating capping materials is composed of carbon-doped silicon nitride, and the other material is composed of silicon carbide.

[0083] In another aspect, a nanowire or nanoribbon structure is used to implement backside contact exposure uniformity. In a specific example, a nanowire or nanoribbon release process can be performed by replacing the gate trench. An example of such a release process is described below. In addition, in another aspect, back-end (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein can be implemented to achieve front-side and back-side interconnect integration for nanowire transistors. The embodiments described herein can provide methods for achieving relatively wider interconnect spacing. The result can be improved product performance and lower patterning costs. The embodiments can be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0084] One or more embodiments described herein are directed to a dual epitaxial (EPI) connection for a nanowire or nanoribbon transistor using a partial source or drain (SD) and an asymmetric trench contact (TCN) depth. In an embodiment, an integrated circuit structure is fabricated by forming a source-drain opening of a nanowire / nanoribbon transistor partially filled with an SD epitaxial. The remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain sides enables direct contact to a backside interconnect level.

[0085] As an exemplary process flow for fabricating another all-around gate device, Figure 12A-12J Cross-sectional views showing various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure

[0086] refer to Fig. 12A, a method of manufacturing an integrated circuit structure includes: forming a starting stack including alternating sacrificial layers 1204 and nanowires 1206 located above a fin 1202 (e.g., a silicon fin). The nanowires 1206 may be referred to as a vertical arrangement of nanowires. As depicted, a protective cap 1208 may be formed over the alternating sacrificial layers 1204 and nanowires 1206. Also as depicted, a relaxed buffer layer 1252 and a defect modification layer 1250 may be formed under the alternating sacrificial layers 1204 and nanowires 1206.

[0087] refer to Fig. 12B , the gate stack 1210 is formed on the vertical arrangement structure of the horizontal nanowires 1206. Fig. 12C As depicted in , portions of the vertically arranged structure of horizontal nanowires 1206 are then released by removing portions of the sacrificial layer 1204 to provide a recessed sacrificial layer 1204 ′ and cavity 1212 .

[0088] It should be understood that the complete contact can be manufactured without first performing the deep etch and asymmetric contact processing described below. Fig. 12C In either case (e.g., with or without asymmetric contact processing), in an embodiment, the manufacturing process involves using a process scheme that provides a fully-around-gate integrated circuit structure with an epitaxial bump, which can be a vertically discrete source or drain structure.

[0089] refer to Fig.12D , an upper gate spacer 1214 is formed at the sidewalls of the gate structure 1210. A cavity spacer 1216 is formed in the cavity 1212 below the upper gate spacer 1214. A deep trench contact etch is then optionally performed to form a trench 1218 and form a recessed nanowire 1206'. As depicted, there may also be a patterned relaxed buffer layer 1252' and a patterned defect modification layer 1250'.

[0090] like Fig.12E As depicted in , sacrificial material 1220 is then formed in trench 1218. In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0091] refer to Fig.12F , a first epitaxial source or drain structure (e.g., left-hand feature 1222) is formed at a first end of the vertically arranged structure of horizontal nanowire 1206'. A second epitaxial source or drain structure (e.g., right-hand feature 1222) is formed at a second end of the vertically arranged structure of horizontal nanowire 1206'. In an embodiment, as depicted, epitaxial source or drain structure 1222 is a vertically discrete source or drain structure and can be referred to as an epitaxial bump.

[0092] like Figure 12G As depicted in , an interlayer dielectric (ILD) material 1224 is then formed at the sides of the gate electrode 1210 and adjacent to the source or drain structure 1222. Fig.12H , a replacement gate process is used to form a permanent gate dielectric 1228 and a permanent gate electrode 1226. Fig.12I , the ILD material 1224 is then removed. The sacrificial material 1220 is then removed from one of the source drain locations (eg, the right hand side) to form the trench 1232, but the sacrificial material 1220 is not removed from the other of the source drain locations to form the trench 1230.

[0093] refer to Fig.12J , forming a first conductive contact structure 1234 coupled to the first epitaxial source or drain structure (e.g., left-hand feature 1222). Forming a second conductive contact structure 1236 coupled to the second epitaxial source or drain structure (e.g., right-hand feature 1222). The second conductive contact structure 1236 is formed deeper along the fin 1202 than the first conductive contact structure 1234. In an embodiment, although Fig.12J 1202, but the method also includes: forming an exposed surface of a second conductive contact structure 1236 at the bottom of the fin 1202. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, examples of which may include Ti, Ni, Co (for the former) and W, Ru, Co (for the latter).

[0094] In an embodiment, as depicted, the second conductive contact structure 1236 is deeper along the fin 1202 than the first conductive contact structure 1234. In one such embodiment, as depicted, the first conductive contact structure 1234 is not along the fin 1202. In another such embodiment, not depicted, the first conductive contact structure 1234 is partially along the fin 1202.

[0095] In an embodiment, the second conductive contact structure 1236 is along the entire fin 1202. In an embodiment, although not depicted, the second conductive contact structure 1236 has an exposed surface at the bottom of the fin 1202 if the bottom of the fin 1202 is exposed by a backside substrate removal process.

[0096] In another aspect, in order to be able to access two conductive contact structures in a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be manufactured using a backside exposure manufacturing method for a frontside structure. In some exemplary embodiments, the exposure of the backside of a transistor or other device structure requires wafer-level backside processing. In contrast to conventional TSV type technology, the exposure of the backside of a transistor as described herein can be performed at the density of a device unit and even in a sub-region of the device. In addition, such exposure of the backside of a transistor can be performed to substantially remove all donor substrates on which a device layer is disposed during front-side device processing. In this way, micron-deep TSVs become unnecessary when the thickness of the semiconductor in the device unit may be only tens or hundreds of nanometers after the exposure of the backside of the transistor.

[0097] The exposure techniques described herein can enable a paradigm shift from "bottom-up" device manufacturing to "center-out" manufacturing, where the "center" is any layer that is employed in front-side manufacturing, exposed from the back-side, and employed again in back-side manufacturing. Processing both the front-side and the exposed back-side of a device structure can address many of the challenges associated with manufacturing 3D ICs when relying primarily on front-side processing.

[0098] Methods of revealing the back side of the transistor can be used, for example, to remove at least a portion of the carrier layer and the intervening layers of the donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be used.

[0099] In some embodiments, prior to the above steps, the carrier layer is cleaved along a fracture plane substantially parallel to the intermediate layer. A cleavage or fracture process can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cleaved away by practicing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted into the carrier layer to a uniform target depth where a fracture plane is desired. After such a cleavage process, the remaining thickness of the carrier layer in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove a greater thickness of the carrier layer.

[0100] Next, the exposure of the intervening layer is detected. Detection is used to identify the point when the backside surface of the donor substrate has advanced to the point close to the device layer. Any endpoint detection technology known to be suitable for detecting the transition between the materials used in the carrier layer and the intervening layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting the change in light absorption or emission of the backside surface of the donor substrate during the execution of polishing and / or etching. In some other embodiments, the endpoint criteria are associated with the change in light absorption or emission of the byproducts during the polishing or etching of the backside surface of the donor substrate. For example, the absorption or emission wavelength associated with the carrier layer etching byproduct can be changed as a function of the different components of the carrier layer and the intervening layer. In other embodiments, the endpoint criteria are associated with the change in the mass of the substance in the byproduct of polishing or etching the backside surface of the donor substrate. For example, the byproducts of the treatment can be sampled by a quadrupole mass analyzer, and the change in the mass of the substance can be related to the different components of the carrier layer and the intervening layer. In another exemplary embodiment, the endpoint criteria are associated with the change in friction between the backside surface of the donor substrate and the polishing surface in contact with the backside surface of the donor substrate.

[0101] Since non-uniformities in the carrier removal process can be mitigated by the difference in etch rates between the carrier layer and the intervening layer, detection of the intervening layer can be enhanced in cases where the removal process is selective for the carrier layer relative to the intervening layer. Detection can even be skipped if the grinding, polishing and / or etching operation removes the intervening layer at a rate sufficiently lower than the rate at which the carrier layer is removed. If no endpoint criteria are used, then the grinding, polishing and / or etching operation of a predetermined fixed duration can be stopped on the intervening layer material if the thickness of the intervening layer is sufficient for etching selectivity. In some examples, the carrier etch rate:intervening layer etch rate is 3:1-10:1 or greater.

[0102] After exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more component layers in the intervening layer may be removed. For example, the thickness of the intervening layer may be uniformly removed by polishing. Alternatively, the thickness of the intervening layer may be removed using a mask or blanket etching process. The process may employ the same polishing or etching process as used to thin the carrier, or may be a different process with different process parameters. For example, where the intervening layer provides an etch stop for the carrier removal process, the latter operation may employ a different polishing or etching process that is more conducive to the removal of the intervening layer than the removal of the device layer. In the case where the thickness of the intervening layer is to be removed to be less than a few hundred nanometers, the removal process may be relatively slow, may be optimized for uniformity across the wafer, and may be more precisely controlled than the process employed to remove the carrier layer. The CMP process employed may, for example, employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or greater) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layer and embedded in the intervening layer (e.g., as electrical isolation between adjacent device regions).

[0103] For embodiments in which the device layer is exposed by completely removing the intervening layer, the backside processing can begin on the exposed backside of the device layer or a specific device region therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intervening layer and a device region previously fabricated in the device layer (e.g., a source or drain region).

[0104] In some embodiments where wet and / or plasma etching is used to recess the backside of the carrier layer, intervening layer, or device layer, such etching may be a patterned etch or a material selective etch that imparts significant non-planarity or topography to the backside surface of the device layer. As further described below, patterning may be within a device cell (i.e., "intra-cell" patterning) or may be performed across a device cell (i.e., "inter-cell" patterning). In some patterned etch embodiments, at least a portion of the thickness of the intervening layer is employed as a hard mask for backside device layer patterning. Thus, the mask etching process may precede the device layer etching of the corresponding mask.

[0105] The processing scheme described above can produce a donor-host substrate assembly that includes an IC device that exposes the back side of an intermediate layer, the back side of a device layer, and / or the back side of one or more semiconductor regions within a device layer, and / or the front side metallization. Additional backside processing can then be performed on any of these exposed regions during downstream processing.

[0106] As described throughout this application, the substrate is composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, the substrate described herein is a bulk substrate, which is composed of a crystalline silicon, silicon / germanium or germanium layer doped with charge carriers (e.g., but not limited to, phosphorus, arsenic, boron, or a combination thereof) to form an active region. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a crystalline substrate, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate may alternatively be composed of a III-V group material. In an embodiment, the bulk substrate is composed of a III-V group material, such as, but not limited to: gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide or a combination thereof. In one embodiment, the bulk substrate is composed of a III-V group material, and the charge carrier dopant impurity atoms are, for example, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

[0107] As described throughout this application, the isolation region (e.g., shallow trench isolation region or sub-fin isolation region) can be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of a portion of the permanent gate structure from the underlying bulk substrate, or suitable for isolating an active region (e.g., an isolation fin active region) formed within the underlying bulk substrate. For example, in one embodiment, the isolation region is composed of one or more layers of dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or a combination thereof.

[0108] As described throughout this application, the gate line or gate structure may be composed of a gate electrode stack including a gate dielectric layer and a gate electrode layer. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of materials such as but not limited to hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer may include a layer of native oxide formed by the top layers of the semiconductor substrate. In an embodiment, the gate dielectric layer is composed of a high-k portion at the top and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, a portion of the gate dielectric is a “U” shaped structure including a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0109] In one embodiment, the gate electrode is composed of a metal layer, such as, but not limited to: metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxide. In a specific embodiment, the gate electrode is composed of a non-work function setting filling material formed above the metal work function setting layer. Depending on whether the transistor is a PMOS transistor or an NMOS transistor, the gate electrode layer can be composed of a P-type work function metal or an N-type work function metal. In some embodiments, the gate electrode layer can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to: ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxides (e.g., ruthenium oxide). The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9eV and about 5.2eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to: hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). The N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may be composed of a "U"-shaped structure, the U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate, and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In other embodiments of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0110] As described throughout this application, the spacers associated with the gate lines or electrode stacks can be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of the permanent gate structure from an adjacent conductive contact (e.g., a self-aligned contact). For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0111] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or a layer of an insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0112] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. Common examples are lines and structures using copper, which may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term "metal" includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and the like. Therefore, the interconnect may be a single material layer, or may be formed by several layers (including a conductive liner and a filling layer). Any suitable deposition process (e.g., electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In an embodiment, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or an alloy thereof. Interconnects are also sometimes referred to in the art as traces, conductors, wires, metal, or simply interconnects.

[0113] In an embodiment, as also used throughout this specification, the hard mask material is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask materials can be used in different regions to provide different growth or etching selectivities relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer includes a layer of silicon nitride (e.g., silicon nitride), or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material includes a metallic substance. For example, a hard mask or other overlying material may include a layer of titanium or another metal nitride (e.g., titanium nitride). Possibly smaller amounts of other materials (e.g., oxygen) may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used, depending on the particular embodiment. The hard mask layer may be formed by CVD, PVD, or other deposition methods.

[0114] In an embodiment, as also used throughout this specification, 193nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography, etc., are used to perform the lithography operation. Positive or negative photoresists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0115] In an embodiment, the method described herein may involve forming a contact pattern that is very well aligned with an existing gate pattern while eliminating the use of a lithography operation with an extremely tight registration budget. In one such embodiment, the method enables the use of an inherently highly selective wet etch (e.g., relative to a dry or plasma etch) to generate a contact opening. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, as used in other methods, the method enables the elimination of the need for other critical lithography operations for generating contact patterns. In an embodiment, the trench contact grid is not patterned separately, but is formed between polycrystalline (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0116] In addition, the gate stack structure can be manufactured by replacing the gate process. In such a scheme, the dummy gate material (e.g., polysilicon or silicon nitride column material) can be removed and replaced by a permanent gate electrode material. In one such embodiment, in contrast to the earlier processing, a permanent gate dielectric layer is also formed in the process. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including aqueous phosphoric acid.

[0117] In an embodiment, one or more methods described herein substantially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process to obtain a structure. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in a particular such embodiment, an anneal of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius, such as after forming the gate dielectric layer. The annealing is performed before forming the permanent contact.

[0118] In some embodiments, the arrangement of the semiconductor structure or device places the gate contact on the portion of the gate line or gate stack above the isolation region. However, such an arrangement may be regarded as an inefficient use of the layout space. In another embodiment, the semiconductor device has a contact structure that contacts the portion of the gate electrode formed above the active region. Generally, before (e.g., in addition to) forming a gate contact structure (e.g., a via) on the active portion of the gate and in the same layer as the trench contact via, one or more embodiments of the present disclosure include first using a gate alignment trench contact process. Such a process can be implemented to form a trench contact structure for semiconductor structure manufacturing (e.g., for integrated circuit manufacturing). In an embodiment, the trench contact pattern is formed to align with an existing gate pattern. In contrast, other methods typically involve additional lithography processes that closely align the photolithographic contact pattern with the existing gate pattern in combination with selective contact etching. For example, another process may include patterning the polysilicon (gate) grid using a separate patterning of contact features.

[0119] It should be appreciated that the spacing segmentation process and patterning scheme can be implemented to achieve the embodiments described herein, or the spacing segmentation process and patterning scheme can be included as part of the embodiments described herein. The spacing segmentation patterning typically refers to halving the spacing, quartering the spacing, etc. The spacing segmentation scheme can be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to lithograph unidirectional lines (e.g., strictly unidirectional or substantially unidirectional) at predefined spacings. Then the spacing segmentation process is implemented as a technique to increase line density.

[0120] In an embodiment, the term "grid structure" for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a grid structure with a close pitch. In one such embodiment, the close pitch cannot be achieved directly by the selected lithography. For example, a pattern based on the selected lithography can be formed first, but as known in the art, the pitch can be halved by patterning using a spacer mask. Further, the original pitch can be divided into four equal parts by patterning the spacer mask of the second round. Therefore, the grid-like pattern described herein may have metal lines, ILD lines, or hard mask lines spaced at substantially uniform pitches and having substantially uniform widths. For example, in some embodiments, the pitch variation will be within ten percent and the width variation will be within ten percent, and in some embodiments, the pitch variation will be within five percent and the width variation will be within five percent. The pattern can be manufactured by halving the pitch or quartering the pitch or other pitch segmentation methods. In an embodiment, the grid is not necessarily of a single pitch.

[0121] In an embodiment, the blanket film is patterned using a lithography and etching process that may involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartering. It should be understood that other pitch segmentation methods may also be implemented. In any case, in an embodiment, the grid layout may be manufactured by a selected lithography method, such as 193nm immersion lithography (193i). Pitch segmentation may be implemented to increase the density of lines in the grid layout by a factor of n. A grid layout formed using 193i lithography plus "n" times the pitch segmentation may be designated as 193i+P / n pitch segmentation. In one such embodiment, 193nm immersion scaling may be extended for many generations using cost-effective pitch segmentation.

[0122] It should also be understood that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, a dummy gate does not need to be formed before a gate contact is made on the active portion of the gate stack. The above-described gate stack may actually be a permanent gate stack when initially formed. In addition, the processes described herein may be used to manufacture one or more semiconductor devices. The semiconductor device may be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for a logic unit or memory, or a bipolar transistor. In addition, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed dual-gate device, a FIN-FET, a nanowire, or a nanobelt. One or more embodiments may be particularly useful for manufacturing semiconductor devices at a 10 nanometer (10nm) technology node or a sub-10 nanometer (10nm) technology node.

[0123] Additional operations or intermediate operations for FEOL layer or structure fabrication may include standard microelectronics manufacturing processes, such as lithography, etching, thin film deposition, planarization (e.g., chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other actions associated with microelectronic component fabrication. Furthermore, it should be understood that the process operations described for the above process flow may be practiced in an alternative order, not every operation needs to be performed, or additional process operations may be performed, or both.

[0124] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a variety of electronic devices known in the art. For example, in computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, and the like. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, and the like via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0125] Fig.13A computing device 1300 is shown according to one embodiment of the present disclosure. The computing device 1300 houses a board 1302. The board 1302 may include multiple components, including, but not limited to, a processor 1304 and at least one communication chip 1306. The processor 1304 is physically and electrically coupled to the board 1302. In some embodiments, the at least one communication chip 1306 is also physically and electrically coupled to the board 1302. In other embodiments, the communication chip 1306 is part of the processor 1304.

[0126] Depending on the application of computing device 1300, computing device 1300 may include other components that may or may not be physically and electrically coupled to board 1302. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (e.g., hard disk drive, compact disc (CD), digital versatile disc (DVD), etc.).

[0127] The communication chip 1306 can implement wireless communications for transmitting data to and from the computing device 1300. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments, they may not contain wires. The communication chip 1306 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. The computing device 1300 may include multiple communication chips 1306. For example, the first communication chip 1306 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, while the second communication chip 1306 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0128] The processor 1304 of the computing device 1300 includes an integrated circuit die packaged within the processor 1304. In some implementations of the embodiments of the present disclosure, the integrated circuit die of the processor includes one or more structures, such as integrated circuit structures constructed according to implementations of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from a register or memory or both to transform the electronic data into other electronic data that can be stored in a register or memory or both.

[0129] The communication chip 1306 also includes an integrated circuit die packaged within the communication chip 1306. According to another embodiment of the present disclosure, the integrated circuit die of the communication chip is constructed according to an embodiment of the present disclosure.

[0130] In further implementations, another component housed within computing device 1300 may contain an integrated circuit die constructed in accordance with implementations of embodiments of the present disclosure.

[0131] In various embodiments, computing device 1300 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, computing device 1300 may be any other electronic device that processes data.

[0132] Fig.14 An interposer 1400 including one or more embodiments of the present disclosure is shown. Interposer 1400 is an intermediate substrate for bridging a first substrate 1402 to a second substrate 1404. For example, first substrate 1402 may be an integrated circuit die. For example, second substrate 1404 may be a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 1400 is to extend connections to a wider pitch or to rewire connections to different connections. For example, interposer 1400 may couple an integrated circuit die to a ball grid array (BGA) 1406, which may then be coupled to second substrate 1404. In some embodiments, first substrate 1402 and second substrate 1404 are attached to opposite sides of interposer 1400. In other embodiments, first substrate 1402 and second substrate 1404 are attached to the same side of interposer 1400. And in other embodiments, three or more substrates are interconnected through interposer 1400.

[0133] The interposer 1400 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material (e.g., polyimide). In other embodiments, the interposer 1400 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0134] The interposer 1400 may include metal interconnects 1408 and vias 1410, including but not limited to through silicon vias (TSVs) 1412. The interposer 1400 may also include embedded devices 1414, including both passive devices and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1400. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used to manufacture the interposer 1400 or to manufacture components included in the interposer 1400.

[0135] Fig.15 is an isometric view of a mobile computing platform 1500 employing an integrated circuit (IC) fabricated according to one or more processes described herein or including one or more features described herein, in accordance with an embodiment of the present disclosure.

[0136] The mobile computing platform 1500 can be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, the mobile computing platform 1500 can be any of a tablet computer, a smart phone, a laptop computer, etc., and includes a display screen 1505 that is a touch screen (capacitive, inductive, resistive, etc.) in an exemplary embodiment, a chip-level (SoC) or package-level integrated system 1510, and a battery 1513. As shown in the figure, the higher the integration in the system 1510 achieved by a higher transistor packaging density, the larger the portion of the mobile computing platform 1500 that can be occupied by a battery 1513 or a non-volatile storage device (such as a solid-state drive), or the larger the transistor gate count for improving the functionality of the platform. Similarly, the greater the carrier mobility of each transistor in the system 1510, the greater the functionality. Similarly, the technology described herein can achieve improvements in performance and form factors in the mobile computing platform 1500.

[0137] The integrated system 1510 is further shown in the expanded view 1520. In an exemplary embodiment, the packaged device 1577 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or a graphics processor) manufactured according to one or more processes described herein or including one or more features described herein. The packaged device 1577 may also be coupled to the board 1560 together with one or more of its power management integrated circuit (PMIC) 1515, an RF (wireless) integrated circuit (RFIC) 1525 including a broadband RF (wireless) transmitter and / or receiver (e.g., an analog front end module including a digital baseband and further including a power amplifier on the transmit path and a low noise amplifier on the receive path), and a controller 1511. Functionally, the PMIC 1515 performs battery power regulation, DC to DC conversion, etc., and therefore has an input coupled to the battery 1513 and has an output that provides a current source to all other functional modules. As further shown, in an exemplary embodiment, RFIC 1525 has an output coupled to an antenna to provide for implementing any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth or derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G and higher. In alternative embodiments, each of these board-level modules may be integrated into a separate IC coupled to a packaging substrate of packaged device 1577, or integrated into a single IC (SoC) coupled to a packaging substrate of packaged device 1577.

[0138] In another aspect, semiconductor packages are used to protect an integrated circuit (IC) chip or die and also provide an electrical interface for the die to external circuitry. As the demand for smaller electronic devices continues to increase, semiconductor packages are designed to be even more compact and must support greater circuit densities. In addition, the demand for higher performance devices creates a need for an improved semiconductor package that can achieve a thin package profile and low overall warpage that is compatible with subsequent assembly processing.

[0139] In an embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount the die to a ceramic or organic package substrate. Specifically, a C4 solder ball connection can be implemented to provide a flip chip interconnection between a semiconductor device and a substrate. Flip chip or controlled collapse chip connection (C4) is a type of installation for semiconductor devices (e.g., integrated circuit (IC) chips, MEMS, or components) that utilize solder bumps instead of wire bonding. Solder bumps are deposited on C4 pads located on the top side of the substrate package. In order to mount the semiconductor device on the substrate, it is flipped over and placed on the mounting area with the active side facing down. Solder bumps are used to directly connect the semiconductor device to the substrate.

[0140] Fig.16 A cross-sectional view of a flip-chip mounted die is shown in accordance with an embodiment of the present disclosure.

[0141] refer to Fig.16 According to an embodiment of the present disclosure, device 1600 includes a die 1602, such as an integrated circuit (IC) manufactured according to one or more processes described herein or including one or more features described herein. Die 1602 includes metallized pads 1604 located thereon. A package substrate 1606 (e.g., a ceramic or organic substrate) includes connections 1608 located thereon. Die 1602 and package substrate 1606 are electrically connected via solder balls 1610 coupled to metallized pads 1604 and connections 1608. An underfill material 1612 surrounds solder balls 1610.

[0142] The processing performed on a flip chip can be similar to regular IC manufacturing, but with some additional operations. Near the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically consists of a variety of processes. A small dot of solder is then deposited on each metallized pad. The chip is then cut from the wafer as normal. To attach the flip chip to a circuit, the chip is turned upside down to bring the solder dots down to the connectors located on the underlying electronics or circuit board. The solder is then re-melted to create an electrical connection, typically using an ultrasonic or alternative reflow process. This also leaves a small space between the chip's circuitry and the underlying mounting. In most cases, it is then "bottom-filled" with an electrically insulating adhesive to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joints are not stressed by the differential heating of the chip and the rest of the system.

[0143] In other embodiments, newer packaging and die-to-die interconnect methods, such as through silicon vias (TSVs) and silicon interposers, are implemented in accordance with embodiments of the present disclosure to manufacture high-performance multi-chip modules (MCMs) and system-in-package (SiPs) that incorporate integrated circuits (ICs) manufactured according to one or more processes described herein or that include one or more features described herein.

[0144] Thus, embodiments of the present disclosure include integrated circuit structures having backside contact exposure uniformity and methods of fabricating integrated circuit structures having backside contact exposure uniformity.

[0145] Although specific embodiments have been described above, even if only a single embodiment is described with respect to a particular feature, these embodiments are not intended to limit the scope of the present disclosure. Unless otherwise specified, the examples of features provided in the present disclosure are intended to be illustrative rather than restrictive. The above description is intended to cover such substitutions, modifications, and equivalents that are obvious to those skilled in the art having the benefit of the present disclosure.

[0146] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, during the examination of this application (or an application claiming priority thereto), new claims may be made for any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of independent claims, and features from corresponding independent claims may be combined in any appropriate manner, not merely in the specific combinations listed in the appended claims.

[0147] The following examples relate to further embodiments. The various features of the different embodiments can be combined in different ways with some features included and other features not included to suit a variety of different applications.

[0148] Example embodiment 1: An integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is located above the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is located at one end of the plurality of horizontally stacked nanowires. A conductive source or drain contact is located vertically below and in contact with a bottom of the epitaxial source or drain structure. The conductive source or drain contact is located in a cavity in an isolation layer. The isolation layer extends laterally below the gate stack.

[0149] Example 2: The integrated circuit structure according to Example 1, wherein the cavity extends beyond the epitaxial source or drain structure in a direction parallel to the gate stack, and the cavity is confined to the epitaxial source or drain structure in a direction toward the gate stack.

[0150] Example 3: The integrated circuit structure according to Example 2, wherein the cavity extends beyond two opposite edges of the epitaxial source or drain structure in a direction parallel to the gate stack.

[0151] Example Embodiment 4: The integrated circuit structure of Example Embodiment 2, wherein the cavity extends beyond only a single edge of the epitaxial source or drain structure in a direction parallel to the gate stack.

[0152] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3 or 4, further comprising a second epitaxial source or drain structure at a second end of the plurality of horizontally stacked nanowires.

[0153] Example 6: An integrated circuit structure includes a fin. A gate stack is located on the fin. An epitaxial source or drain structure is located at an end of the fin. A conductive source or drain contact is located vertically below and in contact with a bottom of the epitaxial source or drain structure. The conductive source or drain contact is located in a cavity in an isolation layer. The isolation layer extends laterally below the gate stack.

[0154] Example 7: The integrated circuit structure of Example 6, wherein the cavity extends beyond the epitaxial source or drain structure in a direction parallel to the gate stack, and the cavity is confined to the epitaxial source or drain structure in a direction toward the gate stack.

[0155] Example 8: The integrated circuit structure of Example 7, wherein the cavity extends beyond two opposite edges of the epitaxial source or drain structure in a direction parallel to the gate stack.

[0156] Example Embodiment 9: The integrated circuit structure of Example Embodiment 7, wherein the cavity extends beyond only a single edge of the epitaxial source or drain structure in a direction parallel to the gate stack.

[0157] Example 10: The integrated circuit structure of Example 6, 7, 8 or 9, further comprising a second epitaxial source or drain structure at the second end of the fin.

[0158] Example embodiment 11: A computing device, comprising: a board and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure including a plurality of horizontally stacked nanowires or fins. A gate stack is located above the plurality of horizontally stacked nanowires or fins. An epitaxial source or drain structure is located at one end of the plurality of horizontally stacked nanowires or fins. A conductive source or drain contact is vertically located below and in contact with a bottom of the epitaxial source or drain structure. The conductive source or drain contact is located in a cavity in an isolation layer. The isolation layer extends laterally below the gate stack.

[0159] Example 12: The computing device according to Example 11, comprising a stack of nanowires.

[0160] Example embodiment 13: The computing device according to example embodiment 11 or 12, comprising a fin.

[0161] Exemplary Embodiment 14: The computing device of Exemplary Embodiment 11, 12 or 13, further comprising a memory coupled to the board.

[0162] Exemplary Embodiment 15: The computing device according to Exemplary Embodiment 11, 12, 13 or 14, further comprising: a communication chip coupled to the board.

[0163] Exemplary Embodiment 16: The computing device of Exemplary Embodiment 11, 12, 13, 14, or 15, further comprising a battery coupled to the board.

[0164] Exemplary Embodiment 17: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, or 16, further comprising a camera coupled to the board.

[0165] Exemplary Embodiment 18: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a display coupled to the board.

[0166] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0167] Exemplary Embodiment 20: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: multiple horizontally stacked nanowires; a gate stack disposed above the plurality of horizontally stacked nanowires; an epitaxial source or drain structure located at one end of the plurality of horizontally stacked nanowires; as well as A conductive source or drain contact portion, wherein the conductive source or drain contact portion is vertically located below and in contact with the bottom of the epitaxial source or drain structure, and the conductive source or drain contact portion is located in a cavity in an isolation layer, and the isolation layer extends laterally below the gate stack.

2. The integrated circuit structure according to claim 1, wherein: The cavity extends beyond the epitaxial source or drain structure in a direction parallel to the gate stack, and the cavity is confined to the epitaxial source or drain structure in a direction toward the gate stack.

3. The integrated circuit structure according to claim 2, wherein: The cavity extends beyond two opposing edges of the epitaxial source or drain structure in the direction parallel to the gate stack.

4. The integrated circuit structure according to claim 2, wherein: The cavity extends beyond only a single edge of the epitaxial source or drain structure in the direction parallel to the gate stack.

5. The integrated circuit structure of claim 1, 2, 3 or 4, further comprising: A second epitaxial source or drain structure is located at a second end of the plurality of horizontally stacked nanowires.

6. An integrated circuit structure comprising: fins; a gate stack, the gate stack being located on the fin; an epitaxial source or drain structure located at one end of the fin; and A conductive source or drain contact portion, wherein the conductive source or drain contact portion is vertically located below and in contact with the bottom of the epitaxial source or drain structure, and the conductive source or drain contact portion is located in a cavity in an isolation layer, and the isolation layer extends laterally below the gate stack.

7. The integrated circuit structure according to claim 6, wherein: The cavity extends beyond the epitaxial source or drain structure in a direction parallel to the gate stack, and the cavity is confined to the epitaxial source or drain structure in a direction toward the gate stack.

8. The integrated circuit structure according to claim 7, wherein: The cavity extends beyond two opposing edges of the epitaxial source or drain structure in the direction parallel to the gate stack.

9. The integrated circuit structure according to claim 7, wherein: The cavity extends beyond only a single edge of the epitaxial source or drain structure in the direction parallel to the gate stack.

10. The integrated circuit structure of claim 6, 7, 8 or 9, further comprising: A second epitaxial source or drain structure is located at a second end of the fin.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: multiple horizontally stacked nanowires or fins; a gate stack disposed on the plurality of horizontally stacked nanowires or the fins; an epitaxial source or drain structure located at one end of the plurality of horizontally stacked nanowires or the fin; and A conductive source or drain contact portion, wherein the conductive source or drain contact portion is vertically located below and in contact with the bottom of the epitaxial source or drain structure, and the conductive source or drain contact portion is located in a cavity in an isolation layer, and the isolation layer extends laterally below the gate stack.

12. The computing device of claim 11, comprising the plurality of horizontally stacked nanowires.

13. The computing device of claim 11 or 12, comprising the fin.

14. The computing device according to claim 11 or 12, further comprising: A memory is coupled to the board.

15. The computing device according to claim 11 or 12, further comprising: A communication chip is coupled to the board.

16. The computing device according to claim 11 or 12, further comprising: A battery coupled to the board.

17. The computing device according to claim 11 or 12, further comprising: A camera is coupled to the board.

18. The computing device according to claim 11 or 12, further comprising: A display is coupled to the panel.

19. The computing device according to claim 11 or 12, wherein: The component is a packaged integrated circuit die.

20. The computing device according to claim 11 or 12, wherein: The component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

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