Semiconductor structure

Abstract

A semiconductor structure includes a first circuit region having first fin active regions extending longitudinally in a first direction, each first fin active region including a first channel region; a second circuit region having second fin active regions extending longitudinally in the first direction, each of the second fin active regions including a second channel region; a gate connector region between the first circuit region and the second circuit region and separating the first circuit region from the second circuit region, the gate connector region having a filter fin extending longitudinally in the first direction; and a gate structure extending in a second direction across the first circuit region, the gate connector region, and the second circuit region over the first and second channel regions and the filter fin. A portion of the gate structure in the gate connector region has a greater electrical resistivity than portions of the gate structure in the first and second circuit regions.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures. Background Art

[0002] The electronics industry continues to experience a growing demand for smaller, faster electronic devices that are able to simultaneously support more and more complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance, and low-power ICs. To date, these goals have been achieved in large part by reducing IC size (e.g., minimum IC component size), thereby increasing production efficiency and reducing associated costs. However, this scaling down has also increased the complexity of the IC manufacturing process. Therefore, achieving continued advancements in IC devices and their performance requires similar advancements in IC manufacturing processes and technologies.

[0003] As the technology node becomes smaller, the signal coupling between adjacent transistors becomes more obvious. Therefore, the dummy region between adjacent transistors should have enough spacing for proper isolation. In the dummy region, there are no active devices. However, the common gate structure can still span the dummy region and extend to connect and land on multiple channel regions spanning multiple transistor devices. Therefore, the dummy region can also be referred to as a gate connector area or a gate connector area. In this way, the gate input signal to a transistor device can also be coupled to the adjacent transistor device or even coupled to the gate of other transistor devices outside the adjacent transistor device. In some applications, these gate input signals may have signal components or losses that are not suitable for transmission to adjacent transistor devices or other transistor devices sharing the same gate structure. In other words, these gate input signals may need to be adjusted and filtered to improve performance.

[0004] Thus, while existing structures for dummy regions between adjacent transistors are generally adequate for their intended purposes, they are not completely satisfactory in every respect. Summary of the invention

[0005] According to one aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a first circuit region, having a first fin active region extending longitudinally in a first direction above a substrate, each first fin active region including a first channel region between first source / drain components; a second circuit region, having a second fin active region extending longitudinally in the first direction above the substrate, each second fin active region including a second channel region between second source / drain components; a gate connector region, located between the first circuit region and the second circuit region and separating the first circuit region and the second circuit region, the gate connector region having a filter fin extending longitudinally in the first direction above the substrate; and a gate structure, extending across the first circuit region, the gate connector region and the second circuit region in a second direction perpendicular to the first direction, the gate structure being arranged above the first channel region and the second channel region and above the filter fin, wherein the gate structure includes a gate dielectric located above the top surface and side surfaces of the first fin active region, the second fin active region and the filter fin, wherein a portion of the gate structure in the gate connector region has a greater resistivity than a portion of the gate structure in the first circuit region and the second circuit region.

[0006] According to another aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a transistor region having a fin active region extending longitudinally along a first direction on a substrate, each fin active region including a channel region between source / drain components; a filter region adjacent to the transistor region along a second direction perpendicular to the first direction, the filter region having filter fins extending longitudinally along the first direction on the substrate; and a gate structure having a gate dielectric and a gate fill metal above the gate dielectric, the gate structure extending across the transistor region and the filter region along the second direction, and the gate structure being arranged directly above the channel region of the fin active region and directly above the filter fin, wherein the source / drain components of the fin active region include epitaxial components, and the filter fin has no epitaxial components.

[0007] According to another aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a transistor region having a fin active region extending longitudinally along a first direction on a substrate, each fin active region comprising a channel region between source / drain components; a filter region adjacent to the transistor region along a second direction perpendicular to the first direction, the filter region having a filter fin extending longitudinally along the first direction above the substrate; a first gate structure having a first gate dielectric and a first gate electrode above the first gate dielectric, the first gate structure extending across the transistor region and the filter region along the second direction, and the first gate structure being disposed above a first group of channel regions and the filter fins; a second gate structure having a second gate dielectric and a second gate electrode above the second gate dielectric, the second gate structure extending across the transistor region and the filter region along the second direction, and the second gate structure being disposed above a second group of channel regions and the filter fins; and an interlayer dielectric (ILD) layer having a first dielectric portion surrounding the source / drain components, a second dielectric portion surrounding the filter fins, and the second dielectric portion having a dielectric constant greater than that of the first dielectric portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of the present invention and, therefore, should not be considered limiting of the scope, as the present invention may be equally well applied to other embodiments. In addition, the drawings may implicitly describe features that are not explicitly described in the detailed description.

[0009] Figure 1 A semiconductor structure illustrated by a circuit diagram showing gate signals according to an embodiment of the present disclosure is shown.

[0010] Figure 2 A gate signal passing through a low pass filter according to an embodiment of the present disclosure is shown.

[0011] Figure 3A-3B A semiconductor structure with a filter fin according to an embodiment of the present disclosure is shown.

[0012] Figure 4A-4B A semiconductor structure having a filter fin according to another embodiment of the present disclosure is shown.

[0013] Figure 4C A graph showing capacitance-voltage (CV) characteristics of a MOSFET device according to an embodiment of the present disclosure is shown.

[0014] Figure 5A-Figure 5BA semiconductor structure having a filter fin according to another embodiment of the present disclosure is shown.

[0015] Figure 6A-6B A semiconductor structure having a filter fin according to another embodiment of the present disclosure is shown.

[0016] Figure 7A-7D A semiconductor structure having a filter fin according to another embodiment of the present disclosure is shown.

[0017] Figure 8A-8D A semiconductor structure having a filter fin according to another embodiment of the present disclosure is shown.

[0018] Figure 9A-9B and Figure 10A-10C A semiconductor structure having a filter fin according to another embodiment of the present disclosure is shown.

[0019] Figures 11A-11D A semiconductor structure having a filter fin according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0022] In addition, when a number or a range of numbers is described with "about", "approximately", "substantially", etc., the term is intended to cover numbers within a reasonable range, taking into account the variations inherent in the manufacturing process understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with the numbers, the number or range of numbers covers a reasonable range (including the described numbers), such as within + / -10% of the described numbers. For example, a material layer with a thickness of "about 5nm" may include a size range of 4.5nm to 5.5nm, where the manufacturing tolerance associated with the deposited material layer is + / -10% known to those of ordinary skill in the art. When comparing the size or size of one component to another, the phrases "substantially the same", "substantially the same", "similar in size", etc. can be understood as features compared within a range of + / -10%. In addition, the dimensions of different components disclosed may implicitly disclose the size ratios between different components. Further, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0023] The present disclosure relates to a semiconductor structure with a filter fin for gate signal filtering. Specifically, the filter fin is incorporated in a dummy region between transistor regions. The dummy region does not have an active transistor device, while the transistor region has an active transistor device. The dummy region may be referred to as a gate connector region because the gate structure spans the gate connector region to land on the transistor device in the adjacent transistor region. However, since the dummy region in the present embodiment includes a filter fin for performing signal filtering, the dummy region is referred to as a filter circuit region herein. The present disclosure describes that an input gate signal in a transistor region is filtered by a structural configuration in a filter circuit region so that only low-frequency signals pass through to adjacent transistor regions, but high-frequency signals and losses are absorbed by the filter fin in the filter circuit region. And routed toward the substrate. The filter fin is configured to cause changes in the resistance and capacitance of the gate structure, which produces path resistance and parasitic capacitance to form a low-pass filter. Other ways of affecting the low-pass filter may include changing the size and material of the metal gate, the filter fin, or both in the filter circuit region. Additionally or alternatively, adding a top dielectric on the filter fins, metal gates, and / or adding metal contacts on the filter fins or metal gates may provide additional signal paths for signal filtering.

[0024] Figure 1A semiconductor structure 100 is shown, which is exemplified as a circuit diagram showing an input gate signal 500. The semiconductor structure 100 includes a filter circuit region 300 (also referred to as a dummy region or gate connector region) sandwiched between transistor circuit regions 200 along the y direction (i.e., the length direction of the metal gate structure). In the present embodiment, the transistor circuit region 200 includes active transistor devices, and the gate connector region 300 does not have active transistor devices. The structural details of the semiconductor structure 100 in the transistor circuit region 200 and the gate connector region 300 will be explained in the following figures.

[0025] like Figure 1 As shown, the filter circuit area 300 is used as a filter circuit that provides different signal paths. In one embodiment, the input gate signal 500 (e.g., the input gate voltage) is applied to the gate structure in the rightmost transistor circuit area 200. As shown in path 1, the input gate signal 500 can pass through the filter circuit area 300 through a series resistor to reach the leftmost transistor circuit area 200. As shown in path 2, the input gate signal 500 can be redirected to the ground through a parallel capacitor. Specifically, when the input gate signal 500 is a low-frequency signal, the input gate signal 500 will pass through path 1 because the parallel capacitor in path 2 acts as an open circuit in the low-frequency mode. And when the input gate signal 500 is a high-frequency signal, the input gate signal 500 will pass through path 2 because the parallel capacitor in path 2 acts as a short circuit to the ground in the high-frequency mode. This is because the current flows through the path with lower impedance. Therefore, low-frequency signals tend to pass through resistors instead of capacitors, while high-frequency signals tend to pass through capacitors instead of resistors. In other words, the filter circuit acts as a low-pass filter, filtering out high-frequency signals and allowing low-frequency signals to pass. In this way, only low-frequency gate signals will bias the gate structure in the leftmost transistor circuit area 200 , while high-frequency signals are filtered out in the filter circuit area 300 .

[0026] Figure 2 Added Figure 1 , and shows the input gate signal 500 through the low pass filter, such as the above Figure 1 As shown, the input gate signal 500 may include a high frequency component and a low frequency component. The high frequency component may include spikes and signal noise that are filtered out in the low pass filter. And the low frequency component passes through the low pass filter to power the gate in the adjacent transistor circuit area 200. In this way, the input gate signal 500 is conditioned and filtered to improve performance.

[0027] Figure 3A 3 shows a top view of a semiconductor structure 100 having a filter fin 304 according to an embodiment of the present disclosure. As shown, Figure 3AThe filter circuit area 300 between adjacent transistor circuit areas 200 is shown, which corresponds in structure to the filter circuit area 300 of FIG. Figure 1 The transistor circuit area 200 and the filter circuit area 300 are described. Each transistor circuit area 200 includes a substrate (eg, Figure 3B The substrate 102 may be a silicon (Si) substrate, or a substrate having other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The one or more fin active regions 204 may include Si, Ge, SiGe, SiC, gallium arsenide (GaAs), gallium nitride (GaN), carbon (C), indium (In), or a combination thereof. For simplicity, Figure 3A Only one fin active area 204 in each transistor circuit region 200 is shown. Figure 3B As shown, one fin active region 204 may represent more than one fin active region 204, for example, four fin active regions 204. Each fin active region 204 extends longitudinally in the x-direction and may be separated from each other by an isolation structure (e.g., Figure 3B Each fin active region 204 may include a source / drain feature 204b (see, for example, Figure 7C ) between the channel regions 204a (see, for example Figure 3B ). The source / drain feature 204b is disposed in a source / drain region adjacent to the channel region 204a, and the source / drain region may be referred to individually or collectively as a source or a drain, depending on the context. The channel region 204a is defined by a portion of the fin active region 204 directly below the gate structure 108, and the source / drain feature 204b is defined by a portion of the fin active region 204 adjacent to the channel region 204a. A source / drain contact 206 is disposed above the source / drain feature 204b. And a source / drain via 210 is disposed above the source / drain contact 206. The source / drain contact 206 and the source / drain via 210 are conductive features that electrically connect the source / source feature 204b to a higher level metal interconnect.

[0028] Still reference Figure 3A , the filter circuit area 300 includes one or more filter fins 304 protruding from the substrate 102. The filter circuit area 300 is also referred to as a dummy area 300 or a gate connector area 300. The filter fins 304 extend longitudinally in the x-direction and may be separated from each other by isolation structures 101. The filter fins 304 may include similar materials as the fin active area 204. Note that the filter fins 304 do not have a particular channel region or source / drain features because they do not form a transistor device. Instead, they act as filter devices to condition the input gate signal.

[0029] Still reference Figure 3A , the gate structure 108 is disposed above and across the adjacent transistor circuit regions 200 and the filter circuit region 300 therebetween. Specifically, the gate structure 108 extends longitudinally in the y direction, is located directly above the channel region 204a of the fin active region 204 and directly above a portion of the filter fin 304. Each gate structure 108 includes a transistor gate portion 208 in the transistor circuit region 200 and a filter gate portion 308 in the filter circuit region 300. Figure 3B As shown, the resistivity of the transistor gate portion 208 and the filter gate portion 308 is different due to various factors. Each gate structure includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The segment of the gate electrode in the filter gate portion 308 is different in composition from the segment of the gate electrode in the transistor gate portion 208. Specifically, the segment of the gate electrode in the filter gate portion 308 has a greater resistivity than the segment of the gate electrode in the transistor gate portion 208. The gate contact 212 is disposed above the transistor gate portion 208 of the gate structure 108. And the gate through hole 214 is disposed above the gate contact 212. The gate through hole 214 is electrically connected to the gate supply voltage Vg that provides the input gate voltage signal.

[0030] Figure 3B Shows Figure 3A A cross-sectional view of the semiconductor structure 100 taken along line BB' in FIG. 1 . In the cross-sectional view, a portion of the gate structure 108 is shown as spanning four filter fins 304 and four fin active areas 204 (or specifically, four channel areas 204a). In one embodiment, the filter fins 304 and the fin active areas 204 have the same or similar fin widths along the y-direction. The filter fins 304 and the fin active areas 204 are separated from each other by an isolation structure 101. The isolation structure 101 provides isolation between adjacent fin structures and may be a shallow trench isolation (STI) layer. The isolation structure 101 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In the present embodiment, the isolation structure 101 is disposed above the semiconductor substrate 102, and each filter fin 304 and fin active area 204 protrudes from the substrate 102 above the isolation structure 101. As Figure 3BAs shown, each of the gate structures 108 includes a gate dielectric 109 that is conformally disposed above the channel region 204a and above the filter fin 304. The gate dielectric 109 may include a high-k dielectric material, such as a material having a dielectric constant greater than that of silicon oxide (k≈3.9). The high-k dielectric material may include a metal oxide, such as hafnium oxide, zirconium oxide, aluminum oxide, or a combination thereof. In some embodiments, the high-k dielectric material includes oxygen and La, Ze, Zn, Y, Ba, N, or a combination thereof. Each of the gate structures 108 also includes a gate electrode above the gate dielectric 109. For simplicity, the transistor gate portion 208 and the filter gate portion 308 may be referred to as the gate electrodes of the respective gate portions. In the present embodiment, the filter gate portion 308 exhibits a higher resistivity than the transistor gate portion 208. This is to provide the necessary resistance and capacitance for filtering high-frequency signals in the filter circuit area 300.

[0031] Still reference Figure 3B , the higher resistivity in the filter gate portion 308 can be achieved in a variety of ways. In one embodiment, the higher resistivity is achieved by packing the filter fins 304 more densely in the filter circuit area. By packing the filter fins 304 more closely to each other, the gate electrodes on the filter fins result in a higher resistivity due to surface contact and filling effects. To achieve this, in one embodiment, the spacing s2 between the filter fins 304 is less than the spacing s1 between the fin active areas 204. This can be achieved by packing more filter fins 304 in the filter circuit area 300 (e.g., 2 fin active areas 204 in each transistor circuit area 200 and 4 or more filter fins 304 in the filter circuit area 300) compared to the fin active areas 204 in the transistor circuit area 200. In one embodiment, the spacing s2 ranges from about 20nm to about 22nm. Due to the design flexibility in the filter circuit area 300, it is possible to modify the spacing s2, while the spacing parameters in the transistor circuit area 200 are usually fixed. In another embodiment, the spacings s1 and s2 are the same, and a higher resistivity is achieved in the filter gate portion 308 by changing the work function or gate electrode material. For example, the filter gate portion 308 comprises a higher resistive metal material than the resistance of the transistor gate portion 208. In one embodiment, the transistor gate portion 208 comprises Ag, Au, Al, Rh, W, Mo, Zn, Co, Ru, Nb, or a combination thereof, and the filter gate portion 308 comprises Ti, TiN, brass, phosphor bronze, cast steel, a metal compound, or a combination thereof. In further embodiments, a higher resistivity may be achieved by a combination of the embodiments described herein.

[0032] Still reference Figure 3B, a gate voltage Vg (eg, input gate signal 500) is applied to transistor gate portion 208 (eg, via Figure 3A For simplicity, Figure 3B The gate contact 212 and the gate via 214 are not shown in the figure. The gate voltage Vg may include signals having both high frequencies and low frequencies. When the signal passes from the transistor gate portion 208 through the filter gate portion 308, high frequency signals such as high frequency noise bypass the gate structure and are absorbed into the filter fin 304 and toward the substrate 102 through capacitive coupling. In one embodiment, the substrate 102 is connected to ground. At the same time, the low frequency signal reaches the adjacent transistor circuit region 200 through the gate electrode of the filter gate portion 308. As shown, the filter fin 304 and the filter gate portion 308 form a Figure 1-Figure 2 The low-pass circuit described. Specifically, the filter gate portion 308 separated from the filter fin 304 by the gate dielectric 109 forms a parallel capacitor shorted to ground for high frequencies (e.g., path 2). And the filter gate portion 308 with higher resistance metal forms a series resistance path for low frequencies (e.g., path 1). The low frequency gate signal then powers the gate of the adjacent transistor device.

[0033] Figure 4A-4B A semiconductor structure 100 having a filter fin 304 is shown according to another embodiment of the present disclosure. Figure 4A-4B and Figure 3A-3B Similar, for the sake of brevity will not be repeated. In order to facilitate high-frequency filtering of high capacitance, Figure 4A-4B An inversion doping scheme is shown to ensure that during operation, high capacitance exists in the filter circuit area 300 and low capacitance exists in the transistor circuit area 200. The inversion doping scheme includes generating a doping profile in which the filter fin 304 is doped with an opposite type of dopant as the channel region 204a of the fin active area 204. For example, in the embodiment shown, the transistor circuit area 200 has a p-type well (or p-type substrate region) for the channel region 204a to form an n-type transistor device. In this way, the filter circuit area 300 is doped with an n-type dopant to achieve inversion doping. In this way, during operation, the fin active area 204 and the filter fin 304 are in different operating modes (inversion versus accumulation).

[0034] To illustrate the mechanism of inversion doping, Figure 4CA capacitance-voltage (CV) characteristic graph of a MOSFET device is shown. During operation (when the gate is turned on), the transistor device is typically operated in an inversion mode. In the inversion mode, high frequencies result in lower capacitance, which is desirable for transistor devices in the transistor circuit region 200 since these regions should not have extraneous parasitic capacitances. However, it is desirable to have higher capacitance in the filter circuit region 300 to achieve a low pass filter effect. If the filter fins 304 are doped with the same type of dopant as in the transistor circuit region 200, the filter fins will operate in the inversion mode as in the channel region 204a, where the capacitance is reduced at high frequencies. If this is the case, the effect of the low pass filter is reduced. By doping the filter fins 304 with the opposite type of dopant, a high capacitance is maintained since the filter fins are in accumulation mode when the transistor device is in inversion mode. As Figure 4C As shown, in accumulation mode, the capacitance remains high regardless of the frequency.

[0035] Reference now Figure 4B , when the gate signal propagates during operation, the p-type doped transistor circuit area 200 operates in an inversion mode and the n-type doped filter circuit area 300 operates in an accumulation mode. In this way, high capacitance is maintained when high frequencies are filtered through the filter fin 304 and low frequencies are passed to the adjacent transistor circuit area 200. N-type dopants may include carbon, phosphorus, arsenic, other N-type dopants, or a combination thereof. P-type dopants may include boron, other P-type dopants, or a combination thereof. It should be noted that for each fin active area 204, the channel region 204a and the source / drain component 204b are oppositely doped. Therefore, in some embodiments, the filter fin 304 is doped with the same type of dopant as the dopant of the source / drain component 204b. In one embodiment, the channel region 204a is doped with boron, the source / drain component 204b is doped with arsenic or phosphorus, and the filter fin 304 is doped with arsenic or phosphorus. Figure 4A-4B It is shown that the transistor circuit area 200 is p-type doped and the filter circuit area is n-type doped. In other embodiments, the transistor circuit area 200 is n-type doped and the filter circuit area is p-type doped.

[0036] Figure 5A-Figure 5B A semiconductor structure 100 having a filter fin 304 is shown according to another embodiment of the present disclosure. Figure 5A-Figure 5B and Figure 3A-3B Similar, for the sake of brevity will not be repeated. Figure 5A-Figure 5B In the embodiment of FIG. 3 , the filter fin 304 is formed wider than the channel region 204 a of the fin active region 204 . Figure 5B, the filter fin 304 has a width w2 along the y direction, the channel region 204a of the fin active region 204 has a width w1 along the y direction, and the width w2 is greater than the width w1. In one embodiment, the ratio of w2 to w1 is about 1 to 3. The wider filter fin 304 results in a larger interface with the gate dielectric 109, thereby providing a larger capacitance for improved gate signal filtering. In other aspects, with respect to the spacing between the fin and gate metal materials in the transistor circuit area 200 and the filter circuit area 300, Figure 5B Possibly Figure 3B similar. Figure 5B Further shown is a gate contact 212 disposed directly above the transistor gate portion 208 of the gate structure 108. The gate contact 212 is electrically connected to a gate supply voltage Vg (e.g., through a gate via 214) that provides an input gate voltage signal. The gate contact 212 is embedded in an interlayer dielectric (ILD) layer 315 disposed above the gate structure 108. The ILD layer 315 may include a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from tetraethoxysilane (TEOS), phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), a low-k dielectric material, other suitable dielectric materials, or combinations thereof.

[0037] Figure 6A-6B A semiconductor structure 100 having a filter fin 304 is shown according to another embodiment of the present disclosure. Figure 6A-6B and Figure 3A-3B Similar, for the sake of brevity will not be repeated. Figure 6A-6B In the embodiment of FIG. 1 , the filter fin 304 is formed to have a greater effective height than the fin active area 204. The effective height is defined as the height protruding above the top surface of the isolation structure 101. Figure 5B, the filter fin 304 has an effective height h2 along the z direction, and the channel region 204a of the fin active region 204 has an effective height h1 along the z direction, and the effective height h2 is greater than the effective height h1. The larger effective height h2 results in a larger interface between the filter fin 304 and the gate dielectric 109, thereby providing a larger capacitance for improved gate signal filtering. Note that although the effective height h2 is greater than the effective height h1, the top surface of the filter fin 304 is substantially coplanar with the top surface of the channel region 204a. That is, the filter fin 304 and the fin active region 204 protrude above the substrate 102 at approximately the same height. The effective heights are different due to the height difference of the isolation structure 101 in the transistor circuit area 200 relative to the isolation structure in the filter circuit area 300. As shown, the portion of the isolation structure 101 in the filter circuit area 300 and surrounding the filter fin 304 is formed shallower in the z direction than the portion of the isolation structure in the transistor circuit area 200. In other words, the top surface of the isolation structure 101 in the transistor circuit region 200 is above the top surface of the isolation structure 101 in the filter circuit region 300 . Figure 6B Further shown is a gate contact 212 disposed directly above the transistor gate portion 208 of the gate structure 108. The gate contact 212 is electrically connected to a gate supply voltage Vg (e.g., through a gate via 214) that provides an input gate voltage signal. The gate contact 212 is embedded in an interlayer dielectric (ILD) layer 315 disposed above the gate structure 108. The ILD layer 315 may include a dielectric material including, for example, silicon oxide, fused silicon dioxide, an oxide formed from tetraethoxysilane (TEOS), phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), a low-k dielectric material, other suitable dielectric materials, or combinations thereof.

[0038] Figure 7A-7D A semiconductor structure 100 having a filter fin 304 is shown according to another embodiment of the present disclosure. Figure 7A-7B and Figure 6A-6B Similar, for the sake of brevity will not be repeated. Figure 7A-7B In the embodiment of the present invention, the additional work function metal layers 207 and 307 can be used as part of the gate structure 108. Figure 7B, the work function metal layer 207 is disposed between the gate dielectric 109 and the transistor gate portion 208, and the work function metal layer 307 is disposed between the gate dielectric 109 and the filter gate portion 308. The additional work function metal layers 207 and 307 provide additional tuning of the gate voltage as needed. The work function metal layers 207 and 307 include a conductive layer of a metal or metal alloy having an appropriate work function, so that the device performance of the corresponding transistor device (e.g., nFET or pFET) is enhanced. The work function metal layers 207 and 307 may include a metal selected from, but not limited to, titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), tungsten aluminide (WAl), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), aluminum (Al), or a combination thereof; and may be deposited by CVD, PVD, and / or other suitable processes. The composition of the work function metal layer 307 for pFET and nFET may be different. In one embodiment, the work function metal layers 207 and 307 include different metal materials. In one embodiment, the work function metal layer 307 includes a higher resistive metal material than the work function metal layer 207. In further embodiments, higher resistivity may be achieved through a combination of embodiments described herein.

[0039] Figure 7C The line CC' taken along the y direction is shown. Fig. 7ACross-sectional view. Line CC' crosses one or more source / drain components 204b and one or more filter fins 304 of the fin active area 204. The source / drain component 204b includes an epitaxial component, while the filter fin 304 does not have an epitaxial component. The epitaxial component may be formed to have an extended profile to form a diamond on top of the source / drain component 204b. In some embodiments, the epitaxial components merge between adjacent fin active regions 204 along the y-direction. The epitaxial components may be doped with n-type dopants and / or p-type dopants. In some embodiments, for n-type transistors, the epitaxial component includes silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., to form a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a Si:C:P epitaxial drain / source component). In some embodiments, for p-type transistors, the epitaxial component includes silicon germanium or germanium and may be doped with boron, other p-type dopants, or a combination thereof (e.g., to form Si:Ge:B epitaxial source / drain components). As shown, the filter fin 304 in the filter circuit area 300 has no epitaxial component and is sandwiched between the source / drain components 204b in the different transistor circuit areas 200. The etch stop layer 211 may be conformally deposited on the sidewalls and top surfaces of the source / drain component 204b and the filter fin 304. In one embodiment, the etch stop layer 211 includes silicon nitride, silicon oxynitride, or silicon carbonitride. An interlayer dielectric (ILD) layer 215, which may include an etch stop layer 211, is disposed above and around the source / drain component 204b and the filter fin 304. The ILD layer 215 may include a material similar to the ILD layer 315 previously described. An etch stop layer 311 having a similar material as etch stop layer 211 is disposed over ILD layer 215, and ILD layer 315 is disposed over etch stop layer 315. In one embodiment, ILD layers 215 and 315 include a different dielectric material than etch stop layers 211 and 311.

[0040] Fig.7D The image taken along the line D-D' in the x direction is shown. Fig. 7A. Line D-D' is along the filter fin 304 and across multiple gate structures 108 (specifically, filter gate portions 308 of the gate structures 108). As shown, for each gate structure 108, a gate dielectric 109 is disposed above the filter fin 304, a work function metal layer 307 is disposed above the gate dielectric 109, and a filter gate portion 308 is disposed above the work function metal layer 307. Each gate structure 108 is separated from each other in the x-direction by an etch stop layer 211 and an ILD layer 215. As shown, the top surfaces of the ILD layer 215 and the gate structure 108 are substantially coplanar. The etch stop layer 311 is disposed above the gate structure 108 and the ILD layer 215. The ILD layer 315 is disposed above the etch stop layer 311.

[0041] Figure 8A-8D A semiconductor structure 100 with a filter fin 304 is shown according to another embodiment of the present disclosure. For the sake of brevity, similar features described in the previous embodiments are not repeated here. In the previous embodiments, gate signal filtering is through the filter fin 304 and vertically downward to the substrate 102, and then the substrate 102 is grounded. Here, in combination with the filter fin 304, gate signal filtering can also be achieved across adjacent filter gate portions 308 in the lateral direction (i.e., the x-direction). Adjacent filter gate portions 308 are portions of adjacent gate structures 108, and adjacent gate structures 108 can extend longitudinally on different channel regions 204a of different portions of the fin active area 204. In an embodiment, a capacitive filter is formed between two adjacent filter gate portions 308 and the high-k dielectric layer (e.g., high-k ILD layer 215a) therebetween. As described with respect to Fig.7DAs described, the dielectric layer between the filter gate portions 308 can be an ILD layer 215. To promote high capacitance, a portion of the ILD layer 215 surrounding and between two adjacent filter gate portions 308 is replaced with a high-k ILD layer 215a. The high-k ILD layer 215a has a higher dielectric constant than the dielectric constant of the ILD layer 215. The high-k ILD layer 215a can include a metal oxide, such as hafnium oxide, zirconium oxide, aluminum oxide, or a combination thereof. In some embodiments, the high-k dielectric material includes oxygen and La, Ze, Zn, Y, Ba, N, or a combination thereof. To further promote high capacitance, two adjacent filter gate portions 308 are widened in the x-direction so that the adjacent filter gate portions 308 are closer to each other. As shown, the lateral spacing between adjacent filter gate portions 308 in the x-direction is less than the lateral spacing between adjacent transistor gate portions 208. In one embodiment, the width of the widened filter gate portion 308 is greater than 1.1 times the width of the transistor gate portion 208. It should be noted that in order to allow for gate signal filtering in the lateral direction from gate to gate, one of the gate structures 108 is provided with an input gate voltage Vg, while the other gate structure 108 is grounded. For example, as shown, a first gate contact 212 is disposed over a transistor gate portion 208 of a first gate structure 108. And a first gate via 214 is disposed over the first gate contact 212. The first gate via 214 is electrically connected to a gate supply voltage Vg that provides an input gate voltage signal. A second gate contact 212 is disposed over a transistor gate portion 208 of a second adjacent gate structure 108. And a second gate via 214 is disposed over the second gate contact 212. The second gate via 214 is electrically connected to ground. In one embodiment, there is a cut metal gate feature (not shown) that separates portions of a gate structure 108 (e.g., the left gate structure 108 shown as grounded) from other portions of the gate structure 108. These other portions of the gate structure 108 are not grounded and remain available for transistor operation.

[0042] Figure 8B The mechanism of high frequency gate signal filtering in the horizontal direction is shown. Figure 8BTwo adjacent filter gate portions 308 of two adjacent gate structures 108 are shown. The two adjacent filter gate portions 308 are labeled as a first filter gate portion 308a and a second filter gate portion 308b. An input gate signal having a high frequency and a low frequency is provided to the first filter gate portion 308a via an input gate voltage Vg. As the gate signal propagates in the y direction, high frequency signals such as high frequency losses propagate horizontally in the x direction into the second filter gate portion 308b due to the above-mentioned capacitive filter. These high frequency signals are then grounded via a ground connection routed to the second filter gate portion 308b. At the same time, the low frequency signals pass through and continue to propagate in the y direction. In addition to the high frequency filtering (such as from the gate structure 108 to the filter fin 304 to ground) Figure 3B In addition to Figure 8B It is also shown that high frequency filtering from the first gate structure 108 to the second gate structure 108 is also possible.

[0043] Figure 8C The line CC' taken along the y direction is shown. Fig. 8A The line CC' crosses one or more source / drain features 204b of the fin active area 204 and one or more filter fins 304. It should be noted that the line CC' also cuts along the filter gate portion 308 because the filter gate portion 308 is widened in this embodiment. Figure 8C and Figure 7C Similarly, similar features are not described again for the sake of brevity. The difference here is that the filter gate portion 308 of the gate structure 108 is disposed above the filter fin 304. As shown, the gate dielectric 109 surrounds the filter fin 304, the work function metal layer 307 is disposed above the gate dielectric 109, and the filter gate portion 308 is disposed above the work function metal layer 307. Here, the filter fin 304 and the filter gate portion 308 are both sandwiched between the source / drain components 204b of different transistor circuit areas 200. In addition, the filter gate portion 308 is embedded in the ILD layer 215 and has a top surface that is coplanar with the top surface of the ILD layer. The etch stop layer 311 is disposed above the top surface of the ILD layer 215 and the filter gate portion 308. It should be noted that in the illustrated embodiment, the sidewalls of the gate dielectric 109 can interface with the sidewalls of the etch stop layer 211.

[0044] Fig.8D The image taken along the line D-D' in the y direction is shown. Fig. 8A Line DD′ crosses one or more source / drain features 204b of the fin active area 204 and one or more filter fins 304. It should be noted that line DD′ also passes through the high-kILD layer 215a and the source / drain contacts 206 and the source / drain vias 210. Fig.8D Shows the Figure 8C Similar features are shown in FIG. 2 , as the cross-section cut also traverses the source / drain features 204 b and the filter fins 304 . However, the cross section shows a high-k ILD layer 215 a disposed above the filter fins 304 , which acts as a dielectric layer for the capacitive filter described above. The high-k ILD layer 215 a is embedded and surrounded by an ILD layer 215 that includes a dielectric having a lower dielectric constant than the high-k ILD layer 215 a. Also in this cross section, the high-k ILD layer 215 a is embedded and surrounded by an ILD layer 215 that includes a dielectric having a lower dielectric constant than the high-k ILD layer 215 a. Fig.8D , the source / drain contact 206 is disposed over the source / drain feature 204 b, and the source / source via 210 is disposed over the source region / drain contact 206. An etch stop layer 411 is disposed over the source / drain contact 206 and over the ILD layer 315, and the ILD layer 415 is disposed over the etch stop layer 411. The etch stop layer 411 may include a material similar to the etch stop layers 211 and 311, and the ILD layer 415 may include a material similar to the ILD layers 215 and 315. In one embodiment, the ILD layers 215, 315, and 415 include a dielectric material different from the etch stop layers 211, 311, and 411. The source / drain contact 206 penetrates the ILD layer 315 and the etch stop layer 311 to land on the source / drain feature 204 b. The source / drain vias 210 penetrate the ILD layer 415 and the etch stop layer 411 to land on the source / drain contacts 206 .

[0045] Figure 9A-9B and Figure 10A-10C A semiconductor structure 100 with a filter fin 304 is shown according to another embodiment of the present disclosure. For the sake of brevity, similar features described in previous embodiments are not repeated here. In previous embodiments, high-frequency gate signals can be filtered downward into the substrate 102 through the filter fin 304 and / or filtered laterally from one gate structure 108 to another adjacent gate structure 108. Here, another way to achieve gate signal filtering is in an upward direction (i.e., the positive z-direction) toward a metal component 213 that is wired to ground. For example, as shown, a gate via 214 connected to a ground node is disposed above the metal component 213. In this embodiment, a capacitive filter is formed by a high-k dielectric layer 317 between the filter gate portion 308 of the gate structure 108 and the metal component 213. Note that, Fig. 9A Also shown is a high-k ILD layer 215a surrounding two adjacent filter gate portions 308, although in some embodiments the high-k ILD layer 215a is omitted.

[0046] Fig. 9B Shows Fig. 9AA cross-sectional view taken along line BB′ in the y-direction. Line BB′ passes through one or more fin active regions 204 and one or more filter fins 304 along the gate structure 108 . Fig. 9B With the above Figure 3B-Figure 7B Similarly, similar features are not described again for the sake of brevity. As shown, the gate structure 108 includes a gate dielectric 109 conformally deposited over the channel region 204a of the fin active region 204, a work function metal layer 207 over the gate dielectric 109 in the transistor circuit region 200, a work function metal layer 307 over the gate dielectric 109 in the filter circuit region 300, a gate of the transistor gate portion 208 over the work function metal layer 207, and a gate of the filter gate portion 308 over the work function metal layer 307. In addition, a high-k dielectric layer 317 is disposed over and lands on the filter gate portion 308, and a metal component 213 is disposed over and lands on the high-k dielectric layer 317. The high-k dielectric layer 317 isolates the filter gate portion 308 from the metal component 213. The high-k dielectric layer 317 may include a material similar to the gate dielectric 109 and / or the high-k ILD layer 215a. The high-k dielectric layer 317 may be laterally surrounded by the transistor gate portion 208, and the top surfaces of the high-k dielectric layer 317 and the transistor gate portion 208 may be substantially coplanar. In one embodiment, the high-k dielectric layer 317 has a thickness greater than 0.8 nm. In other embodiments, the high-k dielectric layer 317 is replaced by a silicon oxide layer having a thickness greater than 1.4 nm. The metal feature 213 penetrates the ILD layer 315 and the etch stop layer 311 to land on the high-k dielectric layer 317. The metal feature 213 is provided through, for example, a gate via 214 disposed thereon (not in Fig. 9B But in Fig. 9A In this configuration, when an input gate signal having high and low frequencies travels in the y direction, high frequency signals such as high frequency losses travel downward in the negative z direction through the filter fin 304 toward the substrate 102, and also travel upward in the positive z direction through the high-k dielectric layer 317 toward the metal feature 213.

[0047] Reference now Figure 10A-10C , additional cross-sectional views are provided. Fig. 10A Reappeared Fig. 9A , Figure 10B-Figure 10C They are shown respectively Fig. 10A Cross-sectional views taken along lines BB' and C'C'. Note that like labeled components may correspond to previously labeled components already described. Fig. 10BA gate structure 108 is shown having a gate dielectric 109 above the filter fin 304, a work function metal layer 307 above the gate dielectric 109, and a gate electrode (i.e., a filter gate portion 308) above the work function metal layer 307. The gate structure 108 is laterally surrounded by a high-k ILD layer 215a, which is disposed above the etch stop layer 211 above the filter fin 304. The ILD layer 215 may be disposed adjacent to the high-k ILD layer 215a and above the etch stop layer 211. A high-k dielectric layer 317 is disposed above the gate structure 108 and between the high-k ILD layers 215a. The high-k dielectric layer 317 may be formed by a metal pullback process that first selectively etches back the gate structure 108 to form a trench, then fills the trench with a high-k material and performs a planarization process. In this way, the top surface of the high-k dielectric layer 317 may be coplanar with the top surfaces of the high-k ILD layer 215a and the ILD layer 215. The etch stop layer 311 is disposed over the high-k dielectric layer 317, the high-k ILD layer 215a, and the ILD layer 215. The ILD layer 315 is disposed over the etch stop layer 311. The metal feature 213 penetrates the ILD layer 315 and the etch stop layer 311 to land on the high-k dielectric layer 317. Fig. 10C Shows Fig. 10B 1 , the gate structure 108 has a gate dielectric 109 above the isolation structure 101, a work function metal layer 207 above the gate dielectric 109, and a gate electrode (i.e., a transistor gate portion 208) above the work function metal layer 207. The gate structure 108 is laterally surrounded by an ILD layer 215. An etch stop layer 311 is disposed above the ILD layer 215 and above the gate structure 108. The ILD layer 315 is disposed above the etch stop layer 311.

[0048] Figures 11A-11DA semiconductor structure 100 with a filter fin 304 is shown according to another embodiment of the present disclosure. For the sake of brevity, similar features described in previous embodiments are not repeated here. In previous embodiments, high frequencies can be filtered out downwardly through the filter fin 304 into the substrate 102, and / or filtered out laterally from one gate structure 108 to another adjacent gate structure 108, and / or filtered out upwardly through the high-k dielectric layer 317 toward the metal component 213. Here, another way to achieve high-frequency gate signal filtering is from the filter gate portion 308 of the gate structure 108 to the adjacent metal contact 206a (in the x-direction) that is wired to ground. For example, as shown, the contact via 210a connected to the ground node is disposed above the metal contact 206a. In this embodiment, a capacitive filter is formed by the filter gate portion 308, the metal contact 206a, and the high-k dielectric layer (e.g., the high-k ILD layer 215a) therebetween. As described with respect to Fig.7D As mentioned, the dielectric layer therebetween may be the ILD layer 215. To promote high capacitance, the ILD layer 215 or a portion thereof surrounding and between two adjacent filter gate portions 308 is replaced with a high-k ILD layer 215a.

[0049] refer to Fig.11A , a metal contact 206a is disposed above the filter fin 304 and extends through the filter circuit area 300 in the y direction. The metal contact 206a is disposed between two adjacent filter gate portions 308 in the x direction. In one embodiment, the metal contact 206a can be aligned with the source / drain contacts 206 in the transistor circuit area 200 in the y direction. In one embodiment, the spacing between the metal contact 206a and the adjacent filter gate portion 308 is less than half of the spacing between adjacent gate structures 108 (or specifically, adjacent transistor gate portions 208) along the x direction.

[0050] Fig. 11B The mechanism of high-frequency gate signal filtering in the horizontal direction between the filter gate portion 308 and the adjacent metal contact 206a is shown. The input gate signal with high frequency and low frequency is provided to the filter gate portion 308 via the input gate voltage Vg. When the gate signal propagates in the y direction, due to the above-mentioned capacitive filter, high-frequency signals such as high-frequency losses propagate horizontally in the x direction into the metal contact 206a. These high-frequency signals are then grounded via the ground connection routed to the metal contact 206a. At the same time, the low-frequency signal passes through and continues to propagate in the y direction. Fig. 11B It is shown that high frequency filtering from the first gate structure 108 to the adjacent metal contact 206a to ground is also possible.

[0051] Fig. 11C Shows Fig.11A A cross-sectional view taken along line CC′ in the y direction. Line CC′ crosses one or more source / drain features 204 b of the fin active area 204 and one or more filter fins 304 . It is worth noting that line CC′ also passes through the metal contact 206 a disposed on the filter fin 304 . Fig. 11C and Fig.8D Similarly, similar features are not described again for the sake of brevity. The difference here is that the metal contact 206a penetrates the ILD layer 315, the etch stop layer 311 and a portion of the high-k ILD layer 215a to land on the top surface of the high-k ILD layer 215a. Fig. 11C In the embodiment, the metal contact 206a does not contact the filter fin 304. However, in other embodiments, the metal contact 206a may directly contact and land on the filter fin 304. The contact via 210a penetrates the ILD layer 415 and the etch stop layer 411 to land on the metal contact 206a. The contact via 210a may be electrically connected to the ground.

[0052] Fig.11D Shows Fig.11A A cross-sectional view taken along line DD′ in the x-direction. Line DD′ passes through two adjacent filter gate portions 308 of two gate structures 108 along the filter fin 304 and through the contact via 210 a therebetween. Fig.11D and Fig.7D Similarly, similar features are not described again for the sake of brevity. The difference is that a high-k ILD layer 215a is introduced that is laterally embedded between the ILD layers 215, wherein the high-k ILD layer 215a surrounds the filter gate portions 308 of two adjacent gate structures 108 and the metal contact 206a therebetween. Fig.11D In the embodiment shown in FIG. 3 , the metal contact 206a penetrates the ILD layer 315, the etch stop layer 311, and a portion of the high-k ILD layer 215a, but does not contact the filter fin 304. However, in other embodiments, the metal contact 206a may directly contact and land on the filter fin 304.

[0053] The present disclosure describes various embodiments of implementing a gate signal low pass filter by utilizing a filter circuit area 300 having a filter fin 304. The filter circuit area 300 is a gate connector area having a filter gate portion 308 connected to a transistor gate portion 208 in a transistor circuit area 200. The filter fin 304 filters out high frequency gate signals while allowing low frequency signals to pass. Note that various embodiments herein can independently implement gate signal filtering, or they can be combined with each other for customized signal conditioning.

[0054] Although not limiting, the present disclosure provides advantages of incorporating filter fins in the gate connector region between transistor circuit regions. One example advantage is filtering high frequency signals or losses through the filter fins and into the substrate so that the gate signal is adjusted when power is supplied to adjacent transistor regions. Another example advantage is adjusting the interface area between the gate dielectric and the filter fin, such as changing the width and height, to increase capacitance, thereby improving high frequency filtering. Another example advantage is doping the filter fins with a dopant of the opposite type to the transistor channel to maintain high capacitance of the filter fins in accumulation mode. Another example advantage is incorporating high-k dielectric materials and metal components in the filter fin region for alternative paths for signal filtering, such as from gate structure to gate structure, from gate structure to adjacent metal contacts, or from gate structure to metal components above the gate structure. Other example advantages include incorporating different gate metal materials (e.g., work function layers) in the gate connector region and the transistor circuit region to adjust resistivity.

[0055] One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a first circuit region, having a first fin active region extending longitudinally in a first direction above a substrate, each first fin active region including a first channel region between first source / drain components; a second circuit region, having a second fin active region extending longitudinally in the first direction above the substrate, each second fin active region including a second channel region between second source / drain components; a gate connector region, located between the first circuit region and the second circuit region and separating the first circuit region and the second circuit region, the gate connector region having a filter fin extending longitudinally in the first direction above the substrate; and a gate structure, extending across the first circuit region, the gate connector region and the second circuit region in a second direction perpendicular to the first direction, the gate structure being disposed above the first channel region and the second channel region and above the filter fin. The gate structure includes a gate dielectric located above the top surface and side surface of the first fin active region, the second fin active region and the filter fin. The portion of the gate structure in the gate connector region has a greater resistivity than the portion of the gate structure in the first circuit region and the second circuit region.

[0056] In one embodiment, the first fin active regions are spaced apart from each other by a first pitch along the second direction, the filter fins are spaced apart from each other by a second pitch along the second direction, and the first pitch is greater than the second pitch.

[0057] In one embodiment, the first fin active area has a first width along the second direction, the filter fin has a second width along the second direction, and the second width is greater than the first width.

[0058] In one embodiment, the first channel region and the second channel region are doped with a first dopant, the filter fin is doped with a second dopant, and the first dopant and the second dopant are opposite type dopants.

[0059] In one embodiment, the semiconductor structure further includes an isolation structure located above the substrate and surrounding the first fin active region, the second fin active region, and the filter fin. The first fin active region has a first height protruding above the top surface of the isolation structure, and the filter fin has a second height protruding above the top surface of the isolation structure, and the second height is greater than the first height.

[0060] In another embodiment, the source / drain features of the first fin active region include epitaxial features of the second dopant, wherein each filter fin is free of epitaxial features.

[0061] In one embodiment, the source / drain features of the first fin active region, the drain / source features of the second fin active region, and the filter fin are surrounded by an interlayer dielectric (ILD) layer. The ILD layer includes a first dielectric portion surrounding the source / drain features of the first fin active region and the second fin active region, a second dielectric portion surrounding the filter fin, and the second dielectric portion has a greater dielectric constant than the first dielectric portion.

[0062] In another embodiment, the first dielectric portion includes a dielectric material having a dielectric constant equal to or less than that of silicon oxide, and the second dielectric portion includes a metal oxide having a dielectric constant greater than that of silicon oxide.

[0063] In another embodiment, the gate structure is a first gate structure, and the semiconductor structure further includes: a second gate structure adjacent to the first gate structure along the first direction, the second gate structure extending across the first circuit region, the gate connector region, and the second circuit region along the second direction, and the second gate structure is disposed above the third channel region of the first fin active region and the second fin active region and above the filter fin, wherein the resistivity of a portion of the second gate structure within the gate connector region is greater than the resistivity of a portion of the second gate structure within the first circuit region and the second circuit region. The width of the portions of the first gate structure and the second gate structure within the gate connector region along the first direction is greater than the width of the portions of the first gate structure and the second gate structure within the first circuit region and the second circuit region. The first gate structure is electrically connected to a gate voltage, and the second gate structure is electrically grounded.

[0064] In another embodiment, the gate structure is a first gate structure, and the semiconductor structure further includes: a second gate structure adjacent to the first gate structure along the first direction, the second gate structure extending across the first circuit region, the gate connector region, and the second circuit region along the second direction, and the second gate structure is disposed above the third channel region of the first fin active region and the second fin active region and above the filter fin, wherein the resistivity of a portion of the second gate structure within the gate connector region is greater than the resistivity of a portion of the second gate structure within the second circuit region; and a metal component located between the first gate structure and the second gate structure along the first direction, the metal component landing on a second portion of the ILD layer and isolated from the first gate structure and the second gate structure. The first gate structure or the second gate structure is electrically connected to a gate voltage, and the metal component is electrically connected to ground.

[0065] In a further embodiment, the semiconductor structure further comprises: a high-k dielectric layer landed on the portion of the gate structure in the gate connector region; a metal component landed on the high-k dielectric layer and isolated from the gate structure. The portion of the gate structure in the first circuit region is electrically connected to the gate voltage, and the metal component is electrically connected to ground.

[0066] Another aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a transistor region having a fin active region extending longitudinally along a first direction on a substrate, each fin active region including a channel region between source / drain components; a filter region adjacent to the transistor region along a second direction perpendicular to the first direction, the filter region having a filter fin extending longitudinally along the first direction on the substrate; and a gate structure having a gate dielectric and a gate fill metal above the gate dielectric, the gate structure extending across the transistor region and the filter region along the second direction, and the gate structure is disposed directly above the channel region of the fin active region and directly above the filter fin. The source / drain components of the fin active region include epitaxial components, and the filter fin has no epitaxial components.

[0067] In a further embodiment, the channel region and the source / drain features have opposite type dopants.The channel region has a first type dopant, and the filter fin has a second type dopant opposite to the first type dopant.

[0068] In another embodiment, the gate structure includes a first gate portion in the transistor region and a second gate portion in the filter region, and the second gate portion has a greater resistivity than the first gate portion.

[0069] In another embodiment, the first gate portion includes Ag, Au, Al, Rh, W, Mo, Zn, Co, Ru, Nb or a combination thereof, and the second gate portion includes Ti, TiN, brass, phosphor bronze, cast steel, a metal compound or a combination thereof.

[0070] In a further embodiment, the semiconductor structure further comprises: a high-k dielectric layer landing on the second gate portion; and a metal component landing on the high-k dielectric layer and isolated from the gate structure. The first gate portion is electrically connected to a gate voltage, and the metal component is electrically grounded.

[0071] In a further embodiment, the semiconductor structure further comprises: a high-k dielectric layer over and surrounding the filter fin; and a metal component landed on the high-k dielectric layer and isolated from the gate structure. The first gate portion is electrically connected to a gate voltage, and the metal component is electrically grounded.

[0072] Another aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a transistor region having fin active regions extending longitudinally along a first direction on a substrate, each fin active region including a channel region between source / drain components; a filter region adjacent to the transistor region along a second direction perpendicular to the first direction, the filter region having filter fins extending longitudinally along the first direction above the substrate; a first gate structure having a first gate dielectric and a first gate electrode above the first gate dielectric, the first gate structure extending across the transistor region and the filter region along the second direction, and the first gate structure being disposed above a first group of channel regions and the filter fins; a second gate structure having a second gate dielectric and a second gate electrode above the second gate dielectric, the second gate structure extending across the transistor region and the filter region along the second direction, and the second gate structure being disposed above a second group of channel regions and the filter fins; and an interlayer dielectric (ILD) layer having a first dielectric portion surrounding the source / drain components, a second dielectric portion surrounding the filter fins, and the second dielectric portion having a dielectric constant greater than that of the first dielectric portion.

[0073] In one embodiment, the spacing between the first gate structure and the second gate structure in the transistor region is a first spacing, the spacing between the first gate structure and the second gate structure in the filter region is a second spacing, and the first spacing is greater than the second spacing. The first gate structure is electrically connected to a gate voltage, and the second gate structure is electrically grounded.

[0074] In one embodiment, the semiconductor structure further includes: a metal component located between the first gate structure and the second gate structure along the first direction, the metal component landing on the second dielectric portion of the ILD layer; and a source / drain contact landing on one of the source / drain components of the fin active region, wherein a top surface of the metal component is coplanar with the source / drain contact.

[0075] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, include: a first circuit region having first fin active regions extending longitudinally in a first direction above the substrate, each of the first fin active regions including a first channel region between first source / drain features; a second circuit region having second fin active regions extending longitudinally in the first direction over the substrate, each of the second fin active regions including a second channel region between second source / drain features; a gate connector region located between the first circuit region and the second circuit region and separating the first circuit region and the second circuit region, the gate connector region having a filter fin extending longitudinally along the first direction above the substrate; and a gate structure extending across the first circuit region, the gate connector region, and the second circuit region in a second direction perpendicular to the first direction, the gate structure being disposed above the first channel region and the second channel region and above the filter fin, wherein the gate structure includes a gate dielectric located above the top surface and side surfaces of the first fin active area, the second fin active area, and the filter fin, Wherein, a portion of the gate structure in the gate connector region has a greater resistivity than portions of the gate structure in the first circuit region and the second circuit region.

2. The semiconductor structure according to claim 1, in, The first fin active regions are spaced apart from each other by a first pitch along the second direction, the filter fins are spaced apart from each other by a second pitch along the second direction, and the first pitch is greater than the second pitch.

3. The semiconductor structure according to claim 1, in, The first fin active area has a first width along the second direction, the filter fin has a second width along the second direction, and the second width is greater than the first width.

4. The semiconductor structure according to claim 1, further comprising: include: an isolation structure located above the substrate and surrounding the first fin active area, the second fin active area and the filter fin, The first fin active region has a first height protruding above the top surface of the isolation structure, the filter fin has a second height protruding above the top surface of the isolation structure, and the second height is greater than the first height.

5. The semiconductor structure according to claim 1, in, The source / drain features of the first fin active region, the drain / source features of the second fin active region, and the filter fin are surrounded by an interlayer dielectric layer, The interlayer dielectric layer includes a first dielectric portion surrounding source / drain components of the first fin active region and the second fin active region, and a second dielectric portion surrounding the filter fin, and the second dielectric portion has a larger dielectric constant than the first dielectric portion.

6. The semiconductor structure according to claim 5, in, The gate structure is a first gate structure, and the semiconductor structure further includes: a second gate structure, adjacent to the first gate structure along the first direction, the second gate structure extending across the first circuit region, the gate connector region and the second circuit region along the second direction, and the second gate structure being disposed above a third channel region of the first fin active region and the second fin active region and above the filter fin, wherein a resistivity of a portion of the second gate structure within the gate connector region is greater than a resistivity of a portion of the second gate structure within the first circuit region and the second circuit region, wherein the width of the portion of the first gate structure and the second gate structure in the gate connector region along the first direction is greater than the width of the portion of the first gate structure and the second gate structure in the first circuit region and the second circuit region, Wherein, the first gate structure is electrically connected to a gate voltage, and the second gate structure is electrically grounded.

7. The semiconductor structure according to claim 5, in, The gate structure is a first gate structure, and the semiconductor structure further includes: a second gate structure adjacent to the first gate structure along the first direction, the second gate structure extending across the first circuit region, the gate connector region and the second circuit region along the second direction, and the second gate structure being disposed over a third channel region of the first fin active region and the second fin active region and over the filter fin, wherein a resistivity of a portion of the second gate structure within the gate connector region is greater than a resistivity of a portion of the second gate structure within the second circuit region; and a metal component located between the first gate structure and the second gate structure along the first direction, the metal component landing on the second portion of the interlayer dielectric layer and isolated from the first gate structure and the second gate structure, The first gate structure or the second gate structure is electrically connected to a gate voltage, and the metal component is electrically connected to ground.

8. A semiconductor structure, include: a transistor region having fin active regions extending longitudinally in a first direction on the substrate, each fin active region including a channel region between source / drain features; a filter region adjacent to the transistor region along a second direction perpendicular to the first direction, the filter region having a filter fin extending longitudinally along the first direction on the substrate; as well as a gate structure having a gate dielectric and a gate fill metal over the gate dielectric, the gate structure extending across the transistor region and the filter region along the second direction, and the gate structure being disposed directly over the channel region of the fin active region and directly over the filter fin, Wherein the source / drain features of the fin active region include epitaxial features, and the filter fin is free of epitaxial features.

9. The semiconductor structure according to claim 8, in, The gate structure includes a first gate portion in the transistor region and a second gate portion in the filter region, and the second gate portion has a greater resistivity than the first gate portion.

10. A semiconductor structure, include: a transistor region having fin active regions extending longitudinally along a first direction on the substrate, each fin active region including a channel region between source / drain features; a filter region adjacent to the transistor region along a second direction perpendicular to the first direction, the filter region having a filter fin extending longitudinally along the first direction over the substrate; a first gate structure having a first gate dielectric and a first gate electrode over the first gate dielectric, the first gate structure extending across the transistor region and the filter region along a second direction, and the first gate structure being disposed over a first set of channel regions and the filter fins; a second gate structure having a second gate dielectric and a second gate electrode over the second gate dielectric, the second gate structure extending across the transistor region and the filter region along the second direction, and the second gate structure being disposed over a second set of channel regions and filter fins; as well as An interlayer dielectric layer has a first dielectric portion surrounding the source / drain feature, a second dielectric portion surrounding the filter fin, and the second dielectric portion has a larger dielectric constant than the first dielectric portion.

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