Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a semiconductor substrate, wherein the semiconductor substrate has a groove; a first dielectric layer, a pinning layer and a second dielectric layer are sequentially arranged on the inner wall of the groove. In the working process of the semiconductor structure, the second dielectric layer can capture charges, the pinning layer is arranged between the first dielectric layer and the second dielectric layer, and the pinning layer can absorb the captured charges, so that the local electric field of the corresponding position is reduced, the accumulation of hot carriers to the top of the first dielectric layer is avoided to cause breakdown of the semiconductor structure, the accumulation of the hot carriers is avoided to damage the semiconductor structure, and the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] An oxide-nitride-oxide stacked structure is generally used in the isolation structure of a semiconductor device to form a shallow trench isolation (STI) to balance stress and ensure smooth progress of subsequent processes.

[0003] However, when a semiconductor device is operating, the nitride traps charge. This trapped charge causes hot carriers in the device to accumulate on top of the oxide in the STI structure, i.e., the shoulder of the active region, thereby affecting the electrical performance of the semiconductor device. For example, the accumulated hot carriers exert a negative voltage on the PMOS (P Metal Oxide Semiconductor), continuously lowering the threshold voltage of the PMOS and causing hot electron-induced breakdown.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the relevant technology that is already known to one of ordinary skill in the art. Summary of the Invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, which can prevent hot carrier accumulation from damaging the semiconductor structure and improve the electrical performance of the semiconductor structure.

[0006] An embodiment of the present disclosure provides a semiconductor structure, comprising: a semiconductor substrate having a trench therein; a first dielectric layer, a pinning layer, and a second dielectric layer sequentially provided on an inner wall of the trench.

[0007] In some embodiments of the present disclosure, the pinned layer is a stacked layer including a first sub-layer and a second sub-layer.

[0008] In some embodiments of the present disclosure, there are multiple stacks.

[0009] In some embodiments of the present disclosure, the material of the first sublayer includes at least one of HfO2, ZrO2, SrTiO3, and TiO2, and the material of the second sublayer includes at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon; or, the material of the first sublayer includes GaAs, and the material of the second sublayer includes SiO2; or, the material of the first sublayer includes a transition metal chalcogenide; the material of the second sublayer includes at least one of Au, Ag, Pt, Mo, Cu, Al, W, and Ni.

[0010] In some embodiments of the present disclosure, the semiconductor substrate includes a plurality of active areas, the trench is located between adjacent active areas, and a portion of the pinning layer is located on the first dielectric layer at a position 1 / 7 to 1 / 6 of the depth from the top surface of the active area to the trench, wherein the depth of the trench is the dimension from the top surface of the active area to the bottom surface of the trench in the vertical direction.

[0011] In some embodiments of the present disclosure, the semiconductor substrate includes multiple active areas, the trench is located between adjacent active areas, the semiconductor structure includes a transistor, the transistor is located in the active area, and in the horizontal direction, the source or drain of the transistor is located on one side of the trench, and the projection of the pinning layer on the transistor along the horizontal direction at least covers the side of the source or the drain.

[0012] In some embodiments of the present disclosure, the semiconductor structure further includes a third dielectric layer located on the second dielectric layer and completely filling the trench.

[0013] In some embodiments of the present disclosure, the material of the first dielectric layer and the third dielectric layer respectively includes at least one of silicon oxide and silicon oxynitride; and the material of the second dielectric layer includes silicon nitride.

[0014] In some embodiments of the present disclosure, the second dielectric layer covers a top surface of the pinned layer.

[0015] An embodiment of the present disclosure also provides a method for preparing a semiconductor structure, comprising: providing a semiconductor substrate and forming a trench on the semiconductor substrate; conformally forming a first dielectric layer on an inner wall of the trench; forming a pinning layer on at least a portion of the first dielectric layer; and forming a second dielectric layer on the inner wall of the trench having the pinning layer formed thereon.

[0016] It can be seen from the above technical solutions that the semiconductor structure of the embodiment of the present disclosure has at least one of the following advantages and positive effects:

[0017] In the embodiment of the present disclosure, when the semiconductor structure is working, the second dielectric layer will capture charges, and a pinning layer is set between the first dielectric layer and the second dielectric layer. The pinning layer can absorb the captured charges, thereby reducing the local electric field at the corresponding position, preventing hot carriers from accumulating to the top of the first dielectric layer to cause breakdown of the semiconductor structure, thereby preventing hot carrier accumulation from damaging the semiconductor structure and improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

[0019] Figure 1 A schematic diagram of a semiconductor substrate according to some embodiments of the present disclosure;

[0020] Figure 2 A schematic diagram illustrating forming trenches on a semiconductor substrate according to some embodiments of the present disclosure;

[0021] Figure 3 A schematic diagram illustrating forming a first dielectric layer according to some embodiments of the present disclosure;

[0022] Figure 4 A schematic diagram illustrating forming a first sub-layer according to some embodiments of the present disclosure;

[0023] Figure 5 A schematic diagram illustrating forming a second sub-layer according to some embodiments of the present disclosure;

[0024] Figure 6 A schematic diagram illustrating forming a second dielectric layer according to some embodiments of the present disclosure;

[0025] Figure 7 A schematic diagram illustrating the formation of a third dielectric layer according to some embodiments of the present disclosure;

[0026] Figure 8 A schematic diagram of a semiconductor structure after planarization processing according to some embodiments of the present disclosure;

[0027] Figure 9 A schematic diagram of a semiconductor structure including a transistor according to some embodiments of the present disclosure;

[0028] Figure 10 The present invention is a flowchart of a method for preparing a semiconductor structure according to some embodiments of the present disclosure.

[0029] Description of reference numerals:

[0030] 1. Semiconductor substrate; 11. Trench; 2. First dielectric layer; 3. Pinning layer; 31. First sublayer; 32. Second sublayer; 4. Second dielectric layer; 5. Third dielectric layer; A. Active area; X, horizontal direction; Y, vertical direction; d, trench depth; 6. Transistor; G, gate; S, source; D, drain. DETAILED DESCRIPTION

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0032] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of this disclosure and in which different exemplary structures that can implement various aspects of the present disclosure are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. In addition, the terms "first", "second", etc. in the claims are used only as marks and are not numerical limitations on their objects.

[0033] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0034] In addition, in the description of the present disclosure, “a plurality of” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0035] As pointed out in the background technology, when the semiconductor device is working, the nitride layer captures charges, and the captured charges will attract hot carriers in the device, causing the hot carriers to continuously accumulate to the shoulder of the active region, which can easily cause breakdown, thereby affecting the performance of the semiconductor device. For example, for PMOS, the accumulated hot carriers will apply a negative voltage to the PMOS, continuously reducing the threshold voltage of the PMOS, resulting in induced breakdown and damaging the PMOS.

[0036] Based on this, Figure 8 and Figure 9 As shown, an embodiment of the present disclosure provides a semiconductor structure, which includes a semiconductor substrate 1 having a trench 11. A first dielectric layer 2, a pinning layer 3, and a second dielectric layer 4 are sequentially provided on the inner wall of the trench 11.

[0037] In the disclosed embodiment, when the semiconductor structure is operating, the second dielectric layer 4 captures charge. A pinning layer 3 is provided between the first dielectric layer 2 and the second dielectric layer 4. The pinning layer 3 absorbs the captured charge, thereby reducing the local electric field at the corresponding location, preventing hot carriers from accumulating on the top of the first dielectric layer 2 (the shoulder of the active region) and causing breakdown of the semiconductor structure. This, in turn, prevents hot carrier accumulation from damaging the semiconductor structure and improves the electrical performance of the semiconductor structure. Furthermore, the first dielectric layer 2 is provided between the pinning layer 3 and the semiconductor substrate 1, so that the pinning layer 3 does not generate Coulomb scattering in the channel region of the semiconductor substrate 1, thereby preventing any impact on the mobility of the semiconductor structure.

[0038] The semiconductor structure of the embodiment of the present disclosure is described in detail below.

[0039] In the embodiments of the present disclosure, the semiconductor structure may be a transistor, such as a PMOS or NMOS. For ease of description, some embodiments of the present disclosure use PMOS as an example, but this does not limit the semiconductor structure of the embodiments of the present disclosure.

[0040] like Figure 1 As shown, the trench 11 on the semiconductor substrate 1 may be a trench 11 where a shallow trench isolation is located, and the trench 11 may be etched on the semiconductor substrate 1 using a wet etching process or a dry etching process.

[0041] The dry etching process may be a plasma etching process, wherein the etching gas used in the plasma etching process may be chlorine gas. By controlling the amount of the etching gas, the etching degree may be controlled. The wet etching process may use hydrofluoric acid as an etchant. By adjusting the concentration of the etchant, the etching degree may also be controlled, thereby controlling the width and depth of the trench 11.

[0042] The semiconductor substrate 1 can be made of silicon, silicon carbide, silicon-on-insulator (SiO2), silicon-on-insulator (SiO2), silicon-germanium-on-insulator (SiGe), or germanium-on-insulator (GeO2). The substrate can also be implanted with certain dopants to modify electrical parameters based on design requirements. The semiconductor substrate 1 can have active areas A, with shallow trench isolation (STI) located between the active areas A. Specifically, trenches 11 are located between adjacent active areas A.

[0043] like Figure 1 As shown, the width of the trench 11 can gradually increase from the bottom end of the trench to the opening of the trench in the vertical direction Y. This is conducive to depositing a film layer on the inner wall of the trench 11 and improving the stability of the functional film layer formed inside the trench 11. The vertical direction Y can be understood as a direction perpendicular to the bottom surface of the trench 11.

[0044] like Figure 8As shown, in some embodiments, the pinning layer 3 is a stack including a first sublayer 31 and a second sublayer 32. That is, the pinning layer 3 includes at least a first sublayer 31 and a second sublayer 32. A large number of interface states will be generated at the contact surface of the first sublayer 31 and the second sublayer 32, and the charges trapped in the dielectric layer can preferentially fill the interface states, that is, the pinning layer 3 can absorb the trapped charges, avoid the accumulation of hot carriers, thereby reducing the change in the threshold voltage of the device and preventing the induced breakdown of hot carriers, such as the induced breakdown of hot electrons. In other words, this interface state of the pinning layer can reduce the accumulation of hot carriers, thereby avoiding the induced breakdown of hot carriers in MOS, such as P-type MOS.

[0045] like Figure 8 As shown, the stack includes a first sublayer 31 and a second sublayer 32. In some embodiments, the pinned layer 3 includes a stack. In the stack, the first sublayer 31 can be disposed on the first dielectric layer 2, and the second sublayer 32 can be disposed on the first sublayer 31, or the second sublayer 32 can be disposed on the first dielectric layer 2, and the first sublayer 31 can be disposed on the second sublayer 32. In other words, the order of the first sublayer 31 and the second sublayer 32 in the stack is not fixed, and the order of the first sublayer 31 and the second sublayer 32 can be adjusted according to actual conditions.

[0046] In some embodiments, multiple layers are stacked. That is, multiple first sublayers 31 and second sublayers 32 are disposed between the first dielectric layer 2 and the second dielectric layer 4. This allows for the formation of multiple interface states, thereby more effectively absorbing charges trapped by the dielectric layers and more thoroughly preventing the accumulation of hot carriers.

[0047] In some embodiments, the number of stacks can be 2, 3, 4, 5 or more, and the number of stacks can be set according to actual conditions. The stacking order of the first sublayers 31 and the second sublayers 32 in the multiple stacks can be the same or different, or partially the same and partially different. This is not particularly limited and can be adjusted according to actual conditions. In some embodiments, the first sublayers 31 and the second sublayers 32 in the multiple stacks are alternately arranged, so that the maximum number of interface states can be formed, which can more effectively absorb the trapped charges, reduce the electric field caused by the charges, and thus reduce the accumulation of hot carriers.

[0048] The semiconductor substrate 1 includes multiple active areas A, with trenches 11 located between adjacent active areas A. In some embodiments, a portion of the pinning layer 3 is located on the first dielectric layer 2 at a position 1 / 7 to 1 / 6 of the depth d from the top surface of the active area A to the trench 11. The depth d of the trench 11 is the dimension from the top surface of the active area A to the bottom surface of the trench 11 in the vertical direction Y. For example, the dimension of the first dielectric layer 2 in the vertical direction Y is 300 to 350 nm. Specifically, in addition to the two extreme values ​​mentioned above, it can also be 310 nm, 320 nm, 330 nm, or 340 nm. Without special limitation here, the pinning layer 3 is located at a position where the depth from the top surface of the active area A to the trench 11 is 50 nm. When the semiconductor structure is operating, without the pinning layer 3, generated hot electrons generally accumulate at the top of the first dielectric layer 2. This top is generally located at a position between the top surface of the active area A and 1 / 7 to 1 / 6 of the depth d of the trench 11. Therefore, placing the pinning layer 3 at this location can effectively absorb trapped charges, prevent hot carrier accumulation on the shoulder of the active area A, and save materials and reduce costs. Alternatively, the pinning layer 3 can be located on the entire inner surface of the first dielectric layer 2 to prevent hot electrons from transferring to the first dielectric layer 2 at various locations.

[0049] In some embodiments, the pinning layer 3 is only formed on the bottom of the first dielectric layer 2 .

[0050] In some embodiments, the pinning layer 3 may also be located on the sidewalls of the first dielectric layer 2. Alternatively, the pinning layer 3 may also be located on the entire sidewalls of the first dielectric layer 2, or at any position greater than 1 / 6 of the depth d from the top surface of the active area A to the trench 11, both of which can achieve shielding of hot electrons.

[0051] As in the above embodiment, the semiconductor substrate 1 includes multiple active areas A, and the trench 11 is located between adjacent active areas A. In some embodiments, the semiconductor structure further includes a transistor 6, which is located in the active area A. In the horizontal direction X, the source S or drain D of the transistor is located on one side of the trench 11, and the projection of the pinning layer 3 on the transistor 6 along the horizontal direction X at least covers the source S or the drain D.

[0052] Specifically, if Figure 9 As shown, trench 11 is located between adjacent active areas A, and transistor 6 is located in the active area. Transistor 6 includes a source S, a drain D, and a gate G. The source S and drain D are located within semiconductor substrate 1. A horizontal direction X is perpendicular to a vertical direction Y. In the horizontal direction X, the area of ​​pinning layer 3 is greater than or equal to the area of ​​source S or drain D. In other words, pinning layer 3 covers source S or drain D, preventing hot carriers from accumulating on the shoulder of active area A and affecting source S or drain D, thereby reducing damage to transistor 6.

[0053] The material of the first sub-layer 31 and the second sub-layer 32 are complementary to each other. In some embodiments, the material of the first sub-layer 31 can be a high-K material, which can include at least one of HfO2, ZrO2, SrTiO3, TiO2, and the material of the second sub-layer 32 can be silicon, specifically, the material of the second sub-layer 32 can include at least one of single crystal silicon, polycrystalline silicon and amorphous silicon. In this way, the high-K material can generate interface states when in contact with the silicon material, effectively absorbing the charges trapped by the second dielectric layer 4.

[0054] In some embodiments, the material of the first sub-layer 31 can include GaAs, and the material of the second sub-layer 32 can include SiO2.

[0055] In some embodiments, the material of the first sub-layer 31 includes a transition metal chalcogenide, with a chemical formula of MX2, where M can be any one of Ti, V, Ta, Mo, W, Re, and X can be at least one of S, Se, Te. The material of the second sub-layer 32 can include at least one of Au, Ag, Pt, Mo, Cu, Al, W and Ni.

[0056] In the above embodiments, the materials of the first sub-layer 31 and the second sub-layer 32, when in contact with each other, can generate interface states, effectively absorbing the charges trapped by the second dielectric layer 4. At the same time, due to the thickness of the first dielectric layer 2 being relatively thick, and optionally, the thickness of the first dielectric layer 2 being greater than 10 nm, (angstrom) or above, so that the pinning layer 3 does not generate Coulomb scattering to the channel of the PMOS, thereby avoiding affecting the mobility of the PMOS.

[0057] In some embodiments, as shown in FIG. 1B, the semiconductor structure further includes a third dielectric layer 5 located on the second dielectric layer 4 and filling the trench 11. Figure 8 Figure 9 As shown in FIG. 1B, the semiconductor structure further includes a third dielectric layer 5 located on the second dielectric layer 4 and filling the trench 11.

[0058] In some embodiments, the material of the first dielectric layer 2 and the third dielectric layer 5 can include at least one of silicon oxide, silicon nitride and silicon oxynitride, respectively. The material of the first dielectric layer 2 can be the same as the material of the third dielectric layer 5, in this way, the material can be changed during the process, simplifying the process. Of course, the material of the first dielectric layer 2 and the third dielectric layer 5 can also be different. The material of the second dielectric layer 4 can be silicon nitride. After the third dielectric layer 5 is formed, the shallow trench isolation is still an oxide-nitride-oxide structure, which can better balance the stress and ensure the smooth progress of the process.

[0059] ​In some embodiments, the semiconductor structure may not include the third dielectric layer 5 described above, but instead the second dielectric layer 4 may completely fill the trench 11. After forming the pinning layer 3, the second dielectric layer 4 may be formed on the pinning layer 3 or on the pinning layer 3 and the first dielectric layer 2 (when the pinning layer 3 is formed only on a portion of the first dielectric layer 2). Thus, the remaining space in the trench 11 may be completely filled with the second dielectric layer 4. This simplifies the process while achieving a certain stress balance.

[0060] In some embodiments, the top surface of the pinned layer 3 is lower than the top surface of the semiconductor substrate 1 , and the second dielectric layer 4 covers the top surface of the pinned layer 3 .

[0061] Specifically, if Figure 8 As shown, the top surfaces of the first dielectric layer 2, the pinning layer 3, and the second dielectric layer 4 are all flush with the top surface of the semiconductor substrate 1. In this embodiment, the top surface of the pinning layer 3 is lower than the top surface of the semiconductor substrate 1, and the second dielectric layer 4 covers the top surface of the pinning layer 3, and the top surface of the second dielectric layer 4 is flush with the top surface of the semiconductor substrate 1. This arrangement can prevent the pinning layer 3 from being exposed to the surface of the semiconductor substrate 1. Based on the material of the pinning layer 3 described above, it can be seen that the pinning layer 3 is conductive. For some semiconductor structures, it is undesirable to expose the pinning layer 3 because the pinning layer 3 exposed on the surface of the semiconductor substrate 1 may short-circuit with other electrical connection structures, posing a risk of damaging the semiconductor structure. To avoid this risk, the second dielectric layer 4 can cover the top surface of the pinning layer 3 so that the top surface of the pinning layer 3 is not exposed to the outside, thereby avoiding short-circuiting with other electrical connection structures.

[0062] Of course, in other embodiments, some semiconductor structures do not have the risk of short circuit between the pinning layer 3 and other electrical connection structures, and the top surface of the pinning layer 3 can be flush with the top surface of the semiconductor substrate 1, that is, the top surfaces of the first dielectric layer 2, the pinning layer 3, the second dielectric layer 4 and the third dielectric layer 5 are all flush with the top surface of the semiconductor substrate 1. In this way, a flat surface can be formed in one step using a chemical mechanical process, which simplifies the process.

[0063] In summary, in the semiconductor structure of the embodiment of the present disclosure, when the semiconductor structure is operating, the second dielectric layer 4 will capture charges, and the pinning layer 3 is provided between the first dielectric layer 2 and the second dielectric layer 4. The pinning layer 3 can absorb the captured charges, thereby reducing the local electric field at the corresponding position, preventing hot carriers from accumulating on the top of the first dielectric layer 2 and causing breakdown of the semiconductor structure, thereby preventing hot carrier accumulation from damaging the semiconductor structure, and improving the electrical performance of the semiconductor structure.

[0064] The present disclosure also provides a method for preparing a semiconductor structure. Figures 1 to 8, shows a schematic diagram of the structure of the semiconductor structure in various steps, such as Figure 10 As shown, a schematic flow chart of a method for preparing a semiconductor structure is shown.

[0065] like Figure 10 As shown, the method for preparing the semiconductor structure according to the embodiment of the present disclosure includes the following steps S101 to S104.

[0066] S101 : providing a semiconductor substrate 1 , and forming a trench 11 on the semiconductor substrate 1 .

[0067] S102 : forming a first dielectric layer 2 conformally on the inner wall of the trench 11 .

[0068] S103 : forming a pinning layer 3 on at least a portion of the first dielectric layer 2 .

[0069] S104 : forming a second dielectric layer 4 on the inner wall of the trench 11 where the pinning layer 3 is formed.

[0070] In the above method, when the semiconductor structure is working, the second dielectric layer 4 will capture charges. A pinning layer is provided between the first dielectric layer 2 and the second dielectric layer 4. The pinning layer 3 can absorb the captured charges, thereby reducing the local electric field at the corresponding position, preventing hot carriers from accumulating on the top of the first dielectric layer 2 to cause breakdown of the semiconductor structure, thereby preventing hot carrier accumulation from damaging the semiconductor structure and improving the electrical performance of the semiconductor structure.

[0071] The following is a detailed description of the method for preparing the semiconductor structure according to the embodiment of the present disclosure.

[0072] S101 : providing a semiconductor substrate 1 , and forming a trench 11 on the semiconductor substrate 1 .

[0073] like Figure 1 and Figure 2 As shown, multiple trenches 11 can be formed in the semiconductor substrate 1. For ease of illustration, only one trench 11 is shown in the figure. The multiple trenches 11 are used to form shallow trench isolation. The active area A of the semiconductor substrate 1 is located between the multiple trenches 11.

[0074] A mask layer having a pattern of trenches 11 can be formed on the semiconductor substrate 1. The pattern of the trenches 11 on the mask layer is transferred to the semiconductor substrate 1 using an etching process to form a plurality of trenches 11. When a wet etching process is used, the depth and width of the trenches 11 can be controlled by controlling the amount and concentration of the etchant. When a dry etching process is used, the depth and width of the trenches 11 can be controlled by controlling the amount and concentration of the etching gas to obtain trenches 11 that meet the requirements.

[0075] In some embodiments, the width of the trench 11 gradually increases from the bottom wall of the trench 11 to the opening in the vertical direction Y, where the width of the trench 11 refers to the distance between the two sidewalls of the trench 11 in the horizontal direction X. In subsequent processes, a deposition process will be used to form the first dielectric layer 2 on the inner wall of the trench 11. Since the width of the trench 11 gradually increases from bottom to top, the material of the first dielectric layer 2 can be evenly deposited on the surface of the inner wall of the trench 11 without any deposition dead corners, making the thickness of the first dielectric layer 2 more uniform and improving its stability.

[0076] S102 : forming a first dielectric layer 2 conformally on the inner wall of the trench 11 .

[0077] like Figure 3 As shown, a first dielectric layer 2 can be formed on the inner wall of the trench 11 and the surface of the semiconductor substrate 1 outside the trench 11 by a deposition process. Here, “conformally formed” can be understood as formed along the surface contour of the inner wall of the trench 11.

[0078] In some embodiments, the deposition process may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, which may be selected based on actual conditions and is not particularly limited herein.

[0079] S103 : forming a pinning layer 3 on at least a portion of the first dielectric layer 2 .

[0080] Specifically, if Figure 4 and Figure 5 As shown, forming the pinning layer 3 on at least a portion of the first dielectric layer 2 includes: forming a stack of a first sub-layer 31 and a second sub-layer 32 on at least a portion of the first dielectric layer 2 .

[0081] like Figure 5 As shown, the stack of the first sublayer 31 and the second sublayer 32 has one. The first sublayer 31 can be formed on the surface of the first dielectric layer 2 by a deposition process, and the second sublayer 32 can be formed on the surface of the first sublayer 31. Of course, the second sublayer 32 can also be formed on the surface of the first dielectric layer 2, and the first sublayer 31 can be formed on the surface of the second sublayer 32.

[0082] In some embodiments, the stack of the first sublayer 31 and the second sublayer 32 has multiple layers, for example, 2, 3, 4, 5 or more layers. For example, when there are two layers, the first sublayer 31, the second sublayer 32, the first sublayer 31 and the second sublayer 32 can be sequentially formed on the first dielectric layer 2, or the second sublayer 32, the first sublayer 31, the second sublayer 32 and the first sublayer 31 can be sequentially formed. Of course, it is best that the first sublayer 31 and the second sublayer 32 appear alternately, which can increase the number of interface states and more effectively absorb the charges captured by the dielectric layer.

[0083] In some embodiments, a pinning layer 3 can be formed on the entire surface of the first dielectric layer 2 to block hot electrons from transferring to the first dielectric layer 2 at various locations. In other embodiments, the pinning layer 3 can be deposited on the first dielectric layer 2 from the top surface of the active area A to 1 / 7 to 1 / 6 of the depth d of the trench 11. Specifically, a blocking layer can be formed on the inner surface of the first dielectric layer 2, and an opening can be formed at the location where the pinning layer 3 is to be deposited to expose the location, and the pinning layer 3 can be formed at the location using a deposition process. Alternatively, the blocking layer can be omitted, and the pinning layer 3 can be deposited on the inner surface of the first dielectric layer 2. The pinning layer 3 can then be patterned to retain only the pinning layer 3 at the desired location. In the absence of the pinning layer 3, when the semiconductor structure is operating, the generated hot electrons tend to accumulate at the top of the first dielectric layer 2, that is, at a position from the top of the first dielectric layer 2 to 1 / 7 to 1 / 6 of the depth of the first dielectric layer 2. Depositing at least a portion of the pinning layer 3 at this position can effectively absorb charges, prevent hot carriers from gathering at the shoulder of the active region A, and simplify the structure.

[0084] In other embodiments, the pinning layer 3 can be formed only on the sidewalls of the first dielectric layer 2 by a deposition process, or on the first dielectric layer 2 at any position greater than 1 / 6 of the depth d from the top surface of the active area A to the trench 11, so as to achieve shielding of hot electrons.

[0085] S104 : forming a second dielectric layer 4 on the inner wall of the trench 11 where the pinning layer 3 is formed.

[0086] like Figure 6 As shown, a second dielectric layer 4 can be formed on the surface of the pinned layer 3 using a deposition process. In some embodiments, the second dielectric layer 4 can be filled in the remaining space of the trench 11 where the pinned layer 3 is formed. That is, the second dielectric layer 4 fills the remaining space of the trench 11. This can simplify the process.

[0087] In some embodiments, as Figure 6 As shown, after the second dielectric layer 4 is formed on the pinning layer 3, it does not fill up the remaining space of the groove 11, but leaves a certain amount of space. In the embodiment of the present disclosure, after the pinning layer 3 is formed, the third dielectric layer 5 is also filled in the remaining space of the groove 11 where the second dielectric layer 4 is formed. Figure 7 As shown, a deposition process can be used to form the third dielectric layer 5. After the third dielectric layer 5 is formed, the structure of the shallow trench isolation is still an oxide-nitride-oxide structure, which can better balance the stress and ensure smooth process.

[0088] In some embodiments, after forming the pinning layer 3 on at least a portion of the first dielectric layer 2 in S1030, the preparation method further includes etching back the pinning layer 3 until the top surface of the pinning layer 3 is lower than the top surface of the semiconductor substrate 1. Then, forming the second dielectric layer 4 on the inner wall of the trench 11 in which the pinning layer 3 is formed in S104 includes forming the second dielectric layer 4 on the inner wall surface of the pinning layer 3 and the top surface of the pinning layer 3.

[0089] Specifically, after forming the second dielectric layer 4 or the third dielectric layer 5, the first dielectric layer 2, the pinning layer 3, the second dielectric layer 4, and the third dielectric layer 5 located on the surface of the semiconductor substrate 1 are removed, so that the isolation structure in the trench 11 is flush with the surface of the semiconductor substrate 1, facilitating the implementation of the next process. The above structure can be polished using a chemical mechanical polishing process to achieve planarization.

[0090] like Figure 8 As shown, after the surface of the semiconductor substrate 1 is ground, the top surface of the pinning layer 3 will be exposed. However, in some semiconductor structures, it is not desirable to expose the pinning layer 3 because the pinning layer 3 has the risk of short-circuiting with other electrical connection structures, which may damage the semiconductor structure. In order to avoid this risk, the pinning layer 3 needs to be insulated and isolated from the outside world. Therefore, in the present embodiment, after the pinning layer 3 is formed, the top surface of the pinning layer 3 can be etched back so that its top surface is lower than the top surface of the semiconductor substrate 1, so that when the second dielectric layer 4 is subsequently formed by a deposition process, the second dielectric layer 4 can be deposited on the top surface of the pinning layer 3, and part of the second dielectric layer 4 is located in the groove 11. When the semiconductor structure is ground so that the top surface of the isolation structure in the groove 11 is flush with the top surface of the semiconductor substrate 1, the top surface of the pinning layer 3 is still covered with the second dielectric layer 4, that is, the pinning layer 3 is not exposed, but is insulated and isolated from the outside world, thereby avoiding the risk of short-circuiting with the electrical connection structure, thereby avoiding damage to the semiconductor structure and improving the conductive performance of the semiconductor structure.

[0091] It should be noted that the amount of back etching on the top surface of the pinning layer 3 cannot be too much. When the pinning layer 3 is covered by the second dielectric layer 4 and is insulated from the outside world, the back etching depth should be as small as possible, so as to improve the shielding effect on hot electrons.

[0092] In summary, according to the preparation method of the embodiment of the present disclosure, when the semiconductor structure is operating, the second dielectric layer 4 will capture charges, and a pinning layer is provided between the first dielectric layer 2 and the second dielectric layer 4. The pinning layer 3 can absorb the captured charges, thereby reducing the local electric field at the corresponding position, preventing hot carriers from accumulating on the top of the first dielectric layer 2 and causing breakdown of the semiconductor structure, thereby preventing hot carrier accumulation from damaging the semiconductor structure and improving the electrical performance of the semiconductor structure.

[0093] It should be understood that the present disclosure is not limited in its application to the detailed structure and arrangement of the components set forth in this specification. The present disclosure is capable of other embodiments and can be implemented and carried out in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All of these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best known ways to implement the present disclosure and will enable those skilled in the art to adopt the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a semiconductor substrate having a trench therein; A first dielectric layer, a pinning layer, and a second dielectric layer for trapping charges are sequentially provided on the inner wall of the trench; Wherein, the pinned layer is a stacked layer including a first sublayer and a second sublayer; The material of the first sublayer includes at least one of HfO2, ZrO2, SrTiO3, and TiO2, and the material of the second sublayer includes at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon; Or, the material of the first sub-layer includes GaAs, and the material of the second sub-layer includes SiO2; Alternatively, the material of the first sublayer includes a transition metal chalcogenide, and the material of the second sublayer includes at least one of Au, Ag, Pt, Mo, Cu, Al, W, and Ni.

2. The semiconductor structure according to claim 1, wherein: The number of the stacked layers is multiple.

3. The semiconductor structure according to claim 1, wherein: The semiconductor substrate includes multiple active areas, the trench is located between adjacent active areas, and part of the pinning layer is located on the first dielectric layer at a position 1 / 7 to 1 / 6 of the depth from the top surface of the active area to the trench, wherein the depth of the trench is the dimension from the top surface of the active area to the bottom surface of the trench in the vertical direction.

4. The semiconductor structure according to claim 1, wherein: The semiconductor substrate includes multiple active areas, the trench is located between adjacent active areas, the semiconductor structure includes a transistor, the transistor is located in the active area, in the horizontal direction, the source or drain of the transistor is located on one side of the trench, and the projection of the pinning layer on the transistor along the horizontal direction at least covers the side of the source or the drain.

5. The semiconductor structure according to claim 1, wherein: Also includes: The third dielectric layer is located on the second dielectric layer and completely fills the trench.

6. The semiconductor structure according to claim 5, wherein: The materials of the first dielectric layer and the third dielectric layer include at least one of silicon oxide and silicon oxynitride; the material of the second dielectric layer includes silicon nitride.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that The second dielectric layer covers a top surface of the pinned layer.

8. A method for preparing a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, and forming a trench on the semiconductor substrate; conformally forming a first dielectric layer on an inner wall of the trench; forming a pinning layer on at least a portion of the first dielectric layer; forming a second dielectric layer for trapping charges on an inner wall of the trench where the pinning layer is formed; Wherein, the pinned layer is a stacked layer including a first sublayer and a second sublayer; The material of the first sublayer includes at least one of HfO2, ZrO2, SrTiO3, and TiO2, and the material of the second sublayer includes at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon; Or, the material of the first sub-layer includes GaAs, and the material of the second sub-layer includes SiO2; Alternatively, the material of the first sublayer includes a transition metal chalcogenide, and the material of the second sublayer includes at least one of Au, Ag, Pt, Mo, Cu, Al, W, and Ni.

Images