NiO-based x Dual-heterojunction enhancement-mode planar-gate vertical bipolar transistor based on Ga2O3

Abstract

The application discloses a NiO x / Ga2O3 double heterojunction enhancement mode planar gate vertical bipolar transistor, and mainly solves the problem that the prior art cannot realize enhancement mode and has poor reverse voltage resistance. The vertical bipolar transistor comprises, from bottom to top, a drain electrode, a substrate, a drift region, a p-type conductive layer, and a gate electrode, and forms a planar gate structure; the drift region is provided with current blocking layers on two sides thereof, the p-type conductive layer is provided with ohmic contact layers on two sides thereof, and the gate electrode is provided with source electrodes on two sides thereof; the substrate and the ohmic contact layers are both high-doped gallium oxide, the drift region is low-doped gallium oxide, the current blocking layers are high-resistivity gallium oxide, and the p-type conductive layer is p-type NiO x ; the p-type NiO x contacts the ohmic contact layers and the drift region to form first and second heterojunctions J1 and J2 respectively. The planar gate structure and the double heterojunctions J1 and J2 can significantly improve the voltage resistance of the device, realize the enhancement mode of the device, and increase the safe working range of the device, and the vertical bipolar transistor can be used for preparing a high-power gallium oxide transistor.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor power electronic devices, and particularly relates to a double-heterojunction enhanced planar gate vertical bipolar transistor, which can be used for power transmission and high-power electric energy conversion. BACKGROUND

[0002] As a new type of ultra-wide bandgap semiconductor material, Ga2O3 power devices have attracted widespread attention in recent years. Due to the bandgap width of E g =4.8eV, according to the relationship between the critical electric field E C and the direct bandgap width E g E C =1.73×10 5 E g 2.5 Ga2O3 has a very high critical breakdown electric field strength E C =8MV / cm. In addition, n-type Ga2O3 material has a doping concentration of 10 15 -10 20 cm -3 , electron mobility μ n =150cm 2 / V·s and electron saturation speed up to v n,sat =2×10 7 cm / s, so Ga2O3 material has great advantages in the field of power devices, and the power factor optimization value Baliga's FoM=εμ n E C 3 is 10 times and 4 times that of the third-generation semiconductors SiC and GaN.

[0003] The patent document with application number 202310698699.2 discloses a "gallium oxide vertical transistor integrated with Schottky diode and preparation method". The device includes: a current blocking layer; a heavily doped contact layer above the current blocking layer; a gate slot; a diode contact slot; an anode electrode penetrating through the current blocking layer and the heavily doped contact layer, a source electrode covering the diode contact slot and the heavily doped contact layer; a gate electrode covering the gate dielectric layer and the source electrode, and the gate electrode has an opening to expose at least part of the gate dielectric layer. The device realizes the integration of Ga2O3 Schottky diode and Ga2O3 vertical transistor, but since it belongs to unipolar devices, it is usually a depletion type device, and the reverse leakage current increases with the increase of reverse voltage, and the reverse voltage withstand capability is poor.

[0004] The patent document with application number CN202111498547.5 discloses a "heterojunction field effect transistor based on Ga2O3 and preparation". As shown in the figure, the device includes: a substrate; a buffer layer; a first semiconductor layer; a second semiconductor layer; a gate dielectric layer; a gate electrode; a source electrode; and a drain electrode. The device is a heterojunction field effect transistor, which is a unipolar device, and the reverse leakage current increases with the increase of reverse voltage, and the reverse voltage withstand capability is poor. Figure 1As shown, it comprises: a source electrode; a substrate layer; a drift region; a drain electrode; a gate electrode; a P-type NiO layer is arranged at both ends of the drift region to form a hetero-PN junction with the N-type Ga2O3 drift layer. The device mainly realizes the control of the vertical channel of the gallium oxide transistor through the hetero-PN junction, thereby realizing the switching characteristics of the transistor. However, since the channel layer is usually wide and parallel to the direction of the reverse electric field, it is difficult to realize the enhancement type device and the higher power optimization value.

[0005] The patent with the application number 202410483432.6 discloses "a fin-type gate wide band gap and super wide band gap MOSFET device integrated with a heterojunction diode". The device comprises: a substrate, an N-type voltage-resistant layer, a P-type semiconductor region, a gate conductor, a dielectric layer, an N-type semiconductor region, an isolation dielectric layer, an ohmic contact metal, and a drain ohmic contact metal. The device is a recessed gate FinFET structure, and the recessed gate can effectively reduce the on-resistance of the device. However, the etching groove introduces a large amount of interface damage, increases the reverse leakage current of the device, and narrows the safe operating area SOA. The device only has a diode part of a heterostructure, and it is also difficult to realize an enhancement type device.

[0006] In addition, although the devices proposed in the above comparative documents adopt a hetero-PN junction structure, they are all unipolar devices in terms of working principle, and it is difficult to realize an enhancement type working mode, which leads to complex back-end circuit design and poor safety performance. SUMMARY

[0007] The purpose of the present application is to overcome the shortcomings of the prior art, and to provide a double-heterojunction enhancement type planar gate vertical bipolar transistor based on NiO x / Ga2O3 and a preparation method thereof, so as to widen the safe operating area of the transistor through the planar gate structure, improve the reverse voltage resistance of the device, and realize the enhancement type working mode of the device through the double-heterojunction.

[0008] The technical solutions for achieving the purpose of the present application include the following:

[0009] 1. A double-heterojunction enhancement type planar gate vertical bipolar transistor based on NiO x / Ga2O3, comprising a substrate 1, a drift region 2, a current blocking layer 3, an ohmic contact layer 4, a p-type conductive layer 5, a drain electrode 6, a source electrode 7, and a gate electrode 8, characterized in that:

[0010] The current blocking layer 3 is made of high-resistivity Ga2O3 material and is distributed on the left and right sides above the drift region 2 to block the flow of current and control the flow path of the current;

[0011] The ohmic contact layer 4 is made of regrown high-doped n-type Ga2O3 material to form a good ohmic contact with the source electrode 7 and is located above the current blocking layers 3 distributed on the two sides;

[0012] The p-type conductive layer 5 is made of p-type conductive material, located above the middle of the drift region 2, and its left and right sides are in contact with the ohmic contact layers 4 on both sides to form the first hetero pn junction J1, and the bottom is in contact with the drift region to form the second hetero pn junction J2, to improve the reverse voltage capacity of the device, and control the flow of electrons from the source electrode to the drain electrode through the two hetero pn junctions, to realize the enhancement mode of the device.

[0013] The gate electrode 8 is located above the p-type conductive layer 5, forming a planar gate structure directly controlling the conduction of the p-type conductive layer from above, to increase the safe working area and simplify the device preparation process.

[0014] Further, the two source electrodes 7 are respectively located above the ohmic contact layers 4 on both sides, the gate electrode 8 is located above the p-type conductive layer 5, and the drain electrode 6 is located below the substrate 1.

[0015] Further, the substrate 1 is made of highly doped n-type Ga2O3 material to reduce the on-resistance of the device and serve as a support for the device, with a thickness T sub ≥300um, and a doping concentration N d,sub : 1×10 17 ≤N d,sub ≤1×10 20 cm -3 ; the drift region 2 is made of low-doped n-type Ga2O3 material for connecting the current blocking layer 3 and the p-type conductive layer 5, with a thickness T drift : 1≤T sub ≤30000nm, and a doping concentration N d,drift : 1×10 15 ≤N d,drift ≤1×10 17 cm -3 .

[0016] Further, the current blocking layer 3 has a thickness T block : 1≤T block ≤1000nm, and a resistivity p block : p block ≥1×10 3 Ω·cm; the ohmic contact layer 4 has a thickness T ohmic : 1≤T ohmic ≤2000nm, and a doping concentration N d,ohmic : N d,ohmic ≥1×10 16 cm -3 ; the p-type conductive layer 5 has a thickness T pNiO : 1≤T pNiO ≤2000nm, and a doping concentration N d,pNiO : Nd,pNiO ≥1×10 17 cm -3 .

[0017] 2. A method for preparing a NiO x / Ga2O3 double heterojunction enhancement mode planar gate vertical bipolar transistor, comprising the following steps:

[0018] 1) Selecting a sample of Ga2O3 drift region 2 epitaxially grown on Ga2O3 substrate 1, and sequentially placing it in acetone, isopropanol, and deionized water for ultrasonic cleaning;

[0019] 2) Transferring the sample to a photoetching operation table, photoetching a current blocking layer 3 region on the drift region 2, and then placing it in a reaction chamber of an ion implanter for ion implantation to form the current blocking layer 3;

[0020] 3) Placing the sample after ion implantation in a reaction chamber of a metal organic chemical vapor deposition system, regrowing an n-type Ga2O3 ohmic contact layer with a doping concentration not less than 1×10 16 cm -3 on the surface of the sample, and removing the regrown Ga2O3 above the photoresist through a stripping process to form an ohmic contact layer 4 aligned with the current blocking layer;

[0021] 4) Transferring the sample to a photoetching operation table, photoetching a p-type conductive layer 5 region on the surface of the sample, depositing a p-type NiO 17 with a doping concentration not less than 1×10 -3 cm x using a magnetron sputtering technology, and removing the NiO x above the photoresist through a stripping process to form the p-type conductive layer 5;

[0022] 5) Placing the sample in a rapid thermal annealing furnace for rapid thermal annealing treatment of the sample to enhance the blocking ability of the current blocking layer and improve the material quality of the regrown n-type Ga2O3 ohmic contact layer and the p-type NiO x conducting layer;

[0023] 6) Placing the sample with the back side facing up in a reaction chamber of an electron beam evaporation deposition system, depositing a drain electrode metal on the back side of the substrate 1 using electron beam evaporation technology, transferring the sample to a photoetching operation table to photoetch a source electrode region in the region of the ohmic contact layer 4, and again transferring the sample to the reaction chamber of the electron beam evaporation deposition system to deposit a source electrode metal on the front side of the sample using electron beam evaporation technology, and removing the source electrode metal above the photoresist using a stripping process;

[0024] 7) Place the sample in a rapid thermal annealing furnace and perform rapid thermal annealing to achieve ohmic contact between the drain electrode and the source electrode, reduce the ohmic contact resistance, and form the drain electrode 6 and the source electrode 7.

[0025] 8) Transfer the sample to the photolithography stage and perform the photolithography on p-type NiO. x The gate electrode 8 region is photolithographically etched above the conductive layer. A layer of gate electrode metal is deposited on the sample surface using electron beam evaporation technology. Then, the gate electrode metal above the photoresist is removed using a lift-off process, and the gate electrode 8 is formed above the p-type conductive layer, thus completing the device fabrication.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] First, the present invention uses a double heterojunction to control the on / off state of the device, which can intrinsically realize the enhancement-mode operation of the device and is not affected by the doping concentration of the material.

[0028] Secondly, the present invention uses a heterogeneous pn junction to bear the reverse voltage, which makes the heterogeneous second pn junction J2 perpendicular to the reverse electric field, significantly reducing the reverse leakage current of the device and improving the device's withstand voltage capability.

[0029] Third, the present invention adopts a planar gate structure, which can increase the safe operating area of ​​the device, avoid etching damage, and simplify the fabrication process.

[0030] Fourth, the present invention uses high-resistivity Ga2O3 as a current blocking layer, which can effectively suppress device leakage current and achieve a high switching ratio.

[0031] Fifth, the ohmic contact layer 4 of the present invention is made of regenerated highly doped n-type Ga2O3 material, which can form a good ohmic contact with the source electrode 7 and reduce the on-resistance of the device. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of an existing heterojunction field-effect transistor based on Ga2O3;

[0033] Figure 2 This is a schematic diagram of the structure of the device of the present invention;

[0034] Figure 3 This invention is prepared Figure 2 A schematic diagram of the device's manufacturing process. Detailed Implementation

[0035] To further illustrate the device structure described in this invention, the following description, in conjunction with the accompanying drawings and specific embodiments, explains the invention based on NiO. x The enhancement-mode planar gate vertical bipolar transistor of Ga2O3 double heterojunction is described in further detail.

[0036] Reference Figure 2The device structure of the present example comprises a substrate 1, a drift region 2, a current blocking layer 3, an ohmic contact layer 4, a p-type conductive layer 5, a drain electrode 6, a source electrode 7 and a gate electrode 8. Among them:

[0037] The substrate 1 is n-type high-doped Ga2O3, with a thickness T sub ≥300um, a doping concentration N d,sub : 1×10 17 ≤N d,sub ≤1×10 20 cm -3 , as a supporting substrate of the device, to reduce the on-resistance.

[0038] The drift region 2 is n-type low-doped Ga2O3, located above the n-type high-doped Ga2O3 substrate 1, with a thickness T drift 1≤T sub ≤30000nm, a doping concentration N d,drift 1×10 15 ≤N d,drift ≤1×10 17 cm -3 , as the main voltage resistance area of the device, to improve the voltage resistance capability of the device.

[0039] The current blocking layer 3 is high-resistivity Ga2O3, located on the left and right sides of the drift region 2, with a thickness T block 1≤T block ≤1000nm, a resistivity p block p block ≥1×10 3 Ω·cm, to block the flow of current and control the flow path of current.

[0040] The ohmic contact layer 4 is n-type high-doped Ga2O3, located above the current blocking layer 3, with a thickness T ohmic 1≤T ohmic ≤2000nm, a doping concentration N d,ohmic N d,ohmic ≥1×10 16 cm -3 , to form a good ohmic contact with the source electrode 7 and reduce the on-resistance.

[0041] The p-type conductive layer 5 is p-type NiO x , located above the drift region 2, with a thickness T pNiO 1≤T pNiO ≤2000nm, a doping concentration N d,pNiO N d,pNiO ≥1×10 17 cm -3The left and right sides of the current blocking layer form a first hetero pn junction J1 with the ohmic contact layer 4, which is used for controlling the conduction of the device; and the lower side of the current blocking layer forms a second hetero pn junction J2 with the drift region 2, which is used for improving the voltage resistance of the device.

[0042] The drain electrode 6 is an ohmic electrode, which is located on the back of the substrate 1, and the metal used in the drain electrode 6 is any one or a combination of any several of Ti, Al, Ni, Au, W, Cr, Ta, Mo, TiC, TiN and TiW.

[0043] The source electrode 7 is an ohmic electrode, which is located above the ohmic contact layer 4, and the metal used in the source electrode 7 is any one or a combination of any several of Ti, Al, Ni, Au, W, Cr, Ta, Mo, TiC, TiN and TiW.

[0044] The gate electrode 8 is an ohmic electrode, which is located above the p-type conductive layer 5 and forms a positive gate structure to directly control the conduction of the p-type conductive layer from above, so as to increase the safe working area range and simplify the device preparation process. The metal used in the gate electrode 8 is any one or a combination of any several of Ni, Au, Pt, Cr, Ta, Mo, TiC, TiN and TiW.

[0045] Referring to Figure 3 , the present application provides three embodiments of the preparation of the enhancement mode planar gate vertical bipolar transistor based on the NiO x / Ga2O3 double heterojunction.

[0046] Embodiment one, the current blocking layer is prepared by ion implantation N, the doping concentration of the ohmic contact layer is 1×10 17 cm -3 , the doping concentration of the p-type conductive layer is 1×10 19 cm -3 , and the thickness of the p-type conductive layer and the ohmic contact layer is 500nm. x The enhancement mode planar gate vertical bipolar transistor based on the NiO

[0047] Step 1, select a sample and clean it, for example Figure 3 a.

[0048] Select an n-type Ga2O3 epitaxial wafer 1 with a thickness of 500μm and a doping concentration of 3×10 18 cm -3 , and an n-type Ga2O3 drift region with a thickness of 10um and a doping concentration of 1×10 16 cm -3 .

[0049] The selected Ga2O3 epitaxial wafer 1 is sequentially placed in acetone, isopropyl alcohol and deionized water for ultrasonic cleaning for 5 minutes,

[0050] The Ga2O3 epitaxial wafer 1 was cleaned with deionized water and dried with nitrogen.

[0051] Step 2: N-ion implantation is performed on epitaxial wafer 1 to form current blocking layer 3.

[0052] The cleaned Ga2O3 sample was subjected to photolithography to expose the ion implantation region, such as... Figure 3 b. Set the parameters for the four N-ion implantations as follows:

[0053] First attempt: Ion incident angle 7 degrees, ion implantation energy 300 keV, ion implantation dose 2.5 × 10⁻⁶. 13 cm -2 ,

[0054] Second time: Ion incident angle was 7 degrees, ion implantation energy was 160 keV, and ion implantation dose was 1.5 × 10⁻⁶. 13 cm -2 ,

[0055] Third time: Ion incident angle was 7 degrees, ion implantation energy was 80 keV, and ion implantation dose was 9 × 10⁻⁶. 12 cm -2 ,

[0056] Fourth time: Ion incident angle is 7 degrees, ion implantation energy is 30 keV, and ion implantation dose is 4 × 10⁻⁶. 12 cm -2 ;

[0057] A current-blocking layer 3 with a depth of 500 nm was formed on both sides above the drift region 2 using ion implantation technology, such as... Figure 3 c.

[0058] Step 3: MOCVD growth of Ga2O3 to prepare ohmic contact layer 4, as shown. Figure 3 d.

[0059] The process conditions were set as follows: reaction chamber temperature 900℃, Ga source flow rate 160 μmol / min, doped Si source flow rate 5 μmol / min, and O source flow rate 300 sccm. A doping concentration of 1×10⁻⁶ was deposited on the current blocking layer 3 using metal-organic chemical vapor deposition (MOCVD). 17 cm -3 A 500nm thick Ga2O3 layer is formed by removing excess Ga2O3 from other parts through a stripping process to create an ohmic contact layer 4.

[0060] Step 4, magnetron sputtering of NiO x 5. Prepare a p-type conductive layer.

[0061] The cleaned Ga2O3 sample was subjected to photolithography to expose the p-type conductive layer region 5, such as... Figure 3 e;

[0062] The process conditions were set as follows: magnetron sputtering power of 50W, reaction chamber temperature of 25℃, Ar flow rate of 140 sccm, and O2 flow rate of 20 sccm. A hole concentration of 1×10⁻⁶ was deposited in the drift region using magnetron sputtering technology. 19 cm -3 p-type NiO with a thickness of 500 nm x The excess NiO is removed through a stripping process. x Forming a p-type conductive layer 5, such as Figure 3 f.

[0063] Step 5: Rapid annealing improves the quality of the current blocking layer 3, the ohmic contact layer 4, and the p-type conductive layer 5.

[0064] The process conditions were set as follows: annealing atmosphere of O2, annealing temperature of 800℃, and annealing time of 30min. The sample was annealed using rapid thermal annealing technology to improve the current blocking ability of the current blocking layer 3 and improve the crystal quality of the ohmic contact layer 4 and the p-type conductive layer 5.

[0065] Step 6: Electron beam evaporation is used to prepare the drain electrode 6, as shown in the figure. Figure 3 g.

[0066] The high voltage is set to 7.5kV, the Ti / Au current to 80 / 150mA, and the pressure to 1×10⁻⁶. -5 The Torr process utilizes electron beam evaporation to sequentially deposit a 60 nm thick Ti metal and a 150 nm thick Au metal on the back side of a gallium oxide substrate to form a drain electrode 6.

[0067] Step 7: Electron beam evaporation is used to prepare the source electrode 7, as shown in the figure. Figure 3 i.

[0068] Photolithography was performed on the Ga2O3 sample to expose the source electrode region, such as... Figure 3 h, set the high voltage to 7.5kV, the Ti / Au current to 80 / 150mA, and the pressure to 1×10 -5 The Torr process involves sequentially depositing a 60 nm thick Ti metal and a 150 nm thick Au metal on the gallium oxide surface using electron beam evaporation. Excess Ti / Au is removed by a stripping process to form the source electrode 7.

[0069] Step 8: Rapid annealing improves the ohmic contact quality between the drain electrode 6 and the source electrode 7.

[0070] The process conditions were set as follows: annealing atmosphere of N2, annealing temperature of 450℃, and annealing time of 1 min. The sample was annealed using rapid thermal annealing technology to improve the ohmic contact quality between the drain electrode 6 and the Ga2O3 substrate and the source electrode 7 and the ohmic contact layer.

[0071] Step 9: Electron beam evaporation is used to prepare the gate electrode 8.

[0072] Photolithography was performed on the Ga2O3 sample to expose the gate electrode region, such as... Figure 3 j;

[0073] The high voltage is set to 7.5kV, the Ni / Au current to 100 / 150mA, and the pressure to 1×10⁻⁶. -5 The Torr process involves sequentially depositing a 50nm thick layer of Ni and a 150nm thick layer of Au on the gallium oxide surface using electron beam evaporation. Excess Ni / Au is then removed via a lift-off process to form the gate electrode 8, completing the device fabrication. Figure 3 k.

[0074] Example 2: The current blocking layer was prepared by ion-implanted Mg, and the ohmic contact layer was doped with a concentration of 1×10⁻⁶. 18 cm -3 The doping concentration of the p-type conductive layer is 1×10⁻⁶. 20 cm -3 Both the p-type conductive layer and the ohmic contact layer are 700 nm thick NiO x / Ga2O3 double heterojunction enhancement-mode planar gate vertical bipolar transistor.

[0075] Step 1: Select a sample and clean it.

[0076] The n-type Ga2O3 substrate was selected with a thickness of 650 μm and a doping concentration of 1 × 10⁻⁶ μm. 18 cm -3 The n-type Ga2O3 drift region has a thickness of 20 μm and a doping concentration of 1 × 10⁻⁶. 16 cm -3 n-type Ga2O3 epitaxial wafer 2;

[0077] The selected Ga2O3 epitaxial wafer 2 was sequentially immersed in acetone, isopropanol, and deionized water for ultrasonic cleaning for 5 minutes each.

[0078] Clean the Ga2O3 epitaxial wafer 2 with deionized water and dry it with nitrogen gas.

[0079] Step 2: Mg ion implantation is performed on epitaxial wafer 2 to form current blocking layer 3, such as... Figure 3 b and Figure 3 c.

[0080] 2,1) Photolithography was performed on the Ga2O3 sample to expose the current blocking layer region.

[0081] 2.2) The sample was placed in the ion implanter chamber, and under the following Mg ion implantation process conditions, ion implantation was performed on both sides above the drift region to prepare a current blocking layer 3 with a depth of 500 nm, namely:

[0082] First attempt: Ion incident angle 7 degrees, ion implantation energy 380 keV, ion implantation dose 3 × 10⁻⁶. 13 cm -2 ,

[0083] Second time: Ion incident angle was 7 degrees, ion implantation energy was 200 keV, and ion implantation dose was 1.5 × 10⁻⁶. 13 cm -2 ,

[0084] Third time: Ion incident angle was 7 degrees, ion implantation energy was 130 keV, and ion implantation dose was 7 × 10⁻⁶. 12 cm -2 ,

[0085] Fourth time: Ion incident angle is 7 degrees, ion implantation energy is 40 keV, and ion implantation dose is 3 × 10⁻⁶. 12 cm -2 ,

[0086] Step 3: An ohmic contact layer 4 is prepared by growing Ga2O3 on the current blocking layer, as shown below. Figure 3 d.

[0087] Using metal-organic chemical vapor deposition (MOCVD), a layer with a doping concentration of 1×10⁻⁶ was deposited on the sample surface under the following conditions: reaction chamber temperature of 900℃, Ga source flow rate of 150 μmol / min, Si source flow rate of 50 μmol / min, and O source flow rate of 300 sccm. 18 cm -3 A 700nm thick Ga2O3 layer was formed by removing excess Ga2O3 from other parts through a stripping process to create an ohmic contact layer 4.

[0088] Step four, prepare p-type conductive layer 5, such as Figure 3 e and Figure 3 f.

[0089] 4.1) Photolithography was performed on the cleaned Ga2O3 sample to expose the p-type conductive layer region;

[0090] 4.2) Using magnetron sputtering technology, under the process conditions of magnetron sputtering power of 30W, reaction chamber temperature of 25℃, Ar flow rate of 90sccm, and O2 flow rate of 30sccm, a hole concentration of 1×10⁻⁶ was deposited on the sample surface. 20 cm -3 p-type NiO with a thickness of 700 nm x Then, excess NiO from other parts is removed through a stripping process. x A p-type conductive layer 5 is formed.

[0091] Step 5: Rapid annealing improves the quality of the current blocking layer 3, ohmic contact layer 4, and p-type conductive layer 5.

[0092] Rapid thermal annealing technology was used to anneal the sample under the process conditions of O2 annealing atmosphere, 800℃ annealing temperature and 60min annealing time, so as to improve the current blocking ability of the current blocking layer 3 and improve the crystal quality of the ohmic contact layer 4 and the p-type conductive layer 5.

[0093] Step six: Electron beam evaporation is used to prepare the drain electrode 6, as shown below. Figure 3 g.

[0094] Electron beam evaporation technology was used to deposit Ti / Au at a high voltage of 7.5kV, a current of 80 / 150mA, and a pressure of 1×10⁻⁶ kJ / m³. -5 Under Torr's process conditions, a 60 nm thick Ti metal and a 150 nm thick Au metal are sequentially deposited on the back side of a gallium oxide substrate to form a drain electrode 6.

[0095] Step 7: Electron beam evaporation is used to prepare the source electrode 7, as shown in the figure. Figure 3 h and Figure 3 i.

[0096] 7.1) Photolithography was performed on the Ga2O3 sample to expose the source electrode region;

[0097] 7.2) Using electron beam evaporation technology, at a high voltage of 7.5kV, a Ti / Au current of 80 / 150mA, and a pressure of 1×10⁻⁶ kJ / m³, the electron beam evaporation was carried out. - 5 Under Torr's process conditions, a 60 nm thick layer of metallic Ti and a 150 nm thick layer of metallic Au are sequentially deposited on the gallium oxide surface, and excess Ti / Au is removed by a stripping process to form the source electrode 7.

[0098] Step 8: Rapid annealing improves the ohmic contact quality between drain electrode 6 and source electrode 7.

[0099] The sample is annealed under the process conditions of N2annealing atmosphere, 450°C annealing temperature, and 1 min annealing time by using the rapid thermal annealing technology to improve the ohmic contact quality between the drain electrode 6 and the Ga2O3 substrate and the ohmic contact quality between the source electrode 7 and the ohmic contact layer.

[0100] Step nine, the gate electrode 8 is prepared by electron beam evaporation. Figure 3 j and Figure 3 k.

[0101] 9.1) The Ga2O3 sample is subjected to photoetching to expose the gate electrode area.

[0102] 9.2) The gate electrode 8 is formed by sequentially depositing 50 nm thick metal Ni and 150 nm thick metal Au on the gallium oxide surface under the process conditions of 7.5 kV high voltage, 100 / 150 mA Ni / Au current, and 1x10 -5 Torr pressure by using the electron beam evaporation technology, and then removing the excess Ni / Au in other parts by the stripping process, thereby completing the device preparation.

[0103] Example three, the current blocking layer is prepared by ion implantation of N and P, the ohmic contact layer has a doping concentration of 1x10 18 cm -3 , the p-type conductive layer has a doping concentration of 5x10 19 cm -3 , and the p-type conductive layer and the ohmic contact layer each have a thickness of 300 nm, thereby preparing a NiO x / Ga2O3 double heterojunction enhanced planar gate vertical bipolar transistor.

[0104] Step A, a substrate is selected and cleaned.

[0105] An n-type Ga2O3 epitaxial wafer 3 having a thickness of 300 μm and a doping concentration of 2x10 18 cm -3 , an n-type Ga2O3 drift region having a thickness of 15 μm and a doping concentration of 1x10 16 cm -3 is selected; the selected Ga2O3 epitaxial wafer 3 is sequentially subjected to ultrasonic cleaning in acetone, isopropyl alcohol, and deionized water for 5 minutes, and then cleaned with deionized water and dried with nitrogen.

[0106] Step B, N and P ion implantation is performed on the epitaxial wafer 2 to form a current blocking layer 3, as Figure 3 b and Figure 3 c.

[0107] The Ga2O3 sample is subjected to photoetching to expose the current blocking layer region, and the sample is placed in an ion implanter chamber to perform four times of N and P ion implantation on the two side regions above the drift region in sequence to form a current blocking layer 3 with a depth of 500 nm, and the ion implantation conditions are as follows:

[0108] First time: the incident angle of N ions is 7 degrees, the ion implantation energy is 300 keV, and the ion implantation dose is 2.5 x 1016 cm-2; 13 -2 The incident angle of P ions is 7 degrees, the ion implantation energy is 580 keV, and the ion implantation dose is 3 x 1016 cm-2; 13 -2 ;

[0109] Second time: the incident angle of N ions is 7 degrees, the ion implantation energy is 160 keV, and the ion implantation dose is 1.5 x 1016 cm-2; 13 -2 The incident angle of P ions is 7 degrees, the ion implantation energy is 325 keV, and the ion implantation dose is 1.5 x 1016 cm-2; 13 -2 ;

[0110] Third time: the incident angle of N ions is 7 degrees, the ion implantation energy is 80 keV, and the ion implantation dose is 9 x 1016 cm-2; 12 -2 The incident angle of P ions is 7 degrees, the ion implantation energy is 150 keV, and the ion implantation dose is 8 x 1016 cm-2; 12 -2 ;

[0111] Fourth time: the incident angle of N ions is 7 degrees, the ion implantation energy is 30 keV, and the ion implantation dose is 4 x 1016 cm-2; 12 -2 The incident angle of P ions is 7 degrees, the ion implantation energy is 50 keV, and the ion implantation dose is 4 x 1016 cm-2; 12 -2 .

[0112] Step C, growing Ga2O3 on the current blocking layer 3 to prepare an ohmic contact layer 4, such as Figure 3 d.

[0113] A layer of metal organic chemical vapor deposition technology is used to deposit a layer of Ga2O3 on the surface of the sample, and the doping concentration is 1 x 1018 cm-3. 18 -3 ​​​​​​​​​A 300nm thick Ga2O3 layer was stripped to remove excess Ga2O3 from other parts to form an ohmic contact layer 4. The process conditions were: reaction chamber temperature of 900℃, Ga source flow rate of 150μmol / min, Si source flow rate of doped atoms of 50μmol / min, and O source flow rate of 300sccm.

[0114] Step D, prepare p-type conductive layer 5, such as Figure 3 e and Figure 3 f.

[0115] The cleaned Ga2O3 sample was subjected to photolithography to expose the p-type conductive layer region. Then, using magnetron sputtering, a hole concentration of 5 × 10⁻⁶ was deposited on the sample surface. 19 cm -3 p-type NiO with a thickness of 300 nm x Then, excess NiO from other parts is removed through a stripping process. x A p-type conductive layer 5 is formed under the following process conditions: magnetron sputtering power of 30W, reaction chamber temperature of 25℃, Ar flow rate of 90sccm, and O2 flow rate of 30sccm.

[0116] Step E, rapid annealing improves the quality of the current blocking layer 3, the ohmic contact layer 4, and the p-type conductive layer 5.

[0117] The sample was annealed using rapid thermal annealing technology to improve the current blocking ability of the current blocking layer 3 and the crystal quality of the ohmic contact layer 4 and the p-type conductive layer 5. The annealing conditions were: annealing atmosphere of N2, annealing temperature of 900℃, and annealing time of 30min.

[0118] Step F: Electron beam evaporation is used to prepare the drain electrode 6, as shown in the figure. Figure 3 g.

[0119] Electron beam evaporation was used to sequentially deposit a 60 nm thick Ti layer and a 150 nm thick Au layer on the back side of a gallium oxide substrate to form the drain electrode 6. The electron beam evaporation process conditions were: high voltage of 7.5 kV, Ti / Au current of 80 / 150 mA, and pressure of 1 × 10⁻⁶ kJ / m³. -5 Torr.

[0120] Step G: Electron beam evaporation is used to prepare the source electrode 7, as shown in the example. Figure 3 h and Figure 3 i.

[0121] The Ga2O3 sample is photoetched to expose the source electrode area, and then metal Ti with a thickness of 60 nm and metal Au with a thickness of 150 nm are deposited on the gallium oxide surface in sequence by using electron beam evaporation technology; then the other part of the excess Ti / Au is removed by a stripping process to form the source electrode 7, and the process conditions of the electron beam evaporation are as follows: high voltage is 7.5 kV, Ti / Au current is 80 / 150 mA, and pressure is 1x10 -5 Torr.

[0122] Step H: rapid annealing to improve the ohmic contact quality of the drain electrode 6 and the source electrode 7.

[0123] The sample is annealed by using rapid thermal annealing technology to improve the ohmic contact quality of the drain electrode 6 and the source electrode 7, and the annealing conditions are as follows: annealing atmosphere is N2, annealing temperature is 450℃, and annealing time is 1 min.

[0124] Step I: electron beam evaporation to prepare the gate electrode 8, such as Figure 3 j and Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure k.

[0125] The Ga2O3 sample is photoetched to expose the gate electrode area, and then metal Ni with a thickness of 50 nm and metal Au with a thickness of 150 nm are deposited on the gallium oxide surface in sequence by using electron beam evaporation technology, and the process conditions are as follows: high voltage is 7.5 kV, Ni / Au current is 100 / 150 mA, and pressure is 1x10 -5 Torr;

[0126] Then, the other part of the excess Ni / Au is removed by a stripping process to form the gate electrode 8, and the device preparation is completed,

[0127] The above description is only three specific examples of the present application, and does not constitute any limitation on the present application. Obviously, for those skilled in the art, after understanding the content and principles of the present application, various modifications and changes in form and details can be made without departing from the principles and structures of the present application. For example, the gate electrode can be made of any one or a combination of Ni, Au, W, Cr, Ta, Mo, Pt, TiC, TiN and TiW, and the source electrode and the drain electrode can be made of Au, W, Cr, Ta, Mo, TiC, TiN, TiW or a combination of two or more thereof. However, the modifications and changes of the basic inventive idea are still within the protection scope of the claims of the present application.

Claims

1. A double heterojunction enhancement mode planar gate vertical bipolar transistor based on NiO x / Ga2O3 comprising a substrate (1), a drift region (2), a current blocking layer (3), an ohmic contact layer (4), a p-type conducting layer (5), a drain electrode (6), a source electrode (7) and a gate electrode (8) characterized in that: The current blocking layer (3) is made of high-resistivity Ga2O3 material, which is distributed on the left and right sides above the drift region (2) to block the flow of current and control the flow path of current. The ohmic contact layer (4) is made of highly doped n-type Ga2O3 material to form good ohmic contact with the source electrode (7), which is located above the current blocking layer (3) distributed on both sides. The p-type conductive layer (5) is made of p-type conductive material, which is located above the middle of the drift region (2) and contacts the ohmic contact layer (4) distributed on both sides to form the first heterojunction pn junction J1, and contacts the drift region below to form the second heterojunction pn junction J2, to improve the reverse voltage withstand capability of the device and control the flow of electrons from the source electrode to the drain electrode through the two heterojunction pn junctions, realizing the enhancement mode working state of the device. The gate electrode (8) is located above the p-type conductive layer (5) to form a planar gate structure that directly controls the conduction of the p-type conductive layer from above, to increase the safe operating area and simplify the device preparation process.

2. The transistor of claim 1, wherein: Two source electrodes (7) are located above the ohmic contact layer (4) on both sides, the gate electrode (8) is located above the p-type conductive layer (5), and the drain electrode (6) is located below the substrate (1).

3. The transistor of claim 1, wherein: The substrate (1) adopts a highly doped n-type Ga2O3 material to reduce the on-resistance of the device and support the device, and the thickness T sub ≥ 300 um, the doping concentration N d,sub is: 1×10 17 ≤ N d,sub ≤ 1×10 20 cm -3 -3 The drift region (2) is made of a low-doped n-type Ga2O3 material for connecting the current blocking layer (3) and the p-type conductive layer (5), and the thickness T drift is: 1≤T sub ≤30000nm, the doping concentration N d,drift is: 1×10 15 ≤N d,drift ≤1×10 17 cm -3 .

4. The transistor of claim 1, wherein: The current blocking layer (3) has a thickness T block of 1 ≤ T block ≤ 1000 nm and an electrical resistivity p block of p block ≥ 1 × 10 3 Ω·cm; The ohmic contact layer (4) has a thickness T ohmic of: 1 ≤ T ohmic ≤ 2000 nm, a doping concentration N d,ohmic of: N d,ohmic ≥ 1 x 10 16 cm -3 -3 The p-type conductive layer (5) has a thickness T pNiO of 1 ≤ T pNiO ≤ 2000 nm, a doping concentration N d, pNiO of N d, pNiO ≥ 1 × 10 17 cm -3 -3.

5. The transistor of claim 1, wherein: The current blocking layer (3) is made of high-resistivity Ga2O3 material, which is injected with ions of any one or combination of N, P, Mg, B, Al, Zn, Se, Fe, Cu, As, Sb, Be, Ca, Sr, Ba.

6. The transistor of claim 1, wherein: The drain electrode (6) is made of any one or combination of Ti, Al, Ni, Au, W, Cr, Ta, Mo, Pt, TiC, TiN, TiW; The source electrode (7) is made of any one or combination of Ti, Al, Ni, Au, W, Cr, Ta, Mo, Pt, TiC, TiN, TiW; The gate electrode (8) is made of any one or combination of Ni, Au, Ti, Al, W, Cr, Ta, Mo, TiC, TiN, TiW.

7. A method of fabricating a NiO x / Ga2O3 double heterojunction enhancement mode planar gate vertical bipolar transistor, characterized by, The method comprises the following steps: 1) Select a sample of Ga2O3 drift region (2) epitaxially grown on Ga2O3 substrate (1), and sequentially place it in acetone, isopropyl alcohol, and deionized water for ultrasonic cleaning; 2) Transfer the sample to a photolithography operation table, and photolithograph the current blocking layer (3) region on the drift region (2), then place it in the reaction chamber of an ion implanter for ion implantation to form the current blocking layer (3); 3) The sample after ion implantation is placed in the reaction chamber of a metal organic chemical vapor deposition system, and a n-type Ga2O3 ohmic contact layer with a doping concentration not less than 1×1018cm-3 is regrown on the surface of the sample, and then the regrown Ga2O3 above the photoresist is removed by a stripping process to form an ohmic contact layer (4) aligned with the current blocking layer. 16 cm -3 -3); 4) Transfer the sample to the photolithography stage and photolithographically print a p-type conductive layer (5) on the sample surface. Then, deposit a layer with a doping concentration of not less than 1×10⁻⁶ using magnetron sputtering. 17 cm -3 p-type NiO x Then, the NiO on top of the photoresist is removed through a stripping process. x , forming a p-type conductive layer (5); 5) Put the sample into a rapid thermal annealing furnace, and perform rapid thermal annealing treatment on the sample to enhance the blocking ability of the current blocking layer and improve the regrown n-type Ga2O3 ohmic contact layer and p-type NiO x material quality of the conductive layer; 6) Place the sample with the back side facing up in the reaction chamber of an electron beam evaporation deposition system, and use electron beam evaporation technology to deposit a drain electrode metal on the back side of the substrate (1), then transfer the sample to a photolithography operation table to photolithograph the source electrode region in the ohmic contact layer (4) region; The sample is transferred again into the reaction chamber of the electron beam evaporation deposition system, and the source electrode metal is deposited on the front side of the sample by using the electron beam evaporation technology, and the source electrode metal above the photoresist is removed by using the stripping process; 7) The sample is placed in a rapid thermal annealing furnace for rapid thermal annealing treatment, to realize ohmic contact of the drain electrode and the source electrode, reduce the ohmic contact resistance, form the drain electrode (6) and the source electrode (7); 8) Transfer the sample to the photoetching operation table, photoetch the gate electrode (8) area on the p-type NiO x Conductive layer, use electron beam evaporation technology to deposit a layer of gate electrode metal on the surface of the sample, and then use the stripping process to remove the gate electrode metal above the photoresist to form a gate electrode (8) on the p-type conductive layer, completing device fabrication.

8. The method of claim 7, wherein: The ion implantation process has the following condition parameters: implantation times 0-20, single implantation dose 0-1×10 14 cm -2 , single implantation energy 0-500keV, and implantation angle 0-90 degrees each time. The condition parameters of the metal organic chemical vapor deposition process are as follows: the flow rate of the Ga source is 0-300 sccm, the flow rate of the O source is 0-300 sccm, the doping impurity is any one or any combination of Si, Ge, and Sn, the impurity flow rate is 0-300 sccm, and the reflection chamber pressure is 0-200 mTorr.

9. The method of claim 7, wherein: The condition parameters of the magnetron sputtering process are as follows: the magnetron sputtering power is 10-300 W, the magnetron sputtering temperature is 0-200°C, the Ar flow rate is 0-300 sccm, and the O2 flow rate is 0-300 sccm; The condition parameters of the electron beam evaporation process are: electron gun voltage 5000-13000V, current intensity 30-200mA, deposition chamber pressure 1x10 -7 -1x10 -5 Torr, deposition rate 0.1-5A / s.

10. The method of claim 7, wherein: The rapid thermal annealing processes in steps 5) and 7) are realized by a rapid annealing furnace, and the process parameters are as follows: The condition parameters of step 5) are as follows: the annealing temperature is 600-1200°C, the annealing atmosphere is N2, O2, or vacuum, and the annealing time is 20-120 minutes; The condition parameters of step 7) are as follows: the annealing temperature is 300-600°C, the annealing atmosphere is N2, and the annealing time is 30-180 seconds.

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