Asymmetric super junction MOSFET structure and manufacturing method thereof

Abstract

An asymmetric super junction MOSFET structure and a manufacturing method thereof, belonging to the field of semiconductor technology, a super junction MOSFET structure, including a substrate and a cell structure; the cell structure includes: a first column region, including an N-type drift region; a second column region, arranged in the first column region, including a column region structure and a gate structure arranged on the column region structure; a third column region, including a side wall P column region, the side wall P column region is an ion implanted P column region, and the side wall P column region is charge balanced with the adjacent N-type drift region; the third column region is arranged between the second column region and the first column region, and the third column region is arranged on one side of the second column region. The present application uses a side wall P column region implanted with deep trench ions, so that the charge balance control between the side wall P column region and the corresponding N-type drift region is more accurate; at the same time, because the PN junction position of the super junction is far away from the etching interface, the electric field at the defect interface is reduced, the reliability of the product is improved, and multiple epitaxy is avoided, which helps to save the manufacturing cost of the super junction MOSFET.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to an asymmetric super junction MOSFET structure and a manufacturing method thereof. Background Art

[0002] Super Junction MOSFET is an advanced power semiconductor device based on charge balance technology. It optimizes the electric field distribution by introducing additional charges between the N-type and P-type regions, thereby reducing the on-resistance and parasitic capacitance.

[0003] In terms of process technology, a super junction can be formed by trench or multiple epitaxial processes. For example, Chinese patent publication number CN113488388A discloses a trench gate super junction VDMOSFET semiconductor device and a method for preparing the same, which includes the following steps: + Growing an N-type epitaxial layer on a substrate; forming a plurality of first trenches on the N-type epitaxial layer; growing a P-type epitaxial layer on the surface of the N-type epitaxial layer and in each of the first trenches; forming a plurality of second trenches on the P-type epitaxial layer; growing an n-type epitaxial layer in each of the second trenches; growing a P- epitaxial layer on the P-type epitaxial layer and the n-type epitaxial layer; forming a plurality of third trenches on the P- epitaxial layer; forming a gate oxide film on the sidewall and bottom of each of the third trenches; forming an n-type epitaxial layer on the surface of the P- epitaxial layer at the opening of the third trench; and forming a gate oxide film on the sidewall and bottom of each of the third trenches. + Source region; p is formed on the surface of P-epitaxial layer + implantation region; burying gate material in the third trench to form a gate; in the p + Injection region, n + A source is formed above the source region, and + The drain electrode is formed on the lower surface of the substrate. The limitation of the etching process and the epitaxial growth process for forming the groove is overcome by repeated epitaxial growth processes.

[0004] However, the super junction formed by multiple epitaxial processes is too complicated and costly, while the super junction formed by etching trenches has poor control over doping, and etching interface defects can easily affect the reliability of the device.

[0005] Therefore, there is an urgent need to develop an asymmetric super junction MOSFET structure and a manufacturing method thereof to solve the problems in the prior art. Summary of the invention

[0006] The purpose of the present invention is to provide an asymmetric super junction MOSFET structure and a manufacturing method thereof, which avoids forming a super junction through multiple epitaxial processes or forming a super junction through etching grooves through ion implantation of side wall P column areas, so as to solve the problem that the current super junction manufacturing process is too complicated or the doping control is poor.

[0007] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0008] An asymmetric super junction MOSFET structure includes a substrate and a cellular structure located on the substrate; the cellular structure includes:

[0009] A first column region, including an N-type drift region;

[0010] A second column region is disposed in the first column region, comprising a column region structure and a gate structure disposed on the column region structure;

[0011] The third column region includes a side wall P column region, wherein the side wall P column region is an ion implanted P column region, and the charge of the side wall P column region is balanced with that of the adjacent N-type drift region; the third column region is arranged between the second column region and the first column region, and the third column region is arranged on one side of the second column region.

[0012] Furthermore, the first column region also includes a sidewall P + area, the side wall P + The area is located on the sidewall P column area, and the sidewall P + The area is ion implanted P + Area; the side wall P + The inclination angle of the region during ion implantation is greater than the inclination angle of the side wall P column region during ion implantation; the side wall P + The depth of the region is not less than the depth of the gate structure.

[0013] Further, the column region structure includes a semiconductor column region or a dielectric column region;

[0014] When the column region structure is a semiconductor column region, the gate structure includes a gate oxide in contact with the semiconductor column region and a gate electrode in contact with the gate oxide; the gate oxide is in contact with the first column region;

[0015] When the column region structure is a dielectric column region, the gate structure includes a gate electrode in contact with the dielectric column region, and a dielectric column region is provided between the gate electrode and the first column region.

[0016] Furthermore, the semiconductor column region is an intrinsic semiconductor column region or a low-doped semiconductor column region; and the dielectric column region is an insulating dielectric column region.

[0017] Furthermore, the first column region also includes a P well region and an N + The N-type drift region is located on the substrate, the P-well region is located on the N-type drift region, and the N + A region is located on the P-well region;

[0018] Or the first column region also includes a current diffusion layer, a P well region and an N+ The N-type drift region is located on the substrate, the current diffusion layer is located on the N-type drift region, the P-well region is located on the current diffusion layer, and the N + The region is located on the P-well region.

[0019] Furthermore, it also includes an N-type drift layer, wherein the N-type drift layer is located on the substrate, and the first column region and the second column region are located on the N-type drift layer.

[0020] Furthermore, a bottom P column region is provided in the N-type drift layer, and the bottom P column region is provided on the top of the N-type drift layer, and the bottom P column region is an ion-implanted P column region; the inclination angle of the bottom P column region during ion injection is equal to the inclination angle of the side wall P column region during ion injection; the bottom P column region and the side wall P column region are formed during the same ion injection.

[0021] Furthermore, one of the cellular structures includes two of the first column regions and one of the second column regions, wherein the second column region is disposed between the two first column regions, and the second column region separates the two first column regions.

[0022] Furthermore, one of the cellular structures includes one first column region and one second column region, and the first column region surrounds the second column region.

[0023] A method for manufacturing an asymmetric super junction MOSFET structure comprises the following steps:

[0024] Constructing an initial MOSFET structure; wherein the initial MOSFET structure includes a substrate, an N-type drift region, a P-well region and an N + district;

[0025] A mask is constructed on the upper surface of the initial MOSFET structure and a deep trench is etched;

[0026] By performing a first ion implantation on one side of the deep trench, a sidewall P column region is constructed on one side of the N-type drift region; the sidewall P column region is charge balanced with the corresponding N-type drift region;

[0027] By performing a second ion implantation on one side of the deep trench, a sidewall P column region is constructed on the sidewall P column region. + district;

[0028] Remove the mask;

[0029] Filling the deep trenches to form pillar structures;

[0030] A gate structure is constructed on top of each stud structure.

[0031] Furthermore, the inclination angle during the first ion implantation is greater than the inclination angle during the second ion implantation; + The depth of the region is not less than the depth of the gate structure; at least three deep trenches are etched, and two deep trenches are located at the ends of both sides of the initial MOSFET structure.

[0032] Furthermore, the masks used in the first ion implantation and the second ion implantation are masks constructed on the upper surface of the initial MOSFET structure.

[0033] Furthermore, the filling of the deep trench to form a pillar region structure comprises the following steps:

[0034] Depositing dielectric in the deep trench to form a dielectric column region;

[0035] The construction of a gate structure on the top of each pillar region structure comprises the following steps:

[0036] Etching a gate trench on the top of each dielectric column region, wherein a dielectric column region is left between the etched gate trench and the first column region;

[0037] A gate electrode is filled in the gate trench.

[0038] Furthermore, the filling of the deep trench to form a pillar region structure comprises the following steps:

[0039] By using an epitaxial backfilling process, semiconductor pillar regions are formed in all deep trenches;

[0040] The construction of a gate structure on the top of each pillar region structure comprises the following steps:

[0041] Etching a gate trench on the top of the dielectric pillar region;

[0042] Depositing gate oxide in the gate trench and filling the gate electrode in the gate oxide;

[0043] Wherein, the gate oxide is in contact with the first column region.

[0044] Furthermore, when etching the deep trench, the depth of the etched deep trench is less than the height of the N-type drift region;

[0045] The shape of the deep groove includes a blind hole or a through groove;

[0046] The first ion implantation on one side of the deep trench comprises:

[0047] By performing a first ion implantation on one side of the deep trench, a sidewall P column region is constructed on one side of the N-type drift region, and a bottom P column region is constructed on the top of the N-type drift layer, wherein the bottom P column region is connected to the sidewall P column region.

[0048] The present invention has the following advantages: through the side wall P column region implanted by deep trench ions, the charge balance control between the side wall P column region and the corresponding N-type drift region can be made more accurate; at the same time, since the PN junction position of the super junction is far away from the etching interface, the electric field at the defective interface is reduced, the reliability of the product is improved, and multiple epitaxy is avoided, which helps to save the manufacturing cost of the super junction MOSFET.

[0049] At the same time, the vertical depth of the P-column area formed by the present application through ion implantation with an inclined angle in the deep groove is only related to the inclined angle of the ion implantation and the groove depth, so that the height of the P-column area formed in this way is no longer limited by the maximum implantation energy and implantation depth of the implanter.

[0050] Other features and advantages of the present invention will be disclosed in detail in the following specific embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a schematic diagram of the overall structure of the first embodiment;

[0052] Figure 2 is a schematic structural diagram of the initial MOSFET structure in Example 1;

[0053] Figure 3 It is a schematic diagram of the structure after etching the deep trench in Example 1;

[0054] Figure 4 The side wall P column region and the side wall P are formed for the first embodiment. + Schematic diagram of the structure after the zone;

[0055] Figure 5 This is a schematic diagram of the structure after the column area structure is formed in Example 1;

[0056] Figure 6 This is a schematic diagram of the structure after etching the gate trench in Example 1;

[0057] Figure 7 It is a schematic diagram of the overall structure of the second embodiment;

[0058] Figure 8 This is a schematic diagram of the overall structure of Embodiment 3;

[0059] Fig. 9 This is a schematic diagram of the electric field strength of each structure when blocking in Example 3;

[0060] Fig.10 This is a schematic diagram of the relationship between the electric field strength and the vertical position during blocking in Example 3;

[0061] Fig.11 It is a cross-sectional view of the overall structure of the fourth embodiment;

[0062] Fig.12 This is a cross-sectional view of the overall structure of Example 5.

[0063] Markings in the figure: 1, substrate; 2, N-type drift region; 3, P-well region; 4, N + Area; 51, side wall P column area; 52, bottom P column area; 6, side wall P + Region; 7, column region structure; 8, gate electrode; 9, gate oxide; 101, N-type drift layer; 102, current diffusion layer; 103, mask. DETAILED DESCRIPTION

[0064] In order to better understand the purpose, structure and function of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings.

[0065] An asymmetric superjunction MOSFET structure, such as Figure 1 As shown, it includes a substrate 1 and a cellular structure arranged on the substrate 1; the cellular structure includes:

[0066] A first column region, located on the substrate 1, including an N-type drift region 2;

[0067] A second column region is arranged in the first column region, comprising a column region structure 7 and a gate structure arranged on the column region structure 7;

[0068] The third column region is located on the substrate 1 and includes a sidewall P column region 51. The sidewall P column region 51 is an ion-implanted P column region. The sidewall P column region 51 is charge balanced with the adjacent N-type drift region 2.

[0069] The third column region is disposed between the second column region and the first column region, and the third column region is disposed on one side of the second column region.

[0070] In this embodiment, one of the cellular structures includes two of the first column regions and one of the second column regions. The second column region is disposed between the two first column regions, and the second column region separates the two first column regions.

[0071] The third column region also includes a sidewall P + Area 6, the side wall P + Region 6 is disposed on the sidewall P column region 51. + Area 6 is ion implanted P + Area; the side wall P + The inclination angle of the region 6 during ion implantation is greater than the inclination angle of the side wall P column region 51 during ion implantation; + The depth of region 6 is not less than the depth of the gate structure.

[0072] In this embodiment, the substrate 1 is a highly doped N-type material; the ion-implanted P column region is a P column region formed by ion implantation; the ion-implanted P + The P region is formed by ion implantation. + Specifically, the ion implantation method may be self-aligned ion implantation.

[0073] Specifically, Figure 1 As shown, in this embodiment, the first column region also includes a P well region 3 and an N + region 4, the N-type drift region 2 is arranged on the substrate 1, the P-well region 3 is arranged on the N-type drift region 2, the N + Region 4 is disposed on the P-well region 3. Optionally, the first pillar region may also be provided with other structures as required.

[0074] In this embodiment, the column region structure 7 is a dielectric column region, such as Figure 1 As shown, the gate structure includes a gate electrode 8 in contact with the dielectric column region, and a dielectric column region exists between the gate electrode 8 and the first column region; the dielectric column region between the gate electrode 8 and the first column region has the same function as the gate oxide.

[0075] Optionally, the material of the dielectric column region is an insulating dielectric, such as SiO2.

[0076] Optionally, the N + A source electrode may be provided on region 4 to form a source.

[0077] Optionally, a plurality of the cellular structures are provided, and the plurality of cellular structures are densely laid on the substrate.

[0078] A method for manufacturing an asymmetric super junction MOSFET structure, such as Figures 2 to 6 As shown, the following steps are included:

[0079] S1: construct the initial MOSFET structure;

[0080] S2: constructing a mask 103 on the upper surface of the initial MOSFET structure and etching a deep trench;

[0081] S3: by performing a first ion implantation on one side of the deep trench, a sidewall P column region 51 is constructed on one side of the N-type drift region 2; the sidewall P column region 51 is charge balanced with the corresponding N-type drift region 2;

[0082] S4: By performing a second ion implantation on one side of the deep trench, a sidewall P column region 51 is formed. + Zone 6;

[0083] S5: remove the mask;

[0084] S6: filling the deep trench to form a pillar region structure 7;

[0085] S7: constructing a gate structure on the top of each pillar region structure 7 .

[0086] like Figure 2 As shown, in this embodiment, the initial MOSFET structure in S1 includes a substrate 1, an N-type drift region 2, a P-well region 3 and an N + Region 4; wherein the N-type drift region 2 is arranged on the substrate 1, the P-well region 3 is arranged on the N-type drift region 2, and the N + Region 4 is arranged on the P-well region 3. The construction of the initial MOSFET structure is prior art and will not be described in detail in this application. The initial MOSFET structure may also be purchased directly. The initial MOSFET structure may also be selected as appropriate according to the needs.

[0087] like Figure 3 As shown, in this embodiment, the mask 103 in S2 is constructed in the N + On the upper surface of region 4, the deep trench penetrates through the N-type drift region 2. Specifically, the etching method may be ICP etching. In this embodiment, the deep trench is a through groove, so as to form two separated first column regions in one unit cell.

[0088] In this embodiment, a mask 103 is required during ion implantation. Figure 4 As shown, the mask 103 used in the first ion implantation in S3 is the mask 103 obtained in S2. The first ion implantation is all performed on the same side of the deep trench and is a small-angle, low-dose tilted implantation. The sidewall P column region 51 is constructed at the lower end of one side of the N-type drift region 2.

[0089] At the same time, if Figure 4 As shown, in this embodiment, the mask 103 used in the second ion implantation in S4 is also the mask 103 obtained in S2. The second ion implantation is also performed on the same side as the first ion implantation, and is a high-dose tilted implantation at a large angle to construct a side wall P column region 51 on the side wall P column region 51. + Area 6. The large angle is greater than the tilt angle during the first ion implantation. + The depth of region 6 is not less than the depth of the gate structure. In this embodiment, it is reflected by the sidewall P + The distance between the region 6 and the substrate 1 is smaller than the distance between the gate structure and the substrate 1 .

[0090] The present application can avoid N by using the mask 103 when etching the deep trench. + The upper portion or surface of region 4 is also implanted with ions.

[0091] Specifically, the ion implantation method may be tilted self-aligned implantation, which is a special ion implantation technology that combines the advantages of self-aligned process and tilted implantation. It is a prior art and will not be described in detail in this application.

[0092] The mask removal step of S5 is used to construct the side wall P column region 51 and the side wall P + After area 6, the mask 103 can be reused to save manufacturing costs.

[0093] like Figure 5 As shown, in this embodiment, three deep trenches are etched, and the S6 fills all the deep trenches to form three pillar region structures 7 .

[0094] In this embodiment, the pillar region structure 7 is a dielectric pillar region, and the filling of the deep trench to form the pillar region structure 7 includes the following steps:

[0095] A dielectric is deposited in the deep trench to form a dielectric column region.

[0096] Specifically, the dielectric is an insulating dielectric, such as SiO2.

[0097] like Figure 6 and Figure 1 As shown, in this embodiment, S7 includes:

[0098] Etching a gate trench at the top of each dielectric column region, wherein a remaining dielectric column region used as a gate oxide is left between the etched gate trench and the first column region in this embodiment;

[0099] A gate electrode 8 is filled in the gate trench to form a gate structure.

[0100] The present application uses the side wall P column region 51 through deep trench ion implantation to make the charge balance control between the side wall P column region 51 and the corresponding N-type drift region 2 more precise; at the same time, since the PN junction position of the super junction is far away from the etching interface, the electric field at the defective interface is reduced, the reliability of the product is improved, and multiple epitaxy is avoided, which helps to save the manufacturing cost of the super junction MOSFET.

[0101] Furthermore, the present application adopts an ion implantation method with different inclination angles in a deep trench, and the vertical depth of the P-column region formed is only related to the inclination angle of the ion implantation and the trench depth, that is, the height of the P-column region formed in this way is no longer limited by the maximum implantation energy and implantation depth of the implanter.

[0102] At the same time, the side wall P column region 51 is formed synchronously with the side wall P column region 51. +Region 6 can reduce the electric field at the bottom of gate oxide 9 and play a protective role in gate oxide 9, thereby realizing a low-cost, high-performance, and high-reliability asymmetric super junction MOSFET structure design.

[0103] The MOSFET structure proposed in the present application, when blocked, the side wall P column region 51 and the N-type drift region 2 form a super junction structure, and the vertical electric field distribution is transformed from the triangular distribution of conventional devices to a rectangular distribution, thereby achieving high withstand voltage.

[0104] At the same time, through the side wall P + Region 6 suppresses the electric field in the gate oxide, and the high electric field is transferred to the sidewall P + The bottom of region 6 improves the reliability of the device. + The gate oxide on the other side of region 6 symmetrically forms a channel in P-well region 3 to conduct current.

[0105] Embodiment 2

[0106] like Figure 7 As shown, the difference between this embodiment and the first embodiment is that:

[0107] The column region structure 7 is a semiconductor column region, and the gate structure includes a gate oxide 9 in contact with the semiconductor column region and a gate electrode 8 in contact with the gate oxide 9; the gate oxide 9 is also in contact with the first column region or the third column region; the gate electrode 8 is not in contact with the semiconductor column region, the first column region or the third column region. The gate oxide 9 is a gate oxide.

[0108] Optionally, the material of the semiconductor column region includes intrinsic semiconductor or low-doped semiconductor.

[0109] During the preparation, the deep trench is filled in S6 to form the pillar region structure 7, which includes the following steps:

[0110] Through the epitaxial backfilling process, semiconductor pillar regions are formed in all deep trenches; in this embodiment, the semiconductor pillar regions are intrinsic semiconductor pillar regions. The epitaxial backfilling process is a prior art and will not be described in detail in this application.

[0111] The step of constructing a gate structure on the top of each column structure 7 in S7 includes the following steps:

[0112] Etching a gate trench on the top of the dielectric column region; in this embodiment, no dielectric column region is provided between the sidewall of the gate trench and the first column region;

[0113] A gate oxide 9 is deposited in the gate trench, and a gate electrode 8 is filled in the gate oxide. The bottom of the gate oxide 9 contacts the semiconductor column region, and the side contacts the first column region or the third column region, and the gate electrode 8 does not contact the semiconductor column region and the first column region.

[0114] The above-mentioned deposition of gate oxide and filling of gate electrode 8 are prior arts and will not be described in detail in this application.

[0115] Embodiment 3

[0116] like Figure 8 As shown, the difference between this embodiment and embodiment 1 or embodiment 2 is that:

[0117] An N-type drift layer 101 is also disposed on the substrate 1 , and the first column region, the second column region and the third column region are located on the N-type drift layer 101 .

[0118] During the preparation, the depth of the deep trench etched in S2 is smaller than the height of the N-type drift region 2 .

[0119] Furthermore, the present embodiment is different from the first embodiment or the second embodiment in that:

[0120] The N-type drift layer 101 is provided with a bottom P column region 52, the bottom P column region 52 is provided at the top of the N-type drift layer 101, and the bottom P column region 52 is an ion-implanted P column region. Optionally, the inclination angle of the bottom P column region 52 during ion implantation is equal to the inclination angle of the sidewall P column region 51 during ion implantation; the bottom P column region 52 and the sidewall P column region 51 are formed during the same ion implantation.

[0121] During the preparation, when the first ion implantation is performed on one side of the deep trench in S3, the method further includes:

[0122] A bottom P column region 52 is constructed on the top of the N-type drift layer 101, and a sidewall P column region 51 is constructed on one side of the N-type drift region 2. The bottom P column region 52 is connected to the sidewall P column region 51. The sidewall P column region 51 is charge balanced with the corresponding N-type drift region 2.

[0123] Specifically, the tilt angle during ion implantation can be adjusted so that a single ion implantation simultaneously forms the connected bottom P column region 52 and the sidewall P column region 51. Optionally, the bottom P column region 52 and the sidewall P column region 51 can also be formed by two ion implantations.

[0124] Optionally, the present embodiment is different from the first embodiment or the second embodiment in that:

[0125] The first column region further includes a current diffusion layer 102. The N-type drift region 2 is disposed on the substrate 1 or the N-type drift layer 101. The current diffusion layer 102 is disposed on the N-type drift region 2. The P-well region 3 is located on the current diffusion layer 102. + Region 4 is located on the P-well region 3 .

[0126] During the preparation, when constructing the initial MOSFET structure in S1, it also includes constructing the current diffusion layer 102. This is the prior art and will not be described in detail in this application.

[0127] like Fig. 9 and Fig.10 As shown, the present application adopts the side wall P + Region 6 suppresses the electric field in the gate oxide, transferring the high electric field to the sidewall P + The bottom of area 6 improves the reliability of the device. Fig. 9 The electric field strength of each structure is represented by color, ranging from 0 MV / cm to 3 MV / cm. Fig.10 for Fig. 9 The electric field strength corresponding to the center line in the vertical position.

[0128] Embodiment 4

[0129] like Fig.11 As shown, the difference between this embodiment and the first, second or third embodiment is that one of the cell structures includes one first column region and one second column region, the first column region surrounds the second column region; the second column region does not separate the first column regions located on both sides thereof. The third column region is arranged on one side of the second column region and between the second column region and the first column region. The sidewall P column region 51 of the third column region is charge balanced with the connected N-type drift region 2.

[0130] In this embodiment, the deep trench etched in S2 is in the shape of a blind hole. The sidewall P column region and the sidewall P+ region are obtained by ion implantation on one side of the deep trench. Specifically, in this embodiment, during the first ion implantation, at least two surfaces inside the N-type drift region are implanted; during the second ion implantation, the number of implanted surfaces is the same as that of the first ion implantation.

[0131] Optionally, the shape of the cellular structure is a right quadrangular prism. The shape of the cellular structure in a top view is a rectangle, the shape of the second column area in a top view is a rectangle; the combined shape of the first column area and the third column area in a top view is a hollow rectangle; the shape of the third column area in a top view is half of the hollow rectangle.

[0132] Embodiment 5

[0133] like Fig.12 As shown, the difference between this embodiment and the fourth embodiment is that the shape of the cellular structure is a straight hexagonal prism.

[0134] Specifically, in this embodiment, during the first ion implantation, three surfaces inside the N-type drift region are implanted; during the second ion implantation, the number of implanted surfaces is the same as that of the first ion implantation.

[0135] Optionally, the shape of the cellular structure in the top view is a regular hexagon, the shape of the second column area in the top view is a regular hexagon; the combined shape of the first column area and the third column area in the top view is a hollow regular hexagon; the shape of the third column area in the top view is half of a hollow regular hexagon.

[0136] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

[0137] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for manufacturing an asymmetric super junction MOSFET structure, characterized in that: The steps include: Constructing an initial MOSFET structure; wherein the initial MOSFET structure includes a substrate, an N-type drift region, a P-well region and an N + district; A mask is constructed on the upper surface of the initial MOSFET structure and a deep trench is etched; By performing the first ion implantation on only one side of the deep trench, a sidewall P column region is constructed on one side of the N-type drift region; the sidewall P column region is charge balanced with the corresponding N-type drift region; By performing a second ion implantation on only one side of the deep trench, a sidewall P column region is formed on the sidewall P column region. + district; removing the mask; Filling the deep trenches to form pillar structures; A gate structure is constructed on top of each stud structure.

2. The method for manufacturing an asymmetric super junction MOSFET structure according to claim 1, characterized in that: The inclination angle during the first ion implantation is greater than the inclination angle during the second ion implantation; the side wall P + The depth of the region is not less than the depth of the gate structure.

3. The method for manufacturing an asymmetric super junction MOSFET structure according to claim 2, characterized in that: The filling of the deep trench to form a pillar region structure comprises the following steps: Depositing dielectric in the deep trench to form a dielectric column region; The construction of a gate structure on the top of each pillar region structure comprises the following steps: Etching a gate trench at the top of each dielectric column region, wherein a dielectric column region is left between the etched gate trench and the N-type drift region; A gate electrode is filled in the gate trench.

4. The method for manufacturing an asymmetric super junction MOSFET structure according to claim 2, characterized in that: The filling of the deep trench to form a pillar region structure comprises the following steps: By using an epitaxial backfilling process, semiconductor pillar regions are formed in all deep trenches; The construction of a gate structure on the top of each pillar region structure comprises the following steps: Etching a gate trench on the top of the semiconductor pillar region; Depositing gate oxide in the gate trench and filling the gate electrode in the gate oxide; Wherein, the gate oxide is in contact with the N-type drift region.

5. The method for manufacturing an asymmetric super junction MOSFET structure according to any one of claims 1 to 4, characterized in that: When etching the deep trench, the depth of the etched deep trench is less than the height of the N-type drift region; The first ion implantation on one side of the deep trench comprises: By performing a first ion implantation on one side of the deep trench, a sidewall P column region is constructed on one side of the N-type drift region, and a bottom P column region is constructed on the top of the N-type drift region, wherein the bottom P column region is connected to the sidewall P column region.

6. An asymmetric super junction MOSFET structure, characterized in that: The method according to any one of claims 1 to 5 comprises a substrate and a cellular structure located on the substrate; the cellular structure comprises: A first column region, including an N-type drift region; A second column region is disposed in the first column region, comprising a column region structure and a gate structure disposed on the column region structure; A third column region, comprising a side wall P column region, wherein the side wall P column region is an ion implanted P column region, and the side wall P column region is charge balanced with an adjacent N-type drift region; the third column region is disposed between the second column region and the first column region, and the third column region is disposed on one side of the second column region; The third column region also includes a sidewall P + area, the side wall P + The area is located on the sidewall P column area, and the sidewall P + The area is ion implanted P + Area; the side wall P + The depth of the region is not less than the depth of the gate structure.

7. The asymmetric super junction MOSFET structure according to claim 6, characterized in that: The side wall P + The inclination angle of the region during ion implantation is greater than the inclination angle of the side wall P column region during ion implantation.

8. The asymmetric super junction MOSFET structure according to claim 7, characterized in that: The column region structure includes a semiconductor column region or a dielectric column region; When the column region structure is a semiconductor column region, the gate structure includes a gate oxide in contact with the semiconductor column region and a gate electrode in contact with the gate oxide; the gate oxide is in contact with the first column region; When the column region structure is a dielectric column region, the gate structure includes a gate electrode in contact with the dielectric column region, and a dielectric column region is provided between the gate electrode and the first column region.

9. The asymmetric super junction MOSFET structure according to claim 8, characterized in that: The semiconductor column region is an intrinsic semiconductor column region or a low-doped semiconductor column region; the dielectric column region is an insulating dielectric column region.

10. The asymmetric super junction MOSFET structure according to claim 9, characterized in that: The first column region also includes a P well region and an N + The N-type drift region is located on the substrate, the P-well region is located on the N-type drift region, and the N + A region is located on the P-well region; Or, the first column region further includes a current diffusion layer, a P well region and an N + The N-type drift region is located on the substrate, the current diffusion layer is located on the N-type drift region, the P-well region is located on the current diffusion layer, and the N + The region is located on the P-well region.

11. The asymmetric super junction MOSFET structure according to any one of claims 6 to 10, characterized in that: It also includes an N-type drift layer, which is located on the substrate, and the first column region and the second column region are located on the N-type drift layer.

12. The asymmetric super junction MOSFET structure according to claim 11, characterized in that: A bottom P column region is provided in the N-type drift layer, and the bottom P column region is provided on the top of the N-type drift layer. The bottom P column region is an ion-implanted P column region. The inclination angle of the bottom P column region during ion implantation is equal to the inclination angle of the side wall P column region during ion implantation. The bottom P column region and the side wall P column region are formed during the same ion implantation.

13. The asymmetric super junction MOSFET structure according to any one of claims 6 to 10 or 12, characterized in that: The second column region is disposed between the two first column regions, and the second column region separates the two first column regions.

14. The asymmetric super junction MOSFET structure according to any one of claims 6 to 10 or 12, characterized in that: The first column region surrounds the second column region.

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