Semiconductor structure and semiconductor device

Abstract

The invention provides a semiconductor structure and a semiconductor device. The semiconductor structure comprises a substrate; the first semiconductor voltage-withstanding layer is located on the substrate, and the conduction type of the first semiconductor voltage-withstanding layer is identical to that of the substrate; the second semiconductor voltage-withstanding layer is located on the side, away from the substrate, of the first semiconductor voltage-withstanding layer, and the conduction type of the second semiconductor voltage-withstanding layer is different from that of the substrate; the first injection region is located in the second semiconductor voltage-withstanding layer, and the conduction type of the first injection region is different from that of the substrate; the second injection region is located in the second semiconductor voltage-withstanding layer and located on one side of the first injection region, the surface, close to the substrate, of the second injection region makes contact with the first semiconductor voltage-withstanding layer, and the conduction type of the second injection region is the same as that of the substrate; the third injection region is located in the second injection region, the conduction type is the same as that of the substrate, and the doping concentration is the same as that of the substrate; and the first trench gate structure is located in the first semiconductor voltage-withstanding layer and the second semiconductor voltage-withstanding layer and is in contact with the first injection region, the second injection region and the third injection region respectively. According to the invention, the problem that the latch-up effect is easy to occur in the groove-type MOS is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a semiconductor device. Background Art

[0002] Trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, MOS for short) is a high-power power electronic device. Because the device has a symmetrical structure on both sides of the trench, the device has no specific source or drain and can achieve source-drain interchangeability; but a parasitic transistor is formed in the structure, which is prone to latch-up effect. Summary of the invention

[0003] The main purpose of the present application is to provide a semiconductor structure and a semiconductor device to at least solve the problem of latch-up effect that trench MOS is prone to in the prior art.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, including: a substrate; a first semiconductor voltage-resistant layer, located on the substrate, the conductivity type of the first semiconductor voltage-resistant layer is the same as the conductivity type of the substrate; a second semiconductor voltage-resistant layer, located on a side of the first semiconductor voltage-resistant layer away from the substrate, the conductivity type of the second semiconductor voltage-resistant layer is different from the conductivity type of the substrate; a first injection region, located in the second semiconductor voltage-resistant layer, the surface of the first injection region away from the substrate is a part of the surface of the second semiconductor voltage-resistant layer away from the substrate, the conductivity type of the first injection region is different from the conductivity type of the substrate; a second injection region, located in the second semiconductor voltage-resistant layer and on one side of the first injection region, the A surface of the second injection region away from the substrate is a partial surface of the second semiconductor voltage-resistant layer away from the substrate, a surface of the second injection region close to the substrate is in contact with the first semiconductor voltage-resistant layer, and the conductivity type of the second injection region is the same as the conductivity type of the substrate; a third injection region is located in the second injection region, a surface of the third injection region away from the substrate is a partial surface of the second semiconductor voltage-resistant layer away from the substrate, the conductivity type of the third injection region is the same as the conductivity type of the substrate, and the doping concentration of the third injection region is equal to the doping concentration of the substrate; a first trench gate structure is located in the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, and is in contact with the first injection region, the second injection region and the third injection region, respectively.

[0005] Optionally, the semiconductor structure also includes: a fourth injection region, located in the second semiconductor voltage-resistant layer and on a side of the first injection region away from the second injection region, the surface of the fourth injection region away from the substrate is a partial surface of the second semiconductor voltage-resistant layer away from the substrate, and the conductivity type of the fourth injection region is different from the conductivity type of the substrate; a second trench gate structure, located in the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, and respectively contacting the first injection region and the fourth injection region.

[0006] Optionally, the second trench gate structure includes: a first trench, located in the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, and respectively contacting the first injection region and the fourth injection region; a first control gate and a first shield gate spaced apart in the first trench in a direction away from the substrate, the surface of the first shield gate away from the substrate being a partial surface of the second semiconductor voltage-resistant layer away from the substrate; a first gate oxide layer, located in the first trench, the first gate oxide layer wrapping the first control gate, and the first gate oxide layer also located on the surface of the first shield gate close to the substrate and on the side of the first shield gate.

[0007] Optionally, the semiconductor structure also includes: a fifth injection region, located in the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, respectively contacting the surface of the second trench gate structure close to the substrate and part of the side surface of the second trench gate structure, and the conductivity type of the fifth injection region is the same as the conductivity type of the substrate.

[0008] Optionally, the semiconductor structure also includes: a first metal layer, located on the surface of the third injection region away from the substrate, the first metal layer being electrically connected to the substrate; a second metal layer, located on the surface of the first injection region away from the substrate; a third metal layer, located on the surface of the fourth injection region away from the substrate, the third metal layer being spaced apart from the second metal layer.

[0009] Optionally, the second metal layer or the third metal layer is electrically connected to the first metal layer.

[0010] Optionally, the semiconductor structure also includes: a sixth injection region, located in the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, respectively contacting the surface of the first trench gate structure close to the substrate and part of the side surface of the first trench gate structure, and the conductivity type of the sixth injection region is the same as the conductivity type of the substrate.

[0011] Optionally, the semiconductor structure further includes: a dielectric layer located on a surface of the first trench gate structure away from the substrate.

[0012] According to another aspect of the present application, a semiconductor device is provided, comprising: any one of the semiconductor structures described above.

[0013] Optionally, the semiconductor device is a silicon carbide device.

[0014] By applying the technical solution of the present application, a third injection region with a conductivity type different from that of the first injection region is formed in the second injection region of the second semiconductor voltage-resistant layer. The conductivity type and doping concentration of the third injection region are the same as those of the substrate, so that the first metal layer in contact with the third injection region can be at the same potential as the substrate. By connecting the first metal layer and the source of the semiconductor structure, the PN junction short circuit of the parasitic transistor in the semiconductor structure is achieved, thereby alleviating the problem of easy conduction of the parasitic transistor in the trench semiconductor structure, enhancing the anti-latch capability of the semiconductor structure, and reducing the risk of latch-up effect in the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present application is shown;

[0017] Figure 2 A schematic diagram of another semiconductor structure provided in an embodiment of the present application is shown;

[0018] Figure 3 A schematic diagram of a structure obtained after step S1 of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0019] Figure 4 A schematic diagram of a structure obtained after step S2 of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0020] Figure 5 A schematic diagram of a structure obtained after step S3 of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0021] Figure 6 A schematic diagram of a structure obtained after step S4 of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0022] Figure 7 A schematic diagram of a structure obtained after step S5 of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0023] Figure 8 A schematic diagram of a structure obtained after step S6 of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0024] Fig. 9 A schematic diagram of a structure obtained after step S7 of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0025] Fig.10 A schematic diagram of a structure obtained after step S8 of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0026] Fig.11 A schematic diagram of a structure obtained after step S9 of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0027] Fig.12 A schematic diagram of a structure obtained after step S10 of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0028] Fig.13 A schematic structural diagram of a semiconductor structure manufacturing method provided in an embodiment of the present application is shown after step S11.

[0029] The above drawings include the following reference numerals:

[0030] 10. substrate; 11. first semiconductor voltage-resistant layer; 12. second semiconductor voltage-resistant layer; 13. first injection region; 14. second injection region; 15. third injection region; 16. first trench gate structure; 17. fourth injection region; 18. second trench gate structure; 19. first control gate; 20. first shield gate; 21. first gate oxide layer; 22. fifth injection region; 23. second control gate; 24. second shield gate; 25. second gate oxide layer; 26. sixth injection region; 27. first metal layer; 28. second metal layer; 29. ​​third metal layer; 30. dielectric layer; 31. first preliminary semiconductor voltage-resistant layer; 32. second preliminary semiconductor voltage-resistant layer; 33. preliminary injection region; 34. first trench; 35. second trench; 36. gate oxide material; 37. polysilicon material; 38. first groove; 39. second groove. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] As introduced in the background technology, the trench MOS in the prior art is prone to the latch-up effect problem. To solve the above technical problem, the embodiments of the present application provide a semiconductor structure and a semiconductor device.

[0035] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0036] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure according to an embodiment of the present application is exemplarily shown, as shown in FIG. Figure 1 As shown, the semiconductor structure comprises:

[0037] Substrate 10;

[0038] Specifically, the conductivity type of the substrate 10 may be P type or N type.

[0039] A first semiconductor voltage-resistant layer 11 is located on the substrate 10, and the conductivity type of the first semiconductor voltage-resistant layer 11 is the same as that of the substrate;

[0040] A second semiconductor voltage-resistant layer 12 is located on a side of the first semiconductor voltage-resistant layer 11 away from the substrate 10, and the conductivity type of the second semiconductor voltage-resistant layer 12 is different from that of the substrate;

[0041] Specifically, the second semiconductor voltage-resistant layer 12 may be directly disposed on the surface of the first semiconductor voltage-resistant layer 11 away from the substrate 10 ; other structural layers may also be disposed between the second semiconductor voltage-resistant layer 12 and the substrate 10 .

[0042] a first injection region 13, located in the second semiconductor voltage-resistant layer 12, wherein a surface of the first injection region 13 away from the substrate 10 is a portion of a surface of the second semiconductor voltage-resistant layer 12 away from the substrate 10, and a conductivity type of the first injection region 13 is different from a conductivity type of the substrate 10;

[0043] Specifically, the first implantation region 13 may be a source region of a semiconductor structure, or may be a drain region of a semiconductor structure.

[0044] a second injection region 14, located in the second semiconductor voltage-resistant layer 12 and on one side of the first injection region 13; a surface of the second injection region 14 away from the substrate 10 is a partial surface of the second semiconductor voltage-resistant layer 12 away from the substrate 10; a surface of the second injection region 14 close to the substrate 10 is in contact with the first semiconductor voltage-resistant layer 11; and a conductivity type of the second injection region 14 is the same as a conductivity type of the substrate 10;

[0045] Specifically, in the thickness direction of the semiconductor structure, the width of the second injection region 14 is the same as the width of the second semiconductor voltage-resistant layer 12 .

[0046] a third injection region 15, located in the second injection region 14, wherein a surface of the third injection region 15 away from the substrate 10 is a surface of the second semiconductor voltage-resistant layer 12 away from the substrate 10, the conductivity type of the third injection region 15 is the same as the conductivity type of the substrate 10, and the doping concentration of the third injection region 15 is equal to the doping concentration of the substrate 10;

[0047] Specifically, the third injection region 15 and the substrate 10 have the same doping concentration and the same conductivity type, so the third injection region 15 and the substrate 10 can achieve the same potential.

[0048] The first trench gate structure 16 is located in the first semiconductor voltage-resistant layer 11 and the second semiconductor voltage-resistant layer 12 , and is in contact with the first injection region 13 , the second injection region 14 and the third injection region 15 , respectively.

[0049] Specifically, the first injection region 13 and the second injection region 14 are respectively located on both sides of the first trench gate structure 16, and are in contact with the first trench gate structure 16. The surface of the third injection region 15 located in the second injection region 14 close to the first trench gate structure 16 is a partial surface of the second injection region 14 close to the first trench gate structure 16, and therefore, the third injection region 15 is also in contact with the first trench gate structure 16.

[0050] Through the embodiment, a first semiconductor voltage-resistant layer and a second semiconductor voltage-resistant layer are sequentially arranged on the substrate, a first trench gate structure extends into the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, a first injection region and a second injection region are arranged in the second semiconductor voltage-resistant layer and are located on both sides of the first trench gate structure, and a third injection region is located in the second injection region and is in contact with the first trench gate structure, wherein the substrate, the first semiconductor voltage-resistant layer, the second injection region and the third injection region have the same conductivity type and are different from the conductivity types of the second semiconductor voltage-resistant layer and the first injection region, and the third injection region has the same doping concentration as the substrate. The present application forms a third injection region with a conductivity type different from that of the first injection region in the second injection region of the second semiconductor voltage-resistant layer, and the conductivity type and doping concentration of the third injection region are the same as those of the substrate, so that the first metal layer in contact with the third injection region can be equipotential with the substrate, and the PN junction short circuit of the parasitic transistor in the semiconductor structure is realized by connecting the first metal layer to the source of the semiconductor structure, thereby alleviating the problem of easy conduction of the parasitic transistor in the trench-type semiconductor structure, enhancing the anti-latch capability of the semiconductor structure, and reducing the risk of latch-up effect in the semiconductor structure.

[0051] In addition, the present application sets up two layers of semiconductor voltage-resistant layers with different conductivity types, so that the first trench gate structure passes through the two layers of semiconductor voltage-resistant layers, thereby ensuring that the semiconductor structure has good voltage-resistant performance and alleviating the problem of premature device breakdown caused by poor quality of the gate oxide layer at the bottom of the trench gate.

[0052] In one alternative, Figure 1As shown, the semiconductor structure also includes: a fourth injection region 17, which is located in the second semiconductor voltage-resistant layer 12 and on the side of the first injection region 13 away from the second injection region 14, the surface of the fourth injection region 17 away from the substrate 10 is a partial surface of the second semiconductor voltage-resistant layer 12 away from the substrate 10, and the conductivity type of the fourth injection region 17 is different from the conductivity type of the substrate 10, that is, the conductivity type of the fourth injection region 17 is the same as the conductivity type of the first injection region 13; a second trench gate structure 18, which is located in the first semiconductor voltage-resistant layer 11 and the second semiconductor voltage-resistant layer 12, and is in contact with the first injection region 13 and the fourth injection region 17, respectively. In this embodiment, a second trench gate structure and a fourth injection region are sequentially arranged on the side of the first injection region away from the second injection region. The first injection region, the second trench gate structure and the fourth injection region constitute a trench gate MOS device. Since the device is a symmetrical structure on both sides of the second trench gate structure, the device can realize source-drain interchange, that is, the first injection region can be used as the source and the fourth injection region as the drain; the first injection region can also be used as the drain and the fourth injection region as the source, so that the semiconductor structure has greater operability. In addition, in the semiconductor structure of the present application, the source and drain regions are both on the surface of the device, so that the device can be connected to other structures through surface through holes when it is packaged. Therefore, the semiconductor structure of the present application can be suitable for CSP (Chip Scale Package) packaging.

[0053] In addition, the semiconductor structure of the present application has a first semiconductor voltage-resistant layer and a second semiconductor voltage-resistant layer, and adopts a trench gate design. The source and drain are isolated by the second trench gate structure, thereby increasing the current path length between the source and the drain, and increasing the length of the voltage-resistant layer between the source and the drain in disguise. While withstanding the voltage, it can achieve an effect similar to that of a vertically conducted VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor transistor, vertical bipolar metal oxide semiconductor device), making full use of the chip area and avoiding the problem of increased device size caused by increased thickness of the voltage-resistant layer of the semiconductor structure; at the same time, the trench gate design can reduce the on-resistance of the semiconductor structure. Compared with the planar gate structure, the semiconductor structure of the present application has a higher voltage-resistant capability under the same chip area.

[0054] In addition, by setting the first trench gate structure and the second trench gate structure, the present application can increase the current path of the semiconductor structure on the basis of realizing the function of the MOS device, thereby ensuring that the semiconductor structure has strong conduction capability and power processing capability.

[0055] Those skilled in the art may configure any suitable trench gate structure as the second trench gate structure, such as a single gate structure, a shielded gate structure, etc. Figure 2 A schematic cross-sectional structure diagram of another semiconductor structure according to an embodiment of the present application is shown as an example. Figure 2 As shown, the second trench gate structure 18 includes: a first trench, located in the first semiconductor voltage-resistant layer 11 and the second semiconductor voltage-resistant layer 12, and respectively in contact with the first injection region 13 and the fourth injection region 17; a first control gate 19 and a first shield gate 20 spaced apart in the first trench in a direction away from the substrate 10, wherein the surface of the first shield gate 20 away from the substrate 10 is a partial surface of the second semiconductor voltage-resistant layer 12 away from the substrate 10; a first gate oxide layer 21, located in the first trench, the first gate oxide layer 21 wraps the first control gate 19, that is, the first gate oxide layer 21 covers all surfaces of the first control gate 19, and the first gate oxide layer 21 is also located on the surface of the first shield gate 20 close to the substrate 10 and on the side of the first shield gate 20, wherein the side of the first shield gate 20 refers to the other surfaces of the first shield gate 20 except the two surfaces opposite to the substrate 10. A shielded gate structure is introduced in this embodiment, so that the second trench gate structure not only has the characteristic of low on-resistance, but also has the advantage of good switching characteristics, thereby further ensuring that the switching characteristics and on-characteristics of the semiconductor structure are good, and at the same time further ensuring that the characteristic on-resistance and gate charge of the semiconductor structure are low.

[0056] Furthermore, if Figure 1 and Figure 2 As shown, the semiconductor structure further includes: a fifth injection region 22, which is located in the first semiconductor voltage-resistant layer 11 and the second semiconductor voltage-resistant layer 12, and is in contact with the surface of the second trench gate structure 18 close to the substrate 10 and part of the side surface of the second trench gate structure 18, respectively, wherein the side surface of the second trench gate structure 18 refers to the other surfaces of the second trench gate structure 18 except the two surfaces opposite to the substrate 10, that is, the fifth injection region 22 wraps the bottom and bottom corner of the second trench gate structure 18, and the conductivity type of the fifth injection region 22 is the same as the conductivity type of the substrate 10. By providing the fifth injection region at the bottom of the second trench gate structure, and the fifth injection region is in contact with the second semiconductor voltage-resistant layer, not only can the bidirectional conduction capability of the semiconductor structure be achieved, but also the bottom electric field concentration effect of the second trench gate structure can be suppressed, ensuring that the bottom gate oxide layer of the second trench gate structure is not broken down.

[0057] Specifically, Figure 2As shown, since the outer layer in the second trench gate structure 18 is the first gate oxide layer 21, the fifth injection region 22 is in contact with the surface of the second trench gate structure 18 close to the substrate 10 and part of the side surface of the second trench gate structure 18, respectively, which means that the fifth injection region 22 is in contact with the surface of the first gate oxide layer 21 close to the substrate 10 and part of the side surface of the first gate oxide layer 21, respectively.

[0058] Similar to the design concept of the second trench gate structure, those skilled in the art can set any suitable trench gate structure as the first trench gate structure, such as a single gate structure, a shielded gate structure, etc. In an exemplary embodiment, Figure 2 As shown, the first trench gate structure 16 includes: a first trench, located in the first semiconductor voltage-resistant layer 11 and the second semiconductor voltage-resistant layer 12, and respectively in contact with the first injection area 13, the second injection area 14 and the third injection area 15; a second control gate 23 and a second shield gate 24 are spaced apart in the second trench in a direction away from the substrate 10, and the surface of the second shield gate 24 away from the substrate 10 is a partial surface of the second semiconductor voltage-resistant layer 12 away from the substrate 10; a second gate oxide layer 25, located in the second trench, the second gate oxide layer 25 wraps the second control gate 23, that is, the second gate oxide layer 25 covers all surfaces of the second control gate 23, and the second gate oxide layer 25 is also located on the surface of the second shield gate 24 close to the substrate 10 and on the side of the second shield gate 24, wherein the side of the second shield gate 24 refers to the other surfaces of the second shield gate 24 except the two surfaces opposite to the substrate 10. A shielded gate structure is introduced in this embodiment, so that the first trench gate structure not only has the characteristic of low on-resistance, but also has the advantage of good switching characteristics, thereby further ensuring that the switching characteristics and on-characteristics of the semiconductor structure are good, and at the same time further ensuring that the characteristic on-resistance and gate charge of the semiconductor structure are low.

[0059] Furthermore, if Figure 1 and Figure 2As shown, the semiconductor structure further includes: a sixth injection region 26, which is located in the first semiconductor voltage-resistant layer 11 and the second semiconductor voltage-resistant layer 12, and is in contact with the surface of the first trench gate structure 16 close to the substrate 10 and part of the side surface of the first trench gate structure 16, wherein the side surface of the first trench gate structure 16 refers to the other surfaces of the first trench gate structure 16 except the two surfaces opposite to the substrate 10, that is, the sixth injection region 26 wraps the bottom and bottom corner of the first trench gate structure 16, and the conductivity type of the sixth injection region 26 is the same as the conductivity type of the substrate 10. By setting the sixth injection region at the bottom of the first trench gate structure, and the sixth injection region is in contact with the second semiconductor voltage-resistant layer, not only can the bidirectional conduction capability of the semiconductor structure be achieved, but also the bottom electric field concentration effect of the first trench gate structure can be suppressed, so as to ensure that the bottom gate oxide layer of the first trench gate structure is not broken down.

[0060] Specifically, Figure 2 As shown, since the outer layer in the first trench gate structure 16 is the second gate oxide layer 25, the sixth injection region 26 is in contact with the surface of the second trench gate structure 18 close to the substrate 10 and part of the side surface of the first trench gate structure 16, respectively, which means that the sixth injection region 26 is in contact with the surface of the second gate oxide layer 25 close to the substrate 10 and part of the side surface of the second gate oxide layer 25, respectively.

[0061] Alternatively, if Figure 2 As shown, the semiconductor structure further includes: a first metal layer 27, located on the surface of the third injection region 15 away from the substrate 10, the first metal layer 27 being electrically connected to the substrate 10; a second metal layer 28, located on the surface of the first injection region 13 away from the substrate 10; a third metal layer 29, located on the surface of the fourth injection region 17 away from the substrate 10, the third metal layer 29 being spaced apart from the second metal layer 28. The source and drain regions of the semiconductor structure are led out through the second metal layer and the third metal layer as the source and drain of the semiconductor structure, and the third injection region is led out through the first metal layer and electrically connected to the substrate, further ensuring that the first metal layer and the substrate are at the same potential.

[0062] In order to further reduce the risk of latch-up effect, in this embodiment, the second metal layer or the third metal layer is electrically connected to the first metal layer. That is, the second metal layer or the third metal layer as the source is electrically connected to the first metal layer to achieve the PN junction short circuit of the parasitic transistor in the semiconductor structure, further alleviating the problem that the parasitic transistor in the trench semiconductor structure is easily turned on, causing the latch-up effect of the trench MOS.

[0063] In addition, if Figure 2As shown, the semiconductor structure further includes: a dielectric layer 30, which is located on the surface of the first trench gate structure 16 away from the substrate 10. The dielectric layer 30 is also located on the surface of the second trench gate structure away from the substrate 10. The dielectric layer plays multiple roles on the surface of the trench gate structure, such as protection, insulation, electric field adjustment, and capacitance enhancement.

[0064] Specifically, in the present application, the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer are both layer structures that withstand high voltage without breakdown, which can ensure that the device can still work normally without damage under high voltage. The second semiconductor voltage-resistant layer is the main voltage-resistant layer, and the first semiconductor voltage-resistant layer is the secondary voltage-resistant layer. The material of the substrate includes but is not limited to semiconductor materials such as single crystal silicon material, epitaxial silicon material and silicon carbide material; the material of the first semiconductor voltage-resistant layer and the material of the second semiconductor voltage-resistant layer can be the same or different, specifically, the material of the first semiconductor voltage-resistant layer includes but is not limited to silicon nitride, silicon carbide and silicon oxide, etc.; the material of the second semiconductor voltage-resistant layer includes but is not limited to silicon nitride, silicon carbide and silicon oxide, etc.; the material of the control gate and the shielding gate can be polycrystalline silicon; the first metal layer, the second metal layer and the third metal layer can be a single-layer metal layer structure or a stacked metal layer structure, and the materials of the three can be the same or different, including but not limited to metal materials such as aluminum, copper and nickel; the material of the dielectric layer is but not limited to silicon oxide, silicon nitride and aluminum oxide, etc.

[0065] In a specific embodiment, the substrate, the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer are all made of silicon carbide, that is, the semiconductor structure is a silicon carbide device. Silicon carbide (SiC) material has the advantages of large bandgap, high thermal conductivity, high breakdown field strength, high electron saturation drift velocity, etc., and is particularly suitable for making high-power, high-frequency, and high-temperature semiconductor power devices.

[0066] In an embodiment of the present application, the doping concentration of the substrate is greater than the doping concentration of the first semiconductor voltage-resistant layer, the doping concentration of the second injection region is the same as the doping concentration of the first semiconductor voltage-resistant layer, the doping concentration of the third injection region is greater than the doping concentration of the second injection region, the doping concentrations of the fifth injection region and the sixth injection region are respectively greater than the doping concentration of the first semiconductor voltage-resistant layer; the doping concentrations of the first injection region and the fourth injection region are respectively greater than the doping concentration of the second semiconductor voltage-resistant layer.

[0067] Taking the conductivity type of the substrate as P type as an example, the conductivity types of the first semiconductor voltage-resistant layer, the second injection region, the third injection region, the fifth injection region and the sixth injection region are all P type, and the conductivity types of the second semiconductor voltage-resistant layer, the first injection region and the fourth injection region are all N type.

[0068] An embodiment of the present application further provides a semiconductor device, which includes any one of the semiconductor structures described above.

[0069] The semiconductor device includes any one of the semiconductor structures described above, which forms a third injection region with a conductivity type different from that of the first injection region in the second injection region of the second semiconductor voltage-resistant layer, and the conductivity type and doping concentration of the third injection region are the same as those of the substrate, so that the first metal layer in contact with the third injection region can be at the same potential as the substrate, and the PN junction short circuit of the parasitic transistor in the semiconductor structure is achieved by connecting the first metal layer and the source of the semiconductor structure, thereby alleviating the problem of easy conduction of the parasitic transistor in the trench semiconductor device, enhancing the anti-latch capability of the semiconductor device, and reducing the risk of latch-up effect in the semiconductor device.

[0070] In a specific embodiment, the semiconductor device is a silicon carbide device. Silicon carbide material has the advantages of large bandgap, high thermal conductivity, high breakdown field strength, high electron saturation drift velocity, etc., and is particularly suitable for making high-power, high-frequency, and high-temperature semiconductor power devices.

[0071] An embodiment of the present application further provides a method for manufacturing the semiconductor structure, the method comprising the following steps:

[0072] Step S1: epitaxially grow a P-type first preliminary semiconductor voltage-resistant layer 31 and an N-type second preliminary semiconductor voltage-resistant layer 32 on a P-type substrate 10 in sequence to obtain Figure 3 In the structure shown, the thickness and doping concentration of the first preliminary semiconductor voltage-resistant layer 31 and the second preliminary semiconductor voltage-resistant layer 32 are determined by the device specifications, the second preliminary semiconductor voltage-resistant layer 32 is the main pressure-bearing layer, and the first preliminary semiconductor voltage-resistant layer 31 is the secondary pressure-bearing layer;

[0073] Step S2: ion implantation is performed on a partial area of ​​the second prepared semiconductor voltage-resistant layer 32 to obtain a P-type second implantation region 14, the doping concentration of the second implantation region 14 is the same as the doping concentration of the first prepared semiconductor voltage-resistant layer 31, ion implantation is performed on a partial area of ​​the second implantation region 14 to obtain a P-type third implantation region 15, the doping concentration of the third implantation region 15 is greater than the doping concentration of the second implantation region 14, the first prepared semiconductor voltage-resistant layer 31 and the second implantation region 14 form an L-shaped P-type conductive region, such as Figure 4 As shown;

[0074] Step S3: Figure 5 As shown, ion implantation is performed on the first preliminary semiconductor voltage-resistant layer 31 to form an N-type preliminary implantation region 33, and the doping concentration of the preliminary implantation region 33 is greater than the ion concentration of the first preliminary semiconductor voltage-resistant layer 31;

[0075] Step S4: Figure 5 and Figure 6 As shown, the structure obtained in step S3 is subjected to trench etching, and the etching is carried out into the first prepared semiconductor voltage-resistant layer 31 to obtain a first trench 34 located in the prepared injection region 33, and a second trench 35 contacting the prepared injection region 33 and the second injection region 14, respectively, as shown in FIG. Figure 6 As shown, the prepared injection regions on both sides of the first trench 34 form the first injection region 13 and the fourth injection region 17 respectively, the remaining first prepared semiconductor voltage-resistant layer 31 forms the first semiconductor voltage-resistant layer 11, and the remaining second prepared semiconductor voltage-resistant layer 32 forms the second semiconductor voltage-resistant layer 12;

[0076] Step S5: Figure 7 As shown, ion implantation and annealing activation are performed on the bottom of the first trench 34 and the second trench 35, a P-type fifth implantation region 22 is formed at the bottom of the first trench 34, and a P-type sixth implantation region 26 is formed at the bottom of the second trench 35, and the doping concentrations of the fifth implantation region 22 and the sixth implantation region 26 are both greater than the doping concentration of the first semiconductor voltage-resistant layer 11;

[0077] Step S6: Figure 8 As shown, a gate oxide material 36 is filled on the bottom surface and sidewall of the first trench 34 and the second trench 35;

[0078] Step S7: Fig. 9 As shown, polysilicon material 37 is filled in the remaining first trench and second trench;

[0079] Step S8: Fig.10 As shown, the polysilicon material 37 is etched back and filled with gate oxide material 36, the remaining polysilicon material in the first trench forms the first control gate 19, and the remaining polysilicon material in the second trench forms the second control gate 23;

[0080] Step S9: Continue to etch back the filled gate oxide material 36 to form a first groove 38 located above the first control gate 19 and a second groove 39 located above the second control gate 23. Fig.11 As shown;

[0081] Step S10: Fill the first groove with polysilicon material to obtain the first shielding gate 20, and fill the second groove with polysilicon material to obtain the second shielding gate 24. Fig.12As shown, the gate oxide material in contact with the first control gate 19 and the first shield gate 20 forms a first gate oxide layer 21, and the three constitute a second trench gate structure 18; the gate oxide material in contact with the second control gate 23 and the second shield gate 24 forms a second gate oxide layer 25, and the three constitute a first trench gate structure 16;

[0082] Step S11: Fig.13 As shown, a dielectric layer 30 is formed on the surface of the first trench gate structure 16 and the second trench gate structure 18, and the dielectric layer 30 also covers the first injection region 13, the fourth injection region 17 and the partial surface of the third injection region 15 away from the substrate 10;

[0083] Step S12: forming a first metal layer 27 on the exposed surface of the third injection region 15 and a portion of the dielectric layer 30, forming a second metal layer 28 on the partially exposed surface of the first injection region 13 and a portion of the dielectric layer 30, and forming a third metal layer 29 on the partially exposed surface of the fourth injection region 17 and a portion of the dielectric layer 30, wherein the third metal layer 29 is spaced apart from the second metal layer 28, to obtain Figure 2 The structure shown.

[0084] In the method, the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer are formed by multiple epitaxy, which not only enhances the voltage-resistant performance of the semiconductor structure; the method of making grooves after multiple epitaxy can accurately control the relative size relationship between the grooves and the semiconductor voltage-resistant layer, making the semiconductor structure closer to the design target, and the design is more operable and can better meet the design requirements, while streamlining the process and reducing the production cost.

[0085] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0086] From the above description, it can be seen that the embodiments described in this application achieve the following technical effects:

[0087] The semiconductor structure of the present application is provided with a first semiconductor voltage-resistant layer and a second semiconductor voltage-resistant layer in sequence on the substrate, a first trench gate structure extends into the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, a first injection region and a second injection region are provided in the second semiconductor voltage-resistant layer and are located on both sides of the first trench gate structure, and a third injection region is located in the second injection region and is in contact with the first trench gate structure, wherein the substrate, the first semiconductor voltage-resistant layer, the second injection region and the third injection region have the same conductivity type and are different from the conductivity types of the second semiconductor voltage-resistant layer and the first injection region, and the third injection region has the same doping concentration as the substrate. The present application forms a third injection region with a conductivity type different from that of the first injection region in the second injection region of the second semiconductor voltage-resistant layer, and the conductivity type and doping concentration of the third injection region are the same as those of the substrate, so that the first metal layer in contact with the third injection region can be equipotential with the substrate, and the PN junction short circuit of the parasitic transistor in the semiconductor structure is realized by connecting the first metal layer to the source of the semiconductor structure, thereby alleviating the problem of easy conduction of the parasitic transistor in the trench-type semiconductor structure, enhancing the anti-latch capability of the semiconductor structure, and reducing the risk of latch-up effect in the semiconductor structure.

[0088] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor structure, It is characterized in that include: substrate; A first semiconductor voltage-resistant layer, located on the substrate, wherein the conductivity type of the first semiconductor voltage-resistant layer is the same as that of the substrate; A second semiconductor voltage-resistant layer is located on a side of the first semiconductor voltage-resistant layer away from the substrate, and the conductivity type of the second semiconductor voltage-resistant layer is different from that of the substrate; a first injection region, located in the second semiconductor voltage-resistant layer, wherein a surface of the first injection region away from the substrate is a portion of a surface of the second semiconductor voltage-resistant layer away from the substrate, and a conductivity type of the first injection region is different from a conductivity type of the substrate; a second injection region, located in the second semiconductor voltage-resistant layer and on one side of the first injection region, a surface of the second injection region away from the substrate being a portion of the surface of the second semiconductor voltage-resistant layer away from the substrate, a surface of the second injection region close to the substrate being in contact with the first semiconductor voltage-resistant layer, and a conductivity type of the second injection region being the same as a conductivity type of the substrate; A third injection region is located in the second injection region, a surface of the third injection region away from the substrate is a surface of the second semiconductor voltage-resistant layer away from the substrate, a conductivity type of the third injection region is the same as a conductivity type of the substrate, and a doping concentration of the third injection region is equal to a doping concentration of the substrate; The first trench gate structure is located in the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, and is in contact with the first injection region, the second injection region and the third injection region respectively.

2. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure further comprises: a fourth injection region, located in the second semiconductor voltage-withstanding layer and on a side of the first injection region away from the second injection region, wherein a surface of the fourth injection region away from the substrate is a portion of a surface of the second semiconductor voltage-withstanding layer away from the substrate, and a conductivity type of the fourth injection region is different from a conductivity type of the substrate; The second trench gate structure is located in the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, and is in contact with the first injection region and the fourth injection region respectively.

3. The semiconductor structure according to claim 2, It is characterized in that The second trench gate structure comprises: A first trench is located in the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, and is in contact with the first injection region and the fourth injection region respectively; A first control gate and a first shield gate are spaced apart and arranged in the first trench in a direction away from the substrate, wherein a surface of the first shield gate away from the substrate is a partial surface of the second semiconductor voltage-resistant layer away from the substrate; A first gate oxide layer is located in the first trench, the first gate oxide layer wraps the first control gate, and the first gate oxide layer is also located on a surface of the first shielding gate close to the substrate and on a side surface of the first shielding gate.

4. The semiconductor structure according to claim 2, It is characterized in that The semiconductor structure further comprises: A fifth injection region is located in the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, and contacts the surface of the second trench gate structure close to the substrate and part of the side surface of the second trench gate structure respectively. The conductivity type of the fifth injection region is the same as the conductivity type of the substrate.

5. The semiconductor structure according to claim 2, It is characterized in that The semiconductor structure further comprises: A first metal layer is located on a surface of the third injection region away from the substrate, and the first metal layer is electrically connected to the substrate; A second metal layer is located on a surface of the first injection region away from the substrate; The third metal layer is located on a surface of the fourth injection region away from the substrate, and the third metal layer is spaced apart from the second metal layer.

6. The semiconductor structure according to claim 5, It is characterized in that The second metal layer or the third metal layer is electrically connected to the first metal layer.

7. The semiconductor structure according to any one of claims 1 to 6, It is characterized in that The semiconductor structure further comprises: The sixth injection region is located in the first semiconductor voltage-resistant layer and the second semiconductor voltage-resistant layer, and contacts the surface of the first trench gate structure close to the substrate and part of the side surface of the first trench gate structure respectively. The conductivity type of the sixth injection region is the same as the conductivity type of the substrate.

8. The semiconductor structure according to any one of claims 1 to 6, It is characterized in that The semiconductor structure further comprises: The dielectric layer is located on a surface of the first trench gate structure away from the substrate.

9. A semiconductor device, It is characterized in that include: The semiconductor structure according to any one of claims 1 to 8.

10. The semiconductor device according to claim 9, It is characterized in that The semiconductor device is a silicon carbide device.

Images