Semiconductor structure and semiconductor device

Abstract

The invention provides a semiconductor structure and a semiconductor device. The semiconductor structure comprises a substrate; an epitaxial layer on the substrate; the doping layer is located on the side, away from the substrate, of the epitaxial layer, and the doping type of the epitaxial layer is different from that of the doping layer; the source region is located in the doping layer, and the surface, away from the substrate, of the source region is the partial surface, away from the substrate, of the doping layer; the drain region is located in the doping layer and located on one side of the source region, and the surface, away from the substrate, of the drain region is the partial surface, away from the substrate, of the doping layer; the trench gate structure is positioned in the epitaxial layer and the doped layer, is positioned between the source region and the drain region and is in contact with the source region and the drain region respectively; the doped well region is located in the epitaxial layer and the doped layer and is in contact with the surface, close to the substrate, of the trench gate structure and part of the side face of the trench gate structure, the doping type of the doped well region is the same as that of the epitaxial layer, and the doping concentration of the doped well region is larger than that of the epitaxial layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a semiconductor device. Background Art

[0002] Currently, trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has become one of the research hotspots due to its advantages such as low on-resistance and small chip area. In the traditional gate oxide preparation process of trench MOSFET, the oxidation rate at the bottom of the trench is much lower than the oxidation rate of the trench sidewalls, resulting in poor gate oxide quality at the bottom of the trench and deterioration of the device breakdown characteristics. Summary of the invention

[0003] The main purpose of the present application is to provide a semiconductor structure and a semiconductor device to at least solve the problem of easy breakdown of trench MOS devices in the prior art.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer located on the substrate; a doping layer located on a side of the epitaxial layer away from the substrate, the doping type of the epitaxial layer being different from the doping type of the doping layer; a source region located in the doping layer, the surface of the source region away from the substrate being the partial surface of the doping layer away from the substrate; a drain region located in the doping layer and located on one side of the source region, the surface of the drain region away from the substrate being the partial surface of the doping layer away from the substrate; a trench gate structure located in the epitaxial layer and the doping layer, located between the source region and the drain region and contacting the source region and the drain region respectively; a doped well region located in the epitaxial layer and the doping layer, and contacting the surface of the trench gate structure close to the substrate and part of the side surface of the trench gate structure respectively, the doping type of the doped well region being the same as the doping type of the epitaxial layer, and the doping concentration of the doped well region being greater than the doping concentration of the epitaxial layer.

[0005] Optionally, the trench gate structure includes: a gate oxide layer, located in the epitaxial layer and the doped layer, and respectively in contact with the source region and the drain region; a shield gate, located in the gate oxide layer, and a surface of the shield gate away from the substrate is a partial surface of the doped layer; a control gate, located in the gate oxide layer, the control gate is spaced apart from the shield gate, and is located on a side of the shield gate close to the substrate.

[0006] Optionally, an orthographic projection of the shielding grid on the substrate coincides with an orthographic projection of the control grid on the substrate.

[0007] Optionally, the orthographic projection of the shielding grid on the substrate is located in the orthographic projection of the control grid on the substrate.

[0008] Optionally, the control grid and the shielding grid are both rectangular structures.

[0009] Optionally, the control gate includes a main body portion and a groove portion which are arranged in contact with each other in a direction away from the substrate, and a portion of the shielding gate extends into the groove portion.

[0010] Optionally, the orthographic projection of the control gate on the predetermined plane is a first projection, the orthographic projection of the doped layer on the predetermined plane is a second projection, and the orthographic projection of the doped well region on the predetermined plane is a third projection, the first projection, the second projection and the third projection at least partially overlap, and the predetermined plane is parallel to the thickness direction of the semiconductor structure.

[0011] Optionally, the semiconductor structure also includes: a dielectric layer located on the surface of the doped layer and in contact with the trench gate structure; a first conductive layer located on the surface of the doped layer and in contact with the source region; and a second conductive layer located on the surface of the doped layer and in contact with the drain region.

[0012] Optionally, materials of the substrate, the epitaxial layer and the doping layer respectively include silicon carbide.

[0013] According to another aspect of the present application, a semiconductor device is provided, comprising: any one of the semiconductor structures described above.

[0014] According to the technical solution of the present application, an epitaxial layer is arranged on a substrate, a doped layer of a different doping type from the epitaxial layer is arranged on the epitaxial layer, a source region and a drain region are arranged in the doped layer at intervals, a trench gate structure is located in the epitaxial layer and the doped layer, and is in contact with the source region and the drain region respectively, a doped well region is located in the epitaxial layer and the doped layer, and is in contact with the bottom surface and part of the side surface of the trench gate structure respectively, the doped well region is the same as the doping type of the epitaxial layer, and the doped well region has a greater doping concentration than the epitaxial layer. The present application arranges epitaxial layers and doped layers of different conductive types on the substrate so that the trench gate structure extends into the epitaxial layer and the doped layer, thereby ensuring that the device has a strong withstand voltage performance, and by forming a doped well region at the bottom of the trench gate structure that wraps the bottom surface and bottom corner of the trench gate, the trench gate bottom electric field concentration effect of the trench gate structure can be suppressed, thereby avoiding the problem of easy device breakdown of the trench MOS device due to the poor quality of the bottom gate oxide layer of the trench gate structure, thereby ensuring the device reliability of the trench MOS device. Moreover, by setting up a trench gate structure, the electric field strength between the source and drain of the semiconductor device is lengthened, the vertical space of the device is effectively utilized, and the problem of increasing the device area on the plane to achieve voltage resistance, which causes a significant increase in the overall area of ​​the device, is avoided. In addition, the doped well region spans the epitaxial layer and the doped layer, and the doping type of the doped well region is the same as the doping type of the epitaxial layer, which can ensure the forward and reverse conduction function of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A schematic diagram of a semiconductor structure provided according to an embodiment of the present application is shown;

[0017] Figure 2 A schematic structural diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0018] Figure 3 A schematic structural diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0019] Figure 4 A schematic diagram of a structure obtained after step S1 of the method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0020] Figure 5 A schematic diagram of a structure obtained after step S2 according to the method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0021] Figure 6A schematic diagram of a structure obtained after step S3 according to the method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0022] Figure 7 A schematic diagram of a structure obtained after the first sub-gate oxide layer is filled in step S4 according to the method for manufacturing a semiconductor structure provided by an embodiment of the present application is shown;

[0023] Figure 8 A schematic diagram of a structure obtained after the gate dielectric material is filled in step S4 according to the method for manufacturing a semiconductor structure provided by an embodiment of the present application is shown;

[0024] Fig. 9 A schematic diagram of a structure obtained after step S5 according to the method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0025] Fig.10 A schematic diagram of a structure obtained after step S6 according to the method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;

[0026] Fig.11 A schematic diagram of a structure obtained after step S7 of the method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown.

[0027] The drawings include the following reference numerals:

[0028] 100, substrate; 101, epitaxial layer; 102, doped layer; 103, source region; 104, drain region; 105, trench gate structure; 106, doped well region; 107, gate oxide layer; 108, shielding gate; 109, control gate; 110, main body; 111, groove portion; 112, dielectric layer; 113, first conductive layer; 114, second conductive layer; 115, first initial epitaxial layer; 116, second initial epitaxial layer; 117, first trench; 118, first sub-gate oxide layer; 119, gate dielectric material; 120, second sub-gate oxide layer; 121, second trench. DETAILED DESCRIPTION

[0029] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0030] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] As introduced in the background technology, the trench MOS device in the prior art has the problem of easy breakdown. To solve the above technical problem, the embodiments of the present application provide a semiconductor structure and a semiconductor device.

[0033] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0034] An embodiment of the present application provides a semiconductor structure. Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure according to an embodiment of the present application is shown as an example. Figure 1 As shown, the semiconductor structure further includes:

[0035] Base 100;

[0036] An epitaxial layer 101 is located on the substrate 100;

[0037] Specifically, the epitaxial layer 101 is an epitaxial layer formed on the substrate 100 by epitaxy, and the doping type of the epitaxial layer 101 can be P-type or N-type; the doping type of the epitaxial layer 101 is the same as the doping type of the substrate 100 .

[0038] A doping layer 102, located on a side of the epitaxial layer 101 away from the substrate 100, wherein the doping type of the epitaxial layer 101 is different from the doping type of the doping layer 102;

[0039] Specifically, the doping layer 102 can be a structural layer formed by epitaxy or ion implantation. The doping layer 102 can be directly arranged on the surface of the epitaxial layer 101 away from the substrate 100; other structural layers can also be arranged between the doping layer 102 and the epitaxial layer 101.

[0040] A source region 103 is located in the doping layer 102, and a surface of the source region 103 away from the substrate 100 is a portion of a surface of the doping layer 102 away from the substrate 100;

[0041] Specifically, the doping type of the source region 103 is the same as the doping type of the doping layer 102 , and the doping concentration of the source region 103 is greater than the doping concentration of the doping layer 102 .

[0042] a drain region 104, located in the doping layer 102 and on one side of the source region 103, wherein a surface of the drain region 104 away from the substrate 100 is a partial surface of the doping layer 102 away from the substrate 100;

[0043] Specifically, the doping type of the drain region 104 is the same as the doping type of the doping layer 102, and the doping concentration of the drain region 104 is greater than the doping concentration of the doping layer 102. The source region 103 and the drain region 104 are disposed in the doping layer 102 at intervals.

[0044] A trench gate structure 105 is located in the epitaxial layer 101 and the doped layer 102, between the source region 103 and the drain region 104 and in contact with the source region 103 and the drain region 104 respectively;

[0045] Specifically, the surface of the trench gate structure away from the substrate 100 is a partial surface of the doping layer 102 .

[0046] The doped well region 106 is located in the epitaxial layer 101 and the doped layer 102, and is respectively in contact with the surface of the trench gate structure 105 close to the substrate 100 and part of the side surface of the trench gate structure 105. The doping type of the doped well region 106 is the same as the doping type of the epitaxial layer 101, and the doping concentration of the doped well region 106 is greater than the doping concentration of the epitaxial layer.

[0047] Through the embodiment, the epitaxial layer is arranged on the substrate, the doped layer with a different doping type from the epitaxial layer is arranged on the epitaxial layer, the source region and the drain region are arranged in the doped layer at intervals, the trench gate structure is located in the epitaxial layer and the doped layer, and is in contact with the source region and the drain region respectively, the doped well region is located in the epitaxial layer and the doped layer, and is in contact with the bottom surface and part of the side surface of the trench gate structure respectively, the doped well region is the same as the doping type of the epitaxial layer, and the doped well region is greater than the doping concentration of the epitaxial layer. The present application arranges epitaxial layers and doped layers of different conductive types on the substrate so that the trench gate structure extends into the epitaxial layer and the doped layer, thereby ensuring that the device has a strong withstand voltage performance, and by forming a doped well region that wraps the bottom surface and bottom corner of the trench gate at the bottom of the trench gate structure, the trench gate bottom electric field concentration effect of the trench gate structure can be suppressed, thereby avoiding the problem of easy device breakdown of the trench MOS device due to the poor quality of the bottom gate oxide layer of the trench gate structure, thereby ensuring the device reliability of the trench MOS device. Moreover, by setting up a trench gate structure, the electric field strength between the source and drain of the semiconductor device is lengthened, the vertical space of the device is effectively utilized, and the problem of increasing the device area on the plane to achieve voltage resistance, which causes a significant increase in the overall area of ​​the device, is avoided. In addition, the doped well region spans the epitaxial layer and the doped layer, and the doping type of the doped well region is the same as the doping type of the epitaxial layer, which can ensure the forward and reverse conduction function of the semiconductor structure.

[0048] Specifically, the substrate can be selected according to the actual needs of the device, and may include a silicon substrate, a germanium substrate, a silicon germanium substrate, a SOI (Silicon On Insulator) substrate, or a GOI (GermaniunOn Insulator) substrate. In other embodiments, the substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc., or a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc. Of course, it may also be other substrates feasible in the prior art.

[0049] A person skilled in the art may set up trench gate structures of various shapes, such as a trench-type single-gate structure, which has a simple process, is easy to implement, and has a low manufacturing cost; or a trench-type split-gate structure, which may improve device performance.

[0050] According to some further embodiments of the present application, Figures 1 to 3As shown, the trench gate structure 105 includes: a gate oxide layer 107, which is located in the epitaxial layer 101 and the doped layer 102, and is in contact with the source region 103 and the drain region 104 respectively; a shield gate 108, which is located in the gate oxide layer 107, and the surface of the shield gate 108 away from the substrate 100 is a partial surface of the doped layer 102; a control gate 109, which is located in the gate oxide layer 107, and the control gate 109 is spaced from the shield gate 108 and is located on a side of the shield gate 108 close to the substrate 100, that is, the gate oxide layer 107 extends from the surface of the doped layer 102 away from the substrate 100 into the epitaxial layer 101, and the gate oxide layer 107 contains gaps, specifically including first gaps and second gaps arranged in a direction away from the substrate 100, the control gate 109 is located in the first gap of the gate oxide layer 107, and the shield gate 108 is located in the second gap of the gate oxide layer 107. In this embodiment, the trench gate structure is set to a shielded trench gate structure, which increases the electric field strength of the trench sidewall, thereby further improving the breakdown voltage of the device, thereby allowing the semiconductor structure to remain stable in high-voltage applications; and the shielded trench gate helps to reduce the on-resistance of the device, reduce parasitic capacitance, and increase the switching speed of the device, thereby further improving the switching characteristics and conduction characteristics of the device; in addition, the shielded trench gate can also reduce the characteristic on-resistance (Rsp) and gate charge (Qg) of the device.

[0051] In the present application, the morphologies of the shielding gate 108 and the control gate 109 and the relative positional relationship therebetween can be flexibly set according to the design requirements of the device.

[0052] In a specific embodiment, Figure 1 As shown, the orthographic projection of the shielding gate 108 on the substrate 100 coincides with the orthographic projection of the control gate 109 on the substrate 100. That is, along the thickness direction of the semiconductor structure, the sidewall of the shielding gate 108 coincides with the sidewall of the control gate 109, and the width of the shielding gate 108 is the same as the width of the control gate 109.

[0053] Another specific embodiment, such as Figure 2 As shown, the orthographic projection of the shielding grid 108 on the substrate 100 is located in the orthographic projection of the control grid 109 on the substrate 100. That is, the width of the shielding grid 108 is smaller than the width of the control grid.

[0054] Specifically, Figure 1 and Figure 2 As shown, the control gate 109 and the shielding gate 108 are both rectangular structures. The manufacturing process of the rectangular control gate and the shielding gate is relatively simple and controllable, thereby reducing the difficulty of manufacturing the semiconductor structure.

[0055] Of course, in addition to the rectangular structure, the shapes of the control grid and the shielding grid may also be other regular or irregular shapes.

[0056] Another specific embodiment, such as Figure 3 As shown, the control gate 109 includes a main body portion 110 and a groove portion 111 which are arranged in contact with each other in a direction away from the substrate 100 , and a portion of the shielding gate 108 extends into the groove portion 111 .

[0057] According to some optional embodiments of the present application, Figure 1 As shown, the orthographic projection of the control gate 109 on the predetermined plane is the first projection, the orthographic projection of the doped layer 102 on the predetermined plane is the second projection, and the orthographic projection of the doped well region 106 on the predetermined plane is the third projection, the first projection, the second projection and the third projection at least partially overlap, and the predetermined plane is parallel to the thickness direction of the semiconductor structure. That is to say, along the thickness direction of the semiconductor structure, the control gate, the doped layer and the doped well region at least partially overlap, further ensuring the accurate control of the electron beam motion trajectory, and at the same time, the source and drain of the semiconductor device can be further interchanged, thereby further ensuring the high performance flexibility of the semiconductor structure.

[0058] In addition, if Figures 1 to 3 As shown, the semiconductor structure further includes: a dielectric layer 112, which is located on the surface of the doped layer 102 and in contact with the trench gate structure 105; a first conductive layer 113, which is located on the surface of the doped layer 102 and in contact with the source region 103; and a second conductive layer 114, which is located on the surface of the doped layer 102 and in contact with the drain region 104. In this embodiment, the source of the semiconductor structure is extracted by forming an ohmic contact between the first conductive layer and the source region; the drain of the semiconductor structure is extracted by forming an ohmic contact between the second conductive layer and the drain region; and the dielectric layer is provided on the trench gate structure to protect, insulate, adjust the electric field, and enhance the capacitance effect of the semiconductor structure.

[0059] It should be noted that the first conductive layer 113 and the second conductive layer 114 are not in contact with each other.

[0060] And, if Figures 1 to 3 As shown, the dielectric layer 112 is also located on a portion of the surface of the source region 103 away from the substrate 100 , and the dielectric layer 112 is also located on a portion of the surface of the drain region 104 away from the substrate 100 .

[0061] Those skilled in the art can select appropriate materials as the materials of the substrate, the epitaxial layer, the doped layer, the gate oxide layer, the shielding gate, the control gate, the dielectric layer, the first conductive layer and the second conductive layer according to actual needs. The materials of the substrate include but are not limited to semiconductor materials such as single crystal silicon materials, epitaxial silicon materials and silicon carbide materials; the materials of the epitaxial layer include but are not limited to silicon nitride, silicon nitride and silicon oxide; the materials of the doped layer include but are not limited to silicon nitride, silicon nitride and silicon oxide; the materials of the gate oxide layer include but are not limited to silicon oxide, silicon nitride and high-K materials; the materials of the shielding gate include but are not limited to metal gate, polysilicon, silicide and two-dimensional materials; the materials of the control gate include but are not limited to metal gate, polysilicon, silicide and two-dimensional materials; the materials of the dielectric layer include but are not limited to silicon oxide, silicon nitride, phosphorus silicon glass and aluminum oxide; the first conductive layer and the second conductive layer can be single-layer conductive layers or stacked conductive layers; the materials of the first conductive layer and the second conductive layer include but are not limited to metal materials or other conductive materials such as aluminum, tungsten, platinum, palladium, titanium, gold and silver. In addition, the doping ion types of the substrate, the epitaxial layer, the doped layer, the source region, the drain region and the doped well region are determined according to their doping types. N-type doping includes but is not limited to doping ions such as phosphorus, arsenic, and antimony, and P-type doping includes but is not limited to doping ions such as boron, aluminum, gallium, and indium.

[0062] The structural layer may be formed by one or more of molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE) and / or other well-known crystal growth processes.

[0063] In an exemplary embodiment of the present application, materials of the substrate, the epitaxial layer and the doping layer respectively include silicon carbide.

[0064] More specifically, the materials of the substrate, the epitaxial layer and the doped layer are respectively silicon carbide, that is, the semiconductor structure of the present application is a silicon carbide semiconductor. Silicon carbide material has the advantages of large bandgap, high thermal conductivity, high breakdown field strength, high electron saturation drift velocity, etc., and is particularly suitable for making high-power, high-frequency, and high-temperature semiconductor power devices.

[0065] The semiconductor structure of the present application can apply chip size packaging technology, which can reduce the size of the packaged chip to 1 / 9 to 1 / 16 of the traditional package, and has the characteristics of high density and high precision.

[0066] The embodiment of the present application also provides a method for manufacturing a semiconductor structure, such as Figure 1 , Figures 4 to 11 As shown, the method comprises the following steps:

[0067] Step S1, such as Figure 4 As shown, a P-type first initial epitaxial layer 115 and an N-type second initial epitaxial layer 116 are sequentially epitaxially grown on a P-type substrate 100. The thickness and doping concentration of the first initial epitaxial layer 115 and the second initial epitaxial layer 116 are determined by the specifications of the semiconductor structure. The materials of the substrate 100, the first initial epitaxial layer 115 and the second initial epitaxial layer 116 are all silicon carbide, wherein the second initial epitaxial layer 116 serves as a main pressure-bearing layer of the semiconductor structure, and the first initial epitaxial layer 115 serves as a secondary pressure-bearing layer of the semiconductor structure.

[0068] Step S2, such as Figure 5 As shown, the second initial epitaxial layer 116 and the first initial epitaxial layer 115 are trench-etched to obtain a first trench 117, the etching depth is greater than the thickness of the second initial epitaxial layer 116, the remaining first initial epitaxial layer 115 forms an epitaxial layer 101, and the remaining second initial epitaxial layer 116 forms a doped layer 102;

[0069] Step S3, such as Figure 6 As shown, ion implantation and annealing activation are performed on the bottom of the first trench 117 to obtain a doped well region 106, the doped well region 106 wraps the bottom surface and part of the sidewall of the first trench 117, and the doping type of the doped well region 106 is P type;

[0070] Step S4, such as Figure 7 and Figure 8 As shown, the first sub-gate oxide layer 118 is filled in the first trench 117 after the implantation, and then the gate dielectric material 119 is filled in the remaining first trench 117;

[0071] Step S5, such as Fig. 9 As shown, the gate dielectric material 119 is etched back and filled with the second sub-gate oxide layer 120 to form a second trench 121 in the first trench 117. The gate dielectric material 119 after etching back forms a control gate 109, and the first sub-gate oxide layer 118 and the second sub-gate oxide layer 120 constitute a gate oxide layer 107;

[0072] Step S6, continue to fill the gate dielectric material 119 in the second trench 121 to form the shielding gate 108, and obtain Fig.10 The trench gate structure 105 is shown;

[0073] Step S7, Fig.11 As shown, N-type ion implantation and annealing activation are performed in the doping layer 102 on both sides of the trench gate structure 105 to form a source region 103 and a drain region 104;

[0074] Step S8, Figure 1As shown, a dielectric layer 112 is formed on the surface of the trench gate structure 105, on a portion of the surface of the source region 103, and on a portion of the surface of the drain region 104; a first conductive layer 113 is formed on the exposed surface of the source region 103 and on a portion of the dielectric layer 112; and a second conductive layer 114 is formed on the exposed surface of the drain region 104 and on a portion of the dielectric layer 112.

[0075] In the method of the present application, the method of making grooves after multiple epitaxy can more accurately control the relative size relationship between the first groove and the epitaxial layer and the doping layer, so that the device is closer to the design target, and the design is more operational and can better meet the design requirements, while streamlining the process and reducing the production cost.

[0076] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0077] An embodiment of the present application also provides a semiconductor device, comprising: any one of the semiconductor structures described above.

[0078] The semiconductor device includes any of the semiconductor structures described above, in which, by arranging epitaxial layers and doped layers of different conductive types on the substrate, the trench gate structure extends into the epitaxial layer and the doped layer, thereby ensuring that the device has a strong withstand voltage performance, and by forming a doped well region at the bottom of the trench gate structure that wraps the bottom surface and bottom corner of the trench gate, the electric field concentration effect at the bottom of the trench gate structure can be suppressed, thereby avoiding the problem of easy breakdown of the device due to the poor quality of the bottom gate oxide layer of the trench gate structure in the trench type MOS device, thereby ensuring the device reliability of the trench type MOS device. In addition, by arranging the trench gate structure, the electric field strength between the source and drain of the semiconductor device is lengthened, the vertical space of the device is effectively utilized, and the problem of increasing the device area on the plane to achieve withstand voltage, resulting in a significant increase in the overall area of ​​the device, is avoided. In addition, the doped well region spans the epitaxial layer and the doped layer, and the doping type of the doped well region is the same as the doping type of the epitaxial layer, thereby ensuring the forward and reverse conduction function of the semiconductor device.

[0079] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0080] From the above description, it can be seen that the embodiments described in this application achieve the following technical effects:

[0081] 1) In the semiconductor structure of the present application, the epitaxial layer is arranged on the substrate, the doped layer with a doping type different from that of the epitaxial layer is arranged on the epitaxial layer, the source region and the drain region are arranged in the doped layer at intervals, the trench gate structure is located in the epitaxial layer and the doped layer, and is in contact with the source region and the drain region respectively, the doped well region is located in the epitaxial layer and the doped layer, and is in contact with the bottom surface and part of the side surface of the trench gate structure respectively, the doped well region is the same as the doping type of the epitaxial layer, and the doped well region is greater than the doping concentration of the epitaxial layer. The present application arranges epitaxial layers and doped layers of different conductive types on the substrate so that the trench gate structure extends into the epitaxial layer and the doped layer, thereby ensuring that the device has a strong withstand voltage performance, and by forming a doped well region at the bottom of the trench gate structure that wraps the bottom surface and bottom corner of the trench gate, the trench gate bottom electric field concentration effect of the trench gate structure can be suppressed, thereby avoiding the problem of easy device breakdown of the trench MOS device due to the poor quality of the bottom gate oxide layer of the trench gate structure, and ensuring the device reliability of the trench MOS device. Moreover, by setting up a trench gate structure, the electric field strength between the source and drain of the semiconductor device is lengthened, the vertical space of the device is effectively utilized, and the problem of increasing the device area on the plane to achieve voltage resistance, which causes a significant increase in the overall area of ​​the device, is avoided. In addition, the doped well region spans the epitaxial layer and the doped layer, and the doping type of the doped well region is the same as the doping type of the epitaxial layer, which can ensure the forward and reverse conduction function of the semiconductor structure.

[0082] 2) The semiconductor device of the present application includes any of the semiconductor structures described above, in which an epitaxial layer and a doped layer of different conductive types are arranged on the substrate so that the trench gate structure extends into the epitaxial layer and the doped layer, thereby ensuring that the device has a strong withstand voltage performance, and by forming a doped well region at the bottom of the trench gate structure that wraps the bottom surface and bottom corner of the trench gate, the electric field concentration effect at the bottom of the trench gate structure can be suppressed, thereby avoiding the problem of easy breakdown of the device due to the poor quality of the bottom gate oxide layer of the trench gate structure in the trench MOS device, thereby ensuring the device reliability of the trench MOS device. In addition, by setting up a trench gate structure, the electric field strength between the source and drain of the semiconductor device is lengthened, effectively utilizing the vertical space of the device, and avoiding the problem of increasing the device area on the plane to achieve withstand voltage, thereby significantly increasing the overall area of ​​the device. In addition, the doped well region spans the epitaxial layer and the doped layer, and the doping type of the doped well region is the same as that of the epitaxial layer, thereby ensuring the forward and reverse conduction function of the semiconductor device.

[0083] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; an epitaxial layer, located on the substrate; a doping layer, located on a side of the epitaxial layer away from the substrate, the doping type of the epitaxial layer being different from the doping type of the doping layer; A source region is located in the doping layer, and a surface of the source region away from the substrate is a portion of the surface of the doping layer away from the substrate; a drain region, located in the doped layer and on one side of the source region, wherein a surface of the drain region away from the substrate is a portion of a surface of the doped layer away from the substrate; A trench gate structure, located in the epitaxial layer and the doped layer, located between the source region and the drain region and contacting the source region and the drain region respectively; A doped well region is located in the epitaxial layer and the doped layer, and is respectively in contact with a surface of the trench gate structure close to the substrate and a portion of the side surface of the trench gate structure. The doping type of the doped well region is the same as the doping type of the epitaxial layer, and the doping concentration of the doped well region is greater than the doping concentration of the epitaxial layer.

2. The semiconductor structure according to claim 1, characterized in that: The trench gate structure comprises: a gate oxide layer, located in the epitaxial layer and the doped layer, and contacting the source region and the drain region respectively; A shielding gate is located in the gate oxide layer, and a surface of the shielding gate away from the substrate is a partial surface of the doping layer; A control gate is located in the gate oxide layer, the control gate is spaced apart from the shielding gate, and is located on a side of the shielding gate close to the substrate.

3. The semiconductor structure according to claim 2, characterized in that: The orthographic projection of the shielding grid on the substrate coincides with the orthographic projection of the control grid on the substrate.

4. The semiconductor structure according to claim 2, characterized in that: The orthographic projection of the shielding grid on the substrate is located in the orthographic projection of the control grid on the substrate.

5. The semiconductor structure according to claim 2, characterized in that: The control grid and the shielding grid are both rectangular structures.

6. The semiconductor structure according to claim 2, characterized in that: The control gate includes a main body portion and a groove portion which are arranged in contact with each other in a direction away from the substrate, and a portion of the shielding gate extends into the groove portion.

7. The semiconductor structure according to any one of claims 2 to 6, characterized in that: The orthographic projection of the control gate on the predetermined plane is a first projection, the orthographic projection of the doped layer on the predetermined plane is a second projection, and the orthographic projection of the doped well region on the predetermined plane is a third projection. The first projection, the second projection and the third projection at least partially overlap, and the predetermined plane is parallel to the thickness direction of the semiconductor structure.

8. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The semiconductor structure further comprises: a dielectric layer, located on the surface of the doped layer and in contact with the trench gate structure; A first conductive layer, located on the surface of the doped layer and in contact with the source region; The second conductive layer is located on the surface of the doped layer and is in contact with the drain region.

9. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The materials of the substrate, the epitaxial layer and the doping layer respectively include silicon carbide.

10. A semiconductor device, characterized in that: include: The semiconductor structure according to any one of claims 1 to 9.

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