Semiconductor device

Abstract

The invention discloses a semiconductor device. The semiconductor device comprises a substrate; a base region of the first conductivity type; a field stop layer of the first conductivity type; a cathode metal layer; the emitter layer is arranged on one side, facing the first main surface, of the base region, and one side, deviating from the base region, of the emitter layer forms at least part of the first main surface; an anode metal layer; and the buried layer of the first conduction type is arranged in the emitter layer, and the buried layer and the emitter layer are arranged at intervals on the two sides of the first direction. Therefore, the buried layer is arranged on the emitter layer, and the buried layer and the emitter layer are arranged at intervals on the two sides of the first direction, so that the first parasitic junction and the second parasitic junction which are opposite in direction can be introduced into the semiconductor device, and on the premise that the forward conduction performance of the semiconductor device is not influenced or slightly influenced, the semiconductor device can be improved. The avalanche tolerance of the semiconductor device is improved, and thermal damage of the semiconductor device is prevented.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] The avalanche tolerance of a power device is a measure of the maximum energy that the device can withstand when it is subjected to overshoot voltage or current and working in an avalanche state. It is a key indicator of power devices and affects the safety and reliability of the system.

[0003] In the related technology, the structural design of the diode element is not reasonable enough, and there is an avalanche breakdown weak point. Avalanche breakdown always occurs at a specific location. The avalanche current flows through this location, providing a low conduction current path, causing more current to flow through this location, forming a high current density current filament, causing thermal damage, and thus resulting in a reduction in avalanche tolerance. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device having a higher avalanche withstand capability.

[0005] According to an embodiment of the present invention, a semiconductor device includes: a substrate, the substrate having a first main surface and a second main surface on the opposite side of the first main surface, the first main surface and the second main surface being spaced apart in a first direction; a base region of a first conductivity type, the base region being arranged in the substrate and located between the first main surface and the second main surface; a field stop layer of a first conductivity type, the field stop layer being arranged on a side of the base region facing the second main surface, and a side of the field stop layer facing away from the base region constituting at least a portion of the second main surface; a cathode metal layer, the cathode metal layer being arranged on the second main surface; an emitter layer of a second conductivity type, the emitter layer being arranged on a side of the base region facing the first main surface, and a side of the emitter layer facing away from the base region constituting at least a portion of the first main surface; an anode metal layer, the anode metal layer being arranged on the first main surface; a buried layer of a first conductivity type, the buried layer being arranged in the emitter layer, and the buried layer and the emitter layer being spaced apart on both sides of the first direction.

[0006] Therefore, by setting a buried layer in the emitter layer so that the buried layer and the emitter layer are spaced apart on both sides of the first direction, a first parasitic junction and a second parasitic junction in opposite directions can be introduced into the semiconductor device, thereby improving the avalanche tolerance of the semiconductor device and preventing thermal damage to the semiconductor device without affecting or slightly affecting the forward conduction performance of the semiconductor device.

[0007] In some examples of the present invention, the distance from the side of the buried layer adjacent to the first main surface to the side of the emitter layer adjacent to the first main surface is L1, and the distance from the side of the buried layer away from the first main surface to the side of the emitter layer away from the first main surface is L2, and L1 and L2 satisfy the relationship: L1=L2.

[0008] In some examples of the present invention, the thickness of the buried layer in the first direction is D1, and L1, L2 and D1 satisfy the relationship: L1=L2≤D1.

[0009] In some examples of the present invention, the thickness of the emitter layer in the first direction is D2, and D2 and D1 satisfy the relationship: 1 / 3≤D1 / D2<3 / 4.

[0010] In some examples of the present invention, there are multiple buried layers, and the multiple buried layers are spaced apart in the second direction, wherein the first direction and the second direction are perpendicular to each other.

[0011] In some examples of the present invention, there is a spacing distance L3 between two adjacent buried layers, and the spacing distances L3 between any two of the plurality of buried layers are equal.

[0012] In some examples of the present invention, the thicknesses D1 of the plurality of buried layers in the first direction are all equal.

[0013] In some examples of the present invention, the total length of the plurality of buried layers in the second direction is L4, the length of the emitter layer in the first direction is L5, and L4 and L5 satisfy the relationship: 0<L4 / L5≤1 / 5.

[0014] In some examples of the present invention, the ion doping concentration of the buried layer is greater than the ion doping concentration of the base region.

[0015] In some examples of the present invention, the semiconductor device is a fast recovery diode.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 2 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention.

[0020] Reference numerals:

[0021] 100. Semiconductor devices;

[0022] 10. substrate; 101. first main surface; 102. second main surface; 11. base region; 12. field stop layer; 13. emitter layer; 14. buried layer; 20. cathode metal layer; 30. anode metal layer;

[0023] 40, main junction; 50, first parasitic junction; 60, second parasitic junction; 70, equivalent resistance; 80, cathode; 90, anode. DETAILED DESCRIPTION

[0024] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0025] Reference below Figure 1 and Figure 2 A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 includes but is not limited to a fast recovery diode. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description.

[0026] Combination Figure 1 and Figure 2 As shown, the semiconductor device 100 according to the present invention may mainly include: a substrate 10, a base region 11 of a first conductivity type, a field stop layer 12 of a first conductivity type, an emitter layer 13 of a second conductivity type, a cathode metal layer 20, an anode metal layer 30 and a buried layer 14 of a first conductivity type.

[0027] The substrate 10 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, and the first main surface 101 and the second main surface 102 are arranged at intervals in the first direction. The base region 11 is arranged on the substrate 10 and is located between the first main surface 101 and the second main surface 102, the field stop layer 12 is arranged on the side of the base region 11 facing the second main surface 102, and the side of the field stop layer 12 away from the base region 11 constitutes at least a part of the second main surface 102, the emitter layer 13 is arranged on the side of the base region 11 facing the first main surface 101, and the side of the emitter layer 13 away from the base region 11 constitutes at least a part of the first main surface 101, and the cathode metal layer 20 is arranged on the second main surface 102, and the anode metal layer 30 is arranged on the first main surface 101.

[0028] In this way, the basic structure of the semiconductor device 100 can be formed, and a PN junction can be formed between the emitter and the base region 11 of the semiconductor device 100. The PN junction is defined as the main junction 40. When a forward voltage is applied to the semiconductor device 100, the main junction 40 is turned on, and the semiconductor device 100 can be forward-conducted, and when a reverse voltage is applied to the semiconductor device 100, the main junction 40 is not turned on, and the semiconductor device 100 can be reverse-cut off.

[0029] It should be noted that when the reverse voltage applied to the semiconductor device 100 exceeds its rated voltage and reaches the breakdown voltage, the impact ionization of the main junction 40 intensifies and eventually forms an avalanche current. The energy generated by the high voltage and high current is dissipated in the form of heat, causing the temperature of the semiconductor device 100 to continue to rise. When the temperature rises to a temperature that exceeds the limit temperature that the semiconductor device 100 can withstand, it will cause irreversible damage.

[0030] The avalanche withstand of the semiconductor device 100 is a measure of the maximum energy that the device can withstand when it is subjected to overshoot voltage or current and works in an avalanche state. It is a key indicator of the semiconductor device 100 and affects the safety and reliability of the system. The semiconductor device 100 may have avalanche breakdown weak points due to factors such as manufacturing process and special structure. Avalanche breakdown always occurs at a specific location. The avalanche current flows through the location, providing a low conduction current path, causing more current to flow through the location, forming a high current density current filament, causing thermal damage, and thus reducing the avalanche energy.

[0031] By arranging the buried layer 14 in the emitter layer 13, the buried layer 14 is extended in the second direction, and the buried layer 14 and the emitter layer 13 are spaced apart on both sides of the first direction, wherein the first direction is perpendicular to the second direction. In this way, the buried layer 14 can form a PN junction with the emitter layer 13 located between the buried layer 14 and the first main surface 101, and the PN junction is defined as the first parasitic junction 50, and the buried layer 14 can also form a PN junction with the emitter layer 13 located between the buried layer 14 and the base region 11, and the PN junction is defined as the second parasitic junction 60, and the emitter layer 13 spaced apart from the buried layer 14 in the second direction can be equivalent to a resistor.

[0032] The first parasitic junction 50 and the second parasitic junction 60 are in opposite directions, and the first parasitic junction 50 and the main junction 40 are in the same direction. In the equivalent circuit of the semiconductor device 100, the first parasitic junction 50 and the second parasitic junction 60 are connected in series and then connected in parallel with the equivalent resistor 70, and the main junction 40 is located in the main loop, and the main junction 40 is connected in series with the first parasitic junction 50, the second parasitic junction 60 and the equivalent resistor 70 respectively.

[0033] When a forward voltage is applied to the semiconductor device 100 , the main junction 40 and the equivalent resistor 70 are turned on, holes are injected into the base region 11 from the emitter layer 13 , and electrons are injected into the base region 11 from the field stop layer 12 . The two together constitute a forward current from the anode 90 to the cathode 80 .

[0034] When a reverse voltage is applied to the semiconductor device 100, the main junction 40 and the first parasitic junction 50 jointly bear the withstand voltage. When a weak point exists at a certain position of the main junction 40 and avalanche breakdown occurs in advance, the avalanche breakdown generates a large current passing through the equivalent resistor 70, and the voltage drop on the equivalent resistor 70 causes the first parasitic junction 50 to also avalanche breakdown. The electrons generated by the avalanche breakdown of the first parasitic junction 50 move toward the cathode 80, passing through the boundary between the emitter layer 13 and the base region 11, which can reduce the effective carrier concentration of the base region 11 and the electric field gradient, thereby reducing the peak electric field strength of the main junction 40, inhibiting the avalanche breakdown of the main junction 40 at this position, and avoiding the avalanche current concentration and current filament formation at the weak point. And after the avalanche breakdown of the main junction 40 stops, the voltage drop on the equivalent resistor 70 becomes smaller, which is less than the breakdown voltage of the first parasitic junction 50, and the avalanche breakdown of the first parasitic junction 50 also stops accordingly.

[0035] That is, when a reverse voltage is applied to the semiconductor device 100, the avalanche breakdown of the main junction 40 is suppressed by the avalanche breakdown of the first parasitic junction 50, which in turn can suppress the avalanche breakdown of the first parasitic junction 50, thereby suppressing the avalanche current concentration and current filament formation of the semiconductor device 100, thereby improving the avalanche tolerance of the semiconductor device 100 and preventing thermal damage to the semiconductor device 100.

[0036] Therefore, by setting a buried layer 14 in the emitter layer 13, the buried layer 14 and the emitter layer 13 are spaced apart on both sides of the first direction. In this way, a first parasitic junction 50 and a second parasitic junction 60 in opposite directions can be introduced into the semiconductor device 100. Under the premise of not affecting or slightly affecting the forward conduction performance of the semiconductor device 100, the avalanche tolerance of the semiconductor device 100 is improved and thermal damage of the semiconductor device 100 is prevented.

[0037] Combination Figure 1 and Figure 2 As shown, the distance from the side of the buried layer 14 adjacent to the first main surface 101 to the side of the emitter layer 13 adjacent to the first main surface 101 is L1, and the distance from the side of the buried layer 14 away from the first main surface 101 to the side of the emitter layer 13 away from the first main surface 101 is L2, and L1 and L2 satisfy the relationship: L1>0, L2>0, so that the buried layer 14 and the emitter layer 13 are spaced apart on both sides of the first direction, ensuring the normal formation of the main junction 40 and the first parasitic junction 50, and ensuring the improvement of the avalanche tolerance of the semiconductor device 100.

[0038] In a specific embodiment of the present invention, Figure 1 and Figure 2 As shown, L1 and L2 satisfy the relationship: L1 = L2, which can optimize the working performance of the main junction 40 and the first parasitic junction 50, thereby improving the working performance of the semiconductor device 100 and ensuring the effective improvement of the avalanche tolerance of the semiconductor device 100.

[0039] Furthermore, the thickness of the buried layer 14 in the first direction is D1, and L1, L2 and D1 satisfy the relationship: L1=L2≤D1. This can optimize the working performance of the main junction 40 and the first parasitic junction 50, thereby improving the working performance of the semiconductor device 100 and ensuring the effective improvement of the avalanche tolerance of the semiconductor device 100.

[0040] Combination Figure 1 and Figure 2 As shown, the thickness of the emitter layer 13 in the first direction is D2, and D2 and D1 satisfy the relationship: 1 / 3≤D1 / D2≤3 / 4.

[0041] Specifically, the thickness of the equivalent resistor 70 in parallel with the buried layer 14 in the first direction is equal to the thickness of the buried layer 14 in the first direction, and the thickness of the equivalent resistor 70 in the first direction affects the resistance value of the equivalent resistor 70, thereby affecting the voltage drop of the first parasitic junction 50. By setting the ratio of the thickness of the buried layer 14 in the first direction to the thickness of the emitter layer 13 in the first direction to be not less than 1 / 3, it can be ensured that the voltage division on the equivalent resistor 70 can reach the breakdown voltage of the first parasitic junction 50, thereby ensuring the improvement of the avalanche tolerance of the semiconductor device 100.

[0042] Furthermore, by setting the ratio of the thickness of the buried layer 14 in the first direction to the thickness of the emitter layer 13 in the first direction to be no greater than 3 / 4, the sum of the distances between the buried layer 14 and the emitter layer 13 on both sides in the first direction can be set within a reasonable range, thereby avoiding the distance between the buried layer 14 and the emitter layer 13 on both sides in the first direction being too small, thereby avoiding the direct tunneling effect of carriers and avoiding a short circuit between the anode 90 and the cathode 80, thereby further improving the reliability of the semiconductor device 100 and improving the working performance of the semiconductor device 100.

[0043] Combination Figure 1 and Figure 2 As shown, there are multiple buried layers 14, and the multiple buried layers 14 are arranged at intervals in the second direction, wherein the first direction and the second direction are perpendicular to each other. Specifically, different from setting a large-sized buried layer extending in the second direction in the emitter layer, the present application sets multiple buried layers 14 and arranges the multiple buried layers 14 at intervals in the second direction, so that multiple first parasitic junctions 50, multiple second parasitic junctions 60 and multiple equivalent resistors 70 arranged at intervals in the second direction can be formed in the emitter layer 13. No matter where the weak point occurs in the second direction, the adjacent first parasitic junctions 50 and equivalent resistors 70 can play a role, improve the avalanche tolerance, and thus further improve the reliability of the semiconductor device 100.

[0044] Furthermore, combined with Figure 1 and Figure 2 As shown, there is a spacing distance L3 between two adjacent buried layers 14, and any two spacing distances L3 in the plurality of buried layers 14 are equal. Specifically, the length of the equivalent resistor 70 in parallel with the buried layer 14 in the second direction is equal to the spacing distance between the two adjacent buried layers 14, and the length of the equivalent resistor 70 in the second direction will affect the resistance value of the equivalent resistor 70, and further affect the voltage drop of the first parasitic junction 50. By making any two spacing distances in the plurality of buried layers 14 equal, it is convenient to make the resistance value of the equivalent resistor 70 between the two adjacent buried layers 14 the same, so that the uniformity of the current semiconductor device 100 can be improved, and the working performance of the semiconductor device 100 can be improved.

[0045] Combination Figure 1 and Figure 2 As shown, the thickness D1 of each buried layer 14 in the first direction is equal. Specifically, the thickness of the equivalent resistor 70 in parallel with the buried layer 14 in the first direction is equal to the thickness of the buried layer 14 in the first direction, and the thickness of the equivalent resistor 70 in the first direction affects the resistance value of the equivalent resistor 70, thereby affecting the voltage drop of the first parasitic junction 50. By making the thickness of each buried layer 14 in the first direction equal, it is convenient to make the resistance value of the equivalent resistor 70 between two adjacent buried layers 14 the same, thereby improving the uniformity of the current semiconductor device 100 and improving the working performance of the semiconductor device 100.

[0046] Furthermore, the total length of the plurality of buried layers 14 in the second direction is L4, the length of the emitter layer 13 in the first direction is L5, and L4 and L5 satisfy the relationship: 0<L4 / L5≤1 / 5.

[0047] Specifically, the total length of the multiple buried layers 14 in the second direction will not only affect the improvement of avalanche resistance, but also affect the forward conduction voltage drop of the semiconductor device 100. On the one hand, by setting the ratio of the total length of the multiple buried layers 14 in the second direction to the length of the emitter layer 13 in the first direction to be greater than 0, the improvement of avalanche resistance can be ensured. On the other hand, by setting the ratio of the total length of the multiple buried layers 14 in the second direction to the length of the emitter layer 13 in the first direction to be no greater than 1 / 5, the increase of the forward conduction voltage drop can be avoided, and the forward conduction performance of the semiconductor device 100 can be ensured.

[0048] Combination Figure 1 As shown, the ion doping concentration of the buried layer 14 is greater than the ion doping concentration of the base region 11 .

[0049] Specifically, by setting the ion doping concentration of the field stop layer 12 to be much greater than the ion doping concentration of the base region 11, the avalanche breakdown voltage of the first parasitic junction 50 can be made much smaller than the avalanche breakdown voltage of the main junction 40. Therefore, when a reverse voltage is applied to the semiconductor device 100, the main junction 40 bears most of the withstand voltage and the first parasitic junction 50 only bears a small part of the withstand voltage.

[0050] When a weak point exists at a certain position of the main junction 40 and avalanche breakdown occurs prematurely, the avalanche breakdown generates a large current passing through the equivalent resistor 70, ensuring that the voltage drop on the equivalent resistor 70 can reach the breakdown voltage of the first parasitic junction 50, causing the first parasitic junction 50 to also undergo avalanche breakdown, thereby ensuring that the avalanche current concentration of the semiconductor device 100 and the formation of current filaments are effectively suppressed, thereby improving the avalanche tolerance of the semiconductor device 100 and preventing thermal damage to the semiconductor device 100.

[0051] In some embodiments of the present invention, the semiconductor device 100 is a fast recovery diode.

[0052] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0053] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0054] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A substrate (10), the substrate (10) having a first main surface (101) and a second main surface (102) on the opposite side of the first main surface (101), the first main surface (101) and the second main surface (102) being arranged at intervals in a first direction; A base region (11) of a first conductivity type, the base region (11) being arranged on the substrate (10) and located between the first main surface (101) and the second main surface (102); a field stop layer (12) of a first conductivity type, the field stop layer (12) being arranged on a side of the base region (11) facing the second main surface (102), and a side of the field stop layer (12) facing away from the base region (11) constituting at least a portion of the second main surface (102); a cathode metal layer (20), the cathode metal layer (20) being arranged on the second main surface (102); an emitter layer (13) of a second conductivity type, the emitter layer (13) being arranged on a side of the base region (11) facing the first main surface (101), and a side of the emitter layer (13) facing away from the base region (11) constituting at least a portion of the first main surface (101); an anode metal layer (30), the anode metal layer (30) being arranged on the first main surface (101); A buried layer (14) of a first conductive type is arranged in the emitter layer (13), and the buried layer (14) and the emitter layer (13) are arranged at intervals on both sides of a first direction.

2. The semiconductor device according to claim 1, wherein: The distance from the side of the buried layer (14) adjacent to the first main surface (101) to the side of the emitter layer (13) adjacent to the first main surface (101) is L1, and the distance from the side of the buried layer (14) away from the first main surface (101) to the side of the emitter layer (13) away from the first main surface (101) is L2, and L1 and L2 satisfy the relationship: L1=L2.

3. The semiconductor device according to claim 2, wherein: The buried layer (14) has a thickness D1 in the first direction, and L1, L2 and D1 satisfy the relationship: L1=L2≤D1.

4. The semiconductor device according to claim 3, wherein: The thickness of the emitter layer (13) in the first direction is D2, and D2 and D1 satisfy the relationship: 1 / 3≤D1 / D2<3 / 4.

5. The semiconductor device according to claim 1, wherein: There are a plurality of buried layers (14), and the plurality of buried layers (14) are arranged at intervals in a second direction, wherein the first direction and the second direction are perpendicular to each other.

6. The semiconductor device according to claim 5, wherein: There is a spacing distance L3 between two adjacent buried layers (14), and the spacing distance L3 between any two of the plurality of buried layers (14) is equal.

7. The semiconductor device according to claim 6, wherein: The thickness D1 of the plurality of buried layers (14) in the first direction are all equal.

8. The semiconductor device according to claim 5, wherein: The total length of the plurality of buried layers (14) in the second direction is L4, the length of the emitter layer (13) in the first direction is L5, and L4 and L5 satisfy the relationship: 0<L4 / L5≤1 / 5.

9. The semiconductor device according to claim 1, wherein: The ion doping concentration of the buried layer (14) is greater than the ion doping concentration of the base region (11).

10. The semiconductor device according to claim 1, wherein: The semiconductor device (100) is a fast recovery diode.

Images