Semiconductor under-voltage locking chip circuit
By using components such as sampling circuits, current mirror circuits and hysteresis circuits in semiconductor undervoltage locking chip circuits, combined with temperature compensation, the problems of power consumption, area and reference voltage design difficulty of traditional undervoltage protection circuits are solved, and the problem of power consumption, area and reference voltage design is realized. Stable output control and low power consumption effect in low input voltage and low temperature drift environments.
Patent Information
- Application Number
- CN202411343920.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2024-12-17
AI Technical Summary
Traditional semiconductor undervoltage protection circuits face contradictions between power consumption and area during design, and the reference voltage design is difficult, especially in low input voltage and low temperature drift environments.
A semiconductor undervoltage locking chip circuit is designed, using sampling circuit, current mirror circuit, hysteresis circuit, comparison circuit and output and shaping module. By directly sampling the power supply, and using transistors and MOS tubes to form the current mirror and hysteresis part , combined with temperature compensation, optimize the stability of the output control signal.
It effectively reduces the design difficulty of traditional undervoltage circuits on the reference part, improves the temperature stability of the output signal, and is suitable for low input voltage and low temperature drift environments. It has small dynamic power consumption and steep edges, achieving better design results.
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Figure CN119154224A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor undervoltage lockout chip circuit. Background Art
[0002] The sampling part of the traditional undervoltage protection circuit uses resistor voltage division. All sampling resistors use the same process and have the same temperature coefficient. The comparison voltage after power supply voltage division will not be affected by the process and temperature, so the threshold value obtained does not change much. However, there are also some disadvantages. For example, if you want to reduce power consumption, you must increase the resistance of the voltage divider resistor, but this will also increase the chip area. For example, when the power supply voltage is 5V, if you want to get a sampling branch current of lμA, the total resistance of the sampling resistor must reach 5MQ, which occupies a large chip area. Therefore, when designing the circuit, you must fully consider the two factors of power consumption and area to get the optimal design.
[0003] In related technologies, such as Figure 1 As shown, the conventional undervoltage protection circuit is connected to multiple sampling resistors of a power supply, a comparator and a switch MOS tube connected to the sampling resistors, and an undervoltage chip, the switch MOS tube is connected to both ends of one of the sampling resistors, and the gate of the switch MOS tube is connected to the signal output end; the positive input end of the comparator is connected between the two sampling resistors, the negative input end of the comparator is used to connect the reference voltage, the output end of the comparator is connected to the undervoltage signal, and the output end of the undervoltage chip is connected to the signal output end.
[0004] However, the undervoltage protection circuit has a simple structure, mature design concept, and uses a small number of components, but the presence of the sampling resistor will cause a contradiction between the circuit area and power consumption. The larger the resistance, the smaller the power consumption, but the large resistor will occupy a larger chip area; the smaller the resistance, the smaller the chip area, but the power consumption will be greater. Since the circuit requires a reference voltage as a comparison voltage, when the minimum operating voltage of the chip power supply is low, this will increase the difficulty of reference design. Summary of the invention
[0005] The present invention provides a semiconductor under-voltage lockout chip circuit, aiming to solve the problems of high design difficulty and poor under-voltage protection effect of the existing semiconductor under-voltage lockout chip circuit.
[0006] The embodiment of the present invention provides a semiconductor undervoltage lockout chip circuit, including: a power supply, a sampling circuit, a current mirror circuit, a hysteresis circuit, a comparison circuit, an output and shaping module, and a signal output terminal;
[0007] The input end of the sampling circuit is connected to the power supply, the output end of the sampling circuit is respectively connected to the input end of the hysteresis circuit and the input end of the current mirror circuit, the output end of the hysteresis circuit is connected to the output end of the output and shaping module, the output end of the current mirror circuit is respectively connected to the output end of the comparison circuit and the input end of the output and shaping module, the input end of the comparison circuit is connected to the power supply, and the output end of the output and shaping module is connected to the signal output end.
[0008] Preferably, the sampling circuit includes a first resistor, a second resistor and a first transistor;
[0009] The first end of the first resistor serves as the input end of the sampling circuit, and the second end of the first resistor is respectively connected to the first end of the second resistor and the input end of the hysteresis circuit; the second end of the second resistor is connected to the collector of the first transistor, the emitter of the first transistor serves as the output end of the sampling circuit, and the base of the first transistor is connected to the collector of the first transistor.
[0010] Preferably, the current mirror circuit includes a second triode, a third triode, a fourth triode and a third resistor;
[0011] The collector of the second transistor serves as the input end of the current mirror circuit, and the base of the second transistor is respectively connected to the base of the third transistor and the base of the fourth transistor; the base of the second transistor is also connected to the collector of the second transistor; the collector of the third transistor is connected to the output end of the comparison circuit, the emitter of the third transistor is connected to the first end of the third resistor, the emitter of the second transistor, the second end of the third resistor and the emitter of the fourth transistor are connected and grounded; the collector of the fourth transistor serves as the output end of the current mirror circuit.
[0012] Preferably, the comparison circuit includes a first MOS tube and a second MOS tube, the source of the first MOS tube and the source of the second MOS tube are connected and serve as the input end of the comparison circuit, the gate of the first MOS tube is connected to the gate of the second MOS tube, and the drain of the first MOS tube is respectively connected to the collector of the third transistor and the gate of the first MOS tube; the gate of the second MOS tube serves as the output end of the comparison circuit.
[0013] Preferably, the output and shaping module includes: a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and an inverter;
[0014] The source of the third MOS tube is connected to the source of the eighth MOS tube and connected to the power supply, the gate of the third MOS tube is used to connect to an external logic control circuit, the drain of the third MOS tube is respectively connected to the source of the fourth MOS tube and the drain of the eighth MOS tube, and the gate of the eighth MOS tube is respectively connected to the output end of the inverter and the gate of the seventh MOS tube; the output end of the inverter also serves as the output end of the output and shaping module;
[0015] The gate of the fourth MOS tube is connected to the gate of the fifth MOS tube and serves as the input end of the output and shaping module; the drain of the fourth MOS tube is respectively connected to the drain of the fifth MOS tube and the input end of the inverter, the source of the fifth MOS tube is respectively connected to the drain of the sixth MOS tube and the drain of the seventh MOS tube, the drain of the sixth MOS tube is connected to the gate of the sixth MOS tube; the source of the sixth MOS tube is connected to the source of the seventh MOS tube and is grounded.
[0016] Preferably, the hysteresis circuit is a ninth MOS tube, the source of the ninth MOS tube is connected to the power supply, the drain of the ninth MOS tube is connected to the second end of the first resistor; and the gate of the ninth MOS tube is connected to the signal output end.
[0017] Compared with the prior art, the beneficial effect of the present invention is that, by connecting the input end of the sampling circuit to the power supply, the output end of the sampling circuit is respectively connected to the input end of the hysteresis circuit and the input end of the current mirror circuit, the output end of the hysteresis circuit is connected to the output end of the output and shaping module, the output end of the current mirror circuit is respectively connected to the output end of the comparison circuit and the input end of the output and shaping module, the input end of the comparison circuit is connected to the power supply, and the output end of the output and shaping module is connected to the signal output end. In this way, the high difficulty of the design of the reference part of the traditional undervoltage circuit can be overcome. At the same time, the temperature compensation part is integrated into the circuit, so that the output control signal changes less with temperature, and can be effectively applied to the design requiring low input voltage and low temperature drift. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:
[0019] Figure 1 This is the circuit diagram of a traditional undervoltage lockout chip circuit;
[0020] Figure 2 is a circuit diagram of a semiconductor undervoltage lockout chip circuit provided by an embodiment of the present invention;
[0021] Figure 3 is a circuit diagram of an output and shaping module provided by an embodiment of the present invention;
[0022] Figure 4 is an output and power consumption diagram of a conventional under-voltage lockout circuit provided by an embodiment of the present invention;
[0023] Figure 5 1 is an output and power consumption diagram of a semiconductor undervoltage lockout chip circuit provided by an embodiment of the present invention.
[0024] Among them, 1. sampling circuit, 2. current mirror circuit, 3. hysteresis circuit, 4. comparison circuit, 5. output and shaping module. DETAILED DESCRIPTION
[0025] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0026] Combined with Figure 2-Figure 5 As shown, an embodiment of the present invention provides a semiconductor undervoltage lockout chip circuit, including: a power supply VDD, a sampling circuit 1, a current mirror circuit 2, a hysteresis circuit 3, a comparison circuit 4, an output and shaping module 5, and a signal output terminal OUT; the input terminal of the sampling circuit 1 is connected to the power supply VDD, the output terminal of the sampling circuit 1 is respectively connected to the input terminal of the hysteresis circuit 3 and the input terminal of the current mirror circuit 2, the output terminal of the hysteresis circuit 3 is connected to the output terminal of the output and shaping module 5, the output terminal of the current mirror circuit 2 is respectively connected to the output terminal of the comparison circuit 4 and the input terminal of the output and shaping module 5, the input terminal of the comparison circuit 4 is connected to the power supply VDD, and the output terminal of the output and shaping module 5 is connected to the signal output terminal OUT. In this way, the high difficulty of the design of the reference part of the traditional undervoltage circuit can be overcome. At the same time, the temperature compensation part is integrated into the circuit, so that the output control signal changes less with temperature, and can be effectively applied to the design requiring low input voltage and low temperature drift.
[0027] In this embodiment, the sampling circuit 1 includes a first resistor R0, a second resistor R1 and a first transistor Q1;
[0028] The first end of the first resistor R0 serves as the input end of the sampling circuit 1, and the second end of the first resistor R0 is respectively connected to the first end of the second resistor R1 and the input end of the hysteresis circuit 3; the second end of the second resistor R1 is connected to the collector of the first transistor Q1, the emitter of the first transistor Q1 serves as the output end of the sampling circuit 1, and the base of the first transistor Q1 is connected to the collector of the first transistor Q1.
[0029] In this embodiment, the current mirror circuit 2 includes a second transistor Q2, a third transistor Q3, a fourth transistor Q4 and a third resistor R2;
[0030] The collector of the second transistor Q2 serves as the input end of the current mirror circuit 2, and the base of the second transistor Q2 is respectively connected to the base of the third transistor Q3 and the base of the fourth transistor Q4; the base of the second transistor Q2 is also connected to the collector of the second transistor Q2; the collector of the third transistor Q3 is connected to the output end of the comparison circuit 4, the emitter of the third transistor Q3 is connected to the first end of the third resistor R2, the emitter of the second transistor Q2, the second end of the third resistor R2 and the emitter of the fourth transistor Q4 are connected and grounded; the collector of the fourth transistor Q4 serves as the output end of the current mirror circuit 2.
[0031] In this embodiment, the comparison circuit 4 includes a first MOS transistor M1 and a second MOS transistor M2, the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are connected and serve as the input end of the comparison circuit 4, the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are connected, and the drain of the first MOS transistor M1 is respectively connected to the collector of the third triode Q3 and the gate of the first MOS transistor M1; the gate of the second MOS transistor M2 serves as the output end of the comparison circuit 4.
[0032] In this embodiment, the output and shaping module 5 includes: a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8 and an inverter INV;
[0033] The source of the third MOS tube M3 is connected to the source of the eighth MOS tube M8 and connected to the power supply VDD, the gate of the third MOS tube M3 is used to connect to an external logic control circuit, the drain of the third MOS tube M3 is respectively connected to the source of the fourth MOS tube M4 and the drain of the eighth MOS tube M8, and the gate of the eighth MOS tube M8 is respectively connected to the output end of the inverter INV and the gate of the seventh MOS tube M7; the output end of the inverter INV also serves as the output end of the output and shaping module 5;
[0034] The gate of the fourth MOS tube M4 is connected to the gate of the fifth MOS tube M5 and serves as the input end of the output and shaping module 5; the drain of the fourth MOS tube M4 is respectively connected to the drain of the fifth MOS tube M5 and the input end of the inverter INV, the source of the fifth MOS tube M5 is respectively connected to the drain of the sixth MOS tube M6 and the drain of the seventh MOS tube M7, the drain of the sixth MOS tube M6 is connected to the gate of the sixth MOS tube M6; the source of the sixth MOS tube M6 is connected to the source of the seventh MOS tube M7 and is grounded.
[0035] In this embodiment, the hysteresis circuit 3 is a ninth MOS transistor M0, a source of the ninth MOS transistor M0 is connected to the power supply VDD, a drain of the ninth MOS transistor M0 is connected to the second end of the first resistor R0; and a gate of the ninth MOS transistor M0 is connected to the signal output terminal OUT.
[0036] In this embodiment, the circuit is composed of transistors Q1-Q4, MOS tubes M0-M2 and output and shaping modules. Among them, the first resistor R0, the second resistor R1, the first transistor Q1 and the second transistor Q2 constitute a sampling circuit of the power supply voltage VDD, and the first transistor Q1 of the diode connection can rely on its conduction voltage to reduce the size of the sampling resistor of the branch; the second transistor Q2, the third transistor Q3 and the third resistor R2 constitute a micro-current source, and at the same time form a current mirror with the fourth transistor Q4; the current mirror current formed by the first MOS tube M1 and the second MOS tube M2 is compared with the current generated by the micro-current source; the first resistor R0 not only serves as a sampling resistor, but also constitutes the hysteresis part of the circuit with the ninth MOS tube M0; the output and shaping module 5 is a same-direction output.
[0037] In this embodiment, by directly sampling the voltage of the power supply, a current comparison method is used to determine whether the power supply voltage is in a normal working state. When the chip is first powered, the power supply voltage VDD gradually increases from the initial value. Initially, due to the presence of the first transistor Q1 and the second transistor Q2 of the triode connection, VDD cannot reach its conduction threshold, so the circuit cannot work normally. As VDD gradually rises, when it reaches the conduction voltage of the first transistor Q1 and the second transistor Q2, the branch where they are located begins to form a current path, and the fourth transistor Q4 generates a conduction current through the current mirror. At the same time, the micro-current source also starts to work normally. By setting a suitable resistance value of the third resistor R2, the collector current I1 of the third transistor Q3 can be greater than the collector current I4 of the fourth transistor Q4. Then, the current I1 is mirrored to I2 through the current mirror composed of the first MOS tube M1 and the second MOS tube M2.
[0038] Assume that (W / L)MI: (W / L)M2 = 1: 1, that is, I1 = I2, and according to I1>I4, it can be obtained theoretically that 12>14, but since the second MOS tube M2 and the fourth transistor Q4 are a series circuit, in order to satisfy the current I2 = I4, the current I2 must be reduced. It can be seen from the VI characteristic curve of the MOS tube that the current of the transistor in the saturation region is greater than the current in the linear region. Therefore, the only way to reduce I2 is to increase the drain voltage of the second MOS tube M2, so that it enters the linear region from the saturation region, and obtains OUT as a high level through the same-direction output and shaping module 5, and at this time the PMOS tube Mo is turned off, and Fan continues to work as a sampling resistor; as the power supply voltage VDD continues to increase, I0 and I4 gradually increase.
[0039] At this time, since the second MOS tube M2 is in the linear region, its current tends to be constant. When the current increases to I4>I2, in order to balance the current, the drain voltage of the second MOS tube M2 is forced to decrease, and the second MOS tube M2 enters the saturation region from the linear region. After passing through the output and shaping module, the output signal OUT is flipped to a low level. At this time, the ninth MOS tube M0 is turned on, the first resistor R0 is no longer involved in the voltage division part, and the entire system starts to work normally.
[0040] The principle when the power supply voltage is reduced is the same as when the power supply voltage is increased, but the flip threshold is different due to the existence of the first resistor R0 and the ninth MOS tube M0. The output signal OUT will control the entire chip or key modules according to the different requirements of each chip to protect the circuit. When the transistor is in forward bias, the collector current can be expressed as:
[0041]
[0042] Assume that the threshold voltages of the first transistor Q1 and the second transistor Q2 are equal, and use V BE It means that the power supply voltage sampling current of the circuit can be expressed as:
[0043]
[0044] The current generated by the micro-current source composed of the second transistor Q2, the third transistor Q3 and the third resistor R2 can be obtained by formula (3). Assume that the ratio of the emitter areas of the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 is l:n:l.
[0045]
[0046] From the above analysis, it can be seen that when the current I1 is equal to the current I4, the control signal OUT changes, that is, the power supply voltage when Io=I1 is the rising threshold voltage of the protection circuit. Combining formula (2), the rising threshold voltage VDD can be obtained thH .
[0047] VDD thH =I1(R0+R1)+2V BE (4);
[0048] And combined with Io=Il=14 and formula (3), the current Il can be expressed as:
[0049]
[0050] Combining the above two formulas, we can get VDD thH .
[0051] VDD thH =K1V T +2V BE (6);
[0052] in Assuming that the first resistor R0, the second resistor R1 and the third resistor R2 are ideal resistors, K1 is a constant that has nothing to do with temperature, VT has a positive temperature coefficient, and V BE It has a negative temperature coefficient, so in the entire temperature range, the flip threshold of the protection circuit will have a temperature characteristic similar to a bandgap. The ninth MOS tube M0 and the first resistor R0 form a hysteresis loop. When the power supply voltage VDD gradually increases, when its value reaches the threshold voltage, the control signal OUT changes from a high level to a low level. At this time, the ninth MOS tube M0 is turned on and the first resistor R0 is short-circuited. When the power supply voltage gradually decreases, since the first resistor R0 is short-circuited, the power supply voltage needs to be reduced to a level lower than VDD. thH A lower voltage output can cause a jump, and this lower voltage is called the falling threshold voltage, denoted by VDDthL The difference between the rising threshold voltage and the falling threshold voltage is called the hysteresis voltage, which can be expressed by equation (8).
[0053] VDD thL =I1R1+2V BE (7);
[0054] △VDD thH =VDD thH -VDD thL (8);
[0055] Combining the output signal flip condition I0=I1, formula (5) and formula (7) can be obtained:
[0056] VDD thL =K2V T +2V BE (8);
[0057] in It is a constant that has nothing to do with temperature. It can be seen that VDD thL It also has a temperature characteristic similar to the band gap. By setting the values of related components, the low temperature drift characteristic of the output signal can be achieved.
[0058] It can be seen from formulas (6) and (8) that the rising and falling thresholds of the protection circuit proposed by the present invention will be affected by the ratio of the emitter areas of the first resistor R0, the second resistor R1, the third resistor R2 and the second transistor Q2, the third transistor Q3 and the fourth transistor Q4. By adjusting the values of each parameter, the required threshold can be obtained, and the hysteresis of the undervoltage protection can be adjusted by changing the value of the resistor core. It is worth noting that the change of each parameter will also affect its temperature characteristics. Therefore, when designing, it is necessary to realize the low temperature drift characteristics by calculating the values of each parameter.
[0059] See Figure 3 When the input voltage IN rises to a certain value, the voltage will cause the circuit composed of the MOS tubes M3 to M6 to form a path. The third MOS tube M3 and the sixth MOS tube M6 are connected by diodes to reduce the current of the branch. At the same time, due to the existence of the seventh MOS tube M7 and the eighth MOS tube M8, this part has a hysteresis effect.
[0060] Combined with the current comparison part of the undervoltage protection circuit, when the power supply voltage enters the normal working state from undervoltage, the gate voltage VIN of the third MOS tube M3 decreases, so that the drain voltage VD increases. Due to the existence of the third MOS tube M3, the maximum value of its drain voltage VD cannot reach its highest voltage. When the drain voltage VD of the fourth MOS tube M4 reaches the flip threshold of the inverter INV, the output signal OUT jumps to a low level, and the eighth MOS tube M8 is turned on, pulling VD to VDD to prevent the inverter INV from being in a feed-through state all the time, thereby reducing power consumption. At this time, the response of this part is:
[0061]
[0062] When the power supply voltage changes from a normal state to an undervoltage state, the gate voltage VIN of the fourth MOS tube M4 increases, thereby reducing the drain voltage VD. Due to the existence of the sixth MOS tube M6, the minimum value of its drain voltage VD cannot reach the ground. When VD reaches the flip threshold of the inverter INV, the output signal OUT flips to a high level, the seventh MOS tube M7 is turned on, and the VD level is pulled to the ground, so that the NMOS tube of the inverter is turned off, and the inverter INV is out of the feed-through state, reducing power consumption. At this time, the response of this part is:
[0063]
[0064] Figure 4 is an output and power consumption diagram of a conventional under-voltage lockout circuit provided by an embodiment of the present invention; Figure 5 1 is an output and power consumption diagram of a semiconductor undervoltage lockout chip circuit provided by an embodiment of the present invention. As can be seen from the figure, the dynamic power consumption of the output and rectification module proposed by the present invention is much smaller than that of the traditional method, and the edge is steeper.
[0065] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.
[0066] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.
Claims
1. A semiconductor undervoltage lockout chip circuit, It is characterized in that include: Power supply, sampling circuit, current mirror circuit, hysteresis circuit, comparison circuit, output and shaping module and signal output terminal; The input end of the sampling circuit is connected to the power supply, the output end of the sampling circuit is respectively connected to the input end of the hysteresis circuit and the input end of the current mirror circuit, the output end of the hysteresis circuit is connected to the output end of the output and shaping module, the output end of the current mirror circuit is respectively connected to the output end of the comparison circuit and the input end of the output and shaping module, the input end of the comparison circuit is connected to the power supply, and the output end of the output and shaping module is connected to the signal output end.
2. The semiconductor undervoltage lockout chip circuit as claimed in claim 1, It is characterized in that The sampling circuit includes a first resistor, a second resistor and a first transistor; The first end of the first resistor serves as the input end of the sampling circuit, and the second end of the first resistor is respectively connected to the first end of the second resistor and the input end of the hysteresis circuit; the second end of the second resistor is connected to the collector of the first transistor, the emitter of the first transistor serves as the output end of the sampling circuit, and the base of the first transistor is connected to the collector of the first transistor.
3. The semiconductor undervoltage lockout chip circuit as claimed in claim 2, It is characterized in that The current mirror circuit includes a second triode, a third triode, a fourth triode and a third resistor; The collector of the second transistor serves as the input end of the current mirror circuit, and the base of the second transistor is respectively connected to the base of the third transistor and the base of the fourth transistor; the base of the second transistor is also connected to the collector of the second transistor; the collector of the third transistor is connected to the output end of the comparison circuit, the emitter of the third transistor is connected to the first end of the third resistor, the emitter of the second transistor, the second end of the third resistor and the emitter of the fourth transistor are connected and grounded; the collector of the fourth transistor serves as the output end of the current mirror circuit.
4. The semiconductor undervoltage lockout chip circuit as claimed in claim 3, It is characterized in that The comparison circuit comprises a first MOS tube and a second MOS tube, the source of the first MOS tube is connected to the source of the second MOS tube and serves as an input end of the comparison circuit, the gate of the first MOS tube is connected to the gate of the second MOS tube, and the drain of the first MOS tube is respectively connected to the collector of the third triode and the gate of the first MOS tube; The gate of the second MOS tube serves as the output end of the comparison circuit.
5. The semiconductor undervoltage lockout chip circuit as claimed in claim 4, It is characterized in that The output and shaping module includes: a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and an inverter; The source of the third MOS tube is connected to the source of the eighth MOS tube and connected to the power supply, the gate of the third MOS tube is used to connect to an external logic control circuit, the drain of the third MOS tube is respectively connected to the source of the fourth MOS tube and the drain of the eighth MOS tube, and the gate of the eighth MOS tube is respectively connected to the output end of the inverter and the gate of the seventh MOS tube; the output end of the inverter also serves as the output end of the output and shaping module; The gate of the fourth MOS tube is connected to the gate of the fifth MOS tube and serves as the input end of the output and shaping module; the drain of the fourth MOS tube is respectively connected to the drain of the fifth MOS tube and the input end of the inverter, the source of the fifth MOS tube is respectively connected to the drain of the sixth MOS tube and the drain of the seventh MOS tube, the drain of the sixth MOS tube is connected to the gate of the sixth MOS tube; the source of the sixth MOS tube is connected to the source of the seventh MOS tube and is grounded.
6. The semiconductor undervoltage lockout chip circuit as claimed in claim 2, It is characterized in that The hysteresis circuit is a ninth MOS tube, the source of the ninth MOS tube is connected to the power supply, the drain of the ninth MOS tube is connected to the second end of the first resistor; the gate of the ninth MOS tube is connected to the signal output end.